1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * dwc3-pci.c - PCI Specific glue layer 4 * 5 * Copyright (C) 2010-2011 Texas Instruments Incorporated - https://www.ti.com 6 * 7 * Authors: Felipe Balbi <balbi@ti.com>, 8 * Sebastian Andrzej Siewior <bigeasy@linutronix.de> 9 */ 10 11 #include <linux/kernel.h> 12 #include <linux/module.h> 13 #include <linux/slab.h> 14 #include <linux/pci.h> 15 #include <linux/workqueue.h> 16 #include <linux/pm_runtime.h> 17 #include <linux/platform_device.h> 18 #include <linux/gpio/consumer.h> 19 #include <linux/gpio/machine.h> 20 #include <linux/acpi.h> 21 #include <linux/delay.h> 22 23 #define PCI_DEVICE_ID_INTEL_BYT 0x0f37 24 #define PCI_DEVICE_ID_INTEL_MRFLD 0x119e 25 #define PCI_DEVICE_ID_INTEL_BSW 0x22b7 26 #define PCI_DEVICE_ID_INTEL_SPTLP 0x9d30 27 #define PCI_DEVICE_ID_INTEL_SPTH 0xa130 28 #define PCI_DEVICE_ID_INTEL_BXT 0x0aaa 29 #define PCI_DEVICE_ID_INTEL_BXT_M 0x1aaa 30 #define PCI_DEVICE_ID_INTEL_APL 0x5aaa 31 #define PCI_DEVICE_ID_INTEL_KBP 0xa2b0 32 #define PCI_DEVICE_ID_INTEL_CMLLP 0x02ee 33 #define PCI_DEVICE_ID_INTEL_CMLH 0x06ee 34 #define PCI_DEVICE_ID_INTEL_GLK 0x31aa 35 #define PCI_DEVICE_ID_INTEL_CNPLP 0x9dee 36 #define PCI_DEVICE_ID_INTEL_CNPH 0xa36e 37 #define PCI_DEVICE_ID_INTEL_CNPV 0xa3b0 38 #define PCI_DEVICE_ID_INTEL_ICLLP 0x34ee 39 #define PCI_DEVICE_ID_INTEL_EHL 0x4b7e 40 #define PCI_DEVICE_ID_INTEL_TGPLP 0xa0ee 41 #define PCI_DEVICE_ID_INTEL_TGPH 0x43ee 42 #define PCI_DEVICE_ID_INTEL_JSP 0x4dee 43 #define PCI_DEVICE_ID_INTEL_ADL 0x465e 44 #define PCI_DEVICE_ID_INTEL_ADLP 0x51ee 45 #define PCI_DEVICE_ID_INTEL_ADLM 0x54ee 46 #define PCI_DEVICE_ID_INTEL_ADLS 0x7ae1 47 #define PCI_DEVICE_ID_INTEL_RPLS 0x7a61 48 #define PCI_DEVICE_ID_INTEL_MTLP 0x7ec1 49 #define PCI_DEVICE_ID_INTEL_MTL 0x7e7e 50 #define PCI_DEVICE_ID_INTEL_TGL 0x9a15 51 #define PCI_DEVICE_ID_AMD_MR 0x163a 52 53 #define PCI_INTEL_BXT_DSM_GUID "732b85d5-b7a7-4a1b-9ba0-4bbd00ffd511" 54 #define PCI_INTEL_BXT_FUNC_PMU_PWR 4 55 #define PCI_INTEL_BXT_STATE_D0 0 56 #define PCI_INTEL_BXT_STATE_D3 3 57 58 #define GP_RWBAR 1 59 #define GP_RWREG1 0xa0 60 #define GP_RWREG1_ULPI_REFCLK_DISABLE (1 << 17) 61 62 /** 63 * struct dwc3_pci - Driver private structure 64 * @dwc3: child dwc3 platform_device 65 * @pci: our link to PCI bus 66 * @guid: _DSM GUID 67 * @has_dsm_for_pm: true for devices which need to run _DSM on runtime PM 68 * @wakeup_work: work for asynchronous resume 69 */ 70 struct dwc3_pci { 71 struct platform_device *dwc3; 72 struct pci_dev *pci; 73 74 guid_t guid; 75 76 unsigned int has_dsm_for_pm:1; 77 struct work_struct wakeup_work; 78 }; 79 80 static const struct acpi_gpio_params reset_gpios = { 0, 0, false }; 81 static const struct acpi_gpio_params cs_gpios = { 1, 0, false }; 82 83 static const struct acpi_gpio_mapping acpi_dwc3_byt_gpios[] = { 84 { "reset-gpios", &reset_gpios, 1 }, 85 { "cs-gpios", &cs_gpios, 1 }, 86 { }, 87 }; 88 89 static struct gpiod_lookup_table platform_bytcr_gpios = { 90 .dev_id = "0000:00:16.0", 91 .table = { 92 GPIO_LOOKUP("INT33FC:00", 54, "cs", GPIO_ACTIVE_HIGH), 93 GPIO_LOOKUP("INT33FC:02", 14, "reset", GPIO_ACTIVE_HIGH), 94 {} 95 }, 96 }; 97 98 static int dwc3_byt_enable_ulpi_refclock(struct pci_dev *pci) 99 { 100 void __iomem *reg; 101 u32 value; 102 103 reg = pcim_iomap(pci, GP_RWBAR, 0); 104 if (!reg) 105 return -ENOMEM; 106 107 value = readl(reg + GP_RWREG1); 108 if (!(value & GP_RWREG1_ULPI_REFCLK_DISABLE)) 109 goto unmap; /* ULPI refclk already enabled */ 110 111 value &= ~GP_RWREG1_ULPI_REFCLK_DISABLE; 112 writel(value, reg + GP_RWREG1); 113 /* This comes from the Intel Android x86 tree w/o any explanation */ 114 msleep(100); 115 unmap: 116 pcim_iounmap(pci, reg); 117 return 0; 118 } 119 120 static const struct property_entry dwc3_pci_intel_properties[] = { 121 PROPERTY_ENTRY_STRING("dr_mode", "peripheral"), 122 PROPERTY_ENTRY_BOOL("linux,sysdev_is_parent"), 123 {} 124 }; 125 126 static const struct property_entry dwc3_pci_intel_phy_charger_detect_properties[] = { 127 PROPERTY_ENTRY_STRING("dr_mode", "peripheral"), 128 PROPERTY_ENTRY_BOOL("snps,dis_u2_susphy_quirk"), 129 PROPERTY_ENTRY_BOOL("linux,phy_charger_detect"), 130 {} 131 }; 132 133 static const struct property_entry dwc3_pci_intel_byt_properties[] = { 134 PROPERTY_ENTRY_STRING("dr_mode", "peripheral"), 135 PROPERTY_ENTRY_BOOL("snps,dis_u2_susphy_quirk"), 136 PROPERTY_ENTRY_BOOL("linux,sysdev_is_parent"), 137 {} 138 }; 139 140 static const struct property_entry dwc3_pci_mrfld_properties[] = { 141 PROPERTY_ENTRY_STRING("dr_mode", "otg"), 142 PROPERTY_ENTRY_STRING("linux,extcon-name", "mrfld_bcove_pwrsrc"), 143 PROPERTY_ENTRY_BOOL("snps,dis_u3_susphy_quirk"), 144 PROPERTY_ENTRY_BOOL("snps,dis_u2_susphy_quirk"), 145 PROPERTY_ENTRY_BOOL("snps,usb2-gadget-lpm-disable"), 146 PROPERTY_ENTRY_BOOL("linux,sysdev_is_parent"), 147 {} 148 }; 149 150 static const struct property_entry dwc3_pci_amd_properties[] = { 151 PROPERTY_ENTRY_BOOL("snps,has-lpm-erratum"), 152 PROPERTY_ENTRY_U8("snps,lpm-nyet-threshold", 0xf), 153 PROPERTY_ENTRY_BOOL("snps,u2exit_lfps_quirk"), 154 PROPERTY_ENTRY_BOOL("snps,u2ss_inp3_quirk"), 155 PROPERTY_ENTRY_BOOL("snps,req_p1p2p3_quirk"), 156 PROPERTY_ENTRY_BOOL("snps,del_p1p2p3_quirk"), 157 PROPERTY_ENTRY_BOOL("snps,del_phy_power_chg_quirk"), 158 PROPERTY_ENTRY_BOOL("snps,lfps_filter_quirk"), 159 PROPERTY_ENTRY_BOOL("snps,rx_detect_poll_quirk"), 160 PROPERTY_ENTRY_BOOL("snps,tx_de_emphasis_quirk"), 161 PROPERTY_ENTRY_U8("snps,tx_de_emphasis", 1), 162 /* FIXME these quirks should be removed when AMD NL tapes out */ 163 PROPERTY_ENTRY_BOOL("snps,disable_scramble_quirk"), 164 PROPERTY_ENTRY_BOOL("snps,dis_u3_susphy_quirk"), 165 PROPERTY_ENTRY_BOOL("snps,dis_u2_susphy_quirk"), 166 PROPERTY_ENTRY_BOOL("linux,sysdev_is_parent"), 167 {} 168 }; 169 170 static const struct property_entry dwc3_pci_mr_properties[] = { 171 PROPERTY_ENTRY_STRING("dr_mode", "otg"), 172 PROPERTY_ENTRY_BOOL("usb-role-switch"), 173 PROPERTY_ENTRY_STRING("role-switch-default-mode", "host"), 174 PROPERTY_ENTRY_BOOL("linux,sysdev_is_parent"), 175 {} 176 }; 177 178 static const struct software_node dwc3_pci_intel_swnode = { 179 .properties = dwc3_pci_intel_properties, 180 }; 181 182 static const struct software_node dwc3_pci_intel_phy_charger_detect_swnode = { 183 .properties = dwc3_pci_intel_phy_charger_detect_properties, 184 }; 185 186 static const struct software_node dwc3_pci_intel_byt_swnode = { 187 .properties = dwc3_pci_intel_byt_properties, 188 }; 189 190 static const struct software_node dwc3_pci_intel_mrfld_swnode = { 191 .properties = dwc3_pci_mrfld_properties, 192 }; 193 194 static const struct software_node dwc3_pci_amd_swnode = { 195 .properties = dwc3_pci_amd_properties, 196 }; 197 198 static const struct software_node dwc3_pci_amd_mr_swnode = { 199 .properties = dwc3_pci_mr_properties, 200 }; 201 202 static int dwc3_pci_quirks(struct dwc3_pci *dwc, 203 const struct software_node *swnode) 204 { 205 struct pci_dev *pdev = dwc->pci; 206 207 if (pdev->vendor == PCI_VENDOR_ID_INTEL) { 208 if (pdev->device == PCI_DEVICE_ID_INTEL_BXT || 209 pdev->device == PCI_DEVICE_ID_INTEL_BXT_M || 210 pdev->device == PCI_DEVICE_ID_INTEL_EHL) { 211 guid_parse(PCI_INTEL_BXT_DSM_GUID, &dwc->guid); 212 dwc->has_dsm_for_pm = true; 213 } 214 215 if (pdev->device == PCI_DEVICE_ID_INTEL_BYT) { 216 struct gpio_desc *gpio; 217 int ret; 218 219 /* On BYT the FW does not always enable the refclock */ 220 ret = dwc3_byt_enable_ulpi_refclock(pdev); 221 if (ret) 222 return ret; 223 224 ret = devm_acpi_dev_add_driver_gpios(&pdev->dev, 225 acpi_dwc3_byt_gpios); 226 if (ret) 227 dev_dbg(&pdev->dev, "failed to add mapping table\n"); 228 229 /* 230 * A lot of BYT devices lack ACPI resource entries for 231 * the GPIOs, add a fallback mapping to the reference 232 * design GPIOs which all boards seem to use. 233 */ 234 gpiod_add_lookup_table(&platform_bytcr_gpios); 235 236 /* 237 * These GPIOs will turn on the USB2 PHY. Note that we have to 238 * put the gpio descriptors again here because the phy driver 239 * might want to grab them, too. 240 */ 241 gpio = gpiod_get_optional(&pdev->dev, "cs", GPIOD_OUT_LOW); 242 if (IS_ERR(gpio)) 243 return PTR_ERR(gpio); 244 245 gpiod_set_value_cansleep(gpio, 1); 246 gpiod_put(gpio); 247 248 gpio = gpiod_get_optional(&pdev->dev, "reset", GPIOD_OUT_LOW); 249 if (IS_ERR(gpio)) 250 return PTR_ERR(gpio); 251 252 if (gpio) { 253 gpiod_set_value_cansleep(gpio, 1); 254 gpiod_put(gpio); 255 usleep_range(10000, 11000); 256 } 257 258 /* 259 * Make the pdev name predictable (only 1 DWC3 on BYT) 260 * and patch the phy dev-name into the lookup table so 261 * that the phy-driver can get the GPIOs. 262 */ 263 dwc->dwc3->id = PLATFORM_DEVID_NONE; 264 platform_bytcr_gpios.dev_id = "dwc3.ulpi"; 265 266 /* 267 * Some Android tablets with a Crystal Cove PMIC 268 * (INT33FD), rely on the TUSB1211 phy for charger 269 * detection. These can be identified by them _not_ 270 * using the standard ACPI battery and ac drivers. 271 */ 272 if (acpi_dev_present("INT33FD", "1", 2) && 273 acpi_quirk_skip_acpi_ac_and_battery()) { 274 dev_info(&pdev->dev, "Using TUSB1211 phy for charger detection\n"); 275 swnode = &dwc3_pci_intel_phy_charger_detect_swnode; 276 } 277 } 278 } 279 280 return device_add_software_node(&dwc->dwc3->dev, swnode); 281 } 282 283 #ifdef CONFIG_PM 284 static void dwc3_pci_resume_work(struct work_struct *work) 285 { 286 struct dwc3_pci *dwc = container_of(work, struct dwc3_pci, wakeup_work); 287 struct platform_device *dwc3 = dwc->dwc3; 288 int ret; 289 290 ret = pm_runtime_get_sync(&dwc3->dev); 291 if (ret) { 292 pm_runtime_put_sync_autosuspend(&dwc3->dev); 293 return; 294 } 295 296 pm_runtime_mark_last_busy(&dwc3->dev); 297 pm_runtime_put_sync_autosuspend(&dwc3->dev); 298 } 299 #endif 300 301 static int dwc3_pci_probe(struct pci_dev *pci, const struct pci_device_id *id) 302 { 303 struct dwc3_pci *dwc; 304 struct resource res[2]; 305 int ret; 306 struct device *dev = &pci->dev; 307 308 ret = pcim_enable_device(pci); 309 if (ret) { 310 dev_err(dev, "failed to enable pci device\n"); 311 return -ENODEV; 312 } 313 314 pci_set_master(pci); 315 316 dwc = devm_kzalloc(dev, sizeof(*dwc), GFP_KERNEL); 317 if (!dwc) 318 return -ENOMEM; 319 320 dwc->dwc3 = platform_device_alloc("dwc3", PLATFORM_DEVID_AUTO); 321 if (!dwc->dwc3) 322 return -ENOMEM; 323 324 memset(res, 0x00, sizeof(struct resource) * ARRAY_SIZE(res)); 325 326 res[0].start = pci_resource_start(pci, 0); 327 res[0].end = pci_resource_end(pci, 0); 328 res[0].name = "dwc_usb3"; 329 res[0].flags = IORESOURCE_MEM; 330 331 res[1].start = pci->irq; 332 res[1].name = "dwc_usb3"; 333 res[1].flags = IORESOURCE_IRQ; 334 335 ret = platform_device_add_resources(dwc->dwc3, res, ARRAY_SIZE(res)); 336 if (ret) { 337 dev_err(dev, "couldn't add resources to dwc3 device\n"); 338 goto err; 339 } 340 341 dwc->pci = pci; 342 dwc->dwc3->dev.parent = dev; 343 ACPI_COMPANION_SET(&dwc->dwc3->dev, ACPI_COMPANION(dev)); 344 345 ret = dwc3_pci_quirks(dwc, (void *)id->driver_data); 346 if (ret) 347 goto err; 348 349 ret = platform_device_add(dwc->dwc3); 350 if (ret) { 351 dev_err(dev, "failed to register dwc3 device\n"); 352 goto err; 353 } 354 355 device_init_wakeup(dev, true); 356 pci_set_drvdata(pci, dwc); 357 pm_runtime_put(dev); 358 #ifdef CONFIG_PM 359 INIT_WORK(&dwc->wakeup_work, dwc3_pci_resume_work); 360 #endif 361 362 return 0; 363 err: 364 device_remove_software_node(&dwc->dwc3->dev); 365 platform_device_put(dwc->dwc3); 366 return ret; 367 } 368 369 static void dwc3_pci_remove(struct pci_dev *pci) 370 { 371 struct dwc3_pci *dwc = pci_get_drvdata(pci); 372 struct pci_dev *pdev = dwc->pci; 373 374 if (pdev->device == PCI_DEVICE_ID_INTEL_BYT) 375 gpiod_remove_lookup_table(&platform_bytcr_gpios); 376 #ifdef CONFIG_PM 377 cancel_work_sync(&dwc->wakeup_work); 378 #endif 379 device_init_wakeup(&pci->dev, false); 380 pm_runtime_get(&pci->dev); 381 device_remove_software_node(&dwc->dwc3->dev); 382 platform_device_unregister(dwc->dwc3); 383 } 384 385 static const struct pci_device_id dwc3_pci_id_table[] = { 386 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_BSW), 387 (kernel_ulong_t) &dwc3_pci_intel_swnode, }, 388 389 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_BYT), 390 (kernel_ulong_t) &dwc3_pci_intel_byt_swnode, }, 391 392 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_MRFLD), 393 (kernel_ulong_t) &dwc3_pci_intel_mrfld_swnode, }, 394 395 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_CMLLP), 396 (kernel_ulong_t) &dwc3_pci_intel_swnode, }, 397 398 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_CMLH), 399 (kernel_ulong_t) &dwc3_pci_intel_swnode, }, 400 401 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_SPTLP), 402 (kernel_ulong_t) &dwc3_pci_intel_swnode, }, 403 404 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_SPTH), 405 (kernel_ulong_t) &dwc3_pci_intel_swnode, }, 406 407 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_BXT), 408 (kernel_ulong_t) &dwc3_pci_intel_swnode, }, 409 410 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_BXT_M), 411 (kernel_ulong_t) &dwc3_pci_intel_swnode, }, 412 413 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_APL), 414 (kernel_ulong_t) &dwc3_pci_intel_swnode, }, 415 416 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_KBP), 417 (kernel_ulong_t) &dwc3_pci_intel_swnode, }, 418 419 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_GLK), 420 (kernel_ulong_t) &dwc3_pci_intel_swnode, }, 421 422 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_CNPLP), 423 (kernel_ulong_t) &dwc3_pci_intel_swnode, }, 424 425 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_CNPH), 426 (kernel_ulong_t) &dwc3_pci_intel_swnode, }, 427 428 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_CNPV), 429 (kernel_ulong_t) &dwc3_pci_intel_swnode, }, 430 431 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ICLLP), 432 (kernel_ulong_t) &dwc3_pci_intel_swnode, }, 433 434 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_EHL), 435 (kernel_ulong_t) &dwc3_pci_intel_swnode, }, 436 437 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_TGPLP), 438 (kernel_ulong_t) &dwc3_pci_intel_swnode, }, 439 440 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_TGPH), 441 (kernel_ulong_t) &dwc3_pci_intel_swnode, }, 442 443 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_JSP), 444 (kernel_ulong_t) &dwc3_pci_intel_swnode, }, 445 446 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ADL), 447 (kernel_ulong_t) &dwc3_pci_intel_swnode, }, 448 449 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ADLP), 450 (kernel_ulong_t) &dwc3_pci_intel_swnode, }, 451 452 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ADLM), 453 (kernel_ulong_t) &dwc3_pci_intel_swnode, }, 454 455 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ADLS), 456 (kernel_ulong_t) &dwc3_pci_intel_swnode, }, 457 458 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_RPLS), 459 (kernel_ulong_t) &dwc3_pci_intel_swnode, }, 460 461 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_MTLP), 462 (kernel_ulong_t) &dwc3_pci_intel_swnode, }, 463 464 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_MTL), 465 (kernel_ulong_t) &dwc3_pci_intel_swnode, }, 466 467 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_TGL), 468 (kernel_ulong_t) &dwc3_pci_intel_swnode, }, 469 470 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_NL_USB), 471 (kernel_ulong_t) &dwc3_pci_amd_swnode, }, 472 473 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_MR), 474 (kernel_ulong_t)&dwc3_pci_amd_mr_swnode, }, 475 476 { } /* Terminating Entry */ 477 }; 478 MODULE_DEVICE_TABLE(pci, dwc3_pci_id_table); 479 480 #if defined(CONFIG_PM) || defined(CONFIG_PM_SLEEP) 481 static int dwc3_pci_dsm(struct dwc3_pci *dwc, int param) 482 { 483 union acpi_object *obj; 484 union acpi_object tmp; 485 union acpi_object argv4 = ACPI_INIT_DSM_ARGV4(1, &tmp); 486 487 if (!dwc->has_dsm_for_pm) 488 return 0; 489 490 tmp.type = ACPI_TYPE_INTEGER; 491 tmp.integer.value = param; 492 493 obj = acpi_evaluate_dsm(ACPI_HANDLE(&dwc->pci->dev), &dwc->guid, 494 1, PCI_INTEL_BXT_FUNC_PMU_PWR, &argv4); 495 if (!obj) { 496 dev_err(&dwc->pci->dev, "failed to evaluate _DSM\n"); 497 return -EIO; 498 } 499 500 ACPI_FREE(obj); 501 502 return 0; 503 } 504 #endif /* CONFIG_PM || CONFIG_PM_SLEEP */ 505 506 #ifdef CONFIG_PM 507 static int dwc3_pci_runtime_suspend(struct device *dev) 508 { 509 struct dwc3_pci *dwc = dev_get_drvdata(dev); 510 511 if (device_can_wakeup(dev)) 512 return dwc3_pci_dsm(dwc, PCI_INTEL_BXT_STATE_D3); 513 514 return -EBUSY; 515 } 516 517 static int dwc3_pci_runtime_resume(struct device *dev) 518 { 519 struct dwc3_pci *dwc = dev_get_drvdata(dev); 520 int ret; 521 522 ret = dwc3_pci_dsm(dwc, PCI_INTEL_BXT_STATE_D0); 523 if (ret) 524 return ret; 525 526 queue_work(pm_wq, &dwc->wakeup_work); 527 528 return 0; 529 } 530 #endif /* CONFIG_PM */ 531 532 #ifdef CONFIG_PM_SLEEP 533 static int dwc3_pci_suspend(struct device *dev) 534 { 535 struct dwc3_pci *dwc = dev_get_drvdata(dev); 536 537 return dwc3_pci_dsm(dwc, PCI_INTEL_BXT_STATE_D3); 538 } 539 540 static int dwc3_pci_resume(struct device *dev) 541 { 542 struct dwc3_pci *dwc = dev_get_drvdata(dev); 543 544 return dwc3_pci_dsm(dwc, PCI_INTEL_BXT_STATE_D0); 545 } 546 #endif /* CONFIG_PM_SLEEP */ 547 548 static const struct dev_pm_ops dwc3_pci_dev_pm_ops = { 549 SET_SYSTEM_SLEEP_PM_OPS(dwc3_pci_suspend, dwc3_pci_resume) 550 SET_RUNTIME_PM_OPS(dwc3_pci_runtime_suspend, dwc3_pci_runtime_resume, 551 NULL) 552 }; 553 554 static struct pci_driver dwc3_pci_driver = { 555 .name = "dwc3-pci", 556 .id_table = dwc3_pci_id_table, 557 .probe = dwc3_pci_probe, 558 .remove = dwc3_pci_remove, 559 .driver = { 560 .pm = &dwc3_pci_dev_pm_ops, 561 } 562 }; 563 564 MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>"); 565 MODULE_LICENSE("GPL v2"); 566 MODULE_DESCRIPTION("DesignWare USB3 PCI Glue Layer"); 567 568 module_pci_driver(dwc3_pci_driver); 569