1 // SPDX-License-Identifier: GPL-2.0 2 /** 3 * dwc3-pci.c - PCI Specific glue layer 4 * 5 * Copyright (C) 2010-2011 Texas Instruments Incorporated - https://www.ti.com 6 * 7 * Authors: Felipe Balbi <balbi@ti.com>, 8 * Sebastian Andrzej Siewior <bigeasy@linutronix.de> 9 */ 10 11 #include <linux/kernel.h> 12 #include <linux/module.h> 13 #include <linux/slab.h> 14 #include <linux/pci.h> 15 #include <linux/workqueue.h> 16 #include <linux/pm_runtime.h> 17 #include <linux/platform_device.h> 18 #include <linux/gpio/consumer.h> 19 #include <linux/gpio/machine.h> 20 #include <linux/acpi.h> 21 #include <linux/delay.h> 22 23 #define PCI_DEVICE_ID_INTEL_BYT 0x0f37 24 #define PCI_DEVICE_ID_INTEL_MRFLD 0x119e 25 #define PCI_DEVICE_ID_INTEL_BSW 0x22b7 26 #define PCI_DEVICE_ID_INTEL_SPTLP 0x9d30 27 #define PCI_DEVICE_ID_INTEL_SPTH 0xa130 28 #define PCI_DEVICE_ID_INTEL_BXT 0x0aaa 29 #define PCI_DEVICE_ID_INTEL_BXT_M 0x1aaa 30 #define PCI_DEVICE_ID_INTEL_APL 0x5aaa 31 #define PCI_DEVICE_ID_INTEL_KBP 0xa2b0 32 #define PCI_DEVICE_ID_INTEL_CMLLP 0x02ee 33 #define PCI_DEVICE_ID_INTEL_CMLH 0x06ee 34 #define PCI_DEVICE_ID_INTEL_GLK 0x31aa 35 #define PCI_DEVICE_ID_INTEL_CNPLP 0x9dee 36 #define PCI_DEVICE_ID_INTEL_CNPH 0xa36e 37 #define PCI_DEVICE_ID_INTEL_CNPV 0xa3b0 38 #define PCI_DEVICE_ID_INTEL_ICLLP 0x34ee 39 #define PCI_DEVICE_ID_INTEL_EHLLP 0x4b7e 40 #define PCI_DEVICE_ID_INTEL_TGPLP 0xa0ee 41 #define PCI_DEVICE_ID_INTEL_TGPH 0x43ee 42 #define PCI_DEVICE_ID_INTEL_JSP 0x4dee 43 44 #define PCI_INTEL_BXT_DSM_GUID "732b85d5-b7a7-4a1b-9ba0-4bbd00ffd511" 45 #define PCI_INTEL_BXT_FUNC_PMU_PWR 4 46 #define PCI_INTEL_BXT_STATE_D0 0 47 #define PCI_INTEL_BXT_STATE_D3 3 48 49 #define GP_RWBAR 1 50 #define GP_RWREG1 0xa0 51 #define GP_RWREG1_ULPI_REFCLK_DISABLE (1 << 17) 52 53 /** 54 * struct dwc3_pci - Driver private structure 55 * @dwc3: child dwc3 platform_device 56 * @pci: our link to PCI bus 57 * @guid: _DSM GUID 58 * @has_dsm_for_pm: true for devices which need to run _DSM on runtime PM 59 * @wakeup_work: work for asynchronous resume 60 */ 61 struct dwc3_pci { 62 struct platform_device *dwc3; 63 struct pci_dev *pci; 64 65 guid_t guid; 66 67 unsigned int has_dsm_for_pm:1; 68 struct work_struct wakeup_work; 69 }; 70 71 static const struct acpi_gpio_params reset_gpios = { 0, 0, false }; 72 static const struct acpi_gpio_params cs_gpios = { 1, 0, false }; 73 74 static const struct acpi_gpio_mapping acpi_dwc3_byt_gpios[] = { 75 { "reset-gpios", &reset_gpios, 1 }, 76 { "cs-gpios", &cs_gpios, 1 }, 77 { }, 78 }; 79 80 static struct gpiod_lookup_table platform_bytcr_gpios = { 81 .dev_id = "0000:00:16.0", 82 .table = { 83 GPIO_LOOKUP("INT33FC:00", 54, "reset", GPIO_ACTIVE_HIGH), 84 GPIO_LOOKUP("INT33FC:02", 14, "cs", GPIO_ACTIVE_HIGH), 85 {} 86 }, 87 }; 88 89 static int dwc3_byt_enable_ulpi_refclock(struct pci_dev *pci) 90 { 91 void __iomem *reg; 92 u32 value; 93 94 reg = pcim_iomap(pci, GP_RWBAR, 0); 95 if (!reg) 96 return -ENOMEM; 97 98 value = readl(reg + GP_RWREG1); 99 if (!(value & GP_RWREG1_ULPI_REFCLK_DISABLE)) 100 goto unmap; /* ULPI refclk already enabled */ 101 102 value &= ~GP_RWREG1_ULPI_REFCLK_DISABLE; 103 writel(value, reg + GP_RWREG1); 104 /* This comes from the Intel Android x86 tree w/o any explanation */ 105 msleep(100); 106 unmap: 107 pcim_iounmap(pci, reg); 108 return 0; 109 } 110 111 static const struct property_entry dwc3_pci_intel_properties[] = { 112 PROPERTY_ENTRY_STRING("dr_mode", "peripheral"), 113 PROPERTY_ENTRY_BOOL("linux,sysdev_is_parent"), 114 {} 115 }; 116 117 static const struct property_entry dwc3_pci_mrfld_properties[] = { 118 PROPERTY_ENTRY_STRING("dr_mode", "otg"), 119 PROPERTY_ENTRY_STRING("linux,extcon-name", "mrfld_bcove_pwrsrc"), 120 PROPERTY_ENTRY_BOOL("linux,sysdev_is_parent"), 121 {} 122 }; 123 124 static const struct property_entry dwc3_pci_amd_properties[] = { 125 PROPERTY_ENTRY_BOOL("snps,has-lpm-erratum"), 126 PROPERTY_ENTRY_U8("snps,lpm-nyet-threshold", 0xf), 127 PROPERTY_ENTRY_BOOL("snps,u2exit_lfps_quirk"), 128 PROPERTY_ENTRY_BOOL("snps,u2ss_inp3_quirk"), 129 PROPERTY_ENTRY_BOOL("snps,req_p1p2p3_quirk"), 130 PROPERTY_ENTRY_BOOL("snps,del_p1p2p3_quirk"), 131 PROPERTY_ENTRY_BOOL("snps,del_phy_power_chg_quirk"), 132 PROPERTY_ENTRY_BOOL("snps,lfps_filter_quirk"), 133 PROPERTY_ENTRY_BOOL("snps,rx_detect_poll_quirk"), 134 PROPERTY_ENTRY_BOOL("snps,tx_de_emphasis_quirk"), 135 PROPERTY_ENTRY_U8("snps,tx_de_emphasis", 1), 136 /* FIXME these quirks should be removed when AMD NL tapes out */ 137 PROPERTY_ENTRY_BOOL("snps,disable_scramble_quirk"), 138 PROPERTY_ENTRY_BOOL("snps,dis_u3_susphy_quirk"), 139 PROPERTY_ENTRY_BOOL("snps,dis_u2_susphy_quirk"), 140 PROPERTY_ENTRY_BOOL("linux,sysdev_is_parent"), 141 {} 142 }; 143 144 static int dwc3_pci_quirks(struct dwc3_pci *dwc) 145 { 146 struct pci_dev *pdev = dwc->pci; 147 148 if (pdev->vendor == PCI_VENDOR_ID_INTEL) { 149 if (pdev->device == PCI_DEVICE_ID_INTEL_BXT || 150 pdev->device == PCI_DEVICE_ID_INTEL_BXT_M || 151 pdev->device == PCI_DEVICE_ID_INTEL_EHLLP) { 152 guid_parse(PCI_INTEL_BXT_DSM_GUID, &dwc->guid); 153 dwc->has_dsm_for_pm = true; 154 } 155 156 if (pdev->device == PCI_DEVICE_ID_INTEL_BYT) { 157 struct gpio_desc *gpio; 158 int ret; 159 160 /* On BYT the FW does not always enable the refclock */ 161 ret = dwc3_byt_enable_ulpi_refclock(pdev); 162 if (ret) 163 return ret; 164 165 ret = devm_acpi_dev_add_driver_gpios(&pdev->dev, 166 acpi_dwc3_byt_gpios); 167 if (ret) 168 dev_dbg(&pdev->dev, "failed to add mapping table\n"); 169 170 /* 171 * A lot of BYT devices lack ACPI resource entries for 172 * the GPIOs, add a fallback mapping to the reference 173 * design GPIOs which all boards seem to use. 174 */ 175 gpiod_add_lookup_table(&platform_bytcr_gpios); 176 177 /* 178 * These GPIOs will turn on the USB2 PHY. Note that we have to 179 * put the gpio descriptors again here because the phy driver 180 * might want to grab them, too. 181 */ 182 gpio = gpiod_get_optional(&pdev->dev, "cs", GPIOD_OUT_LOW); 183 if (IS_ERR(gpio)) 184 return PTR_ERR(gpio); 185 186 gpiod_set_value_cansleep(gpio, 1); 187 gpiod_put(gpio); 188 189 gpio = gpiod_get_optional(&pdev->dev, "reset", GPIOD_OUT_LOW); 190 if (IS_ERR(gpio)) 191 return PTR_ERR(gpio); 192 193 if (gpio) { 194 gpiod_set_value_cansleep(gpio, 1); 195 gpiod_put(gpio); 196 usleep_range(10000, 11000); 197 } 198 } 199 } 200 201 return 0; 202 } 203 204 #ifdef CONFIG_PM 205 static void dwc3_pci_resume_work(struct work_struct *work) 206 { 207 struct dwc3_pci *dwc = container_of(work, struct dwc3_pci, wakeup_work); 208 struct platform_device *dwc3 = dwc->dwc3; 209 int ret; 210 211 ret = pm_runtime_get_sync(&dwc3->dev); 212 if (ret) { 213 pm_runtime_put_sync_autosuspend(&dwc3->dev); 214 return; 215 } 216 217 pm_runtime_mark_last_busy(&dwc3->dev); 218 pm_runtime_put_sync_autosuspend(&dwc3->dev); 219 } 220 #endif 221 222 static int dwc3_pci_probe(struct pci_dev *pci, const struct pci_device_id *id) 223 { 224 struct property_entry *p = (struct property_entry *)id->driver_data; 225 struct dwc3_pci *dwc; 226 struct resource res[2]; 227 int ret; 228 struct device *dev = &pci->dev; 229 230 ret = pcim_enable_device(pci); 231 if (ret) { 232 dev_err(dev, "failed to enable pci device\n"); 233 return -ENODEV; 234 } 235 236 pci_set_master(pci); 237 238 dwc = devm_kzalloc(dev, sizeof(*dwc), GFP_KERNEL); 239 if (!dwc) 240 return -ENOMEM; 241 242 dwc->dwc3 = platform_device_alloc("dwc3", PLATFORM_DEVID_AUTO); 243 if (!dwc->dwc3) 244 return -ENOMEM; 245 246 memset(res, 0x00, sizeof(struct resource) * ARRAY_SIZE(res)); 247 248 res[0].start = pci_resource_start(pci, 0); 249 res[0].end = pci_resource_end(pci, 0); 250 res[0].name = "dwc_usb3"; 251 res[0].flags = IORESOURCE_MEM; 252 253 res[1].start = pci->irq; 254 res[1].name = "dwc_usb3"; 255 res[1].flags = IORESOURCE_IRQ; 256 257 ret = platform_device_add_resources(dwc->dwc3, res, ARRAY_SIZE(res)); 258 if (ret) { 259 dev_err(dev, "couldn't add resources to dwc3 device\n"); 260 goto err; 261 } 262 263 dwc->pci = pci; 264 dwc->dwc3->dev.parent = dev; 265 ACPI_COMPANION_SET(&dwc->dwc3->dev, ACPI_COMPANION(dev)); 266 267 ret = platform_device_add_properties(dwc->dwc3, p); 268 if (ret < 0) 269 goto err; 270 271 ret = dwc3_pci_quirks(dwc); 272 if (ret) 273 goto err; 274 275 ret = platform_device_add(dwc->dwc3); 276 if (ret) { 277 dev_err(dev, "failed to register dwc3 device\n"); 278 goto err; 279 } 280 281 device_init_wakeup(dev, true); 282 pci_set_drvdata(pci, dwc); 283 pm_runtime_put(dev); 284 #ifdef CONFIG_PM 285 INIT_WORK(&dwc->wakeup_work, dwc3_pci_resume_work); 286 #endif 287 288 return 0; 289 err: 290 platform_device_put(dwc->dwc3); 291 return ret; 292 } 293 294 static void dwc3_pci_remove(struct pci_dev *pci) 295 { 296 struct dwc3_pci *dwc = pci_get_drvdata(pci); 297 struct pci_dev *pdev = dwc->pci; 298 299 if (pdev->device == PCI_DEVICE_ID_INTEL_BYT) 300 gpiod_remove_lookup_table(&platform_bytcr_gpios); 301 #ifdef CONFIG_PM 302 cancel_work_sync(&dwc->wakeup_work); 303 #endif 304 device_init_wakeup(&pci->dev, false); 305 pm_runtime_get(&pci->dev); 306 platform_device_unregister(dwc->dwc3); 307 } 308 309 static const struct pci_device_id dwc3_pci_id_table[] = { 310 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_BSW), 311 (kernel_ulong_t) &dwc3_pci_intel_properties }, 312 313 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_BYT), 314 (kernel_ulong_t) &dwc3_pci_intel_properties, }, 315 316 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_MRFLD), 317 (kernel_ulong_t) &dwc3_pci_mrfld_properties, }, 318 319 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_CMLLP), 320 (kernel_ulong_t) &dwc3_pci_intel_properties, }, 321 322 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_CMLH), 323 (kernel_ulong_t) &dwc3_pci_intel_properties, }, 324 325 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_SPTLP), 326 (kernel_ulong_t) &dwc3_pci_intel_properties, }, 327 328 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_SPTH), 329 (kernel_ulong_t) &dwc3_pci_intel_properties, }, 330 331 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_BXT), 332 (kernel_ulong_t) &dwc3_pci_intel_properties, }, 333 334 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_BXT_M), 335 (kernel_ulong_t) &dwc3_pci_intel_properties, }, 336 337 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_APL), 338 (kernel_ulong_t) &dwc3_pci_intel_properties, }, 339 340 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_KBP), 341 (kernel_ulong_t) &dwc3_pci_intel_properties, }, 342 343 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_GLK), 344 (kernel_ulong_t) &dwc3_pci_intel_properties, }, 345 346 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_CNPLP), 347 (kernel_ulong_t) &dwc3_pci_intel_properties, }, 348 349 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_CNPH), 350 (kernel_ulong_t) &dwc3_pci_intel_properties, }, 351 352 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_CNPV), 353 (kernel_ulong_t) &dwc3_pci_intel_properties, }, 354 355 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ICLLP), 356 (kernel_ulong_t) &dwc3_pci_intel_properties, }, 357 358 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_EHLLP), 359 (kernel_ulong_t) &dwc3_pci_intel_properties, }, 360 361 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_TGPLP), 362 (kernel_ulong_t) &dwc3_pci_intel_properties, }, 363 364 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_TGPH), 365 (kernel_ulong_t) &dwc3_pci_intel_properties, }, 366 367 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_JSP), 368 (kernel_ulong_t) &dwc3_pci_intel_properties, }, 369 370 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_NL_USB), 371 (kernel_ulong_t) &dwc3_pci_amd_properties, }, 372 { } /* Terminating Entry */ 373 }; 374 MODULE_DEVICE_TABLE(pci, dwc3_pci_id_table); 375 376 #if defined(CONFIG_PM) || defined(CONFIG_PM_SLEEP) 377 static int dwc3_pci_dsm(struct dwc3_pci *dwc, int param) 378 { 379 union acpi_object *obj; 380 union acpi_object tmp; 381 union acpi_object argv4 = ACPI_INIT_DSM_ARGV4(1, &tmp); 382 383 if (!dwc->has_dsm_for_pm) 384 return 0; 385 386 tmp.type = ACPI_TYPE_INTEGER; 387 tmp.integer.value = param; 388 389 obj = acpi_evaluate_dsm(ACPI_HANDLE(&dwc->pci->dev), &dwc->guid, 390 1, PCI_INTEL_BXT_FUNC_PMU_PWR, &argv4); 391 if (!obj) { 392 dev_err(&dwc->pci->dev, "failed to evaluate _DSM\n"); 393 return -EIO; 394 } 395 396 ACPI_FREE(obj); 397 398 return 0; 399 } 400 #endif /* CONFIG_PM || CONFIG_PM_SLEEP */ 401 402 #ifdef CONFIG_PM 403 static int dwc3_pci_runtime_suspend(struct device *dev) 404 { 405 struct dwc3_pci *dwc = dev_get_drvdata(dev); 406 407 if (device_can_wakeup(dev)) 408 return dwc3_pci_dsm(dwc, PCI_INTEL_BXT_STATE_D3); 409 410 return -EBUSY; 411 } 412 413 static int dwc3_pci_runtime_resume(struct device *dev) 414 { 415 struct dwc3_pci *dwc = dev_get_drvdata(dev); 416 int ret; 417 418 ret = dwc3_pci_dsm(dwc, PCI_INTEL_BXT_STATE_D0); 419 if (ret) 420 return ret; 421 422 queue_work(pm_wq, &dwc->wakeup_work); 423 424 return 0; 425 } 426 #endif /* CONFIG_PM */ 427 428 #ifdef CONFIG_PM_SLEEP 429 static int dwc3_pci_suspend(struct device *dev) 430 { 431 struct dwc3_pci *dwc = dev_get_drvdata(dev); 432 433 return dwc3_pci_dsm(dwc, PCI_INTEL_BXT_STATE_D3); 434 } 435 436 static int dwc3_pci_resume(struct device *dev) 437 { 438 struct dwc3_pci *dwc = dev_get_drvdata(dev); 439 440 return dwc3_pci_dsm(dwc, PCI_INTEL_BXT_STATE_D0); 441 } 442 #endif /* CONFIG_PM_SLEEP */ 443 444 static const struct dev_pm_ops dwc3_pci_dev_pm_ops = { 445 SET_SYSTEM_SLEEP_PM_OPS(dwc3_pci_suspend, dwc3_pci_resume) 446 SET_RUNTIME_PM_OPS(dwc3_pci_runtime_suspend, dwc3_pci_runtime_resume, 447 NULL) 448 }; 449 450 static struct pci_driver dwc3_pci_driver = { 451 .name = "dwc3-pci", 452 .id_table = dwc3_pci_id_table, 453 .probe = dwc3_pci_probe, 454 .remove = dwc3_pci_remove, 455 .driver = { 456 .pm = &dwc3_pci_dev_pm_ops, 457 } 458 }; 459 460 MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>"); 461 MODULE_LICENSE("GPL v2"); 462 MODULE_DESCRIPTION("DesignWare USB3 PCI Glue Layer"); 463 464 module_pci_driver(dwc3_pci_driver); 465