1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * dwc3-pci.c - PCI Specific glue layer 4 * 5 * Copyright (C) 2010-2011 Texas Instruments Incorporated - https://www.ti.com 6 * 7 * Authors: Felipe Balbi <balbi@ti.com>, 8 * Sebastian Andrzej Siewior <bigeasy@linutronix.de> 9 */ 10 11 #include <linux/kernel.h> 12 #include <linux/module.h> 13 #include <linux/slab.h> 14 #include <linux/pci.h> 15 #include <linux/workqueue.h> 16 #include <linux/pm_runtime.h> 17 #include <linux/platform_device.h> 18 #include <linux/gpio/consumer.h> 19 #include <linux/gpio/machine.h> 20 #include <linux/acpi.h> 21 #include <linux/delay.h> 22 23 #define PCI_DEVICE_ID_INTEL_BYT 0x0f37 24 #define PCI_DEVICE_ID_INTEL_MRFLD 0x119e 25 #define PCI_DEVICE_ID_INTEL_BSW 0x22b7 26 #define PCI_DEVICE_ID_INTEL_SPTLP 0x9d30 27 #define PCI_DEVICE_ID_INTEL_SPTH 0xa130 28 #define PCI_DEVICE_ID_INTEL_BXT 0x0aaa 29 #define PCI_DEVICE_ID_INTEL_BXT_M 0x1aaa 30 #define PCI_DEVICE_ID_INTEL_APL 0x5aaa 31 #define PCI_DEVICE_ID_INTEL_KBP 0xa2b0 32 #define PCI_DEVICE_ID_INTEL_CMLLP 0x02ee 33 #define PCI_DEVICE_ID_INTEL_CMLH 0x06ee 34 #define PCI_DEVICE_ID_INTEL_GLK 0x31aa 35 #define PCI_DEVICE_ID_INTEL_CNPLP 0x9dee 36 #define PCI_DEVICE_ID_INTEL_CNPH 0xa36e 37 #define PCI_DEVICE_ID_INTEL_CNPV 0xa3b0 38 #define PCI_DEVICE_ID_INTEL_ICLLP 0x34ee 39 #define PCI_DEVICE_ID_INTEL_EHL 0x4b7e 40 #define PCI_DEVICE_ID_INTEL_TGPLP 0xa0ee 41 #define PCI_DEVICE_ID_INTEL_TGPH 0x43ee 42 #define PCI_DEVICE_ID_INTEL_JSP 0x4dee 43 #define PCI_DEVICE_ID_INTEL_ADL 0x460e 44 #define PCI_DEVICE_ID_INTEL_ADL_PCH 0x51ee 45 #define PCI_DEVICE_ID_INTEL_ADLN 0x465e 46 #define PCI_DEVICE_ID_INTEL_ADLN_PCH 0x54ee 47 #define PCI_DEVICE_ID_INTEL_ADLS 0x7ae1 48 #define PCI_DEVICE_ID_INTEL_RPL 0xa70e 49 #define PCI_DEVICE_ID_INTEL_RPLS 0x7a61 50 #define PCI_DEVICE_ID_INTEL_MTLM 0x7eb1 51 #define PCI_DEVICE_ID_INTEL_MTLP 0x7ec1 52 #define PCI_DEVICE_ID_INTEL_MTLS 0x7f6f 53 #define PCI_DEVICE_ID_INTEL_MTL 0x7e7e 54 #define PCI_DEVICE_ID_INTEL_TGL 0x9a15 55 #define PCI_DEVICE_ID_AMD_MR 0x163a 56 57 #define PCI_INTEL_BXT_DSM_GUID "732b85d5-b7a7-4a1b-9ba0-4bbd00ffd511" 58 #define PCI_INTEL_BXT_FUNC_PMU_PWR 4 59 #define PCI_INTEL_BXT_STATE_D0 0 60 #define PCI_INTEL_BXT_STATE_D3 3 61 62 #define GP_RWBAR 1 63 #define GP_RWREG1 0xa0 64 #define GP_RWREG1_ULPI_REFCLK_DISABLE (1 << 17) 65 66 /** 67 * struct dwc3_pci - Driver private structure 68 * @dwc3: child dwc3 platform_device 69 * @pci: our link to PCI bus 70 * @guid: _DSM GUID 71 * @has_dsm_for_pm: true for devices which need to run _DSM on runtime PM 72 * @wakeup_work: work for asynchronous resume 73 */ 74 struct dwc3_pci { 75 struct platform_device *dwc3; 76 struct pci_dev *pci; 77 78 guid_t guid; 79 80 unsigned int has_dsm_for_pm:1; 81 struct work_struct wakeup_work; 82 }; 83 84 static const struct acpi_gpio_params reset_gpios = { 0, 0, false }; 85 static const struct acpi_gpio_params cs_gpios = { 1, 0, false }; 86 87 static const struct acpi_gpio_mapping acpi_dwc3_byt_gpios[] = { 88 { "reset-gpios", &reset_gpios, 1 }, 89 { "cs-gpios", &cs_gpios, 1 }, 90 { }, 91 }; 92 93 static struct gpiod_lookup_table platform_bytcr_gpios = { 94 .dev_id = "0000:00:16.0", 95 .table = { 96 GPIO_LOOKUP("INT33FC:00", 54, "cs", GPIO_ACTIVE_HIGH), 97 GPIO_LOOKUP("INT33FC:02", 14, "reset", GPIO_ACTIVE_HIGH), 98 {} 99 }, 100 }; 101 102 static int dwc3_byt_enable_ulpi_refclock(struct pci_dev *pci) 103 { 104 void __iomem *reg; 105 u32 value; 106 107 reg = pcim_iomap(pci, GP_RWBAR, 0); 108 if (!reg) 109 return -ENOMEM; 110 111 value = readl(reg + GP_RWREG1); 112 if (!(value & GP_RWREG1_ULPI_REFCLK_DISABLE)) 113 goto unmap; /* ULPI refclk already enabled */ 114 115 value &= ~GP_RWREG1_ULPI_REFCLK_DISABLE; 116 writel(value, reg + GP_RWREG1); 117 /* This comes from the Intel Android x86 tree w/o any explanation */ 118 msleep(100); 119 unmap: 120 pcim_iounmap(pci, reg); 121 return 0; 122 } 123 124 static const struct property_entry dwc3_pci_intel_properties[] = { 125 PROPERTY_ENTRY_STRING("dr_mode", "peripheral"), 126 PROPERTY_ENTRY_BOOL("linux,sysdev_is_parent"), 127 {} 128 }; 129 130 static const struct property_entry dwc3_pci_intel_phy_charger_detect_properties[] = { 131 PROPERTY_ENTRY_STRING("dr_mode", "peripheral"), 132 PROPERTY_ENTRY_BOOL("snps,dis_u2_susphy_quirk"), 133 PROPERTY_ENTRY_BOOL("linux,phy_charger_detect"), 134 PROPERTY_ENTRY_BOOL("linux,sysdev_is_parent"), 135 {} 136 }; 137 138 static const struct property_entry dwc3_pci_intel_byt_properties[] = { 139 PROPERTY_ENTRY_STRING("dr_mode", "peripheral"), 140 PROPERTY_ENTRY_BOOL("snps,dis_u2_susphy_quirk"), 141 PROPERTY_ENTRY_BOOL("linux,sysdev_is_parent"), 142 {} 143 }; 144 145 static const struct property_entry dwc3_pci_mrfld_properties[] = { 146 PROPERTY_ENTRY_STRING("dr_mode", "otg"), 147 PROPERTY_ENTRY_STRING("linux,extcon-name", "mrfld_bcove_pwrsrc"), 148 PROPERTY_ENTRY_BOOL("snps,dis_u3_susphy_quirk"), 149 PROPERTY_ENTRY_BOOL("snps,dis_u2_susphy_quirk"), 150 PROPERTY_ENTRY_BOOL("snps,usb2-gadget-lpm-disable"), 151 PROPERTY_ENTRY_BOOL("linux,sysdev_is_parent"), 152 {} 153 }; 154 155 static const struct property_entry dwc3_pci_amd_properties[] = { 156 PROPERTY_ENTRY_BOOL("snps,has-lpm-erratum"), 157 PROPERTY_ENTRY_U8("snps,lpm-nyet-threshold", 0xf), 158 PROPERTY_ENTRY_BOOL("snps,u2exit_lfps_quirk"), 159 PROPERTY_ENTRY_BOOL("snps,u2ss_inp3_quirk"), 160 PROPERTY_ENTRY_BOOL("snps,req_p1p2p3_quirk"), 161 PROPERTY_ENTRY_BOOL("snps,del_p1p2p3_quirk"), 162 PROPERTY_ENTRY_BOOL("snps,del_phy_power_chg_quirk"), 163 PROPERTY_ENTRY_BOOL("snps,lfps_filter_quirk"), 164 PROPERTY_ENTRY_BOOL("snps,rx_detect_poll_quirk"), 165 PROPERTY_ENTRY_BOOL("snps,tx_de_emphasis_quirk"), 166 PROPERTY_ENTRY_U8("snps,tx_de_emphasis", 1), 167 /* FIXME these quirks should be removed when AMD NL tapes out */ 168 PROPERTY_ENTRY_BOOL("snps,disable_scramble_quirk"), 169 PROPERTY_ENTRY_BOOL("snps,dis_u3_susphy_quirk"), 170 PROPERTY_ENTRY_BOOL("snps,dis_u2_susphy_quirk"), 171 PROPERTY_ENTRY_BOOL("linux,sysdev_is_parent"), 172 {} 173 }; 174 175 static const struct property_entry dwc3_pci_mr_properties[] = { 176 PROPERTY_ENTRY_STRING("dr_mode", "otg"), 177 PROPERTY_ENTRY_BOOL("usb-role-switch"), 178 PROPERTY_ENTRY_STRING("role-switch-default-mode", "host"), 179 PROPERTY_ENTRY_BOOL("linux,sysdev_is_parent"), 180 {} 181 }; 182 183 static const struct software_node dwc3_pci_intel_swnode = { 184 .properties = dwc3_pci_intel_properties, 185 }; 186 187 static const struct software_node dwc3_pci_intel_phy_charger_detect_swnode = { 188 .properties = dwc3_pci_intel_phy_charger_detect_properties, 189 }; 190 191 static const struct software_node dwc3_pci_intel_byt_swnode = { 192 .properties = dwc3_pci_intel_byt_properties, 193 }; 194 195 static const struct software_node dwc3_pci_intel_mrfld_swnode = { 196 .properties = dwc3_pci_mrfld_properties, 197 }; 198 199 static const struct software_node dwc3_pci_amd_swnode = { 200 .properties = dwc3_pci_amd_properties, 201 }; 202 203 static const struct software_node dwc3_pci_amd_mr_swnode = { 204 .properties = dwc3_pci_mr_properties, 205 }; 206 207 static int dwc3_pci_quirks(struct dwc3_pci *dwc, 208 const struct software_node *swnode) 209 { 210 struct pci_dev *pdev = dwc->pci; 211 212 if (pdev->vendor == PCI_VENDOR_ID_INTEL) { 213 if (pdev->device == PCI_DEVICE_ID_INTEL_BXT || 214 pdev->device == PCI_DEVICE_ID_INTEL_BXT_M || 215 pdev->device == PCI_DEVICE_ID_INTEL_EHL) { 216 guid_parse(PCI_INTEL_BXT_DSM_GUID, &dwc->guid); 217 dwc->has_dsm_for_pm = true; 218 } 219 220 if (pdev->device == PCI_DEVICE_ID_INTEL_BYT) { 221 struct gpio_desc *gpio; 222 int ret; 223 224 /* On BYT the FW does not always enable the refclock */ 225 ret = dwc3_byt_enable_ulpi_refclock(pdev); 226 if (ret) 227 return ret; 228 229 ret = devm_acpi_dev_add_driver_gpios(&pdev->dev, 230 acpi_dwc3_byt_gpios); 231 if (ret) 232 dev_dbg(&pdev->dev, "failed to add mapping table\n"); 233 234 /* 235 * A lot of BYT devices lack ACPI resource entries for 236 * the GPIOs. If the ACPI entry for the GPIO controller 237 * is present add a fallback mapping to the reference 238 * design GPIOs which all boards seem to use. 239 */ 240 if (acpi_dev_present("INT33FC", NULL, -1)) 241 gpiod_add_lookup_table(&platform_bytcr_gpios); 242 243 /* 244 * These GPIOs will turn on the USB2 PHY. Note that we have to 245 * put the gpio descriptors again here because the phy driver 246 * might want to grab them, too. 247 */ 248 gpio = gpiod_get_optional(&pdev->dev, "cs", GPIOD_OUT_LOW); 249 if (IS_ERR(gpio)) 250 return PTR_ERR(gpio); 251 252 gpiod_set_value_cansleep(gpio, 1); 253 gpiod_put(gpio); 254 255 gpio = gpiod_get_optional(&pdev->dev, "reset", GPIOD_OUT_LOW); 256 if (IS_ERR(gpio)) 257 return PTR_ERR(gpio); 258 259 if (gpio) { 260 gpiod_set_value_cansleep(gpio, 1); 261 gpiod_put(gpio); 262 usleep_range(10000, 11000); 263 } 264 265 /* 266 * Make the pdev name predictable (only 1 DWC3 on BYT) 267 * and patch the phy dev-name into the lookup table so 268 * that the phy-driver can get the GPIOs. 269 */ 270 dwc->dwc3->id = PLATFORM_DEVID_NONE; 271 platform_bytcr_gpios.dev_id = "dwc3.ulpi"; 272 273 /* 274 * Some Android tablets with a Crystal Cove PMIC 275 * (INT33FD), rely on the TUSB1211 phy for charger 276 * detection. These can be identified by them _not_ 277 * using the standard ACPI battery and ac drivers. 278 */ 279 if (acpi_dev_present("INT33FD", "1", 2) && 280 acpi_quirk_skip_acpi_ac_and_battery()) { 281 dev_info(&pdev->dev, "Using TUSB1211 phy for charger detection\n"); 282 swnode = &dwc3_pci_intel_phy_charger_detect_swnode; 283 } 284 } 285 } 286 287 return device_add_software_node(&dwc->dwc3->dev, swnode); 288 } 289 290 #ifdef CONFIG_PM 291 static void dwc3_pci_resume_work(struct work_struct *work) 292 { 293 struct dwc3_pci *dwc = container_of(work, struct dwc3_pci, wakeup_work); 294 struct platform_device *dwc3 = dwc->dwc3; 295 int ret; 296 297 ret = pm_runtime_get_sync(&dwc3->dev); 298 if (ret < 0) { 299 pm_runtime_put_sync_autosuspend(&dwc3->dev); 300 return; 301 } 302 303 pm_runtime_mark_last_busy(&dwc3->dev); 304 pm_runtime_put_sync_autosuspend(&dwc3->dev); 305 } 306 #endif 307 308 static int dwc3_pci_probe(struct pci_dev *pci, const struct pci_device_id *id) 309 { 310 struct dwc3_pci *dwc; 311 struct resource res[2]; 312 int ret; 313 struct device *dev = &pci->dev; 314 315 ret = pcim_enable_device(pci); 316 if (ret) { 317 dev_err(dev, "failed to enable pci device\n"); 318 return -ENODEV; 319 } 320 321 pci_set_master(pci); 322 323 dwc = devm_kzalloc(dev, sizeof(*dwc), GFP_KERNEL); 324 if (!dwc) 325 return -ENOMEM; 326 327 dwc->dwc3 = platform_device_alloc("dwc3", PLATFORM_DEVID_AUTO); 328 if (!dwc->dwc3) 329 return -ENOMEM; 330 331 memset(res, 0x00, sizeof(struct resource) * ARRAY_SIZE(res)); 332 333 res[0].start = pci_resource_start(pci, 0); 334 res[0].end = pci_resource_end(pci, 0); 335 res[0].name = "dwc_usb3"; 336 res[0].flags = IORESOURCE_MEM; 337 338 res[1].start = pci->irq; 339 res[1].name = "dwc_usb3"; 340 res[1].flags = IORESOURCE_IRQ; 341 342 ret = platform_device_add_resources(dwc->dwc3, res, ARRAY_SIZE(res)); 343 if (ret) { 344 dev_err(dev, "couldn't add resources to dwc3 device\n"); 345 goto err; 346 } 347 348 dwc->pci = pci; 349 dwc->dwc3->dev.parent = dev; 350 ACPI_COMPANION_SET(&dwc->dwc3->dev, ACPI_COMPANION(dev)); 351 352 ret = dwc3_pci_quirks(dwc, (void *)id->driver_data); 353 if (ret) 354 goto err; 355 356 ret = platform_device_add(dwc->dwc3); 357 if (ret) { 358 dev_err(dev, "failed to register dwc3 device\n"); 359 goto err; 360 } 361 362 device_init_wakeup(dev, true); 363 pci_set_drvdata(pci, dwc); 364 pm_runtime_put(dev); 365 #ifdef CONFIG_PM 366 INIT_WORK(&dwc->wakeup_work, dwc3_pci_resume_work); 367 #endif 368 369 return 0; 370 err: 371 device_remove_software_node(&dwc->dwc3->dev); 372 platform_device_put(dwc->dwc3); 373 return ret; 374 } 375 376 static void dwc3_pci_remove(struct pci_dev *pci) 377 { 378 struct dwc3_pci *dwc = pci_get_drvdata(pci); 379 struct pci_dev *pdev = dwc->pci; 380 381 if (pdev->device == PCI_DEVICE_ID_INTEL_BYT) 382 gpiod_remove_lookup_table(&platform_bytcr_gpios); 383 #ifdef CONFIG_PM 384 cancel_work_sync(&dwc->wakeup_work); 385 #endif 386 device_init_wakeup(&pci->dev, false); 387 pm_runtime_get(&pci->dev); 388 device_remove_software_node(&dwc->dwc3->dev); 389 platform_device_unregister(dwc->dwc3); 390 } 391 392 static const struct pci_device_id dwc3_pci_id_table[] = { 393 { PCI_DEVICE_DATA(INTEL, BSW, &dwc3_pci_intel_swnode) }, 394 { PCI_DEVICE_DATA(INTEL, BYT, &dwc3_pci_intel_byt_swnode) }, 395 { PCI_DEVICE_DATA(INTEL, MRFLD, &dwc3_pci_intel_mrfld_swnode) }, 396 { PCI_DEVICE_DATA(INTEL, CMLLP, &dwc3_pci_intel_swnode) }, 397 { PCI_DEVICE_DATA(INTEL, CMLH, &dwc3_pci_intel_swnode) }, 398 { PCI_DEVICE_DATA(INTEL, SPTLP, &dwc3_pci_intel_swnode) }, 399 { PCI_DEVICE_DATA(INTEL, SPTH, &dwc3_pci_intel_swnode) }, 400 { PCI_DEVICE_DATA(INTEL, BXT, &dwc3_pci_intel_swnode) }, 401 { PCI_DEVICE_DATA(INTEL, BXT_M, &dwc3_pci_intel_swnode) }, 402 { PCI_DEVICE_DATA(INTEL, APL, &dwc3_pci_intel_swnode) }, 403 { PCI_DEVICE_DATA(INTEL, KBP, &dwc3_pci_intel_swnode) }, 404 { PCI_DEVICE_DATA(INTEL, GLK, &dwc3_pci_intel_swnode) }, 405 { PCI_DEVICE_DATA(INTEL, CNPLP, &dwc3_pci_intel_swnode) }, 406 { PCI_DEVICE_DATA(INTEL, CNPH, &dwc3_pci_intel_swnode) }, 407 { PCI_DEVICE_DATA(INTEL, CNPV, &dwc3_pci_intel_swnode) }, 408 { PCI_DEVICE_DATA(INTEL, ICLLP, &dwc3_pci_intel_swnode) }, 409 { PCI_DEVICE_DATA(INTEL, EHL, &dwc3_pci_intel_swnode) }, 410 { PCI_DEVICE_DATA(INTEL, TGPLP, &dwc3_pci_intel_swnode) }, 411 { PCI_DEVICE_DATA(INTEL, TGPH, &dwc3_pci_intel_swnode) }, 412 { PCI_DEVICE_DATA(INTEL, JSP, &dwc3_pci_intel_swnode) }, 413 { PCI_DEVICE_DATA(INTEL, ADL, &dwc3_pci_intel_swnode) }, 414 { PCI_DEVICE_DATA(INTEL, ADL_PCH, &dwc3_pci_intel_swnode) }, 415 { PCI_DEVICE_DATA(INTEL, ADLN, &dwc3_pci_intel_swnode) }, 416 { PCI_DEVICE_DATA(INTEL, ADLN_PCH, &dwc3_pci_intel_swnode) }, 417 { PCI_DEVICE_DATA(INTEL, ADLS, &dwc3_pci_intel_swnode) }, 418 { PCI_DEVICE_DATA(INTEL, RPL, &dwc3_pci_intel_swnode) }, 419 { PCI_DEVICE_DATA(INTEL, RPLS, &dwc3_pci_intel_swnode) }, 420 { PCI_DEVICE_DATA(INTEL, MTLM, &dwc3_pci_intel_swnode) }, 421 { PCI_DEVICE_DATA(INTEL, MTLP, &dwc3_pci_intel_swnode) }, 422 { PCI_DEVICE_DATA(INTEL, MTL, &dwc3_pci_intel_swnode) }, 423 { PCI_DEVICE_DATA(INTEL, MTLS, &dwc3_pci_intel_swnode) }, 424 { PCI_DEVICE_DATA(INTEL, TGL, &dwc3_pci_intel_swnode) }, 425 426 { PCI_DEVICE_DATA(AMD, NL_USB, &dwc3_pci_amd_swnode) }, 427 { PCI_DEVICE_DATA(AMD, MR, &dwc3_pci_amd_mr_swnode) }, 428 429 { } /* Terminating Entry */ 430 }; 431 MODULE_DEVICE_TABLE(pci, dwc3_pci_id_table); 432 433 #if defined(CONFIG_PM) || defined(CONFIG_PM_SLEEP) 434 static int dwc3_pci_dsm(struct dwc3_pci *dwc, int param) 435 { 436 union acpi_object *obj; 437 union acpi_object tmp; 438 union acpi_object argv4 = ACPI_INIT_DSM_ARGV4(1, &tmp); 439 440 if (!dwc->has_dsm_for_pm) 441 return 0; 442 443 tmp.type = ACPI_TYPE_INTEGER; 444 tmp.integer.value = param; 445 446 obj = acpi_evaluate_dsm(ACPI_HANDLE(&dwc->pci->dev), &dwc->guid, 447 1, PCI_INTEL_BXT_FUNC_PMU_PWR, &argv4); 448 if (!obj) { 449 dev_err(&dwc->pci->dev, "failed to evaluate _DSM\n"); 450 return -EIO; 451 } 452 453 ACPI_FREE(obj); 454 455 return 0; 456 } 457 #endif /* CONFIG_PM || CONFIG_PM_SLEEP */ 458 459 #ifdef CONFIG_PM 460 static int dwc3_pci_runtime_suspend(struct device *dev) 461 { 462 struct dwc3_pci *dwc = dev_get_drvdata(dev); 463 464 if (device_can_wakeup(dev)) 465 return dwc3_pci_dsm(dwc, PCI_INTEL_BXT_STATE_D3); 466 467 return -EBUSY; 468 } 469 470 static int dwc3_pci_runtime_resume(struct device *dev) 471 { 472 struct dwc3_pci *dwc = dev_get_drvdata(dev); 473 int ret; 474 475 ret = dwc3_pci_dsm(dwc, PCI_INTEL_BXT_STATE_D0); 476 if (ret) 477 return ret; 478 479 queue_work(pm_wq, &dwc->wakeup_work); 480 481 return 0; 482 } 483 #endif /* CONFIG_PM */ 484 485 #ifdef CONFIG_PM_SLEEP 486 static int dwc3_pci_suspend(struct device *dev) 487 { 488 struct dwc3_pci *dwc = dev_get_drvdata(dev); 489 490 return dwc3_pci_dsm(dwc, PCI_INTEL_BXT_STATE_D3); 491 } 492 493 static int dwc3_pci_resume(struct device *dev) 494 { 495 struct dwc3_pci *dwc = dev_get_drvdata(dev); 496 497 return dwc3_pci_dsm(dwc, PCI_INTEL_BXT_STATE_D0); 498 } 499 #endif /* CONFIG_PM_SLEEP */ 500 501 static const struct dev_pm_ops dwc3_pci_dev_pm_ops = { 502 SET_SYSTEM_SLEEP_PM_OPS(dwc3_pci_suspend, dwc3_pci_resume) 503 SET_RUNTIME_PM_OPS(dwc3_pci_runtime_suspend, dwc3_pci_runtime_resume, 504 NULL) 505 }; 506 507 static struct pci_driver dwc3_pci_driver = { 508 .name = "dwc3-pci", 509 .id_table = dwc3_pci_id_table, 510 .probe = dwc3_pci_probe, 511 .remove = dwc3_pci_remove, 512 .driver = { 513 .pm = &dwc3_pci_dev_pm_ops, 514 } 515 }; 516 517 MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>"); 518 MODULE_LICENSE("GPL v2"); 519 MODULE_DESCRIPTION("DesignWare USB3 PCI Glue Layer"); 520 521 module_pci_driver(dwc3_pci_driver); 522