1 // SPDX-License-Identifier: GPL-2.0 2 /** 3 * dwc3-pci.c - PCI Specific glue layer 4 * 5 * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com 6 * 7 * Authors: Felipe Balbi <balbi@ti.com>, 8 * Sebastian Andrzej Siewior <bigeasy@linutronix.de> 9 */ 10 11 #include <linux/kernel.h> 12 #include <linux/module.h> 13 #include <linux/slab.h> 14 #include <linux/pci.h> 15 #include <linux/workqueue.h> 16 #include <linux/pm_runtime.h> 17 #include <linux/platform_device.h> 18 #include <linux/gpio/consumer.h> 19 #include <linux/gpio/machine.h> 20 #include <linux/acpi.h> 21 #include <linux/delay.h> 22 23 #define PCI_DEVICE_ID_INTEL_BYT 0x0f37 24 #define PCI_DEVICE_ID_INTEL_MRFLD 0x119e 25 #define PCI_DEVICE_ID_INTEL_BSW 0x22b7 26 #define PCI_DEVICE_ID_INTEL_SPTLP 0x9d30 27 #define PCI_DEVICE_ID_INTEL_SPTH 0xa130 28 #define PCI_DEVICE_ID_INTEL_BXT 0x0aaa 29 #define PCI_DEVICE_ID_INTEL_BXT_M 0x1aaa 30 #define PCI_DEVICE_ID_INTEL_APL 0x5aaa 31 #define PCI_DEVICE_ID_INTEL_KBP 0xa2b0 32 #define PCI_DEVICE_ID_INTEL_CMLLP 0x02ee 33 #define PCI_DEVICE_ID_INTEL_CMLH 0x06ee 34 #define PCI_DEVICE_ID_INTEL_GLK 0x31aa 35 #define PCI_DEVICE_ID_INTEL_CNPLP 0x9dee 36 #define PCI_DEVICE_ID_INTEL_CNPH 0xa36e 37 #define PCI_DEVICE_ID_INTEL_CNPV 0xa3b0 38 #define PCI_DEVICE_ID_INTEL_ICLLP 0x34ee 39 #define PCI_DEVICE_ID_INTEL_EHLLP 0x4b7e 40 #define PCI_DEVICE_ID_INTEL_TGPLP 0xa0ee 41 42 #define PCI_INTEL_BXT_DSM_GUID "732b85d5-b7a7-4a1b-9ba0-4bbd00ffd511" 43 #define PCI_INTEL_BXT_FUNC_PMU_PWR 4 44 #define PCI_INTEL_BXT_STATE_D0 0 45 #define PCI_INTEL_BXT_STATE_D3 3 46 47 #define GP_RWBAR 1 48 #define GP_RWREG1 0xa0 49 #define GP_RWREG1_ULPI_REFCLK_DISABLE (1 << 17) 50 51 /** 52 * struct dwc3_pci - Driver private structure 53 * @dwc3: child dwc3 platform_device 54 * @pci: our link to PCI bus 55 * @guid: _DSM GUID 56 * @has_dsm_for_pm: true for devices which need to run _DSM on runtime PM 57 * @wakeup_work: work for asynchronous resume 58 */ 59 struct dwc3_pci { 60 struct platform_device *dwc3; 61 struct pci_dev *pci; 62 63 guid_t guid; 64 65 unsigned int has_dsm_for_pm:1; 66 struct work_struct wakeup_work; 67 }; 68 69 static const struct acpi_gpio_params reset_gpios = { 0, 0, false }; 70 static const struct acpi_gpio_params cs_gpios = { 1, 0, false }; 71 72 static const struct acpi_gpio_mapping acpi_dwc3_byt_gpios[] = { 73 { "reset-gpios", &reset_gpios, 1 }, 74 { "cs-gpios", &cs_gpios, 1 }, 75 { }, 76 }; 77 78 static struct gpiod_lookup_table platform_bytcr_gpios = { 79 .dev_id = "0000:00:16.0", 80 .table = { 81 GPIO_LOOKUP("INT33FC:00", 54, "reset", GPIO_ACTIVE_HIGH), 82 GPIO_LOOKUP("INT33FC:02", 14, "cs", GPIO_ACTIVE_HIGH), 83 {} 84 }, 85 }; 86 87 static int dwc3_byt_enable_ulpi_refclock(struct pci_dev *pci) 88 { 89 void __iomem *reg; 90 u32 value; 91 92 reg = pcim_iomap(pci, GP_RWBAR, 0); 93 if (!reg) 94 return -ENOMEM; 95 96 value = readl(reg + GP_RWREG1); 97 if (!(value & GP_RWREG1_ULPI_REFCLK_DISABLE)) 98 goto unmap; /* ULPI refclk already enabled */ 99 100 value &= ~GP_RWREG1_ULPI_REFCLK_DISABLE; 101 writel(value, reg + GP_RWREG1); 102 /* This comes from the Intel Android x86 tree w/o any explanation */ 103 msleep(100); 104 unmap: 105 pcim_iounmap(pci, reg); 106 return 0; 107 } 108 109 static const struct property_entry dwc3_pci_intel_properties[] = { 110 PROPERTY_ENTRY_STRING("dr_mode", "peripheral"), 111 PROPERTY_ENTRY_BOOL("linux,sysdev_is_parent"), 112 {} 113 }; 114 115 static const struct property_entry dwc3_pci_mrfld_properties[] = { 116 PROPERTY_ENTRY_STRING("dr_mode", "otg"), 117 PROPERTY_ENTRY_BOOL("linux,sysdev_is_parent"), 118 {} 119 }; 120 121 static const struct property_entry dwc3_pci_amd_properties[] = { 122 PROPERTY_ENTRY_BOOL("snps,has-lpm-erratum"), 123 PROPERTY_ENTRY_U8("snps,lpm-nyet-threshold", 0xf), 124 PROPERTY_ENTRY_BOOL("snps,u2exit_lfps_quirk"), 125 PROPERTY_ENTRY_BOOL("snps,u2ss_inp3_quirk"), 126 PROPERTY_ENTRY_BOOL("snps,req_p1p2p3_quirk"), 127 PROPERTY_ENTRY_BOOL("snps,del_p1p2p3_quirk"), 128 PROPERTY_ENTRY_BOOL("snps,del_phy_power_chg_quirk"), 129 PROPERTY_ENTRY_BOOL("snps,lfps_filter_quirk"), 130 PROPERTY_ENTRY_BOOL("snps,rx_detect_poll_quirk"), 131 PROPERTY_ENTRY_BOOL("snps,tx_de_emphasis_quirk"), 132 PROPERTY_ENTRY_U8("snps,tx_de_emphasis", 1), 133 /* FIXME these quirks should be removed when AMD NL tapes out */ 134 PROPERTY_ENTRY_BOOL("snps,disable_scramble_quirk"), 135 PROPERTY_ENTRY_BOOL("snps,dis_u3_susphy_quirk"), 136 PROPERTY_ENTRY_BOOL("snps,dis_u2_susphy_quirk"), 137 PROPERTY_ENTRY_BOOL("linux,sysdev_is_parent"), 138 {} 139 }; 140 141 static int dwc3_pci_quirks(struct dwc3_pci *dwc) 142 { 143 struct pci_dev *pdev = dwc->pci; 144 145 if (pdev->vendor == PCI_VENDOR_ID_INTEL) { 146 if (pdev->device == PCI_DEVICE_ID_INTEL_BXT || 147 pdev->device == PCI_DEVICE_ID_INTEL_BXT_M) { 148 guid_parse(PCI_INTEL_BXT_DSM_GUID, &dwc->guid); 149 dwc->has_dsm_for_pm = true; 150 } 151 152 if (pdev->device == PCI_DEVICE_ID_INTEL_BYT) { 153 struct gpio_desc *gpio; 154 int ret; 155 156 /* On BYT the FW does not always enable the refclock */ 157 ret = dwc3_byt_enable_ulpi_refclock(pdev); 158 if (ret) 159 return ret; 160 161 ret = devm_acpi_dev_add_driver_gpios(&pdev->dev, 162 acpi_dwc3_byt_gpios); 163 if (ret) 164 dev_dbg(&pdev->dev, "failed to add mapping table\n"); 165 166 /* 167 * A lot of BYT devices lack ACPI resource entries for 168 * the GPIOs, add a fallback mapping to the reference 169 * design GPIOs which all boards seem to use. 170 */ 171 gpiod_add_lookup_table(&platform_bytcr_gpios); 172 173 /* 174 * These GPIOs will turn on the USB2 PHY. Note that we have to 175 * put the gpio descriptors again here because the phy driver 176 * might want to grab them, too. 177 */ 178 gpio = gpiod_get_optional(&pdev->dev, "cs", GPIOD_OUT_LOW); 179 if (IS_ERR(gpio)) 180 return PTR_ERR(gpio); 181 182 gpiod_set_value_cansleep(gpio, 1); 183 gpiod_put(gpio); 184 185 gpio = gpiod_get_optional(&pdev->dev, "reset", GPIOD_OUT_LOW); 186 if (IS_ERR(gpio)) 187 return PTR_ERR(gpio); 188 189 if (gpio) { 190 gpiod_set_value_cansleep(gpio, 1); 191 gpiod_put(gpio); 192 usleep_range(10000, 11000); 193 } 194 } 195 } 196 197 return 0; 198 } 199 200 #ifdef CONFIG_PM 201 static void dwc3_pci_resume_work(struct work_struct *work) 202 { 203 struct dwc3_pci *dwc = container_of(work, struct dwc3_pci, wakeup_work); 204 struct platform_device *dwc3 = dwc->dwc3; 205 int ret; 206 207 ret = pm_runtime_get_sync(&dwc3->dev); 208 if (ret) 209 return; 210 211 pm_runtime_mark_last_busy(&dwc3->dev); 212 pm_runtime_put_sync_autosuspend(&dwc3->dev); 213 } 214 #endif 215 216 static int dwc3_pci_probe(struct pci_dev *pci, const struct pci_device_id *id) 217 { 218 struct property_entry *p = (struct property_entry *)id->driver_data; 219 struct dwc3_pci *dwc; 220 struct resource res[2]; 221 int ret; 222 struct device *dev = &pci->dev; 223 224 ret = pcim_enable_device(pci); 225 if (ret) { 226 dev_err(dev, "failed to enable pci device\n"); 227 return -ENODEV; 228 } 229 230 pci_set_master(pci); 231 232 dwc = devm_kzalloc(dev, sizeof(*dwc), GFP_KERNEL); 233 if (!dwc) 234 return -ENOMEM; 235 236 dwc->dwc3 = platform_device_alloc("dwc3", PLATFORM_DEVID_AUTO); 237 if (!dwc->dwc3) 238 return -ENOMEM; 239 240 memset(res, 0x00, sizeof(struct resource) * ARRAY_SIZE(res)); 241 242 res[0].start = pci_resource_start(pci, 0); 243 res[0].end = pci_resource_end(pci, 0); 244 res[0].name = "dwc_usb3"; 245 res[0].flags = IORESOURCE_MEM; 246 247 res[1].start = pci->irq; 248 res[1].name = "dwc_usb3"; 249 res[1].flags = IORESOURCE_IRQ; 250 251 ret = platform_device_add_resources(dwc->dwc3, res, ARRAY_SIZE(res)); 252 if (ret) { 253 dev_err(dev, "couldn't add resources to dwc3 device\n"); 254 goto err; 255 } 256 257 dwc->pci = pci; 258 dwc->dwc3->dev.parent = dev; 259 ACPI_COMPANION_SET(&dwc->dwc3->dev, ACPI_COMPANION(dev)); 260 261 ret = platform_device_add_properties(dwc->dwc3, p); 262 if (ret < 0) 263 goto err; 264 265 ret = dwc3_pci_quirks(dwc); 266 if (ret) 267 goto err; 268 269 ret = platform_device_add(dwc->dwc3); 270 if (ret) { 271 dev_err(dev, "failed to register dwc3 device\n"); 272 goto err; 273 } 274 275 device_init_wakeup(dev, true); 276 pci_set_drvdata(pci, dwc); 277 pm_runtime_put(dev); 278 #ifdef CONFIG_PM 279 INIT_WORK(&dwc->wakeup_work, dwc3_pci_resume_work); 280 #endif 281 282 return 0; 283 err: 284 platform_device_put(dwc->dwc3); 285 return ret; 286 } 287 288 static void dwc3_pci_remove(struct pci_dev *pci) 289 { 290 struct dwc3_pci *dwc = pci_get_drvdata(pci); 291 struct pci_dev *pdev = dwc->pci; 292 293 if (pdev->device == PCI_DEVICE_ID_INTEL_BYT) 294 gpiod_remove_lookup_table(&platform_bytcr_gpios); 295 #ifdef CONFIG_PM 296 cancel_work_sync(&dwc->wakeup_work); 297 #endif 298 device_init_wakeup(&pci->dev, false); 299 pm_runtime_get(&pci->dev); 300 platform_device_unregister(dwc->dwc3); 301 } 302 303 static const struct pci_device_id dwc3_pci_id_table[] = { 304 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_BSW), 305 (kernel_ulong_t) &dwc3_pci_intel_properties }, 306 307 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_BYT), 308 (kernel_ulong_t) &dwc3_pci_intel_properties, }, 309 310 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_MRFLD), 311 (kernel_ulong_t) &dwc3_pci_mrfld_properties, }, 312 313 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_CMLLP), 314 (kernel_ulong_t) &dwc3_pci_intel_properties, }, 315 316 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_CMLH), 317 (kernel_ulong_t) &dwc3_pci_intel_properties, }, 318 319 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_SPTLP), 320 (kernel_ulong_t) &dwc3_pci_intel_properties, }, 321 322 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_SPTH), 323 (kernel_ulong_t) &dwc3_pci_intel_properties, }, 324 325 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_BXT), 326 (kernel_ulong_t) &dwc3_pci_intel_properties, }, 327 328 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_BXT_M), 329 (kernel_ulong_t) &dwc3_pci_intel_properties, }, 330 331 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_APL), 332 (kernel_ulong_t) &dwc3_pci_intel_properties, }, 333 334 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_KBP), 335 (kernel_ulong_t) &dwc3_pci_intel_properties, }, 336 337 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_GLK), 338 (kernel_ulong_t) &dwc3_pci_intel_properties, }, 339 340 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_CNPLP), 341 (kernel_ulong_t) &dwc3_pci_intel_properties, }, 342 343 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_CNPH), 344 (kernel_ulong_t) &dwc3_pci_intel_properties, }, 345 346 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_CNPV), 347 (kernel_ulong_t) &dwc3_pci_intel_properties, }, 348 349 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ICLLP), 350 (kernel_ulong_t) &dwc3_pci_intel_properties, }, 351 352 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_EHLLP), 353 (kernel_ulong_t) &dwc3_pci_intel_properties, }, 354 355 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_TGPLP), 356 (kernel_ulong_t) &dwc3_pci_intel_properties, }, 357 358 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_NL_USB), 359 (kernel_ulong_t) &dwc3_pci_amd_properties, }, 360 { } /* Terminating Entry */ 361 }; 362 MODULE_DEVICE_TABLE(pci, dwc3_pci_id_table); 363 364 #if defined(CONFIG_PM) || defined(CONFIG_PM_SLEEP) 365 static int dwc3_pci_dsm(struct dwc3_pci *dwc, int param) 366 { 367 union acpi_object *obj; 368 union acpi_object tmp; 369 union acpi_object argv4 = ACPI_INIT_DSM_ARGV4(1, &tmp); 370 371 if (!dwc->has_dsm_for_pm) 372 return 0; 373 374 tmp.type = ACPI_TYPE_INTEGER; 375 tmp.integer.value = param; 376 377 obj = acpi_evaluate_dsm(ACPI_HANDLE(&dwc->pci->dev), &dwc->guid, 378 1, PCI_INTEL_BXT_FUNC_PMU_PWR, &argv4); 379 if (!obj) { 380 dev_err(&dwc->pci->dev, "failed to evaluate _DSM\n"); 381 return -EIO; 382 } 383 384 ACPI_FREE(obj); 385 386 return 0; 387 } 388 #endif /* CONFIG_PM || CONFIG_PM_SLEEP */ 389 390 #ifdef CONFIG_PM 391 static int dwc3_pci_runtime_suspend(struct device *dev) 392 { 393 struct dwc3_pci *dwc = dev_get_drvdata(dev); 394 395 if (device_can_wakeup(dev)) 396 return dwc3_pci_dsm(dwc, PCI_INTEL_BXT_STATE_D3); 397 398 return -EBUSY; 399 } 400 401 static int dwc3_pci_runtime_resume(struct device *dev) 402 { 403 struct dwc3_pci *dwc = dev_get_drvdata(dev); 404 int ret; 405 406 ret = dwc3_pci_dsm(dwc, PCI_INTEL_BXT_STATE_D0); 407 if (ret) 408 return ret; 409 410 queue_work(pm_wq, &dwc->wakeup_work); 411 412 return 0; 413 } 414 #endif /* CONFIG_PM */ 415 416 #ifdef CONFIG_PM_SLEEP 417 static int dwc3_pci_suspend(struct device *dev) 418 { 419 struct dwc3_pci *dwc = dev_get_drvdata(dev); 420 421 return dwc3_pci_dsm(dwc, PCI_INTEL_BXT_STATE_D3); 422 } 423 424 static int dwc3_pci_resume(struct device *dev) 425 { 426 struct dwc3_pci *dwc = dev_get_drvdata(dev); 427 428 return dwc3_pci_dsm(dwc, PCI_INTEL_BXT_STATE_D0); 429 } 430 #endif /* CONFIG_PM_SLEEP */ 431 432 static const struct dev_pm_ops dwc3_pci_dev_pm_ops = { 433 SET_SYSTEM_SLEEP_PM_OPS(dwc3_pci_suspend, dwc3_pci_resume) 434 SET_RUNTIME_PM_OPS(dwc3_pci_runtime_suspend, dwc3_pci_runtime_resume, 435 NULL) 436 }; 437 438 static struct pci_driver dwc3_pci_driver = { 439 .name = "dwc3-pci", 440 .id_table = dwc3_pci_id_table, 441 .probe = dwc3_pci_probe, 442 .remove = dwc3_pci_remove, 443 .driver = { 444 .pm = &dwc3_pci_dev_pm_ops, 445 } 446 }; 447 448 MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>"); 449 MODULE_LICENSE("GPL v2"); 450 MODULE_DESCRIPTION("DesignWare USB3 PCI Glue Layer"); 451 452 module_pci_driver(dwc3_pci_driver); 453