1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * dwc3-pci.c - PCI Specific glue layer 4 * 5 * Copyright (C) 2010-2011 Texas Instruments Incorporated - https://www.ti.com 6 * 7 * Authors: Felipe Balbi <balbi@ti.com>, 8 * Sebastian Andrzej Siewior <bigeasy@linutronix.de> 9 */ 10 11 #include <linux/kernel.h> 12 #include <linux/module.h> 13 #include <linux/slab.h> 14 #include <linux/pci.h> 15 #include <linux/workqueue.h> 16 #include <linux/pm_runtime.h> 17 #include <linux/platform_device.h> 18 #include <linux/gpio/consumer.h> 19 #include <linux/gpio/machine.h> 20 #include <linux/acpi.h> 21 #include <linux/delay.h> 22 23 #define PCI_DEVICE_ID_INTEL_BYT 0x0f37 24 #define PCI_DEVICE_ID_INTEL_MRFLD 0x119e 25 #define PCI_DEVICE_ID_INTEL_BSW 0x22b7 26 #define PCI_DEVICE_ID_INTEL_SPTLP 0x9d30 27 #define PCI_DEVICE_ID_INTEL_SPTH 0xa130 28 #define PCI_DEVICE_ID_INTEL_BXT 0x0aaa 29 #define PCI_DEVICE_ID_INTEL_BXT_M 0x1aaa 30 #define PCI_DEVICE_ID_INTEL_APL 0x5aaa 31 #define PCI_DEVICE_ID_INTEL_KBP 0xa2b0 32 #define PCI_DEVICE_ID_INTEL_CMLLP 0x02ee 33 #define PCI_DEVICE_ID_INTEL_CMLH 0x06ee 34 #define PCI_DEVICE_ID_INTEL_GLK 0x31aa 35 #define PCI_DEVICE_ID_INTEL_CNPLP 0x9dee 36 #define PCI_DEVICE_ID_INTEL_CNPH 0xa36e 37 #define PCI_DEVICE_ID_INTEL_CNPV 0xa3b0 38 #define PCI_DEVICE_ID_INTEL_ICLLP 0x34ee 39 #define PCI_DEVICE_ID_INTEL_EHL 0x4b7e 40 #define PCI_DEVICE_ID_INTEL_TGPLP 0xa0ee 41 #define PCI_DEVICE_ID_INTEL_TGPH 0x43ee 42 #define PCI_DEVICE_ID_INTEL_JSP 0x4dee 43 #define PCI_DEVICE_ID_INTEL_ADLP 0x51ee 44 #define PCI_DEVICE_ID_INTEL_ADLM 0x54ee 45 #define PCI_DEVICE_ID_INTEL_ADLS 0x7ae1 46 #define PCI_DEVICE_ID_INTEL_RPLS 0x7a61 47 #define PCI_DEVICE_ID_INTEL_TGL 0x9a15 48 #define PCI_DEVICE_ID_AMD_MR 0x163a 49 50 #define PCI_INTEL_BXT_DSM_GUID "732b85d5-b7a7-4a1b-9ba0-4bbd00ffd511" 51 #define PCI_INTEL_BXT_FUNC_PMU_PWR 4 52 #define PCI_INTEL_BXT_STATE_D0 0 53 #define PCI_INTEL_BXT_STATE_D3 3 54 55 #define GP_RWBAR 1 56 #define GP_RWREG1 0xa0 57 #define GP_RWREG1_ULPI_REFCLK_DISABLE (1 << 17) 58 59 /** 60 * struct dwc3_pci - Driver private structure 61 * @dwc3: child dwc3 platform_device 62 * @pci: our link to PCI bus 63 * @guid: _DSM GUID 64 * @has_dsm_for_pm: true for devices which need to run _DSM on runtime PM 65 * @wakeup_work: work for asynchronous resume 66 */ 67 struct dwc3_pci { 68 struct platform_device *dwc3; 69 struct pci_dev *pci; 70 71 guid_t guid; 72 73 unsigned int has_dsm_for_pm:1; 74 struct work_struct wakeup_work; 75 }; 76 77 static const struct acpi_gpio_params reset_gpios = { 0, 0, false }; 78 static const struct acpi_gpio_params cs_gpios = { 1, 0, false }; 79 80 static const struct acpi_gpio_mapping acpi_dwc3_byt_gpios[] = { 81 { "reset-gpios", &reset_gpios, 1 }, 82 { "cs-gpios", &cs_gpios, 1 }, 83 { }, 84 }; 85 86 static struct gpiod_lookup_table platform_bytcr_gpios = { 87 .dev_id = "0000:00:16.0", 88 .table = { 89 GPIO_LOOKUP("INT33FC:00", 54, "cs", GPIO_ACTIVE_HIGH), 90 GPIO_LOOKUP("INT33FC:02", 14, "reset", GPIO_ACTIVE_HIGH), 91 {} 92 }, 93 }; 94 95 static int dwc3_byt_enable_ulpi_refclock(struct pci_dev *pci) 96 { 97 void __iomem *reg; 98 u32 value; 99 100 reg = pcim_iomap(pci, GP_RWBAR, 0); 101 if (!reg) 102 return -ENOMEM; 103 104 value = readl(reg + GP_RWREG1); 105 if (!(value & GP_RWREG1_ULPI_REFCLK_DISABLE)) 106 goto unmap; /* ULPI refclk already enabled */ 107 108 value &= ~GP_RWREG1_ULPI_REFCLK_DISABLE; 109 writel(value, reg + GP_RWREG1); 110 /* This comes from the Intel Android x86 tree w/o any explanation */ 111 msleep(100); 112 unmap: 113 pcim_iounmap(pci, reg); 114 return 0; 115 } 116 117 static const struct property_entry dwc3_pci_intel_properties[] = { 118 PROPERTY_ENTRY_STRING("dr_mode", "peripheral"), 119 PROPERTY_ENTRY_BOOL("linux,sysdev_is_parent"), 120 {} 121 }; 122 123 static const struct property_entry dwc3_pci_intel_byt_properties[] = { 124 PROPERTY_ENTRY_STRING("dr_mode", "peripheral"), 125 PROPERTY_ENTRY_BOOL("snps,dis_u2_susphy_quirk"), 126 PROPERTY_ENTRY_BOOL("linux,sysdev_is_parent"), 127 {} 128 }; 129 130 static const struct property_entry dwc3_pci_mrfld_properties[] = { 131 PROPERTY_ENTRY_STRING("dr_mode", "otg"), 132 PROPERTY_ENTRY_STRING("linux,extcon-name", "mrfld_bcove_pwrsrc"), 133 PROPERTY_ENTRY_BOOL("snps,dis_u3_susphy_quirk"), 134 PROPERTY_ENTRY_BOOL("snps,dis_u2_susphy_quirk"), 135 PROPERTY_ENTRY_BOOL("snps,usb2-gadget-lpm-disable"), 136 PROPERTY_ENTRY_BOOL("linux,sysdev_is_parent"), 137 {} 138 }; 139 140 static const struct property_entry dwc3_pci_amd_properties[] = { 141 PROPERTY_ENTRY_BOOL("snps,has-lpm-erratum"), 142 PROPERTY_ENTRY_U8("snps,lpm-nyet-threshold", 0xf), 143 PROPERTY_ENTRY_BOOL("snps,u2exit_lfps_quirk"), 144 PROPERTY_ENTRY_BOOL("snps,u2ss_inp3_quirk"), 145 PROPERTY_ENTRY_BOOL("snps,req_p1p2p3_quirk"), 146 PROPERTY_ENTRY_BOOL("snps,del_p1p2p3_quirk"), 147 PROPERTY_ENTRY_BOOL("snps,del_phy_power_chg_quirk"), 148 PROPERTY_ENTRY_BOOL("snps,lfps_filter_quirk"), 149 PROPERTY_ENTRY_BOOL("snps,rx_detect_poll_quirk"), 150 PROPERTY_ENTRY_BOOL("snps,tx_de_emphasis_quirk"), 151 PROPERTY_ENTRY_U8("snps,tx_de_emphasis", 1), 152 /* FIXME these quirks should be removed when AMD NL tapes out */ 153 PROPERTY_ENTRY_BOOL("snps,disable_scramble_quirk"), 154 PROPERTY_ENTRY_BOOL("snps,dis_u3_susphy_quirk"), 155 PROPERTY_ENTRY_BOOL("snps,dis_u2_susphy_quirk"), 156 PROPERTY_ENTRY_BOOL("linux,sysdev_is_parent"), 157 {} 158 }; 159 160 static const struct property_entry dwc3_pci_mr_properties[] = { 161 PROPERTY_ENTRY_STRING("dr_mode", "otg"), 162 PROPERTY_ENTRY_BOOL("usb-role-switch"), 163 PROPERTY_ENTRY_STRING("role-switch-default-mode", "host"), 164 PROPERTY_ENTRY_BOOL("linux,sysdev_is_parent"), 165 {} 166 }; 167 168 static const struct software_node dwc3_pci_intel_swnode = { 169 .properties = dwc3_pci_intel_properties, 170 }; 171 172 static const struct software_node dwc3_pci_intel_byt_swnode = { 173 .properties = dwc3_pci_intel_byt_properties, 174 }; 175 176 static const struct software_node dwc3_pci_intel_mrfld_swnode = { 177 .properties = dwc3_pci_mrfld_properties, 178 }; 179 180 static const struct software_node dwc3_pci_amd_swnode = { 181 .properties = dwc3_pci_amd_properties, 182 }; 183 184 static const struct software_node dwc3_pci_amd_mr_swnode = { 185 .properties = dwc3_pci_mr_properties, 186 }; 187 188 static int dwc3_pci_quirks(struct dwc3_pci *dwc) 189 { 190 struct pci_dev *pdev = dwc->pci; 191 192 if (pdev->vendor == PCI_VENDOR_ID_INTEL) { 193 if (pdev->device == PCI_DEVICE_ID_INTEL_BXT || 194 pdev->device == PCI_DEVICE_ID_INTEL_BXT_M || 195 pdev->device == PCI_DEVICE_ID_INTEL_EHL) { 196 guid_parse(PCI_INTEL_BXT_DSM_GUID, &dwc->guid); 197 dwc->has_dsm_for_pm = true; 198 } 199 200 if (pdev->device == PCI_DEVICE_ID_INTEL_BYT) { 201 struct gpio_desc *gpio; 202 int ret; 203 204 /* On BYT the FW does not always enable the refclock */ 205 ret = dwc3_byt_enable_ulpi_refclock(pdev); 206 if (ret) 207 return ret; 208 209 ret = devm_acpi_dev_add_driver_gpios(&pdev->dev, 210 acpi_dwc3_byt_gpios); 211 if (ret) 212 dev_dbg(&pdev->dev, "failed to add mapping table\n"); 213 214 /* 215 * A lot of BYT devices lack ACPI resource entries for 216 * the GPIOs, add a fallback mapping to the reference 217 * design GPIOs which all boards seem to use. 218 */ 219 gpiod_add_lookup_table(&platform_bytcr_gpios); 220 221 /* 222 * These GPIOs will turn on the USB2 PHY. Note that we have to 223 * put the gpio descriptors again here because the phy driver 224 * might want to grab them, too. 225 */ 226 gpio = gpiod_get_optional(&pdev->dev, "cs", GPIOD_OUT_LOW); 227 if (IS_ERR(gpio)) 228 return PTR_ERR(gpio); 229 230 gpiod_set_value_cansleep(gpio, 1); 231 gpiod_put(gpio); 232 233 gpio = gpiod_get_optional(&pdev->dev, "reset", GPIOD_OUT_LOW); 234 if (IS_ERR(gpio)) 235 return PTR_ERR(gpio); 236 237 if (gpio) { 238 gpiod_set_value_cansleep(gpio, 1); 239 gpiod_put(gpio); 240 usleep_range(10000, 11000); 241 } 242 } 243 } 244 245 return 0; 246 } 247 248 #ifdef CONFIG_PM 249 static void dwc3_pci_resume_work(struct work_struct *work) 250 { 251 struct dwc3_pci *dwc = container_of(work, struct dwc3_pci, wakeup_work); 252 struct platform_device *dwc3 = dwc->dwc3; 253 int ret; 254 255 ret = pm_runtime_get_sync(&dwc3->dev); 256 if (ret) { 257 pm_runtime_put_sync_autosuspend(&dwc3->dev); 258 return; 259 } 260 261 pm_runtime_mark_last_busy(&dwc3->dev); 262 pm_runtime_put_sync_autosuspend(&dwc3->dev); 263 } 264 #endif 265 266 static int dwc3_pci_probe(struct pci_dev *pci, const struct pci_device_id *id) 267 { 268 struct dwc3_pci *dwc; 269 struct resource res[2]; 270 int ret; 271 struct device *dev = &pci->dev; 272 273 ret = pcim_enable_device(pci); 274 if (ret) { 275 dev_err(dev, "failed to enable pci device\n"); 276 return -ENODEV; 277 } 278 279 pci_set_master(pci); 280 281 dwc = devm_kzalloc(dev, sizeof(*dwc), GFP_KERNEL); 282 if (!dwc) 283 return -ENOMEM; 284 285 dwc->dwc3 = platform_device_alloc("dwc3", PLATFORM_DEVID_AUTO); 286 if (!dwc->dwc3) 287 return -ENOMEM; 288 289 memset(res, 0x00, sizeof(struct resource) * ARRAY_SIZE(res)); 290 291 res[0].start = pci_resource_start(pci, 0); 292 res[0].end = pci_resource_end(pci, 0); 293 res[0].name = "dwc_usb3"; 294 res[0].flags = IORESOURCE_MEM; 295 296 res[1].start = pci->irq; 297 res[1].name = "dwc_usb3"; 298 res[1].flags = IORESOURCE_IRQ; 299 300 ret = platform_device_add_resources(dwc->dwc3, res, ARRAY_SIZE(res)); 301 if (ret) { 302 dev_err(dev, "couldn't add resources to dwc3 device\n"); 303 goto err; 304 } 305 306 dwc->pci = pci; 307 dwc->dwc3->dev.parent = dev; 308 ACPI_COMPANION_SET(&dwc->dwc3->dev, ACPI_COMPANION(dev)); 309 310 ret = device_add_software_node(&dwc->dwc3->dev, (void *)id->driver_data); 311 if (ret < 0) 312 goto err; 313 314 ret = dwc3_pci_quirks(dwc); 315 if (ret) 316 goto err; 317 318 ret = platform_device_add(dwc->dwc3); 319 if (ret) { 320 dev_err(dev, "failed to register dwc3 device\n"); 321 goto err; 322 } 323 324 device_init_wakeup(dev, true); 325 pci_set_drvdata(pci, dwc); 326 pm_runtime_put(dev); 327 #ifdef CONFIG_PM 328 INIT_WORK(&dwc->wakeup_work, dwc3_pci_resume_work); 329 #endif 330 331 return 0; 332 err: 333 device_remove_software_node(&dwc->dwc3->dev); 334 platform_device_put(dwc->dwc3); 335 return ret; 336 } 337 338 static void dwc3_pci_remove(struct pci_dev *pci) 339 { 340 struct dwc3_pci *dwc = pci_get_drvdata(pci); 341 struct pci_dev *pdev = dwc->pci; 342 343 if (pdev->device == PCI_DEVICE_ID_INTEL_BYT) 344 gpiod_remove_lookup_table(&platform_bytcr_gpios); 345 #ifdef CONFIG_PM 346 cancel_work_sync(&dwc->wakeup_work); 347 #endif 348 device_init_wakeup(&pci->dev, false); 349 pm_runtime_get(&pci->dev); 350 device_remove_software_node(&dwc->dwc3->dev); 351 platform_device_unregister(dwc->dwc3); 352 } 353 354 static const struct pci_device_id dwc3_pci_id_table[] = { 355 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_BSW), 356 (kernel_ulong_t) &dwc3_pci_intel_swnode, }, 357 358 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_BYT), 359 (kernel_ulong_t) &dwc3_pci_intel_byt_swnode, }, 360 361 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_MRFLD), 362 (kernel_ulong_t) &dwc3_pci_intel_mrfld_swnode, }, 363 364 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_CMLLP), 365 (kernel_ulong_t) &dwc3_pci_intel_swnode, }, 366 367 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_CMLH), 368 (kernel_ulong_t) &dwc3_pci_intel_swnode, }, 369 370 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_SPTLP), 371 (kernel_ulong_t) &dwc3_pci_intel_swnode, }, 372 373 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_SPTH), 374 (kernel_ulong_t) &dwc3_pci_intel_swnode, }, 375 376 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_BXT), 377 (kernel_ulong_t) &dwc3_pci_intel_swnode, }, 378 379 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_BXT_M), 380 (kernel_ulong_t) &dwc3_pci_intel_swnode, }, 381 382 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_APL), 383 (kernel_ulong_t) &dwc3_pci_intel_swnode, }, 384 385 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_KBP), 386 (kernel_ulong_t) &dwc3_pci_intel_swnode, }, 387 388 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_GLK), 389 (kernel_ulong_t) &dwc3_pci_intel_swnode, }, 390 391 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_CNPLP), 392 (kernel_ulong_t) &dwc3_pci_intel_swnode, }, 393 394 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_CNPH), 395 (kernel_ulong_t) &dwc3_pci_intel_swnode, }, 396 397 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_CNPV), 398 (kernel_ulong_t) &dwc3_pci_intel_swnode, }, 399 400 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ICLLP), 401 (kernel_ulong_t) &dwc3_pci_intel_swnode, }, 402 403 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_EHL), 404 (kernel_ulong_t) &dwc3_pci_intel_swnode, }, 405 406 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_TGPLP), 407 (kernel_ulong_t) &dwc3_pci_intel_swnode, }, 408 409 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_TGPH), 410 (kernel_ulong_t) &dwc3_pci_intel_swnode, }, 411 412 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_JSP), 413 (kernel_ulong_t) &dwc3_pci_intel_swnode, }, 414 415 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ADLP), 416 (kernel_ulong_t) &dwc3_pci_intel_swnode, }, 417 418 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ADLM), 419 (kernel_ulong_t) &dwc3_pci_intel_swnode, }, 420 421 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ADLS), 422 (kernel_ulong_t) &dwc3_pci_intel_swnode, }, 423 424 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_RPLS), 425 (kernel_ulong_t) &dwc3_pci_intel_swnode, }, 426 427 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_TGL), 428 (kernel_ulong_t) &dwc3_pci_intel_swnode, }, 429 430 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_NL_USB), 431 (kernel_ulong_t) &dwc3_pci_amd_swnode, }, 432 433 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_MR), 434 (kernel_ulong_t)&dwc3_pci_amd_mr_swnode, }, 435 436 { } /* Terminating Entry */ 437 }; 438 MODULE_DEVICE_TABLE(pci, dwc3_pci_id_table); 439 440 #if defined(CONFIG_PM) || defined(CONFIG_PM_SLEEP) 441 static int dwc3_pci_dsm(struct dwc3_pci *dwc, int param) 442 { 443 union acpi_object *obj; 444 union acpi_object tmp; 445 union acpi_object argv4 = ACPI_INIT_DSM_ARGV4(1, &tmp); 446 447 if (!dwc->has_dsm_for_pm) 448 return 0; 449 450 tmp.type = ACPI_TYPE_INTEGER; 451 tmp.integer.value = param; 452 453 obj = acpi_evaluate_dsm(ACPI_HANDLE(&dwc->pci->dev), &dwc->guid, 454 1, PCI_INTEL_BXT_FUNC_PMU_PWR, &argv4); 455 if (!obj) { 456 dev_err(&dwc->pci->dev, "failed to evaluate _DSM\n"); 457 return -EIO; 458 } 459 460 ACPI_FREE(obj); 461 462 return 0; 463 } 464 #endif /* CONFIG_PM || CONFIG_PM_SLEEP */ 465 466 #ifdef CONFIG_PM 467 static int dwc3_pci_runtime_suspend(struct device *dev) 468 { 469 struct dwc3_pci *dwc = dev_get_drvdata(dev); 470 471 if (device_can_wakeup(dev)) 472 return dwc3_pci_dsm(dwc, PCI_INTEL_BXT_STATE_D3); 473 474 return -EBUSY; 475 } 476 477 static int dwc3_pci_runtime_resume(struct device *dev) 478 { 479 struct dwc3_pci *dwc = dev_get_drvdata(dev); 480 int ret; 481 482 ret = dwc3_pci_dsm(dwc, PCI_INTEL_BXT_STATE_D0); 483 if (ret) 484 return ret; 485 486 queue_work(pm_wq, &dwc->wakeup_work); 487 488 return 0; 489 } 490 #endif /* CONFIG_PM */ 491 492 #ifdef CONFIG_PM_SLEEP 493 static int dwc3_pci_suspend(struct device *dev) 494 { 495 struct dwc3_pci *dwc = dev_get_drvdata(dev); 496 497 return dwc3_pci_dsm(dwc, PCI_INTEL_BXT_STATE_D3); 498 } 499 500 static int dwc3_pci_resume(struct device *dev) 501 { 502 struct dwc3_pci *dwc = dev_get_drvdata(dev); 503 504 return dwc3_pci_dsm(dwc, PCI_INTEL_BXT_STATE_D0); 505 } 506 #endif /* CONFIG_PM_SLEEP */ 507 508 static const struct dev_pm_ops dwc3_pci_dev_pm_ops = { 509 SET_SYSTEM_SLEEP_PM_OPS(dwc3_pci_suspend, dwc3_pci_resume) 510 SET_RUNTIME_PM_OPS(dwc3_pci_runtime_suspend, dwc3_pci_runtime_resume, 511 NULL) 512 }; 513 514 static struct pci_driver dwc3_pci_driver = { 515 .name = "dwc3-pci", 516 .id_table = dwc3_pci_id_table, 517 .probe = dwc3_pci_probe, 518 .remove = dwc3_pci_remove, 519 .driver = { 520 .pm = &dwc3_pci_dev_pm_ops, 521 } 522 }; 523 524 MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>"); 525 MODULE_LICENSE("GPL v2"); 526 MODULE_DESCRIPTION("DesignWare USB3 PCI Glue Layer"); 527 528 module_pci_driver(dwc3_pci_driver); 529