1 // SPDX-License-Identifier: GPL-2.0 2 /** 3 * dwc3-pci.c - PCI Specific glue layer 4 * 5 * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com 6 * 7 * Authors: Felipe Balbi <balbi@ti.com>, 8 * Sebastian Andrzej Siewior <bigeasy@linutronix.de> 9 */ 10 11 #include <linux/kernel.h> 12 #include <linux/module.h> 13 #include <linux/slab.h> 14 #include <linux/pci.h> 15 #include <linux/workqueue.h> 16 #include <linux/pm_runtime.h> 17 #include <linux/platform_device.h> 18 #include <linux/gpio/consumer.h> 19 #include <linux/gpio/machine.h> 20 #include <linux/acpi.h> 21 #include <linux/delay.h> 22 23 #define PCI_DEVICE_ID_INTEL_BYT 0x0f37 24 #define PCI_DEVICE_ID_INTEL_MRFLD 0x119e 25 #define PCI_DEVICE_ID_INTEL_BSW 0x22b7 26 #define PCI_DEVICE_ID_INTEL_SPTLP 0x9d30 27 #define PCI_DEVICE_ID_INTEL_SPTH 0xa130 28 #define PCI_DEVICE_ID_INTEL_BXT 0x0aaa 29 #define PCI_DEVICE_ID_INTEL_BXT_M 0x1aaa 30 #define PCI_DEVICE_ID_INTEL_APL 0x5aaa 31 #define PCI_DEVICE_ID_INTEL_KBP 0xa2b0 32 #define PCI_DEVICE_ID_INTEL_CMLLP 0x02ee 33 #define PCI_DEVICE_ID_INTEL_CMLH 0x06ee 34 #define PCI_DEVICE_ID_INTEL_GLK 0x31aa 35 #define PCI_DEVICE_ID_INTEL_CNPLP 0x9dee 36 #define PCI_DEVICE_ID_INTEL_CNPH 0xa36e 37 #define PCI_DEVICE_ID_INTEL_CNPV 0xa3b0 38 #define PCI_DEVICE_ID_INTEL_ICLLP 0x34ee 39 #define PCI_DEVICE_ID_INTEL_EHLLP 0x4b7e 40 #define PCI_DEVICE_ID_INTEL_TGPLP 0xa0ee 41 42 #define PCI_INTEL_BXT_DSM_GUID "732b85d5-b7a7-4a1b-9ba0-4bbd00ffd511" 43 #define PCI_INTEL_BXT_FUNC_PMU_PWR 4 44 #define PCI_INTEL_BXT_STATE_D0 0 45 #define PCI_INTEL_BXT_STATE_D3 3 46 47 #define GP_RWBAR 1 48 #define GP_RWREG1 0xa0 49 #define GP_RWREG1_ULPI_REFCLK_DISABLE (1 << 17) 50 51 /** 52 * struct dwc3_pci - Driver private structure 53 * @dwc3: child dwc3 platform_device 54 * @pci: our link to PCI bus 55 * @guid: _DSM GUID 56 * @has_dsm_for_pm: true for devices which need to run _DSM on runtime PM 57 * @wakeup_work: work for asynchronous resume 58 */ 59 struct dwc3_pci { 60 struct platform_device *dwc3; 61 struct pci_dev *pci; 62 63 guid_t guid; 64 65 unsigned int has_dsm_for_pm:1; 66 struct work_struct wakeup_work; 67 }; 68 69 static const struct acpi_gpio_params reset_gpios = { 0, 0, false }; 70 static const struct acpi_gpio_params cs_gpios = { 1, 0, false }; 71 72 static const struct acpi_gpio_mapping acpi_dwc3_byt_gpios[] = { 73 { "reset-gpios", &reset_gpios, 1 }, 74 { "cs-gpios", &cs_gpios, 1 }, 75 { }, 76 }; 77 78 static struct gpiod_lookup_table platform_bytcr_gpios = { 79 .dev_id = "0000:00:16.0", 80 .table = { 81 GPIO_LOOKUP("INT33FC:00", 54, "reset", GPIO_ACTIVE_HIGH), 82 GPIO_LOOKUP("INT33FC:02", 14, "cs", GPIO_ACTIVE_HIGH), 83 {} 84 }, 85 }; 86 87 static int dwc3_byt_enable_ulpi_refclock(struct pci_dev *pci) 88 { 89 void __iomem *reg; 90 u32 value; 91 92 reg = pcim_iomap(pci, GP_RWBAR, 0); 93 if (!reg) 94 return -ENOMEM; 95 96 value = readl(reg + GP_RWREG1); 97 if (!(value & GP_RWREG1_ULPI_REFCLK_DISABLE)) 98 goto unmap; /* ULPI refclk already enabled */ 99 100 value &= ~GP_RWREG1_ULPI_REFCLK_DISABLE; 101 writel(value, reg + GP_RWREG1); 102 /* This comes from the Intel Android x86 tree w/o any explanation */ 103 msleep(100); 104 unmap: 105 pcim_iounmap(pci, reg); 106 return 0; 107 } 108 109 static const struct property_entry dwc3_pci_intel_properties[] = { 110 PROPERTY_ENTRY_STRING("dr_mode", "peripheral"), 111 PROPERTY_ENTRY_BOOL("linux,sysdev_is_parent"), 112 {} 113 }; 114 115 static const struct property_entry dwc3_pci_mrfld_properties[] = { 116 PROPERTY_ENTRY_STRING("dr_mode", "otg"), 117 PROPERTY_ENTRY_STRING("linux,extcon-name", "mrfld_bcove_pwrsrc"), 118 PROPERTY_ENTRY_BOOL("linux,sysdev_is_parent"), 119 {} 120 }; 121 122 static const struct property_entry dwc3_pci_amd_properties[] = { 123 PROPERTY_ENTRY_BOOL("snps,has-lpm-erratum"), 124 PROPERTY_ENTRY_U8("snps,lpm-nyet-threshold", 0xf), 125 PROPERTY_ENTRY_BOOL("snps,u2exit_lfps_quirk"), 126 PROPERTY_ENTRY_BOOL("snps,u2ss_inp3_quirk"), 127 PROPERTY_ENTRY_BOOL("snps,req_p1p2p3_quirk"), 128 PROPERTY_ENTRY_BOOL("snps,del_p1p2p3_quirk"), 129 PROPERTY_ENTRY_BOOL("snps,del_phy_power_chg_quirk"), 130 PROPERTY_ENTRY_BOOL("snps,lfps_filter_quirk"), 131 PROPERTY_ENTRY_BOOL("snps,rx_detect_poll_quirk"), 132 PROPERTY_ENTRY_BOOL("snps,tx_de_emphasis_quirk"), 133 PROPERTY_ENTRY_U8("snps,tx_de_emphasis", 1), 134 /* FIXME these quirks should be removed when AMD NL tapes out */ 135 PROPERTY_ENTRY_BOOL("snps,disable_scramble_quirk"), 136 PROPERTY_ENTRY_BOOL("snps,dis_u3_susphy_quirk"), 137 PROPERTY_ENTRY_BOOL("snps,dis_u2_susphy_quirk"), 138 PROPERTY_ENTRY_BOOL("linux,sysdev_is_parent"), 139 {} 140 }; 141 142 static int dwc3_pci_quirks(struct dwc3_pci *dwc) 143 { 144 struct pci_dev *pdev = dwc->pci; 145 146 if (pdev->vendor == PCI_VENDOR_ID_INTEL) { 147 if (pdev->device == PCI_DEVICE_ID_INTEL_BXT || 148 pdev->device == PCI_DEVICE_ID_INTEL_BXT_M) { 149 guid_parse(PCI_INTEL_BXT_DSM_GUID, &dwc->guid); 150 dwc->has_dsm_for_pm = true; 151 } 152 153 if (pdev->device == PCI_DEVICE_ID_INTEL_BYT) { 154 struct gpio_desc *gpio; 155 int ret; 156 157 /* On BYT the FW does not always enable the refclock */ 158 ret = dwc3_byt_enable_ulpi_refclock(pdev); 159 if (ret) 160 return ret; 161 162 ret = devm_acpi_dev_add_driver_gpios(&pdev->dev, 163 acpi_dwc3_byt_gpios); 164 if (ret) 165 dev_dbg(&pdev->dev, "failed to add mapping table\n"); 166 167 /* 168 * A lot of BYT devices lack ACPI resource entries for 169 * the GPIOs, add a fallback mapping to the reference 170 * design GPIOs which all boards seem to use. 171 */ 172 gpiod_add_lookup_table(&platform_bytcr_gpios); 173 174 /* 175 * These GPIOs will turn on the USB2 PHY. Note that we have to 176 * put the gpio descriptors again here because the phy driver 177 * might want to grab them, too. 178 */ 179 gpio = gpiod_get_optional(&pdev->dev, "cs", GPIOD_OUT_LOW); 180 if (IS_ERR(gpio)) 181 return PTR_ERR(gpio); 182 183 gpiod_set_value_cansleep(gpio, 1); 184 gpiod_put(gpio); 185 186 gpio = gpiod_get_optional(&pdev->dev, "reset", GPIOD_OUT_LOW); 187 if (IS_ERR(gpio)) 188 return PTR_ERR(gpio); 189 190 if (gpio) { 191 gpiod_set_value_cansleep(gpio, 1); 192 gpiod_put(gpio); 193 usleep_range(10000, 11000); 194 } 195 } 196 } 197 198 return 0; 199 } 200 201 #ifdef CONFIG_PM 202 static void dwc3_pci_resume_work(struct work_struct *work) 203 { 204 struct dwc3_pci *dwc = container_of(work, struct dwc3_pci, wakeup_work); 205 struct platform_device *dwc3 = dwc->dwc3; 206 int ret; 207 208 ret = pm_runtime_get_sync(&dwc3->dev); 209 if (ret) { 210 pm_runtime_put_sync_autosuspend(&dwc3->dev); 211 return; 212 } 213 214 pm_runtime_mark_last_busy(&dwc3->dev); 215 pm_runtime_put_sync_autosuspend(&dwc3->dev); 216 } 217 #endif 218 219 static int dwc3_pci_probe(struct pci_dev *pci, const struct pci_device_id *id) 220 { 221 struct property_entry *p = (struct property_entry *)id->driver_data; 222 struct dwc3_pci *dwc; 223 struct resource res[2]; 224 int ret; 225 struct device *dev = &pci->dev; 226 227 ret = pcim_enable_device(pci); 228 if (ret) { 229 dev_err(dev, "failed to enable pci device\n"); 230 return -ENODEV; 231 } 232 233 pci_set_master(pci); 234 235 dwc = devm_kzalloc(dev, sizeof(*dwc), GFP_KERNEL); 236 if (!dwc) 237 return -ENOMEM; 238 239 dwc->dwc3 = platform_device_alloc("dwc3", PLATFORM_DEVID_AUTO); 240 if (!dwc->dwc3) 241 return -ENOMEM; 242 243 memset(res, 0x00, sizeof(struct resource) * ARRAY_SIZE(res)); 244 245 res[0].start = pci_resource_start(pci, 0); 246 res[0].end = pci_resource_end(pci, 0); 247 res[0].name = "dwc_usb3"; 248 res[0].flags = IORESOURCE_MEM; 249 250 res[1].start = pci->irq; 251 res[1].name = "dwc_usb3"; 252 res[1].flags = IORESOURCE_IRQ; 253 254 ret = platform_device_add_resources(dwc->dwc3, res, ARRAY_SIZE(res)); 255 if (ret) { 256 dev_err(dev, "couldn't add resources to dwc3 device\n"); 257 goto err; 258 } 259 260 dwc->pci = pci; 261 dwc->dwc3->dev.parent = dev; 262 ACPI_COMPANION_SET(&dwc->dwc3->dev, ACPI_COMPANION(dev)); 263 264 ret = platform_device_add_properties(dwc->dwc3, p); 265 if (ret < 0) 266 goto err; 267 268 ret = dwc3_pci_quirks(dwc); 269 if (ret) 270 goto err; 271 272 ret = platform_device_add(dwc->dwc3); 273 if (ret) { 274 dev_err(dev, "failed to register dwc3 device\n"); 275 goto err; 276 } 277 278 device_init_wakeup(dev, true); 279 pci_set_drvdata(pci, dwc); 280 pm_runtime_put(dev); 281 #ifdef CONFIG_PM 282 INIT_WORK(&dwc->wakeup_work, dwc3_pci_resume_work); 283 #endif 284 285 return 0; 286 err: 287 platform_device_put(dwc->dwc3); 288 return ret; 289 } 290 291 static void dwc3_pci_remove(struct pci_dev *pci) 292 { 293 struct dwc3_pci *dwc = pci_get_drvdata(pci); 294 struct pci_dev *pdev = dwc->pci; 295 296 if (pdev->device == PCI_DEVICE_ID_INTEL_BYT) 297 gpiod_remove_lookup_table(&platform_bytcr_gpios); 298 #ifdef CONFIG_PM 299 cancel_work_sync(&dwc->wakeup_work); 300 #endif 301 device_init_wakeup(&pci->dev, false); 302 pm_runtime_get(&pci->dev); 303 platform_device_unregister(dwc->dwc3); 304 } 305 306 static const struct pci_device_id dwc3_pci_id_table[] = { 307 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_BSW), 308 (kernel_ulong_t) &dwc3_pci_intel_properties }, 309 310 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_BYT), 311 (kernel_ulong_t) &dwc3_pci_intel_properties, }, 312 313 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_MRFLD), 314 (kernel_ulong_t) &dwc3_pci_mrfld_properties, }, 315 316 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_CMLLP), 317 (kernel_ulong_t) &dwc3_pci_intel_properties, }, 318 319 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_CMLH), 320 (kernel_ulong_t) &dwc3_pci_intel_properties, }, 321 322 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_SPTLP), 323 (kernel_ulong_t) &dwc3_pci_intel_properties, }, 324 325 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_SPTH), 326 (kernel_ulong_t) &dwc3_pci_intel_properties, }, 327 328 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_BXT), 329 (kernel_ulong_t) &dwc3_pci_intel_properties, }, 330 331 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_BXT_M), 332 (kernel_ulong_t) &dwc3_pci_intel_properties, }, 333 334 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_APL), 335 (kernel_ulong_t) &dwc3_pci_intel_properties, }, 336 337 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_KBP), 338 (kernel_ulong_t) &dwc3_pci_intel_properties, }, 339 340 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_GLK), 341 (kernel_ulong_t) &dwc3_pci_intel_properties, }, 342 343 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_CNPLP), 344 (kernel_ulong_t) &dwc3_pci_intel_properties, }, 345 346 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_CNPH), 347 (kernel_ulong_t) &dwc3_pci_intel_properties, }, 348 349 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_CNPV), 350 (kernel_ulong_t) &dwc3_pci_intel_properties, }, 351 352 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ICLLP), 353 (kernel_ulong_t) &dwc3_pci_intel_properties, }, 354 355 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_EHLLP), 356 (kernel_ulong_t) &dwc3_pci_intel_properties, }, 357 358 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_TGPLP), 359 (kernel_ulong_t) &dwc3_pci_intel_properties, }, 360 361 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_NL_USB), 362 (kernel_ulong_t) &dwc3_pci_amd_properties, }, 363 { } /* Terminating Entry */ 364 }; 365 MODULE_DEVICE_TABLE(pci, dwc3_pci_id_table); 366 367 #if defined(CONFIG_PM) || defined(CONFIG_PM_SLEEP) 368 static int dwc3_pci_dsm(struct dwc3_pci *dwc, int param) 369 { 370 union acpi_object *obj; 371 union acpi_object tmp; 372 union acpi_object argv4 = ACPI_INIT_DSM_ARGV4(1, &tmp); 373 374 if (!dwc->has_dsm_for_pm) 375 return 0; 376 377 tmp.type = ACPI_TYPE_INTEGER; 378 tmp.integer.value = param; 379 380 obj = acpi_evaluate_dsm(ACPI_HANDLE(&dwc->pci->dev), &dwc->guid, 381 1, PCI_INTEL_BXT_FUNC_PMU_PWR, &argv4); 382 if (!obj) { 383 dev_err(&dwc->pci->dev, "failed to evaluate _DSM\n"); 384 return -EIO; 385 } 386 387 ACPI_FREE(obj); 388 389 return 0; 390 } 391 #endif /* CONFIG_PM || CONFIG_PM_SLEEP */ 392 393 #ifdef CONFIG_PM 394 static int dwc3_pci_runtime_suspend(struct device *dev) 395 { 396 struct dwc3_pci *dwc = dev_get_drvdata(dev); 397 398 if (device_can_wakeup(dev)) 399 return dwc3_pci_dsm(dwc, PCI_INTEL_BXT_STATE_D3); 400 401 return -EBUSY; 402 } 403 404 static int dwc3_pci_runtime_resume(struct device *dev) 405 { 406 struct dwc3_pci *dwc = dev_get_drvdata(dev); 407 int ret; 408 409 ret = dwc3_pci_dsm(dwc, PCI_INTEL_BXT_STATE_D0); 410 if (ret) 411 return ret; 412 413 queue_work(pm_wq, &dwc->wakeup_work); 414 415 return 0; 416 } 417 #endif /* CONFIG_PM */ 418 419 #ifdef CONFIG_PM_SLEEP 420 static int dwc3_pci_suspend(struct device *dev) 421 { 422 struct dwc3_pci *dwc = dev_get_drvdata(dev); 423 424 return dwc3_pci_dsm(dwc, PCI_INTEL_BXT_STATE_D3); 425 } 426 427 static int dwc3_pci_resume(struct device *dev) 428 { 429 struct dwc3_pci *dwc = dev_get_drvdata(dev); 430 431 return dwc3_pci_dsm(dwc, PCI_INTEL_BXT_STATE_D0); 432 } 433 #endif /* CONFIG_PM_SLEEP */ 434 435 static const struct dev_pm_ops dwc3_pci_dev_pm_ops = { 436 SET_SYSTEM_SLEEP_PM_OPS(dwc3_pci_suspend, dwc3_pci_resume) 437 SET_RUNTIME_PM_OPS(dwc3_pci_runtime_suspend, dwc3_pci_runtime_resume, 438 NULL) 439 }; 440 441 static struct pci_driver dwc3_pci_driver = { 442 .name = "dwc3-pci", 443 .id_table = dwc3_pci_id_table, 444 .probe = dwc3_pci_probe, 445 .remove = dwc3_pci_remove, 446 .driver = { 447 .pm = &dwc3_pci_dev_pm_ops, 448 } 449 }; 450 451 MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>"); 452 MODULE_LICENSE("GPL v2"); 453 MODULE_DESCRIPTION("DesignWare USB3 PCI Glue Layer"); 454 455 module_pci_driver(dwc3_pci_driver); 456