1 // SPDX-License-Identifier: GPL-2.0 2 /** 3 * dwc3-pci.c - PCI Specific glue layer 4 * 5 * Copyright (C) 2010-2011 Texas Instruments Incorporated - https://www.ti.com 6 * 7 * Authors: Felipe Balbi <balbi@ti.com>, 8 * Sebastian Andrzej Siewior <bigeasy@linutronix.de> 9 */ 10 11 #include <linux/kernel.h> 12 #include <linux/module.h> 13 #include <linux/slab.h> 14 #include <linux/pci.h> 15 #include <linux/workqueue.h> 16 #include <linux/pm_runtime.h> 17 #include <linux/platform_device.h> 18 #include <linux/gpio/consumer.h> 19 #include <linux/gpio/machine.h> 20 #include <linux/acpi.h> 21 #include <linux/delay.h> 22 23 #define PCI_DEVICE_ID_INTEL_BYT 0x0f37 24 #define PCI_DEVICE_ID_INTEL_MRFLD 0x119e 25 #define PCI_DEVICE_ID_INTEL_BSW 0x22b7 26 #define PCI_DEVICE_ID_INTEL_SPTLP 0x9d30 27 #define PCI_DEVICE_ID_INTEL_SPTH 0xa130 28 #define PCI_DEVICE_ID_INTEL_BXT 0x0aaa 29 #define PCI_DEVICE_ID_INTEL_BXT_M 0x1aaa 30 #define PCI_DEVICE_ID_INTEL_APL 0x5aaa 31 #define PCI_DEVICE_ID_INTEL_KBP 0xa2b0 32 #define PCI_DEVICE_ID_INTEL_CMLLP 0x02ee 33 #define PCI_DEVICE_ID_INTEL_CMLH 0x06ee 34 #define PCI_DEVICE_ID_INTEL_GLK 0x31aa 35 #define PCI_DEVICE_ID_INTEL_CNPLP 0x9dee 36 #define PCI_DEVICE_ID_INTEL_CNPH 0xa36e 37 #define PCI_DEVICE_ID_INTEL_CNPV 0xa3b0 38 #define PCI_DEVICE_ID_INTEL_ICLLP 0x34ee 39 #define PCI_DEVICE_ID_INTEL_EHLLP 0x4b7e 40 #define PCI_DEVICE_ID_INTEL_TGPLP 0xa0ee 41 #define PCI_DEVICE_ID_INTEL_TGPH 0x43ee 42 #define PCI_DEVICE_ID_INTEL_JSP 0x4dee 43 #define PCI_DEVICE_ID_INTEL_ADLP 0x51ee 44 #define PCI_DEVICE_ID_INTEL_ADLS 0x7ae1 45 #define PCI_DEVICE_ID_INTEL_TGL 0x9a15 46 47 #define PCI_INTEL_BXT_DSM_GUID "732b85d5-b7a7-4a1b-9ba0-4bbd00ffd511" 48 #define PCI_INTEL_BXT_FUNC_PMU_PWR 4 49 #define PCI_INTEL_BXT_STATE_D0 0 50 #define PCI_INTEL_BXT_STATE_D3 3 51 52 #define GP_RWBAR 1 53 #define GP_RWREG1 0xa0 54 #define GP_RWREG1_ULPI_REFCLK_DISABLE (1 << 17) 55 56 /** 57 * struct dwc3_pci - Driver private structure 58 * @dwc3: child dwc3 platform_device 59 * @pci: our link to PCI bus 60 * @guid: _DSM GUID 61 * @has_dsm_for_pm: true for devices which need to run _DSM on runtime PM 62 * @wakeup_work: work for asynchronous resume 63 */ 64 struct dwc3_pci { 65 struct platform_device *dwc3; 66 struct pci_dev *pci; 67 68 guid_t guid; 69 70 unsigned int has_dsm_for_pm:1; 71 struct work_struct wakeup_work; 72 }; 73 74 static const struct acpi_gpio_params reset_gpios = { 0, 0, false }; 75 static const struct acpi_gpio_params cs_gpios = { 1, 0, false }; 76 77 static const struct acpi_gpio_mapping acpi_dwc3_byt_gpios[] = { 78 { "reset-gpios", &reset_gpios, 1 }, 79 { "cs-gpios", &cs_gpios, 1 }, 80 { }, 81 }; 82 83 static struct gpiod_lookup_table platform_bytcr_gpios = { 84 .dev_id = "0000:00:16.0", 85 .table = { 86 GPIO_LOOKUP("INT33FC:00", 54, "reset", GPIO_ACTIVE_HIGH), 87 GPIO_LOOKUP("INT33FC:02", 14, "cs", GPIO_ACTIVE_HIGH), 88 {} 89 }, 90 }; 91 92 static int dwc3_byt_enable_ulpi_refclock(struct pci_dev *pci) 93 { 94 void __iomem *reg; 95 u32 value; 96 97 reg = pcim_iomap(pci, GP_RWBAR, 0); 98 if (!reg) 99 return -ENOMEM; 100 101 value = readl(reg + GP_RWREG1); 102 if (!(value & GP_RWREG1_ULPI_REFCLK_DISABLE)) 103 goto unmap; /* ULPI refclk already enabled */ 104 105 value &= ~GP_RWREG1_ULPI_REFCLK_DISABLE; 106 writel(value, reg + GP_RWREG1); 107 /* This comes from the Intel Android x86 tree w/o any explanation */ 108 msleep(100); 109 unmap: 110 pcim_iounmap(pci, reg); 111 return 0; 112 } 113 114 static const struct property_entry dwc3_pci_intel_properties[] = { 115 PROPERTY_ENTRY_STRING("dr_mode", "peripheral"), 116 PROPERTY_ENTRY_BOOL("linux,sysdev_is_parent"), 117 {} 118 }; 119 120 static const struct property_entry dwc3_pci_mrfld_properties[] = { 121 PROPERTY_ENTRY_STRING("dr_mode", "otg"), 122 PROPERTY_ENTRY_STRING("linux,extcon-name", "mrfld_bcove_pwrsrc"), 123 PROPERTY_ENTRY_BOOL("linux,sysdev_is_parent"), 124 {} 125 }; 126 127 static const struct property_entry dwc3_pci_amd_properties[] = { 128 PROPERTY_ENTRY_BOOL("snps,has-lpm-erratum"), 129 PROPERTY_ENTRY_U8("snps,lpm-nyet-threshold", 0xf), 130 PROPERTY_ENTRY_BOOL("snps,u2exit_lfps_quirk"), 131 PROPERTY_ENTRY_BOOL("snps,u2ss_inp3_quirk"), 132 PROPERTY_ENTRY_BOOL("snps,req_p1p2p3_quirk"), 133 PROPERTY_ENTRY_BOOL("snps,del_p1p2p3_quirk"), 134 PROPERTY_ENTRY_BOOL("snps,del_phy_power_chg_quirk"), 135 PROPERTY_ENTRY_BOOL("snps,lfps_filter_quirk"), 136 PROPERTY_ENTRY_BOOL("snps,rx_detect_poll_quirk"), 137 PROPERTY_ENTRY_BOOL("snps,tx_de_emphasis_quirk"), 138 PROPERTY_ENTRY_U8("snps,tx_de_emphasis", 1), 139 /* FIXME these quirks should be removed when AMD NL tapes out */ 140 PROPERTY_ENTRY_BOOL("snps,disable_scramble_quirk"), 141 PROPERTY_ENTRY_BOOL("snps,dis_u3_susphy_quirk"), 142 PROPERTY_ENTRY_BOOL("snps,dis_u2_susphy_quirk"), 143 PROPERTY_ENTRY_BOOL("linux,sysdev_is_parent"), 144 {} 145 }; 146 147 static const struct software_node dwc3_pci_intel_swnode = { 148 .properties = dwc3_pci_intel_properties, 149 }; 150 151 static const struct software_node dwc3_pci_intel_mrfld_swnode = { 152 .properties = dwc3_pci_mrfld_properties, 153 }; 154 155 static const struct software_node dwc3_pci_amd_swnode = { 156 .properties = dwc3_pci_amd_properties, 157 }; 158 159 static int dwc3_pci_quirks(struct dwc3_pci *dwc) 160 { 161 struct pci_dev *pdev = dwc->pci; 162 163 if (pdev->vendor == PCI_VENDOR_ID_INTEL) { 164 if (pdev->device == PCI_DEVICE_ID_INTEL_BXT || 165 pdev->device == PCI_DEVICE_ID_INTEL_BXT_M || 166 pdev->device == PCI_DEVICE_ID_INTEL_EHLLP) { 167 guid_parse(PCI_INTEL_BXT_DSM_GUID, &dwc->guid); 168 dwc->has_dsm_for_pm = true; 169 } 170 171 if (pdev->device == PCI_DEVICE_ID_INTEL_BYT) { 172 struct gpio_desc *gpio; 173 int ret; 174 175 /* On BYT the FW does not always enable the refclock */ 176 ret = dwc3_byt_enable_ulpi_refclock(pdev); 177 if (ret) 178 return ret; 179 180 ret = devm_acpi_dev_add_driver_gpios(&pdev->dev, 181 acpi_dwc3_byt_gpios); 182 if (ret) 183 dev_dbg(&pdev->dev, "failed to add mapping table\n"); 184 185 /* 186 * A lot of BYT devices lack ACPI resource entries for 187 * the GPIOs, add a fallback mapping to the reference 188 * design GPIOs which all boards seem to use. 189 */ 190 gpiod_add_lookup_table(&platform_bytcr_gpios); 191 192 /* 193 * These GPIOs will turn on the USB2 PHY. Note that we have to 194 * put the gpio descriptors again here because the phy driver 195 * might want to grab them, too. 196 */ 197 gpio = gpiod_get_optional(&pdev->dev, "cs", GPIOD_OUT_LOW); 198 if (IS_ERR(gpio)) 199 return PTR_ERR(gpio); 200 201 gpiod_set_value_cansleep(gpio, 1); 202 gpiod_put(gpio); 203 204 gpio = gpiod_get_optional(&pdev->dev, "reset", GPIOD_OUT_LOW); 205 if (IS_ERR(gpio)) 206 return PTR_ERR(gpio); 207 208 if (gpio) { 209 gpiod_set_value_cansleep(gpio, 1); 210 gpiod_put(gpio); 211 usleep_range(10000, 11000); 212 } 213 } 214 } 215 216 return 0; 217 } 218 219 #ifdef CONFIG_PM 220 static void dwc3_pci_resume_work(struct work_struct *work) 221 { 222 struct dwc3_pci *dwc = container_of(work, struct dwc3_pci, wakeup_work); 223 struct platform_device *dwc3 = dwc->dwc3; 224 int ret; 225 226 ret = pm_runtime_get_sync(&dwc3->dev); 227 if (ret) { 228 pm_runtime_put_sync_autosuspend(&dwc3->dev); 229 return; 230 } 231 232 pm_runtime_mark_last_busy(&dwc3->dev); 233 pm_runtime_put_sync_autosuspend(&dwc3->dev); 234 } 235 #endif 236 237 static int dwc3_pci_probe(struct pci_dev *pci, const struct pci_device_id *id) 238 { 239 struct dwc3_pci *dwc; 240 struct resource res[2]; 241 int ret; 242 struct device *dev = &pci->dev; 243 244 ret = pcim_enable_device(pci); 245 if (ret) { 246 dev_err(dev, "failed to enable pci device\n"); 247 return -ENODEV; 248 } 249 250 pci_set_master(pci); 251 252 dwc = devm_kzalloc(dev, sizeof(*dwc), GFP_KERNEL); 253 if (!dwc) 254 return -ENOMEM; 255 256 dwc->dwc3 = platform_device_alloc("dwc3", PLATFORM_DEVID_AUTO); 257 if (!dwc->dwc3) 258 return -ENOMEM; 259 260 memset(res, 0x00, sizeof(struct resource) * ARRAY_SIZE(res)); 261 262 res[0].start = pci_resource_start(pci, 0); 263 res[0].end = pci_resource_end(pci, 0); 264 res[0].name = "dwc_usb3"; 265 res[0].flags = IORESOURCE_MEM; 266 267 res[1].start = pci->irq; 268 res[1].name = "dwc_usb3"; 269 res[1].flags = IORESOURCE_IRQ; 270 271 ret = platform_device_add_resources(dwc->dwc3, res, ARRAY_SIZE(res)); 272 if (ret) { 273 dev_err(dev, "couldn't add resources to dwc3 device\n"); 274 goto err; 275 } 276 277 dwc->pci = pci; 278 dwc->dwc3->dev.parent = dev; 279 ACPI_COMPANION_SET(&dwc->dwc3->dev, ACPI_COMPANION(dev)); 280 281 ret = device_add_software_node(&dwc->dwc3->dev, (void *)id->driver_data); 282 if (ret < 0) 283 goto err; 284 285 ret = dwc3_pci_quirks(dwc); 286 if (ret) 287 goto err; 288 289 ret = platform_device_add(dwc->dwc3); 290 if (ret) { 291 dev_err(dev, "failed to register dwc3 device\n"); 292 goto err; 293 } 294 295 device_init_wakeup(dev, true); 296 pci_set_drvdata(pci, dwc); 297 pm_runtime_put(dev); 298 #ifdef CONFIG_PM 299 INIT_WORK(&dwc->wakeup_work, dwc3_pci_resume_work); 300 #endif 301 302 return 0; 303 err: 304 device_remove_software_node(&dwc->dwc3->dev); 305 platform_device_put(dwc->dwc3); 306 return ret; 307 } 308 309 static void dwc3_pci_remove(struct pci_dev *pci) 310 { 311 struct dwc3_pci *dwc = pci_get_drvdata(pci); 312 struct pci_dev *pdev = dwc->pci; 313 314 if (pdev->device == PCI_DEVICE_ID_INTEL_BYT) 315 gpiod_remove_lookup_table(&platform_bytcr_gpios); 316 #ifdef CONFIG_PM 317 cancel_work_sync(&dwc->wakeup_work); 318 #endif 319 device_init_wakeup(&pci->dev, false); 320 pm_runtime_get(&pci->dev); 321 device_remove_software_node(&dwc->dwc3->dev); 322 platform_device_unregister(dwc->dwc3); 323 } 324 325 static const struct pci_device_id dwc3_pci_id_table[] = { 326 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_BSW), 327 (kernel_ulong_t) &dwc3_pci_intel_swnode, }, 328 329 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_BYT), 330 (kernel_ulong_t) &dwc3_pci_intel_swnode, }, 331 332 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_MRFLD), 333 (kernel_ulong_t) &dwc3_pci_intel_mrfld_swnode, }, 334 335 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_CMLLP), 336 (kernel_ulong_t) &dwc3_pci_intel_swnode, }, 337 338 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_CMLH), 339 (kernel_ulong_t) &dwc3_pci_intel_swnode, }, 340 341 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_SPTLP), 342 (kernel_ulong_t) &dwc3_pci_intel_swnode, }, 343 344 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_SPTH), 345 (kernel_ulong_t) &dwc3_pci_intel_swnode, }, 346 347 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_BXT), 348 (kernel_ulong_t) &dwc3_pci_intel_swnode, }, 349 350 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_BXT_M), 351 (kernel_ulong_t) &dwc3_pci_intel_swnode, }, 352 353 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_APL), 354 (kernel_ulong_t) &dwc3_pci_intel_swnode, }, 355 356 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_KBP), 357 (kernel_ulong_t) &dwc3_pci_intel_swnode, }, 358 359 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_GLK), 360 (kernel_ulong_t) &dwc3_pci_intel_swnode, }, 361 362 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_CNPLP), 363 (kernel_ulong_t) &dwc3_pci_intel_swnode, }, 364 365 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_CNPH), 366 (kernel_ulong_t) &dwc3_pci_intel_swnode, }, 367 368 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_CNPV), 369 (kernel_ulong_t) &dwc3_pci_intel_swnode, }, 370 371 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ICLLP), 372 (kernel_ulong_t) &dwc3_pci_intel_swnode, }, 373 374 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_EHLLP), 375 (kernel_ulong_t) &dwc3_pci_intel_swnode }, 376 377 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_TGPLP), 378 (kernel_ulong_t) &dwc3_pci_intel_swnode, }, 379 380 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_TGPH), 381 (kernel_ulong_t) &dwc3_pci_intel_swnode, }, 382 383 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_JSP), 384 (kernel_ulong_t) &dwc3_pci_intel_swnode, }, 385 386 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ADLP), 387 (kernel_ulong_t) &dwc3_pci_intel_swnode, }, 388 389 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ADLS), 390 (kernel_ulong_t) &dwc3_pci_intel_swnode, }, 391 392 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_TGL), 393 (kernel_ulong_t) &dwc3_pci_intel_swnode, }, 394 395 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_NL_USB), 396 (kernel_ulong_t) &dwc3_pci_amd_swnode, }, 397 { } /* Terminating Entry */ 398 }; 399 MODULE_DEVICE_TABLE(pci, dwc3_pci_id_table); 400 401 #if defined(CONFIG_PM) || defined(CONFIG_PM_SLEEP) 402 static int dwc3_pci_dsm(struct dwc3_pci *dwc, int param) 403 { 404 union acpi_object *obj; 405 union acpi_object tmp; 406 union acpi_object argv4 = ACPI_INIT_DSM_ARGV4(1, &tmp); 407 408 if (!dwc->has_dsm_for_pm) 409 return 0; 410 411 tmp.type = ACPI_TYPE_INTEGER; 412 tmp.integer.value = param; 413 414 obj = acpi_evaluate_dsm(ACPI_HANDLE(&dwc->pci->dev), &dwc->guid, 415 1, PCI_INTEL_BXT_FUNC_PMU_PWR, &argv4); 416 if (!obj) { 417 dev_err(&dwc->pci->dev, "failed to evaluate _DSM\n"); 418 return -EIO; 419 } 420 421 ACPI_FREE(obj); 422 423 return 0; 424 } 425 #endif /* CONFIG_PM || CONFIG_PM_SLEEP */ 426 427 #ifdef CONFIG_PM 428 static int dwc3_pci_runtime_suspend(struct device *dev) 429 { 430 struct dwc3_pci *dwc = dev_get_drvdata(dev); 431 432 if (device_can_wakeup(dev)) 433 return dwc3_pci_dsm(dwc, PCI_INTEL_BXT_STATE_D3); 434 435 return -EBUSY; 436 } 437 438 static int dwc3_pci_runtime_resume(struct device *dev) 439 { 440 struct dwc3_pci *dwc = dev_get_drvdata(dev); 441 int ret; 442 443 ret = dwc3_pci_dsm(dwc, PCI_INTEL_BXT_STATE_D0); 444 if (ret) 445 return ret; 446 447 queue_work(pm_wq, &dwc->wakeup_work); 448 449 return 0; 450 } 451 #endif /* CONFIG_PM */ 452 453 #ifdef CONFIG_PM_SLEEP 454 static int dwc3_pci_suspend(struct device *dev) 455 { 456 struct dwc3_pci *dwc = dev_get_drvdata(dev); 457 458 return dwc3_pci_dsm(dwc, PCI_INTEL_BXT_STATE_D3); 459 } 460 461 static int dwc3_pci_resume(struct device *dev) 462 { 463 struct dwc3_pci *dwc = dev_get_drvdata(dev); 464 465 return dwc3_pci_dsm(dwc, PCI_INTEL_BXT_STATE_D0); 466 } 467 #endif /* CONFIG_PM_SLEEP */ 468 469 static const struct dev_pm_ops dwc3_pci_dev_pm_ops = { 470 SET_SYSTEM_SLEEP_PM_OPS(dwc3_pci_suspend, dwc3_pci_resume) 471 SET_RUNTIME_PM_OPS(dwc3_pci_runtime_suspend, dwc3_pci_runtime_resume, 472 NULL) 473 }; 474 475 static struct pci_driver dwc3_pci_driver = { 476 .name = "dwc3-pci", 477 .id_table = dwc3_pci_id_table, 478 .probe = dwc3_pci_probe, 479 .remove = dwc3_pci_remove, 480 .driver = { 481 .pm = &dwc3_pci_dev_pm_ops, 482 } 483 }; 484 485 MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>"); 486 MODULE_LICENSE("GPL v2"); 487 MODULE_DESCRIPTION("DesignWare USB3 PCI Glue Layer"); 488 489 module_pci_driver(dwc3_pci_driver); 490