1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * dwc3-pci.c - PCI Specific glue layer 4 * 5 * Copyright (C) 2010-2011 Texas Instruments Incorporated - https://www.ti.com 6 * 7 * Authors: Felipe Balbi <balbi@ti.com>, 8 * Sebastian Andrzej Siewior <bigeasy@linutronix.de> 9 */ 10 11 #include <linux/kernel.h> 12 #include <linux/module.h> 13 #include <linux/slab.h> 14 #include <linux/pci.h> 15 #include <linux/workqueue.h> 16 #include <linux/pm_runtime.h> 17 #include <linux/platform_device.h> 18 #include <linux/gpio/consumer.h> 19 #include <linux/gpio/machine.h> 20 #include <linux/acpi.h> 21 #include <linux/delay.h> 22 23 #define PCI_DEVICE_ID_INTEL_BYT 0x0f37 24 #define PCI_DEVICE_ID_INTEL_MRFLD 0x119e 25 #define PCI_DEVICE_ID_INTEL_BSW 0x22b7 26 #define PCI_DEVICE_ID_INTEL_SPTLP 0x9d30 27 #define PCI_DEVICE_ID_INTEL_SPTH 0xa130 28 #define PCI_DEVICE_ID_INTEL_BXT 0x0aaa 29 #define PCI_DEVICE_ID_INTEL_BXT_M 0x1aaa 30 #define PCI_DEVICE_ID_INTEL_APL 0x5aaa 31 #define PCI_DEVICE_ID_INTEL_KBP 0xa2b0 32 #define PCI_DEVICE_ID_INTEL_CMLLP 0x02ee 33 #define PCI_DEVICE_ID_INTEL_CMLH 0x06ee 34 #define PCI_DEVICE_ID_INTEL_GLK 0x31aa 35 #define PCI_DEVICE_ID_INTEL_CNPLP 0x9dee 36 #define PCI_DEVICE_ID_INTEL_CNPH 0xa36e 37 #define PCI_DEVICE_ID_INTEL_CNPV 0xa3b0 38 #define PCI_DEVICE_ID_INTEL_ICLLP 0x34ee 39 #define PCI_DEVICE_ID_INTEL_EHL 0x4b7e 40 #define PCI_DEVICE_ID_INTEL_TGPLP 0xa0ee 41 #define PCI_DEVICE_ID_INTEL_TGPH 0x43ee 42 #define PCI_DEVICE_ID_INTEL_JSP 0x4dee 43 #define PCI_DEVICE_ID_INTEL_ADL 0x465e 44 #define PCI_DEVICE_ID_INTEL_ADLP 0x51ee 45 #define PCI_DEVICE_ID_INTEL_ADLM 0x54ee 46 #define PCI_DEVICE_ID_INTEL_ADLS 0x7ae1 47 #define PCI_DEVICE_ID_INTEL_RPLS 0x7a61 48 #define PCI_DEVICE_ID_INTEL_TGL 0x9a15 49 #define PCI_DEVICE_ID_AMD_MR 0x163a 50 51 #define PCI_INTEL_BXT_DSM_GUID "732b85d5-b7a7-4a1b-9ba0-4bbd00ffd511" 52 #define PCI_INTEL_BXT_FUNC_PMU_PWR 4 53 #define PCI_INTEL_BXT_STATE_D0 0 54 #define PCI_INTEL_BXT_STATE_D3 3 55 56 #define GP_RWBAR 1 57 #define GP_RWREG1 0xa0 58 #define GP_RWREG1_ULPI_REFCLK_DISABLE (1 << 17) 59 60 /** 61 * struct dwc3_pci - Driver private structure 62 * @dwc3: child dwc3 platform_device 63 * @pci: our link to PCI bus 64 * @guid: _DSM GUID 65 * @has_dsm_for_pm: true for devices which need to run _DSM on runtime PM 66 * @wakeup_work: work for asynchronous resume 67 */ 68 struct dwc3_pci { 69 struct platform_device *dwc3; 70 struct pci_dev *pci; 71 72 guid_t guid; 73 74 unsigned int has_dsm_for_pm:1; 75 struct work_struct wakeup_work; 76 }; 77 78 static const struct acpi_gpio_params reset_gpios = { 0, 0, false }; 79 static const struct acpi_gpio_params cs_gpios = { 1, 0, false }; 80 81 static const struct acpi_gpio_mapping acpi_dwc3_byt_gpios[] = { 82 { "reset-gpios", &reset_gpios, 1 }, 83 { "cs-gpios", &cs_gpios, 1 }, 84 { }, 85 }; 86 87 static struct gpiod_lookup_table platform_bytcr_gpios = { 88 .dev_id = "0000:00:16.0", 89 .table = { 90 GPIO_LOOKUP("INT33FC:00", 54, "cs", GPIO_ACTIVE_HIGH), 91 GPIO_LOOKUP("INT33FC:02", 14, "reset", GPIO_ACTIVE_HIGH), 92 {} 93 }, 94 }; 95 96 static int dwc3_byt_enable_ulpi_refclock(struct pci_dev *pci) 97 { 98 void __iomem *reg; 99 u32 value; 100 101 reg = pcim_iomap(pci, GP_RWBAR, 0); 102 if (!reg) 103 return -ENOMEM; 104 105 value = readl(reg + GP_RWREG1); 106 if (!(value & GP_RWREG1_ULPI_REFCLK_DISABLE)) 107 goto unmap; /* ULPI refclk already enabled */ 108 109 value &= ~GP_RWREG1_ULPI_REFCLK_DISABLE; 110 writel(value, reg + GP_RWREG1); 111 /* This comes from the Intel Android x86 tree w/o any explanation */ 112 msleep(100); 113 unmap: 114 pcim_iounmap(pci, reg); 115 return 0; 116 } 117 118 static const struct property_entry dwc3_pci_intel_properties[] = { 119 PROPERTY_ENTRY_STRING("dr_mode", "peripheral"), 120 PROPERTY_ENTRY_BOOL("linux,sysdev_is_parent"), 121 {} 122 }; 123 124 static const struct property_entry dwc3_pci_intel_phy_charger_detect_properties[] = { 125 PROPERTY_ENTRY_STRING("dr_mode", "peripheral"), 126 PROPERTY_ENTRY_BOOL("snps,dis_u2_susphy_quirk"), 127 PROPERTY_ENTRY_BOOL("linux,phy_charger_detect"), 128 {} 129 }; 130 131 static const struct property_entry dwc3_pci_intel_byt_properties[] = { 132 PROPERTY_ENTRY_STRING("dr_mode", "peripheral"), 133 PROPERTY_ENTRY_BOOL("snps,dis_u2_susphy_quirk"), 134 PROPERTY_ENTRY_BOOL("linux,sysdev_is_parent"), 135 {} 136 }; 137 138 static const struct property_entry dwc3_pci_mrfld_properties[] = { 139 PROPERTY_ENTRY_STRING("dr_mode", "otg"), 140 PROPERTY_ENTRY_STRING("linux,extcon-name", "mrfld_bcove_pwrsrc"), 141 PROPERTY_ENTRY_BOOL("snps,dis_u3_susphy_quirk"), 142 PROPERTY_ENTRY_BOOL("snps,dis_u2_susphy_quirk"), 143 PROPERTY_ENTRY_BOOL("snps,usb2-gadget-lpm-disable"), 144 PROPERTY_ENTRY_BOOL("linux,sysdev_is_parent"), 145 {} 146 }; 147 148 static const struct property_entry dwc3_pci_amd_properties[] = { 149 PROPERTY_ENTRY_BOOL("snps,has-lpm-erratum"), 150 PROPERTY_ENTRY_U8("snps,lpm-nyet-threshold", 0xf), 151 PROPERTY_ENTRY_BOOL("snps,u2exit_lfps_quirk"), 152 PROPERTY_ENTRY_BOOL("snps,u2ss_inp3_quirk"), 153 PROPERTY_ENTRY_BOOL("snps,req_p1p2p3_quirk"), 154 PROPERTY_ENTRY_BOOL("snps,del_p1p2p3_quirk"), 155 PROPERTY_ENTRY_BOOL("snps,del_phy_power_chg_quirk"), 156 PROPERTY_ENTRY_BOOL("snps,lfps_filter_quirk"), 157 PROPERTY_ENTRY_BOOL("snps,rx_detect_poll_quirk"), 158 PROPERTY_ENTRY_BOOL("snps,tx_de_emphasis_quirk"), 159 PROPERTY_ENTRY_U8("snps,tx_de_emphasis", 1), 160 /* FIXME these quirks should be removed when AMD NL tapes out */ 161 PROPERTY_ENTRY_BOOL("snps,disable_scramble_quirk"), 162 PROPERTY_ENTRY_BOOL("snps,dis_u3_susphy_quirk"), 163 PROPERTY_ENTRY_BOOL("snps,dis_u2_susphy_quirk"), 164 PROPERTY_ENTRY_BOOL("linux,sysdev_is_parent"), 165 {} 166 }; 167 168 static const struct property_entry dwc3_pci_mr_properties[] = { 169 PROPERTY_ENTRY_STRING("dr_mode", "otg"), 170 PROPERTY_ENTRY_BOOL("usb-role-switch"), 171 PROPERTY_ENTRY_STRING("role-switch-default-mode", "host"), 172 PROPERTY_ENTRY_BOOL("linux,sysdev_is_parent"), 173 {} 174 }; 175 176 static const struct software_node dwc3_pci_intel_swnode = { 177 .properties = dwc3_pci_intel_properties, 178 }; 179 180 static const struct software_node dwc3_pci_intel_phy_charger_detect_swnode = { 181 .properties = dwc3_pci_intel_phy_charger_detect_properties, 182 }; 183 184 static const struct software_node dwc3_pci_intel_byt_swnode = { 185 .properties = dwc3_pci_intel_byt_properties, 186 }; 187 188 static const struct software_node dwc3_pci_intel_mrfld_swnode = { 189 .properties = dwc3_pci_mrfld_properties, 190 }; 191 192 static const struct software_node dwc3_pci_amd_swnode = { 193 .properties = dwc3_pci_amd_properties, 194 }; 195 196 static const struct software_node dwc3_pci_amd_mr_swnode = { 197 .properties = dwc3_pci_mr_properties, 198 }; 199 200 static int dwc3_pci_quirks(struct dwc3_pci *dwc, 201 const struct software_node *swnode) 202 { 203 struct pci_dev *pdev = dwc->pci; 204 205 if (pdev->vendor == PCI_VENDOR_ID_INTEL) { 206 if (pdev->device == PCI_DEVICE_ID_INTEL_BXT || 207 pdev->device == PCI_DEVICE_ID_INTEL_BXT_M || 208 pdev->device == PCI_DEVICE_ID_INTEL_EHL) { 209 guid_parse(PCI_INTEL_BXT_DSM_GUID, &dwc->guid); 210 dwc->has_dsm_for_pm = true; 211 } 212 213 if (pdev->device == PCI_DEVICE_ID_INTEL_BYT) { 214 struct gpio_desc *gpio; 215 int ret; 216 217 /* On BYT the FW does not always enable the refclock */ 218 ret = dwc3_byt_enable_ulpi_refclock(pdev); 219 if (ret) 220 return ret; 221 222 ret = devm_acpi_dev_add_driver_gpios(&pdev->dev, 223 acpi_dwc3_byt_gpios); 224 if (ret) 225 dev_dbg(&pdev->dev, "failed to add mapping table\n"); 226 227 /* 228 * A lot of BYT devices lack ACPI resource entries for 229 * the GPIOs, add a fallback mapping to the reference 230 * design GPIOs which all boards seem to use. 231 */ 232 gpiod_add_lookup_table(&platform_bytcr_gpios); 233 234 /* 235 * These GPIOs will turn on the USB2 PHY. Note that we have to 236 * put the gpio descriptors again here because the phy driver 237 * might want to grab them, too. 238 */ 239 gpio = gpiod_get_optional(&pdev->dev, "cs", GPIOD_OUT_LOW); 240 if (IS_ERR(gpio)) 241 return PTR_ERR(gpio); 242 243 gpiod_set_value_cansleep(gpio, 1); 244 gpiod_put(gpio); 245 246 gpio = gpiod_get_optional(&pdev->dev, "reset", GPIOD_OUT_LOW); 247 if (IS_ERR(gpio)) 248 return PTR_ERR(gpio); 249 250 if (gpio) { 251 gpiod_set_value_cansleep(gpio, 1); 252 gpiod_put(gpio); 253 usleep_range(10000, 11000); 254 } 255 256 /* 257 * Make the pdev name predictable (only 1 DWC3 on BYT) 258 * and patch the phy dev-name into the lookup table so 259 * that the phy-driver can get the GPIOs. 260 */ 261 dwc->dwc3->id = PLATFORM_DEVID_NONE; 262 platform_bytcr_gpios.dev_id = "dwc3.ulpi"; 263 264 /* 265 * Some Android tablets with a Crystal Cove PMIC 266 * (INT33FD), rely on the TUSB1211 phy for charger 267 * detection. These can be identified by them _not_ 268 * using the standard ACPI battery and ac drivers. 269 */ 270 if (acpi_dev_present("INT33FD", "1", 2) && 271 acpi_quirk_skip_acpi_ac_and_battery()) { 272 dev_info(&pdev->dev, "Using TUSB1211 phy for charger detection\n"); 273 swnode = &dwc3_pci_intel_phy_charger_detect_swnode; 274 } 275 } 276 } 277 278 return device_add_software_node(&dwc->dwc3->dev, swnode); 279 } 280 281 #ifdef CONFIG_PM 282 static void dwc3_pci_resume_work(struct work_struct *work) 283 { 284 struct dwc3_pci *dwc = container_of(work, struct dwc3_pci, wakeup_work); 285 struct platform_device *dwc3 = dwc->dwc3; 286 int ret; 287 288 ret = pm_runtime_get_sync(&dwc3->dev); 289 if (ret) { 290 pm_runtime_put_sync_autosuspend(&dwc3->dev); 291 return; 292 } 293 294 pm_runtime_mark_last_busy(&dwc3->dev); 295 pm_runtime_put_sync_autosuspend(&dwc3->dev); 296 } 297 #endif 298 299 static int dwc3_pci_probe(struct pci_dev *pci, const struct pci_device_id *id) 300 { 301 struct dwc3_pci *dwc; 302 struct resource res[2]; 303 int ret; 304 struct device *dev = &pci->dev; 305 306 ret = pcim_enable_device(pci); 307 if (ret) { 308 dev_err(dev, "failed to enable pci device\n"); 309 return -ENODEV; 310 } 311 312 pci_set_master(pci); 313 314 dwc = devm_kzalloc(dev, sizeof(*dwc), GFP_KERNEL); 315 if (!dwc) 316 return -ENOMEM; 317 318 dwc->dwc3 = platform_device_alloc("dwc3", PLATFORM_DEVID_AUTO); 319 if (!dwc->dwc3) 320 return -ENOMEM; 321 322 memset(res, 0x00, sizeof(struct resource) * ARRAY_SIZE(res)); 323 324 res[0].start = pci_resource_start(pci, 0); 325 res[0].end = pci_resource_end(pci, 0); 326 res[0].name = "dwc_usb3"; 327 res[0].flags = IORESOURCE_MEM; 328 329 res[1].start = pci->irq; 330 res[1].name = "dwc_usb3"; 331 res[1].flags = IORESOURCE_IRQ; 332 333 ret = platform_device_add_resources(dwc->dwc3, res, ARRAY_SIZE(res)); 334 if (ret) { 335 dev_err(dev, "couldn't add resources to dwc3 device\n"); 336 goto err; 337 } 338 339 dwc->pci = pci; 340 dwc->dwc3->dev.parent = dev; 341 ACPI_COMPANION_SET(&dwc->dwc3->dev, ACPI_COMPANION(dev)); 342 343 ret = dwc3_pci_quirks(dwc, (void *)id->driver_data); 344 if (ret) 345 goto err; 346 347 ret = platform_device_add(dwc->dwc3); 348 if (ret) { 349 dev_err(dev, "failed to register dwc3 device\n"); 350 goto err; 351 } 352 353 device_init_wakeup(dev, true); 354 pci_set_drvdata(pci, dwc); 355 pm_runtime_put(dev); 356 #ifdef CONFIG_PM 357 INIT_WORK(&dwc->wakeup_work, dwc3_pci_resume_work); 358 #endif 359 360 return 0; 361 err: 362 device_remove_software_node(&dwc->dwc3->dev); 363 platform_device_put(dwc->dwc3); 364 return ret; 365 } 366 367 static void dwc3_pci_remove(struct pci_dev *pci) 368 { 369 struct dwc3_pci *dwc = pci_get_drvdata(pci); 370 struct pci_dev *pdev = dwc->pci; 371 372 if (pdev->device == PCI_DEVICE_ID_INTEL_BYT) 373 gpiod_remove_lookup_table(&platform_bytcr_gpios); 374 #ifdef CONFIG_PM 375 cancel_work_sync(&dwc->wakeup_work); 376 #endif 377 device_init_wakeup(&pci->dev, false); 378 pm_runtime_get(&pci->dev); 379 device_remove_software_node(&dwc->dwc3->dev); 380 platform_device_unregister(dwc->dwc3); 381 } 382 383 static const struct pci_device_id dwc3_pci_id_table[] = { 384 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_BSW), 385 (kernel_ulong_t) &dwc3_pci_intel_swnode, }, 386 387 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_BYT), 388 (kernel_ulong_t) &dwc3_pci_intel_byt_swnode, }, 389 390 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_MRFLD), 391 (kernel_ulong_t) &dwc3_pci_intel_mrfld_swnode, }, 392 393 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_CMLLP), 394 (kernel_ulong_t) &dwc3_pci_intel_swnode, }, 395 396 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_CMLH), 397 (kernel_ulong_t) &dwc3_pci_intel_swnode, }, 398 399 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_SPTLP), 400 (kernel_ulong_t) &dwc3_pci_intel_swnode, }, 401 402 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_SPTH), 403 (kernel_ulong_t) &dwc3_pci_intel_swnode, }, 404 405 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_BXT), 406 (kernel_ulong_t) &dwc3_pci_intel_swnode, }, 407 408 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_BXT_M), 409 (kernel_ulong_t) &dwc3_pci_intel_swnode, }, 410 411 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_APL), 412 (kernel_ulong_t) &dwc3_pci_intel_swnode, }, 413 414 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_KBP), 415 (kernel_ulong_t) &dwc3_pci_intel_swnode, }, 416 417 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_GLK), 418 (kernel_ulong_t) &dwc3_pci_intel_swnode, }, 419 420 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_CNPLP), 421 (kernel_ulong_t) &dwc3_pci_intel_swnode, }, 422 423 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_CNPH), 424 (kernel_ulong_t) &dwc3_pci_intel_swnode, }, 425 426 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_CNPV), 427 (kernel_ulong_t) &dwc3_pci_intel_swnode, }, 428 429 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ICLLP), 430 (kernel_ulong_t) &dwc3_pci_intel_swnode, }, 431 432 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_EHL), 433 (kernel_ulong_t) &dwc3_pci_intel_swnode, }, 434 435 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_TGPLP), 436 (kernel_ulong_t) &dwc3_pci_intel_swnode, }, 437 438 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_TGPH), 439 (kernel_ulong_t) &dwc3_pci_intel_swnode, }, 440 441 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_JSP), 442 (kernel_ulong_t) &dwc3_pci_intel_swnode, }, 443 444 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ADL), 445 (kernel_ulong_t) &dwc3_pci_intel_swnode, }, 446 447 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ADLP), 448 (kernel_ulong_t) &dwc3_pci_intel_swnode, }, 449 450 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ADLM), 451 (kernel_ulong_t) &dwc3_pci_intel_swnode, }, 452 453 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ADLS), 454 (kernel_ulong_t) &dwc3_pci_intel_swnode, }, 455 456 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_RPLS), 457 (kernel_ulong_t) &dwc3_pci_intel_swnode, }, 458 459 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_TGL), 460 (kernel_ulong_t) &dwc3_pci_intel_swnode, }, 461 462 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_NL_USB), 463 (kernel_ulong_t) &dwc3_pci_amd_swnode, }, 464 465 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_MR), 466 (kernel_ulong_t)&dwc3_pci_amd_mr_swnode, }, 467 468 { } /* Terminating Entry */ 469 }; 470 MODULE_DEVICE_TABLE(pci, dwc3_pci_id_table); 471 472 #if defined(CONFIG_PM) || defined(CONFIG_PM_SLEEP) 473 static int dwc3_pci_dsm(struct dwc3_pci *dwc, int param) 474 { 475 union acpi_object *obj; 476 union acpi_object tmp; 477 union acpi_object argv4 = ACPI_INIT_DSM_ARGV4(1, &tmp); 478 479 if (!dwc->has_dsm_for_pm) 480 return 0; 481 482 tmp.type = ACPI_TYPE_INTEGER; 483 tmp.integer.value = param; 484 485 obj = acpi_evaluate_dsm(ACPI_HANDLE(&dwc->pci->dev), &dwc->guid, 486 1, PCI_INTEL_BXT_FUNC_PMU_PWR, &argv4); 487 if (!obj) { 488 dev_err(&dwc->pci->dev, "failed to evaluate _DSM\n"); 489 return -EIO; 490 } 491 492 ACPI_FREE(obj); 493 494 return 0; 495 } 496 #endif /* CONFIG_PM || CONFIG_PM_SLEEP */ 497 498 #ifdef CONFIG_PM 499 static int dwc3_pci_runtime_suspend(struct device *dev) 500 { 501 struct dwc3_pci *dwc = dev_get_drvdata(dev); 502 503 if (device_can_wakeup(dev)) 504 return dwc3_pci_dsm(dwc, PCI_INTEL_BXT_STATE_D3); 505 506 return -EBUSY; 507 } 508 509 static int dwc3_pci_runtime_resume(struct device *dev) 510 { 511 struct dwc3_pci *dwc = dev_get_drvdata(dev); 512 int ret; 513 514 ret = dwc3_pci_dsm(dwc, PCI_INTEL_BXT_STATE_D0); 515 if (ret) 516 return ret; 517 518 queue_work(pm_wq, &dwc->wakeup_work); 519 520 return 0; 521 } 522 #endif /* CONFIG_PM */ 523 524 #ifdef CONFIG_PM_SLEEP 525 static int dwc3_pci_suspend(struct device *dev) 526 { 527 struct dwc3_pci *dwc = dev_get_drvdata(dev); 528 529 return dwc3_pci_dsm(dwc, PCI_INTEL_BXT_STATE_D3); 530 } 531 532 static int dwc3_pci_resume(struct device *dev) 533 { 534 struct dwc3_pci *dwc = dev_get_drvdata(dev); 535 536 return dwc3_pci_dsm(dwc, PCI_INTEL_BXT_STATE_D0); 537 } 538 #endif /* CONFIG_PM_SLEEP */ 539 540 static const struct dev_pm_ops dwc3_pci_dev_pm_ops = { 541 SET_SYSTEM_SLEEP_PM_OPS(dwc3_pci_suspend, dwc3_pci_resume) 542 SET_RUNTIME_PM_OPS(dwc3_pci_runtime_suspend, dwc3_pci_runtime_resume, 543 NULL) 544 }; 545 546 static struct pci_driver dwc3_pci_driver = { 547 .name = "dwc3-pci", 548 .id_table = dwc3_pci_id_table, 549 .probe = dwc3_pci_probe, 550 .remove = dwc3_pci_remove, 551 .driver = { 552 .pm = &dwc3_pci_dev_pm_ops, 553 } 554 }; 555 556 MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>"); 557 MODULE_LICENSE("GPL v2"); 558 MODULE_DESCRIPTION("DesignWare USB3 PCI Glue Layer"); 559 560 module_pci_driver(dwc3_pci_driver); 561