1 /** 2 * dwc3-omap.c - OMAP Specific Glue layer 3 * 4 * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com 5 * 6 * Authors: Felipe Balbi <balbi@ti.com>, 7 * Sebastian Andrzej Siewior <bigeasy@linutronix.de> 8 * 9 * This program is free software: you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License version 2 of 11 * the License as published by the Free Software Foundation. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 */ 18 19 #include <linux/module.h> 20 #include <linux/kernel.h> 21 #include <linux/slab.h> 22 #include <linux/interrupt.h> 23 #include <linux/platform_device.h> 24 #include <linux/platform_data/dwc3-omap.h> 25 #include <linux/pm_runtime.h> 26 #include <linux/dma-mapping.h> 27 #include <linux/ioport.h> 28 #include <linux/io.h> 29 #include <linux/of.h> 30 #include <linux/of_platform.h> 31 #include <linux/extcon.h> 32 #include <linux/regulator/consumer.h> 33 34 #include <linux/usb/otg.h> 35 36 /* 37 * All these registers belong to OMAP's Wrapper around the 38 * DesignWare USB3 Core. 39 */ 40 41 #define USBOTGSS_REVISION 0x0000 42 #define USBOTGSS_SYSCONFIG 0x0010 43 #define USBOTGSS_IRQ_EOI 0x0020 44 #define USBOTGSS_EOI_OFFSET 0x0008 45 #define USBOTGSS_IRQSTATUS_RAW_0 0x0024 46 #define USBOTGSS_IRQSTATUS_0 0x0028 47 #define USBOTGSS_IRQENABLE_SET_0 0x002c 48 #define USBOTGSS_IRQENABLE_CLR_0 0x0030 49 #define USBOTGSS_IRQ0_OFFSET 0x0004 50 #define USBOTGSS_IRQSTATUS_RAW_1 0x0030 51 #define USBOTGSS_IRQSTATUS_1 0x0034 52 #define USBOTGSS_IRQENABLE_SET_1 0x0038 53 #define USBOTGSS_IRQENABLE_CLR_1 0x003c 54 #define USBOTGSS_IRQSTATUS_RAW_2 0x0040 55 #define USBOTGSS_IRQSTATUS_2 0x0044 56 #define USBOTGSS_IRQENABLE_SET_2 0x0048 57 #define USBOTGSS_IRQENABLE_CLR_2 0x004c 58 #define USBOTGSS_IRQSTATUS_RAW_3 0x0050 59 #define USBOTGSS_IRQSTATUS_3 0x0054 60 #define USBOTGSS_IRQENABLE_SET_3 0x0058 61 #define USBOTGSS_IRQENABLE_CLR_3 0x005c 62 #define USBOTGSS_IRQSTATUS_EOI_MISC 0x0030 63 #define USBOTGSS_IRQSTATUS_RAW_MISC 0x0034 64 #define USBOTGSS_IRQSTATUS_MISC 0x0038 65 #define USBOTGSS_IRQENABLE_SET_MISC 0x003c 66 #define USBOTGSS_IRQENABLE_CLR_MISC 0x0040 67 #define USBOTGSS_IRQMISC_OFFSET 0x03fc 68 #define USBOTGSS_UTMI_OTG_CTRL 0x0080 69 #define USBOTGSS_UTMI_OTG_STATUS 0x0084 70 #define USBOTGSS_UTMI_OTG_OFFSET 0x0480 71 #define USBOTGSS_TXFIFO_DEPTH 0x0508 72 #define USBOTGSS_RXFIFO_DEPTH 0x050c 73 #define USBOTGSS_MMRAM_OFFSET 0x0100 74 #define USBOTGSS_FLADJ 0x0104 75 #define USBOTGSS_DEBUG_CFG 0x0108 76 #define USBOTGSS_DEBUG_DATA 0x010c 77 #define USBOTGSS_DEV_EBC_EN 0x0110 78 #define USBOTGSS_DEBUG_OFFSET 0x0600 79 80 /* SYSCONFIG REGISTER */ 81 #define USBOTGSS_SYSCONFIG_DMADISABLE (1 << 16) 82 83 /* IRQ_EOI REGISTER */ 84 #define USBOTGSS_IRQ_EOI_LINE_NUMBER (1 << 0) 85 86 /* IRQS0 BITS */ 87 #define USBOTGSS_IRQO_COREIRQ_ST (1 << 0) 88 89 /* IRQMISC BITS */ 90 #define USBOTGSS_IRQMISC_DMADISABLECLR (1 << 17) 91 #define USBOTGSS_IRQMISC_OEVT (1 << 16) 92 #define USBOTGSS_IRQMISC_DRVVBUS_RISE (1 << 13) 93 #define USBOTGSS_IRQMISC_CHRGVBUS_RISE (1 << 12) 94 #define USBOTGSS_IRQMISC_DISCHRGVBUS_RISE (1 << 11) 95 #define USBOTGSS_IRQMISC_IDPULLUP_RISE (1 << 8) 96 #define USBOTGSS_IRQMISC_DRVVBUS_FALL (1 << 5) 97 #define USBOTGSS_IRQMISC_CHRGVBUS_FALL (1 << 4) 98 #define USBOTGSS_IRQMISC_DISCHRGVBUS_FALL (1 << 3) 99 #define USBOTGSS_IRQMISC_IDPULLUP_FALL (1 << 0) 100 101 /* UTMI_OTG_CTRL REGISTER */ 102 #define USBOTGSS_UTMI_OTG_CTRL_DRVVBUS (1 << 5) 103 #define USBOTGSS_UTMI_OTG_CTRL_CHRGVBUS (1 << 4) 104 #define USBOTGSS_UTMI_OTG_CTRL_DISCHRGVBUS (1 << 3) 105 #define USBOTGSS_UTMI_OTG_CTRL_IDPULLUP (1 << 0) 106 107 /* UTMI_OTG_STATUS REGISTER */ 108 #define USBOTGSS_UTMI_OTG_STATUS_SW_MODE (1 << 31) 109 #define USBOTGSS_UTMI_OTG_STATUS_POWERPRESENT (1 << 9) 110 #define USBOTGSS_UTMI_OTG_STATUS_TXBITSTUFFENABLE (1 << 8) 111 #define USBOTGSS_UTMI_OTG_STATUS_IDDIG (1 << 4) 112 #define USBOTGSS_UTMI_OTG_STATUS_SESSEND (1 << 3) 113 #define USBOTGSS_UTMI_OTG_STATUS_SESSVALID (1 << 2) 114 #define USBOTGSS_UTMI_OTG_STATUS_VBUSVALID (1 << 1) 115 116 struct dwc3_omap { 117 struct device *dev; 118 119 int irq; 120 void __iomem *base; 121 122 u32 utmi_otg_status; 123 u32 utmi_otg_offset; 124 u32 irqmisc_offset; 125 u32 irq_eoi_offset; 126 u32 debug_offset; 127 u32 irq0_offset; 128 129 u32 dma_status:1; 130 131 struct extcon_specific_cable_nb extcon_vbus_dev; 132 struct extcon_specific_cable_nb extcon_id_dev; 133 struct notifier_block vbus_nb; 134 struct notifier_block id_nb; 135 136 struct regulator *vbus_reg; 137 }; 138 139 enum omap_dwc3_vbus_id_status { 140 OMAP_DWC3_ID_FLOAT, 141 OMAP_DWC3_ID_GROUND, 142 OMAP_DWC3_VBUS_OFF, 143 OMAP_DWC3_VBUS_VALID, 144 }; 145 146 static inline u32 dwc3_omap_readl(void __iomem *base, u32 offset) 147 { 148 return readl(base + offset); 149 } 150 151 static inline void dwc3_omap_writel(void __iomem *base, u32 offset, u32 value) 152 { 153 writel(value, base + offset); 154 } 155 156 static u32 dwc3_omap_read_utmi_status(struct dwc3_omap *omap) 157 { 158 return dwc3_omap_readl(omap->base, USBOTGSS_UTMI_OTG_STATUS + 159 omap->utmi_otg_offset); 160 } 161 162 static void dwc3_omap_write_utmi_status(struct dwc3_omap *omap, u32 value) 163 { 164 dwc3_omap_writel(omap->base, USBOTGSS_UTMI_OTG_STATUS + 165 omap->utmi_otg_offset, value); 166 167 } 168 169 static u32 dwc3_omap_read_irq0_status(struct dwc3_omap *omap) 170 { 171 return dwc3_omap_readl(omap->base, USBOTGSS_IRQSTATUS_0 - 172 omap->irq0_offset); 173 } 174 175 static void dwc3_omap_write_irq0_status(struct dwc3_omap *omap, u32 value) 176 { 177 dwc3_omap_writel(omap->base, USBOTGSS_IRQSTATUS_0 - 178 omap->irq0_offset, value); 179 180 } 181 182 static u32 dwc3_omap_read_irqmisc_status(struct dwc3_omap *omap) 183 { 184 return dwc3_omap_readl(omap->base, USBOTGSS_IRQSTATUS_MISC + 185 omap->irqmisc_offset); 186 } 187 188 static void dwc3_omap_write_irqmisc_status(struct dwc3_omap *omap, u32 value) 189 { 190 dwc3_omap_writel(omap->base, USBOTGSS_IRQSTATUS_MISC + 191 omap->irqmisc_offset, value); 192 193 } 194 195 static void dwc3_omap_write_irqmisc_set(struct dwc3_omap *omap, u32 value) 196 { 197 dwc3_omap_writel(omap->base, USBOTGSS_IRQENABLE_SET_MISC + 198 omap->irqmisc_offset, value); 199 200 } 201 202 static void dwc3_omap_write_irq0_set(struct dwc3_omap *omap, u32 value) 203 { 204 dwc3_omap_writel(omap->base, USBOTGSS_IRQENABLE_SET_0 - 205 omap->irq0_offset, value); 206 } 207 208 static void dwc3_omap_write_irqmisc_clr(struct dwc3_omap *omap, u32 value) 209 { 210 dwc3_omap_writel(omap->base, USBOTGSS_IRQENABLE_CLR_MISC + 211 omap->irqmisc_offset, value); 212 } 213 214 static void dwc3_omap_write_irq0_clr(struct dwc3_omap *omap, u32 value) 215 { 216 dwc3_omap_writel(omap->base, USBOTGSS_IRQENABLE_CLR_0 - 217 omap->irq0_offset, value); 218 } 219 220 static void dwc3_omap_set_mailbox(struct dwc3_omap *omap, 221 enum omap_dwc3_vbus_id_status status) 222 { 223 int ret; 224 u32 val; 225 226 switch (status) { 227 case OMAP_DWC3_ID_GROUND: 228 dev_dbg(omap->dev, "ID GND\n"); 229 230 if (omap->vbus_reg) { 231 ret = regulator_enable(omap->vbus_reg); 232 if (ret) { 233 dev_dbg(omap->dev, "regulator enable failed\n"); 234 return; 235 } 236 } 237 238 val = dwc3_omap_read_utmi_status(omap); 239 val &= ~(USBOTGSS_UTMI_OTG_STATUS_IDDIG 240 | USBOTGSS_UTMI_OTG_STATUS_VBUSVALID 241 | USBOTGSS_UTMI_OTG_STATUS_SESSEND); 242 val |= USBOTGSS_UTMI_OTG_STATUS_SESSVALID 243 | USBOTGSS_UTMI_OTG_STATUS_POWERPRESENT; 244 dwc3_omap_write_utmi_status(omap, val); 245 break; 246 247 case OMAP_DWC3_VBUS_VALID: 248 dev_dbg(omap->dev, "VBUS Connect\n"); 249 250 val = dwc3_omap_read_utmi_status(omap); 251 val &= ~USBOTGSS_UTMI_OTG_STATUS_SESSEND; 252 val |= USBOTGSS_UTMI_OTG_STATUS_IDDIG 253 | USBOTGSS_UTMI_OTG_STATUS_VBUSVALID 254 | USBOTGSS_UTMI_OTG_STATUS_SESSVALID 255 | USBOTGSS_UTMI_OTG_STATUS_POWERPRESENT; 256 dwc3_omap_write_utmi_status(omap, val); 257 break; 258 259 case OMAP_DWC3_ID_FLOAT: 260 if (omap->vbus_reg) 261 regulator_disable(omap->vbus_reg); 262 263 case OMAP_DWC3_VBUS_OFF: 264 dev_dbg(omap->dev, "VBUS Disconnect\n"); 265 266 val = dwc3_omap_read_utmi_status(omap); 267 val &= ~(USBOTGSS_UTMI_OTG_STATUS_SESSVALID 268 | USBOTGSS_UTMI_OTG_STATUS_VBUSVALID 269 | USBOTGSS_UTMI_OTG_STATUS_POWERPRESENT); 270 val |= USBOTGSS_UTMI_OTG_STATUS_SESSEND 271 | USBOTGSS_UTMI_OTG_STATUS_IDDIG; 272 dwc3_omap_write_utmi_status(omap, val); 273 break; 274 275 default: 276 dev_dbg(omap->dev, "invalid state\n"); 277 } 278 } 279 280 static irqreturn_t dwc3_omap_interrupt(int irq, void *_omap) 281 { 282 struct dwc3_omap *omap = _omap; 283 u32 reg; 284 285 reg = dwc3_omap_read_irqmisc_status(omap); 286 287 if (reg & USBOTGSS_IRQMISC_DMADISABLECLR) { 288 dev_dbg(omap->dev, "DMA Disable was Cleared\n"); 289 omap->dma_status = false; 290 } 291 292 if (reg & USBOTGSS_IRQMISC_OEVT) 293 dev_dbg(omap->dev, "OTG Event\n"); 294 295 if (reg & USBOTGSS_IRQMISC_DRVVBUS_RISE) 296 dev_dbg(omap->dev, "DRVVBUS Rise\n"); 297 298 if (reg & USBOTGSS_IRQMISC_CHRGVBUS_RISE) 299 dev_dbg(omap->dev, "CHRGVBUS Rise\n"); 300 301 if (reg & USBOTGSS_IRQMISC_DISCHRGVBUS_RISE) 302 dev_dbg(omap->dev, "DISCHRGVBUS Rise\n"); 303 304 if (reg & USBOTGSS_IRQMISC_IDPULLUP_RISE) 305 dev_dbg(omap->dev, "IDPULLUP Rise\n"); 306 307 if (reg & USBOTGSS_IRQMISC_DRVVBUS_FALL) 308 dev_dbg(omap->dev, "DRVVBUS Fall\n"); 309 310 if (reg & USBOTGSS_IRQMISC_CHRGVBUS_FALL) 311 dev_dbg(omap->dev, "CHRGVBUS Fall\n"); 312 313 if (reg & USBOTGSS_IRQMISC_DISCHRGVBUS_FALL) 314 dev_dbg(omap->dev, "DISCHRGVBUS Fall\n"); 315 316 if (reg & USBOTGSS_IRQMISC_IDPULLUP_FALL) 317 dev_dbg(omap->dev, "IDPULLUP Fall\n"); 318 319 dwc3_omap_write_irqmisc_status(omap, reg); 320 321 reg = dwc3_omap_read_irq0_status(omap); 322 323 dwc3_omap_write_irq0_status(omap, reg); 324 325 return IRQ_HANDLED; 326 } 327 328 static int dwc3_omap_remove_core(struct device *dev, void *c) 329 { 330 struct platform_device *pdev = to_platform_device(dev); 331 332 of_device_unregister(pdev); 333 334 return 0; 335 } 336 337 static void dwc3_omap_enable_irqs(struct dwc3_omap *omap) 338 { 339 u32 reg; 340 341 /* enable all IRQs */ 342 reg = USBOTGSS_IRQO_COREIRQ_ST; 343 dwc3_omap_write_irq0_set(omap, reg); 344 345 reg = (USBOTGSS_IRQMISC_OEVT | 346 USBOTGSS_IRQMISC_DRVVBUS_RISE | 347 USBOTGSS_IRQMISC_CHRGVBUS_RISE | 348 USBOTGSS_IRQMISC_DISCHRGVBUS_RISE | 349 USBOTGSS_IRQMISC_IDPULLUP_RISE | 350 USBOTGSS_IRQMISC_DRVVBUS_FALL | 351 USBOTGSS_IRQMISC_CHRGVBUS_FALL | 352 USBOTGSS_IRQMISC_DISCHRGVBUS_FALL | 353 USBOTGSS_IRQMISC_IDPULLUP_FALL); 354 355 dwc3_omap_write_irqmisc_set(omap, reg); 356 } 357 358 static void dwc3_omap_disable_irqs(struct dwc3_omap *omap) 359 { 360 u32 reg; 361 362 /* disable all IRQs */ 363 reg = USBOTGSS_IRQO_COREIRQ_ST; 364 dwc3_omap_write_irq0_clr(omap, reg); 365 366 reg = (USBOTGSS_IRQMISC_OEVT | 367 USBOTGSS_IRQMISC_DRVVBUS_RISE | 368 USBOTGSS_IRQMISC_CHRGVBUS_RISE | 369 USBOTGSS_IRQMISC_DISCHRGVBUS_RISE | 370 USBOTGSS_IRQMISC_IDPULLUP_RISE | 371 USBOTGSS_IRQMISC_DRVVBUS_FALL | 372 USBOTGSS_IRQMISC_CHRGVBUS_FALL | 373 USBOTGSS_IRQMISC_DISCHRGVBUS_FALL | 374 USBOTGSS_IRQMISC_IDPULLUP_FALL); 375 376 dwc3_omap_write_irqmisc_clr(omap, reg); 377 } 378 379 static u64 dwc3_omap_dma_mask = DMA_BIT_MASK(32); 380 381 static int dwc3_omap_id_notifier(struct notifier_block *nb, 382 unsigned long event, void *ptr) 383 { 384 struct dwc3_omap *omap = container_of(nb, struct dwc3_omap, id_nb); 385 386 if (event) 387 dwc3_omap_set_mailbox(omap, OMAP_DWC3_ID_GROUND); 388 else 389 dwc3_omap_set_mailbox(omap, OMAP_DWC3_ID_FLOAT); 390 391 return NOTIFY_DONE; 392 } 393 394 static int dwc3_omap_vbus_notifier(struct notifier_block *nb, 395 unsigned long event, void *ptr) 396 { 397 struct dwc3_omap *omap = container_of(nb, struct dwc3_omap, vbus_nb); 398 399 if (event) 400 dwc3_omap_set_mailbox(omap, OMAP_DWC3_VBUS_VALID); 401 else 402 dwc3_omap_set_mailbox(omap, OMAP_DWC3_VBUS_OFF); 403 404 return NOTIFY_DONE; 405 } 406 407 static void dwc3_omap_map_offset(struct dwc3_omap *omap) 408 { 409 struct device_node *node = omap->dev->of_node; 410 411 /* 412 * Differentiate between OMAP5 and AM437x. 413 * 414 * For OMAP5(ES2.0) and AM437x wrapper revision is same, even 415 * though there are changes in wrapper register offsets. 416 * 417 * Using dt compatible to differentiate AM437x. 418 */ 419 if (of_device_is_compatible(node, "ti,am437x-dwc3")) { 420 omap->irq_eoi_offset = USBOTGSS_EOI_OFFSET; 421 omap->irq0_offset = USBOTGSS_IRQ0_OFFSET; 422 omap->irqmisc_offset = USBOTGSS_IRQMISC_OFFSET; 423 omap->utmi_otg_offset = USBOTGSS_UTMI_OTG_OFFSET; 424 omap->debug_offset = USBOTGSS_DEBUG_OFFSET; 425 } 426 } 427 428 static void dwc3_omap_set_utmi_mode(struct dwc3_omap *omap) 429 { 430 u32 reg; 431 struct device_node *node = omap->dev->of_node; 432 int utmi_mode = 0; 433 434 reg = dwc3_omap_read_utmi_status(omap); 435 436 of_property_read_u32(node, "utmi-mode", &utmi_mode); 437 438 switch (utmi_mode) { 439 case DWC3_OMAP_UTMI_MODE_SW: 440 reg |= USBOTGSS_UTMI_OTG_STATUS_SW_MODE; 441 break; 442 case DWC3_OMAP_UTMI_MODE_HW: 443 reg &= ~USBOTGSS_UTMI_OTG_STATUS_SW_MODE; 444 break; 445 default: 446 dev_dbg(omap->dev, "UNKNOWN utmi mode %d\n", utmi_mode); 447 } 448 449 dwc3_omap_write_utmi_status(omap, reg); 450 } 451 452 static int dwc3_omap_extcon_register(struct dwc3_omap *omap) 453 { 454 int ret; 455 struct device_node *node = omap->dev->of_node; 456 struct extcon_dev *edev; 457 458 if (of_property_read_bool(node, "extcon")) { 459 edev = extcon_get_edev_by_phandle(omap->dev, 0); 460 if (IS_ERR(edev)) { 461 dev_vdbg(omap->dev, "couldn't get extcon device\n"); 462 return -EPROBE_DEFER; 463 } 464 465 omap->vbus_nb.notifier_call = dwc3_omap_vbus_notifier; 466 ret = extcon_register_interest(&omap->extcon_vbus_dev, 467 edev->name, "USB", 468 &omap->vbus_nb); 469 if (ret < 0) 470 dev_vdbg(omap->dev, "failed to register notifier for USB\n"); 471 472 omap->id_nb.notifier_call = dwc3_omap_id_notifier; 473 ret = extcon_register_interest(&omap->extcon_id_dev, 474 edev->name, "USB-HOST", 475 &omap->id_nb); 476 if (ret < 0) 477 dev_vdbg(omap->dev, "failed to register notifier for USB-HOST\n"); 478 479 if (extcon_get_cable_state(edev, "USB") == true) 480 dwc3_omap_set_mailbox(omap, OMAP_DWC3_VBUS_VALID); 481 if (extcon_get_cable_state(edev, "USB-HOST") == true) 482 dwc3_omap_set_mailbox(omap, OMAP_DWC3_ID_GROUND); 483 } 484 485 return 0; 486 } 487 488 static int dwc3_omap_probe(struct platform_device *pdev) 489 { 490 struct device_node *node = pdev->dev.of_node; 491 492 struct dwc3_omap *omap; 493 struct resource *res; 494 struct device *dev = &pdev->dev; 495 struct regulator *vbus_reg = NULL; 496 497 int ret; 498 int irq; 499 500 u32 reg; 501 502 void __iomem *base; 503 504 if (!node) { 505 dev_err(dev, "device node not found\n"); 506 return -EINVAL; 507 } 508 509 omap = devm_kzalloc(dev, sizeof(*omap), GFP_KERNEL); 510 if (!omap) 511 return -ENOMEM; 512 513 platform_set_drvdata(pdev, omap); 514 515 irq = platform_get_irq(pdev, 0); 516 if (irq < 0) { 517 dev_err(dev, "missing IRQ resource\n"); 518 return -EINVAL; 519 } 520 521 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 522 base = devm_ioremap_resource(dev, res); 523 if (IS_ERR(base)) 524 return PTR_ERR(base); 525 526 if (of_property_read_bool(node, "vbus-supply")) { 527 vbus_reg = devm_regulator_get(dev, "vbus"); 528 if (IS_ERR(vbus_reg)) { 529 dev_err(dev, "vbus init failed\n"); 530 return PTR_ERR(vbus_reg); 531 } 532 } 533 534 omap->dev = dev; 535 omap->irq = irq; 536 omap->base = base; 537 omap->vbus_reg = vbus_reg; 538 dev->dma_mask = &dwc3_omap_dma_mask; 539 540 pm_runtime_enable(dev); 541 ret = pm_runtime_get_sync(dev); 542 if (ret < 0) { 543 dev_err(dev, "get_sync failed with err %d\n", ret); 544 goto err0; 545 } 546 547 dwc3_omap_map_offset(omap); 548 dwc3_omap_set_utmi_mode(omap); 549 550 /* check the DMA Status */ 551 reg = dwc3_omap_readl(omap->base, USBOTGSS_SYSCONFIG); 552 omap->dma_status = !!(reg & USBOTGSS_SYSCONFIG_DMADISABLE); 553 554 ret = devm_request_irq(dev, omap->irq, dwc3_omap_interrupt, 0, 555 "dwc3-omap", omap); 556 if (ret) { 557 dev_err(dev, "failed to request IRQ #%d --> %d\n", 558 omap->irq, ret); 559 goto err1; 560 } 561 562 dwc3_omap_enable_irqs(omap); 563 564 ret = dwc3_omap_extcon_register(omap); 565 if (ret < 0) 566 goto err2; 567 568 ret = of_platform_populate(node, NULL, NULL, dev); 569 if (ret) { 570 dev_err(&pdev->dev, "failed to create dwc3 core\n"); 571 goto err3; 572 } 573 574 return 0; 575 576 err3: 577 if (omap->extcon_vbus_dev.edev) 578 extcon_unregister_interest(&omap->extcon_vbus_dev); 579 if (omap->extcon_id_dev.edev) 580 extcon_unregister_interest(&omap->extcon_id_dev); 581 582 err2: 583 dwc3_omap_disable_irqs(omap); 584 585 err1: 586 pm_runtime_put_sync(dev); 587 588 err0: 589 pm_runtime_disable(dev); 590 591 return ret; 592 } 593 594 static int dwc3_omap_remove(struct platform_device *pdev) 595 { 596 struct dwc3_omap *omap = platform_get_drvdata(pdev); 597 598 if (omap->extcon_vbus_dev.edev) 599 extcon_unregister_interest(&omap->extcon_vbus_dev); 600 if (omap->extcon_id_dev.edev) 601 extcon_unregister_interest(&omap->extcon_id_dev); 602 dwc3_omap_disable_irqs(omap); 603 device_for_each_child(&pdev->dev, NULL, dwc3_omap_remove_core); 604 pm_runtime_put_sync(&pdev->dev); 605 pm_runtime_disable(&pdev->dev); 606 607 return 0; 608 } 609 610 static const struct of_device_id of_dwc3_match[] = { 611 { 612 .compatible = "ti,dwc3" 613 }, 614 { 615 .compatible = "ti,am437x-dwc3" 616 }, 617 { }, 618 }; 619 MODULE_DEVICE_TABLE(of, of_dwc3_match); 620 621 #ifdef CONFIG_PM_SLEEP 622 static int dwc3_omap_suspend(struct device *dev) 623 { 624 struct dwc3_omap *omap = dev_get_drvdata(dev); 625 626 omap->utmi_otg_status = dwc3_omap_read_utmi_status(omap); 627 dwc3_omap_disable_irqs(omap); 628 629 return 0; 630 } 631 632 static int dwc3_omap_resume(struct device *dev) 633 { 634 struct dwc3_omap *omap = dev_get_drvdata(dev); 635 636 dwc3_omap_write_utmi_status(omap, omap->utmi_otg_status); 637 dwc3_omap_enable_irqs(omap); 638 639 pm_runtime_disable(dev); 640 pm_runtime_set_active(dev); 641 pm_runtime_enable(dev); 642 643 return 0; 644 } 645 646 static const struct dev_pm_ops dwc3_omap_dev_pm_ops = { 647 648 SET_SYSTEM_SLEEP_PM_OPS(dwc3_omap_suspend, dwc3_omap_resume) 649 }; 650 651 #define DEV_PM_OPS (&dwc3_omap_dev_pm_ops) 652 #else 653 #define DEV_PM_OPS NULL 654 #endif /* CONFIG_PM_SLEEP */ 655 656 static struct platform_driver dwc3_omap_driver = { 657 .probe = dwc3_omap_probe, 658 .remove = dwc3_omap_remove, 659 .driver = { 660 .name = "omap-dwc3", 661 .of_match_table = of_dwc3_match, 662 .pm = DEV_PM_OPS, 663 }, 664 }; 665 666 module_platform_driver(dwc3_omap_driver); 667 668 MODULE_ALIAS("platform:omap-dwc3"); 669 MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>"); 670 MODULE_LICENSE("GPL v2"); 671 MODULE_DESCRIPTION("DesignWare USB3 OMAP Glue Layer"); 672