1 /** 2 * dwc3-omap.c - OMAP Specific Glue layer 3 * 4 * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com 5 * 6 * Authors: Felipe Balbi <balbi@ti.com>, 7 * Sebastian Andrzej Siewior <bigeasy@linutronix.de> 8 * 9 * This program is free software: you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License version 2 of 11 * the License as published by the Free Software Foundation. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 */ 18 19 #include <linux/module.h> 20 #include <linux/kernel.h> 21 #include <linux/slab.h> 22 #include <linux/interrupt.h> 23 #include <linux/platform_device.h> 24 #include <linux/platform_data/dwc3-omap.h> 25 #include <linux/pm_runtime.h> 26 #include <linux/dma-mapping.h> 27 #include <linux/ioport.h> 28 #include <linux/io.h> 29 #include <linux/of.h> 30 #include <linux/of_platform.h> 31 #include <linux/extcon.h> 32 #include <linux/regulator/consumer.h> 33 34 #include <linux/usb/otg.h> 35 36 /* 37 * All these registers belong to OMAP's Wrapper around the 38 * DesignWare USB3 Core. 39 */ 40 41 #define USBOTGSS_REVISION 0x0000 42 #define USBOTGSS_SYSCONFIG 0x0010 43 #define USBOTGSS_IRQ_EOI 0x0020 44 #define USBOTGSS_EOI_OFFSET 0x0008 45 #define USBOTGSS_IRQSTATUS_RAW_0 0x0024 46 #define USBOTGSS_IRQSTATUS_0 0x0028 47 #define USBOTGSS_IRQENABLE_SET_0 0x002c 48 #define USBOTGSS_IRQENABLE_CLR_0 0x0030 49 #define USBOTGSS_IRQ0_OFFSET 0x0004 50 #define USBOTGSS_IRQSTATUS_RAW_1 0x0030 51 #define USBOTGSS_IRQSTATUS_1 0x0034 52 #define USBOTGSS_IRQENABLE_SET_1 0x0038 53 #define USBOTGSS_IRQENABLE_CLR_1 0x003c 54 #define USBOTGSS_IRQSTATUS_RAW_2 0x0040 55 #define USBOTGSS_IRQSTATUS_2 0x0044 56 #define USBOTGSS_IRQENABLE_SET_2 0x0048 57 #define USBOTGSS_IRQENABLE_CLR_2 0x004c 58 #define USBOTGSS_IRQSTATUS_RAW_3 0x0050 59 #define USBOTGSS_IRQSTATUS_3 0x0054 60 #define USBOTGSS_IRQENABLE_SET_3 0x0058 61 #define USBOTGSS_IRQENABLE_CLR_3 0x005c 62 #define USBOTGSS_IRQSTATUS_EOI_MISC 0x0030 63 #define USBOTGSS_IRQSTATUS_RAW_MISC 0x0034 64 #define USBOTGSS_IRQSTATUS_MISC 0x0038 65 #define USBOTGSS_IRQENABLE_SET_MISC 0x003c 66 #define USBOTGSS_IRQENABLE_CLR_MISC 0x0040 67 #define USBOTGSS_IRQMISC_OFFSET 0x03fc 68 #define USBOTGSS_UTMI_OTG_STATUS 0x0080 69 #define USBOTGSS_UTMI_OTG_CTRL 0x0084 70 #define USBOTGSS_UTMI_OTG_OFFSET 0x0480 71 #define USBOTGSS_TXFIFO_DEPTH 0x0508 72 #define USBOTGSS_RXFIFO_DEPTH 0x050c 73 #define USBOTGSS_MMRAM_OFFSET 0x0100 74 #define USBOTGSS_FLADJ 0x0104 75 #define USBOTGSS_DEBUG_CFG 0x0108 76 #define USBOTGSS_DEBUG_DATA 0x010c 77 #define USBOTGSS_DEV_EBC_EN 0x0110 78 #define USBOTGSS_DEBUG_OFFSET 0x0600 79 80 /* SYSCONFIG REGISTER */ 81 #define USBOTGSS_SYSCONFIG_DMADISABLE (1 << 16) 82 83 /* IRQ_EOI REGISTER */ 84 #define USBOTGSS_IRQ_EOI_LINE_NUMBER (1 << 0) 85 86 /* IRQS0 BITS */ 87 #define USBOTGSS_IRQO_COREIRQ_ST (1 << 0) 88 89 /* IRQMISC BITS */ 90 #define USBOTGSS_IRQMISC_DMADISABLECLR (1 << 17) 91 #define USBOTGSS_IRQMISC_OEVT (1 << 16) 92 #define USBOTGSS_IRQMISC_DRVVBUS_RISE (1 << 13) 93 #define USBOTGSS_IRQMISC_CHRGVBUS_RISE (1 << 12) 94 #define USBOTGSS_IRQMISC_DISCHRGVBUS_RISE (1 << 11) 95 #define USBOTGSS_IRQMISC_IDPULLUP_RISE (1 << 8) 96 #define USBOTGSS_IRQMISC_DRVVBUS_FALL (1 << 5) 97 #define USBOTGSS_IRQMISC_CHRGVBUS_FALL (1 << 4) 98 #define USBOTGSS_IRQMISC_DISCHRGVBUS_FALL (1 << 3) 99 #define USBOTGSS_IRQMISC_IDPULLUP_FALL (1 << 0) 100 101 /* UTMI_OTG_STATUS REGISTER */ 102 #define USBOTGSS_UTMI_OTG_STATUS_DRVVBUS (1 << 5) 103 #define USBOTGSS_UTMI_OTG_STATUS_CHRGVBUS (1 << 4) 104 #define USBOTGSS_UTMI_OTG_STATUS_DISCHRGVBUS (1 << 3) 105 #define USBOTGSS_UTMI_OTG_STATUS_IDPULLUP (1 << 0) 106 107 /* UTMI_OTG_CTRL REGISTER */ 108 #define USBOTGSS_UTMI_OTG_CTRL_SW_MODE (1 << 31) 109 #define USBOTGSS_UTMI_OTG_CTRL_POWERPRESENT (1 << 9) 110 #define USBOTGSS_UTMI_OTG_CTRL_TXBITSTUFFENABLE (1 << 8) 111 #define USBOTGSS_UTMI_OTG_CTRL_IDDIG (1 << 4) 112 #define USBOTGSS_UTMI_OTG_CTRL_SESSEND (1 << 3) 113 #define USBOTGSS_UTMI_OTG_CTRL_SESSVALID (1 << 2) 114 #define USBOTGSS_UTMI_OTG_CTRL_VBUSVALID (1 << 1) 115 116 struct dwc3_omap { 117 struct device *dev; 118 119 int irq; 120 void __iomem *base; 121 122 u32 utmi_otg_ctrl; 123 u32 utmi_otg_offset; 124 u32 irqmisc_offset; 125 u32 irq_eoi_offset; 126 u32 debug_offset; 127 u32 irq0_offset; 128 129 u32 dma_status:1; 130 131 struct extcon_specific_cable_nb extcon_vbus_dev; 132 struct extcon_specific_cable_nb extcon_id_dev; 133 struct notifier_block vbus_nb; 134 struct notifier_block id_nb; 135 136 struct regulator *vbus_reg; 137 }; 138 139 enum omap_dwc3_vbus_id_status { 140 OMAP_DWC3_ID_FLOAT, 141 OMAP_DWC3_ID_GROUND, 142 OMAP_DWC3_VBUS_OFF, 143 OMAP_DWC3_VBUS_VALID, 144 }; 145 146 static inline u32 dwc3_omap_readl(void __iomem *base, u32 offset) 147 { 148 return readl(base + offset); 149 } 150 151 static inline void dwc3_omap_writel(void __iomem *base, u32 offset, u32 value) 152 { 153 writel(value, base + offset); 154 } 155 156 static u32 dwc3_omap_read_utmi_ctrl(struct dwc3_omap *omap) 157 { 158 return dwc3_omap_readl(omap->base, USBOTGSS_UTMI_OTG_CTRL + 159 omap->utmi_otg_offset); 160 } 161 162 static void dwc3_omap_write_utmi_ctrl(struct dwc3_omap *omap, u32 value) 163 { 164 dwc3_omap_writel(omap->base, USBOTGSS_UTMI_OTG_CTRL + 165 omap->utmi_otg_offset, value); 166 167 } 168 169 static u32 dwc3_omap_read_irq0_status(struct dwc3_omap *omap) 170 { 171 return dwc3_omap_readl(omap->base, USBOTGSS_IRQSTATUS_0 - 172 omap->irq0_offset); 173 } 174 175 static void dwc3_omap_write_irq0_status(struct dwc3_omap *omap, u32 value) 176 { 177 dwc3_omap_writel(omap->base, USBOTGSS_IRQSTATUS_0 - 178 omap->irq0_offset, value); 179 180 } 181 182 static u32 dwc3_omap_read_irqmisc_status(struct dwc3_omap *omap) 183 { 184 return dwc3_omap_readl(omap->base, USBOTGSS_IRQSTATUS_MISC + 185 omap->irqmisc_offset); 186 } 187 188 static void dwc3_omap_write_irqmisc_status(struct dwc3_omap *omap, u32 value) 189 { 190 dwc3_omap_writel(omap->base, USBOTGSS_IRQSTATUS_MISC + 191 omap->irqmisc_offset, value); 192 193 } 194 195 static void dwc3_omap_write_irqmisc_set(struct dwc3_omap *omap, u32 value) 196 { 197 dwc3_omap_writel(omap->base, USBOTGSS_IRQENABLE_SET_MISC + 198 omap->irqmisc_offset, value); 199 200 } 201 202 static void dwc3_omap_write_irq0_set(struct dwc3_omap *omap, u32 value) 203 { 204 dwc3_omap_writel(omap->base, USBOTGSS_IRQENABLE_SET_0 - 205 omap->irq0_offset, value); 206 } 207 208 static void dwc3_omap_write_irqmisc_clr(struct dwc3_omap *omap, u32 value) 209 { 210 dwc3_omap_writel(omap->base, USBOTGSS_IRQENABLE_CLR_MISC + 211 omap->irqmisc_offset, value); 212 } 213 214 static void dwc3_omap_write_irq0_clr(struct dwc3_omap *omap, u32 value) 215 { 216 dwc3_omap_writel(omap->base, USBOTGSS_IRQENABLE_CLR_0 - 217 omap->irq0_offset, value); 218 } 219 220 static void dwc3_omap_set_mailbox(struct dwc3_omap *omap, 221 enum omap_dwc3_vbus_id_status status) 222 { 223 int ret; 224 u32 val; 225 226 switch (status) { 227 case OMAP_DWC3_ID_GROUND: 228 dev_dbg(omap->dev, "ID GND\n"); 229 230 if (omap->vbus_reg) { 231 ret = regulator_enable(omap->vbus_reg); 232 if (ret) { 233 dev_dbg(omap->dev, "regulator enable failed\n"); 234 return; 235 } 236 } 237 238 val = dwc3_omap_read_utmi_ctrl(omap); 239 val &= ~(USBOTGSS_UTMI_OTG_CTRL_IDDIG 240 | USBOTGSS_UTMI_OTG_CTRL_VBUSVALID 241 | USBOTGSS_UTMI_OTG_CTRL_SESSEND); 242 val |= USBOTGSS_UTMI_OTG_CTRL_SESSVALID 243 | USBOTGSS_UTMI_OTG_CTRL_POWERPRESENT; 244 dwc3_omap_write_utmi_ctrl(omap, val); 245 break; 246 247 case OMAP_DWC3_VBUS_VALID: 248 dev_dbg(omap->dev, "VBUS Connect\n"); 249 250 val = dwc3_omap_read_utmi_ctrl(omap); 251 val &= ~USBOTGSS_UTMI_OTG_CTRL_SESSEND; 252 val |= USBOTGSS_UTMI_OTG_CTRL_IDDIG 253 | USBOTGSS_UTMI_OTG_CTRL_VBUSVALID 254 | USBOTGSS_UTMI_OTG_CTRL_SESSVALID 255 | USBOTGSS_UTMI_OTG_CTRL_POWERPRESENT; 256 dwc3_omap_write_utmi_ctrl(omap, val); 257 break; 258 259 case OMAP_DWC3_ID_FLOAT: 260 if (omap->vbus_reg) 261 regulator_disable(omap->vbus_reg); 262 263 case OMAP_DWC3_VBUS_OFF: 264 dev_dbg(omap->dev, "VBUS Disconnect\n"); 265 266 val = dwc3_omap_read_utmi_ctrl(omap); 267 val &= ~(USBOTGSS_UTMI_OTG_CTRL_SESSVALID 268 | USBOTGSS_UTMI_OTG_CTRL_VBUSVALID 269 | USBOTGSS_UTMI_OTG_CTRL_POWERPRESENT); 270 val |= USBOTGSS_UTMI_OTG_CTRL_SESSEND 271 | USBOTGSS_UTMI_OTG_CTRL_IDDIG; 272 dwc3_omap_write_utmi_ctrl(omap, val); 273 break; 274 275 default: 276 dev_dbg(omap->dev, "invalid state\n"); 277 } 278 } 279 280 static irqreturn_t dwc3_omap_interrupt(int irq, void *_omap) 281 { 282 struct dwc3_omap *omap = _omap; 283 u32 reg; 284 285 reg = dwc3_omap_read_irqmisc_status(omap); 286 287 if (reg & USBOTGSS_IRQMISC_DMADISABLECLR) { 288 dev_dbg(omap->dev, "DMA Disable was Cleared\n"); 289 omap->dma_status = false; 290 } 291 292 if (reg & USBOTGSS_IRQMISC_OEVT) 293 dev_dbg(omap->dev, "OTG Event\n"); 294 295 if (reg & USBOTGSS_IRQMISC_DRVVBUS_RISE) 296 dev_dbg(omap->dev, "DRVVBUS Rise\n"); 297 298 if (reg & USBOTGSS_IRQMISC_CHRGVBUS_RISE) 299 dev_dbg(omap->dev, "CHRGVBUS Rise\n"); 300 301 if (reg & USBOTGSS_IRQMISC_DISCHRGVBUS_RISE) 302 dev_dbg(omap->dev, "DISCHRGVBUS Rise\n"); 303 304 if (reg & USBOTGSS_IRQMISC_IDPULLUP_RISE) 305 dev_dbg(omap->dev, "IDPULLUP Rise\n"); 306 307 if (reg & USBOTGSS_IRQMISC_DRVVBUS_FALL) 308 dev_dbg(omap->dev, "DRVVBUS Fall\n"); 309 310 if (reg & USBOTGSS_IRQMISC_CHRGVBUS_FALL) 311 dev_dbg(omap->dev, "CHRGVBUS Fall\n"); 312 313 if (reg & USBOTGSS_IRQMISC_DISCHRGVBUS_FALL) 314 dev_dbg(omap->dev, "DISCHRGVBUS Fall\n"); 315 316 if (reg & USBOTGSS_IRQMISC_IDPULLUP_FALL) 317 dev_dbg(omap->dev, "IDPULLUP Fall\n"); 318 319 dwc3_omap_write_irqmisc_status(omap, reg); 320 321 reg = dwc3_omap_read_irq0_status(omap); 322 323 dwc3_omap_write_irq0_status(omap, reg); 324 325 return IRQ_HANDLED; 326 } 327 328 static void dwc3_omap_enable_irqs(struct dwc3_omap *omap) 329 { 330 u32 reg; 331 332 /* enable all IRQs */ 333 reg = USBOTGSS_IRQO_COREIRQ_ST; 334 dwc3_omap_write_irq0_set(omap, reg); 335 336 reg = (USBOTGSS_IRQMISC_OEVT | 337 USBOTGSS_IRQMISC_DRVVBUS_RISE | 338 USBOTGSS_IRQMISC_CHRGVBUS_RISE | 339 USBOTGSS_IRQMISC_DISCHRGVBUS_RISE | 340 USBOTGSS_IRQMISC_IDPULLUP_RISE | 341 USBOTGSS_IRQMISC_DRVVBUS_FALL | 342 USBOTGSS_IRQMISC_CHRGVBUS_FALL | 343 USBOTGSS_IRQMISC_DISCHRGVBUS_FALL | 344 USBOTGSS_IRQMISC_IDPULLUP_FALL); 345 346 dwc3_omap_write_irqmisc_set(omap, reg); 347 } 348 349 static void dwc3_omap_disable_irqs(struct dwc3_omap *omap) 350 { 351 u32 reg; 352 353 /* disable all IRQs */ 354 reg = USBOTGSS_IRQO_COREIRQ_ST; 355 dwc3_omap_write_irq0_clr(omap, reg); 356 357 reg = (USBOTGSS_IRQMISC_OEVT | 358 USBOTGSS_IRQMISC_DRVVBUS_RISE | 359 USBOTGSS_IRQMISC_CHRGVBUS_RISE | 360 USBOTGSS_IRQMISC_DISCHRGVBUS_RISE | 361 USBOTGSS_IRQMISC_IDPULLUP_RISE | 362 USBOTGSS_IRQMISC_DRVVBUS_FALL | 363 USBOTGSS_IRQMISC_CHRGVBUS_FALL | 364 USBOTGSS_IRQMISC_DISCHRGVBUS_FALL | 365 USBOTGSS_IRQMISC_IDPULLUP_FALL); 366 367 dwc3_omap_write_irqmisc_clr(omap, reg); 368 } 369 370 static u64 dwc3_omap_dma_mask = DMA_BIT_MASK(32); 371 372 static int dwc3_omap_id_notifier(struct notifier_block *nb, 373 unsigned long event, void *ptr) 374 { 375 struct dwc3_omap *omap = container_of(nb, struct dwc3_omap, id_nb); 376 377 if (event) 378 dwc3_omap_set_mailbox(omap, OMAP_DWC3_ID_GROUND); 379 else 380 dwc3_omap_set_mailbox(omap, OMAP_DWC3_ID_FLOAT); 381 382 return NOTIFY_DONE; 383 } 384 385 static int dwc3_omap_vbus_notifier(struct notifier_block *nb, 386 unsigned long event, void *ptr) 387 { 388 struct dwc3_omap *omap = container_of(nb, struct dwc3_omap, vbus_nb); 389 390 if (event) 391 dwc3_omap_set_mailbox(omap, OMAP_DWC3_VBUS_VALID); 392 else 393 dwc3_omap_set_mailbox(omap, OMAP_DWC3_VBUS_OFF); 394 395 return NOTIFY_DONE; 396 } 397 398 static void dwc3_omap_map_offset(struct dwc3_omap *omap) 399 { 400 struct device_node *node = omap->dev->of_node; 401 402 /* 403 * Differentiate between OMAP5 and AM437x. 404 * 405 * For OMAP5(ES2.0) and AM437x wrapper revision is same, even 406 * though there are changes in wrapper register offsets. 407 * 408 * Using dt compatible to differentiate AM437x. 409 */ 410 if (of_device_is_compatible(node, "ti,am437x-dwc3")) { 411 omap->irq_eoi_offset = USBOTGSS_EOI_OFFSET; 412 omap->irq0_offset = USBOTGSS_IRQ0_OFFSET; 413 omap->irqmisc_offset = USBOTGSS_IRQMISC_OFFSET; 414 omap->utmi_otg_offset = USBOTGSS_UTMI_OTG_OFFSET; 415 omap->debug_offset = USBOTGSS_DEBUG_OFFSET; 416 } 417 } 418 419 static void dwc3_omap_set_utmi_mode(struct dwc3_omap *omap) 420 { 421 u32 reg; 422 struct device_node *node = omap->dev->of_node; 423 int utmi_mode = 0; 424 425 reg = dwc3_omap_read_utmi_ctrl(omap); 426 427 of_property_read_u32(node, "utmi-mode", &utmi_mode); 428 429 switch (utmi_mode) { 430 case DWC3_OMAP_UTMI_MODE_SW: 431 reg |= USBOTGSS_UTMI_OTG_CTRL_SW_MODE; 432 break; 433 case DWC3_OMAP_UTMI_MODE_HW: 434 reg &= ~USBOTGSS_UTMI_OTG_CTRL_SW_MODE; 435 break; 436 default: 437 dev_dbg(omap->dev, "UNKNOWN utmi mode %d\n", utmi_mode); 438 } 439 440 dwc3_omap_write_utmi_ctrl(omap, reg); 441 } 442 443 static int dwc3_omap_extcon_register(struct dwc3_omap *omap) 444 { 445 int ret; 446 struct device_node *node = omap->dev->of_node; 447 struct extcon_dev *edev; 448 449 if (of_property_read_bool(node, "extcon")) { 450 edev = extcon_get_edev_by_phandle(omap->dev, 0); 451 if (IS_ERR(edev)) { 452 dev_vdbg(omap->dev, "couldn't get extcon device\n"); 453 return -EPROBE_DEFER; 454 } 455 456 omap->vbus_nb.notifier_call = dwc3_omap_vbus_notifier; 457 ret = extcon_register_interest(&omap->extcon_vbus_dev, 458 edev->name, "USB", 459 &omap->vbus_nb); 460 if (ret < 0) 461 dev_vdbg(omap->dev, "failed to register notifier for USB\n"); 462 463 omap->id_nb.notifier_call = dwc3_omap_id_notifier; 464 ret = extcon_register_interest(&omap->extcon_id_dev, 465 edev->name, "USB-HOST", 466 &omap->id_nb); 467 if (ret < 0) 468 dev_vdbg(omap->dev, "failed to register notifier for USB-HOST\n"); 469 470 if (extcon_get_cable_state(edev, "USB") == true) 471 dwc3_omap_set_mailbox(omap, OMAP_DWC3_VBUS_VALID); 472 if (extcon_get_cable_state(edev, "USB-HOST") == true) 473 dwc3_omap_set_mailbox(omap, OMAP_DWC3_ID_GROUND); 474 } 475 476 return 0; 477 } 478 479 static int dwc3_omap_probe(struct platform_device *pdev) 480 { 481 struct device_node *node = pdev->dev.of_node; 482 483 struct dwc3_omap *omap; 484 struct resource *res; 485 struct device *dev = &pdev->dev; 486 struct regulator *vbus_reg = NULL; 487 488 int ret; 489 int irq; 490 491 u32 reg; 492 493 void __iomem *base; 494 495 if (!node) { 496 dev_err(dev, "device node not found\n"); 497 return -EINVAL; 498 } 499 500 omap = devm_kzalloc(dev, sizeof(*omap), GFP_KERNEL); 501 if (!omap) 502 return -ENOMEM; 503 504 platform_set_drvdata(pdev, omap); 505 506 irq = platform_get_irq(pdev, 0); 507 if (irq < 0) { 508 dev_err(dev, "missing IRQ resource\n"); 509 return -EINVAL; 510 } 511 512 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 513 base = devm_ioremap_resource(dev, res); 514 if (IS_ERR(base)) 515 return PTR_ERR(base); 516 517 if (of_property_read_bool(node, "vbus-supply")) { 518 vbus_reg = devm_regulator_get(dev, "vbus"); 519 if (IS_ERR(vbus_reg)) { 520 dev_err(dev, "vbus init failed\n"); 521 return PTR_ERR(vbus_reg); 522 } 523 } 524 525 omap->dev = dev; 526 omap->irq = irq; 527 omap->base = base; 528 omap->vbus_reg = vbus_reg; 529 dev->dma_mask = &dwc3_omap_dma_mask; 530 531 pm_runtime_enable(dev); 532 ret = pm_runtime_get_sync(dev); 533 if (ret < 0) { 534 dev_err(dev, "get_sync failed with err %d\n", ret); 535 goto err0; 536 } 537 538 dwc3_omap_map_offset(omap); 539 dwc3_omap_set_utmi_mode(omap); 540 541 /* check the DMA Status */ 542 reg = dwc3_omap_readl(omap->base, USBOTGSS_SYSCONFIG); 543 omap->dma_status = !!(reg & USBOTGSS_SYSCONFIG_DMADISABLE); 544 545 ret = devm_request_irq(dev, omap->irq, dwc3_omap_interrupt, 0, 546 "dwc3-omap", omap); 547 if (ret) { 548 dev_err(dev, "failed to request IRQ #%d --> %d\n", 549 omap->irq, ret); 550 goto err1; 551 } 552 553 dwc3_omap_enable_irqs(omap); 554 555 ret = dwc3_omap_extcon_register(omap); 556 if (ret < 0) 557 goto err2; 558 559 ret = of_platform_populate(node, NULL, NULL, dev); 560 if (ret) { 561 dev_err(&pdev->dev, "failed to create dwc3 core\n"); 562 goto err3; 563 } 564 565 return 0; 566 567 err3: 568 if (omap->extcon_vbus_dev.edev) 569 extcon_unregister_interest(&omap->extcon_vbus_dev); 570 if (omap->extcon_id_dev.edev) 571 extcon_unregister_interest(&omap->extcon_id_dev); 572 573 err2: 574 dwc3_omap_disable_irqs(omap); 575 576 err1: 577 pm_runtime_put_sync(dev); 578 579 err0: 580 pm_runtime_disable(dev); 581 582 return ret; 583 } 584 585 static int dwc3_omap_remove(struct platform_device *pdev) 586 { 587 struct dwc3_omap *omap = platform_get_drvdata(pdev); 588 589 if (omap->extcon_vbus_dev.edev) 590 extcon_unregister_interest(&omap->extcon_vbus_dev); 591 if (omap->extcon_id_dev.edev) 592 extcon_unregister_interest(&omap->extcon_id_dev); 593 dwc3_omap_disable_irqs(omap); 594 of_platform_depopulate(omap->dev); 595 pm_runtime_put_sync(&pdev->dev); 596 pm_runtime_disable(&pdev->dev); 597 598 return 0; 599 } 600 601 static const struct of_device_id of_dwc3_match[] = { 602 { 603 .compatible = "ti,dwc3" 604 }, 605 { 606 .compatible = "ti,am437x-dwc3" 607 }, 608 { }, 609 }; 610 MODULE_DEVICE_TABLE(of, of_dwc3_match); 611 612 #ifdef CONFIG_PM_SLEEP 613 static int dwc3_omap_suspend(struct device *dev) 614 { 615 struct dwc3_omap *omap = dev_get_drvdata(dev); 616 617 omap->utmi_otg_ctrl = dwc3_omap_read_utmi_ctrl(omap); 618 dwc3_omap_disable_irqs(omap); 619 620 return 0; 621 } 622 623 static int dwc3_omap_resume(struct device *dev) 624 { 625 struct dwc3_omap *omap = dev_get_drvdata(dev); 626 627 dwc3_omap_write_utmi_ctrl(omap, omap->utmi_otg_ctrl); 628 dwc3_omap_enable_irqs(omap); 629 630 pm_runtime_disable(dev); 631 pm_runtime_set_active(dev); 632 pm_runtime_enable(dev); 633 634 return 0; 635 } 636 637 static const struct dev_pm_ops dwc3_omap_dev_pm_ops = { 638 639 SET_SYSTEM_SLEEP_PM_OPS(dwc3_omap_suspend, dwc3_omap_resume) 640 }; 641 642 #define DEV_PM_OPS (&dwc3_omap_dev_pm_ops) 643 #else 644 #define DEV_PM_OPS NULL 645 #endif /* CONFIG_PM_SLEEP */ 646 647 static struct platform_driver dwc3_omap_driver = { 648 .probe = dwc3_omap_probe, 649 .remove = dwc3_omap_remove, 650 .driver = { 651 .name = "omap-dwc3", 652 .of_match_table = of_dwc3_match, 653 .pm = DEV_PM_OPS, 654 }, 655 }; 656 657 module_platform_driver(dwc3_omap_driver); 658 659 MODULE_ALIAS("platform:omap-dwc3"); 660 MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>"); 661 MODULE_LICENSE("GPL v2"); 662 MODULE_DESCRIPTION("DesignWare USB3 OMAP Glue Layer"); 663