1 /** 2 * dwc3-omap.c - OMAP Specific Glue layer 3 * 4 * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com 5 * 6 * Authors: Felipe Balbi <balbi@ti.com>, 7 * Sebastian Andrzej Siewior <bigeasy@linutronix.de> 8 * 9 * This program is free software: you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License version 2 of 11 * the License as published by the Free Software Foundation. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 */ 18 19 #include <linux/module.h> 20 #include <linux/kernel.h> 21 #include <linux/slab.h> 22 #include <linux/interrupt.h> 23 #include <linux/platform_device.h> 24 #include <linux/platform_data/dwc3-omap.h> 25 #include <linux/pm_runtime.h> 26 #include <linux/dma-mapping.h> 27 #include <linux/ioport.h> 28 #include <linux/io.h> 29 #include <linux/of.h> 30 #include <linux/of_platform.h> 31 #include <linux/extcon.h> 32 #include <linux/regulator/consumer.h> 33 34 #include <linux/usb/otg.h> 35 36 /* 37 * All these registers belong to OMAP's Wrapper around the 38 * DesignWare USB3 Core. 39 */ 40 41 #define USBOTGSS_REVISION 0x0000 42 #define USBOTGSS_SYSCONFIG 0x0010 43 #define USBOTGSS_IRQ_EOI 0x0020 44 #define USBOTGSS_EOI_OFFSET 0x0008 45 #define USBOTGSS_IRQSTATUS_RAW_0 0x0024 46 #define USBOTGSS_IRQSTATUS_0 0x0028 47 #define USBOTGSS_IRQENABLE_SET_0 0x002c 48 #define USBOTGSS_IRQENABLE_CLR_0 0x0030 49 #define USBOTGSS_IRQ0_OFFSET 0x0004 50 #define USBOTGSS_IRQSTATUS_RAW_1 0x0030 51 #define USBOTGSS_IRQSTATUS_1 0x0034 52 #define USBOTGSS_IRQENABLE_SET_1 0x0038 53 #define USBOTGSS_IRQENABLE_CLR_1 0x003c 54 #define USBOTGSS_IRQSTATUS_RAW_2 0x0040 55 #define USBOTGSS_IRQSTATUS_2 0x0044 56 #define USBOTGSS_IRQENABLE_SET_2 0x0048 57 #define USBOTGSS_IRQENABLE_CLR_2 0x004c 58 #define USBOTGSS_IRQSTATUS_RAW_3 0x0050 59 #define USBOTGSS_IRQSTATUS_3 0x0054 60 #define USBOTGSS_IRQENABLE_SET_3 0x0058 61 #define USBOTGSS_IRQENABLE_CLR_3 0x005c 62 #define USBOTGSS_IRQSTATUS_EOI_MISC 0x0030 63 #define USBOTGSS_IRQSTATUS_RAW_MISC 0x0034 64 #define USBOTGSS_IRQSTATUS_MISC 0x0038 65 #define USBOTGSS_IRQENABLE_SET_MISC 0x003c 66 #define USBOTGSS_IRQENABLE_CLR_MISC 0x0040 67 #define USBOTGSS_IRQMISC_OFFSET 0x03fc 68 #define USBOTGSS_UTMI_OTG_CTRL 0x0080 69 #define USBOTGSS_UTMI_OTG_STATUS 0x0084 70 #define USBOTGSS_UTMI_OTG_OFFSET 0x0480 71 #define USBOTGSS_TXFIFO_DEPTH 0x0508 72 #define USBOTGSS_RXFIFO_DEPTH 0x050c 73 #define USBOTGSS_MMRAM_OFFSET 0x0100 74 #define USBOTGSS_FLADJ 0x0104 75 #define USBOTGSS_DEBUG_CFG 0x0108 76 #define USBOTGSS_DEBUG_DATA 0x010c 77 #define USBOTGSS_DEV_EBC_EN 0x0110 78 #define USBOTGSS_DEBUG_OFFSET 0x0600 79 80 /* SYSCONFIG REGISTER */ 81 #define USBOTGSS_SYSCONFIG_DMADISABLE (1 << 16) 82 83 /* IRQ_EOI REGISTER */ 84 #define USBOTGSS_IRQ_EOI_LINE_NUMBER (1 << 0) 85 86 /* IRQS0 BITS */ 87 #define USBOTGSS_IRQO_COREIRQ_ST (1 << 0) 88 89 /* IRQMISC BITS */ 90 #define USBOTGSS_IRQMISC_DMADISABLECLR (1 << 17) 91 #define USBOTGSS_IRQMISC_OEVT (1 << 16) 92 #define USBOTGSS_IRQMISC_DRVVBUS_RISE (1 << 13) 93 #define USBOTGSS_IRQMISC_CHRGVBUS_RISE (1 << 12) 94 #define USBOTGSS_IRQMISC_DISCHRGVBUS_RISE (1 << 11) 95 #define USBOTGSS_IRQMISC_IDPULLUP_RISE (1 << 8) 96 #define USBOTGSS_IRQMISC_DRVVBUS_FALL (1 << 5) 97 #define USBOTGSS_IRQMISC_CHRGVBUS_FALL (1 << 4) 98 #define USBOTGSS_IRQMISC_DISCHRGVBUS_FALL (1 << 3) 99 #define USBOTGSS_IRQMISC_IDPULLUP_FALL (1 << 0) 100 101 /* UTMI_OTG_CTRL REGISTER */ 102 #define USBOTGSS_UTMI_OTG_CTRL_DRVVBUS (1 << 5) 103 #define USBOTGSS_UTMI_OTG_CTRL_CHRGVBUS (1 << 4) 104 #define USBOTGSS_UTMI_OTG_CTRL_DISCHRGVBUS (1 << 3) 105 #define USBOTGSS_UTMI_OTG_CTRL_IDPULLUP (1 << 0) 106 107 /* UTMI_OTG_STATUS REGISTER */ 108 #define USBOTGSS_UTMI_OTG_STATUS_SW_MODE (1 << 31) 109 #define USBOTGSS_UTMI_OTG_STATUS_POWERPRESENT (1 << 9) 110 #define USBOTGSS_UTMI_OTG_STATUS_TXBITSTUFFENABLE (1 << 8) 111 #define USBOTGSS_UTMI_OTG_STATUS_IDDIG (1 << 4) 112 #define USBOTGSS_UTMI_OTG_STATUS_SESSEND (1 << 3) 113 #define USBOTGSS_UTMI_OTG_STATUS_SESSVALID (1 << 2) 114 #define USBOTGSS_UTMI_OTG_STATUS_VBUSVALID (1 << 1) 115 116 struct dwc3_omap { 117 struct device *dev; 118 119 int irq; 120 void __iomem *base; 121 122 u32 utmi_otg_status; 123 u32 utmi_otg_offset; 124 u32 irqmisc_offset; 125 u32 irq_eoi_offset; 126 u32 debug_offset; 127 u32 irq0_offset; 128 129 u32 dma_status:1; 130 131 struct extcon_specific_cable_nb extcon_vbus_dev; 132 struct extcon_specific_cable_nb extcon_id_dev; 133 struct notifier_block vbus_nb; 134 struct notifier_block id_nb; 135 136 struct regulator *vbus_reg; 137 }; 138 139 enum omap_dwc3_vbus_id_status { 140 OMAP_DWC3_ID_FLOAT, 141 OMAP_DWC3_ID_GROUND, 142 OMAP_DWC3_VBUS_OFF, 143 OMAP_DWC3_VBUS_VALID, 144 }; 145 146 static inline u32 dwc3_omap_readl(void __iomem *base, u32 offset) 147 { 148 return readl(base + offset); 149 } 150 151 static inline void dwc3_omap_writel(void __iomem *base, u32 offset, u32 value) 152 { 153 writel(value, base + offset); 154 } 155 156 static u32 dwc3_omap_read_utmi_status(struct dwc3_omap *omap) 157 { 158 return dwc3_omap_readl(omap->base, USBOTGSS_UTMI_OTG_STATUS + 159 omap->utmi_otg_offset); 160 } 161 162 static void dwc3_omap_write_utmi_status(struct dwc3_omap *omap, u32 value) 163 { 164 dwc3_omap_writel(omap->base, USBOTGSS_UTMI_OTG_STATUS + 165 omap->utmi_otg_offset, value); 166 167 } 168 169 static u32 dwc3_omap_read_irq0_status(struct dwc3_omap *omap) 170 { 171 return dwc3_omap_readl(omap->base, USBOTGSS_IRQSTATUS_0 - 172 omap->irq0_offset); 173 } 174 175 static void dwc3_omap_write_irq0_status(struct dwc3_omap *omap, u32 value) 176 { 177 dwc3_omap_writel(omap->base, USBOTGSS_IRQSTATUS_0 - 178 omap->irq0_offset, value); 179 180 } 181 182 static u32 dwc3_omap_read_irqmisc_status(struct dwc3_omap *omap) 183 { 184 return dwc3_omap_readl(omap->base, USBOTGSS_IRQSTATUS_MISC + 185 omap->irqmisc_offset); 186 } 187 188 static void dwc3_omap_write_irqmisc_status(struct dwc3_omap *omap, u32 value) 189 { 190 dwc3_omap_writel(omap->base, USBOTGSS_IRQSTATUS_MISC + 191 omap->irqmisc_offset, value); 192 193 } 194 195 static void dwc3_omap_write_irqmisc_set(struct dwc3_omap *omap, u32 value) 196 { 197 dwc3_omap_writel(omap->base, USBOTGSS_IRQENABLE_SET_MISC + 198 omap->irqmisc_offset, value); 199 200 } 201 202 static void dwc3_omap_write_irq0_set(struct dwc3_omap *omap, u32 value) 203 { 204 dwc3_omap_writel(omap->base, USBOTGSS_IRQENABLE_SET_0 - 205 omap->irq0_offset, value); 206 } 207 208 static void dwc3_omap_set_mailbox(struct dwc3_omap *omap, 209 enum omap_dwc3_vbus_id_status status) 210 { 211 int ret; 212 u32 val; 213 214 switch (status) { 215 case OMAP_DWC3_ID_GROUND: 216 dev_dbg(omap->dev, "ID GND\n"); 217 218 if (omap->vbus_reg) { 219 ret = regulator_enable(omap->vbus_reg); 220 if (ret) { 221 dev_dbg(omap->dev, "regulator enable failed\n"); 222 return; 223 } 224 } 225 226 val = dwc3_omap_read_utmi_status(omap); 227 val &= ~(USBOTGSS_UTMI_OTG_STATUS_IDDIG 228 | USBOTGSS_UTMI_OTG_STATUS_VBUSVALID 229 | USBOTGSS_UTMI_OTG_STATUS_SESSEND); 230 val |= USBOTGSS_UTMI_OTG_STATUS_SESSVALID 231 | USBOTGSS_UTMI_OTG_STATUS_POWERPRESENT; 232 dwc3_omap_write_utmi_status(omap, val); 233 break; 234 235 case OMAP_DWC3_VBUS_VALID: 236 dev_dbg(omap->dev, "VBUS Connect\n"); 237 238 val = dwc3_omap_read_utmi_status(omap); 239 val &= ~USBOTGSS_UTMI_OTG_STATUS_SESSEND; 240 val |= USBOTGSS_UTMI_OTG_STATUS_IDDIG 241 | USBOTGSS_UTMI_OTG_STATUS_VBUSVALID 242 | USBOTGSS_UTMI_OTG_STATUS_SESSVALID 243 | USBOTGSS_UTMI_OTG_STATUS_POWERPRESENT; 244 dwc3_omap_write_utmi_status(omap, val); 245 break; 246 247 case OMAP_DWC3_ID_FLOAT: 248 if (omap->vbus_reg) 249 regulator_disable(omap->vbus_reg); 250 251 case OMAP_DWC3_VBUS_OFF: 252 dev_dbg(omap->dev, "VBUS Disconnect\n"); 253 254 val = dwc3_omap_read_utmi_status(omap); 255 val &= ~(USBOTGSS_UTMI_OTG_STATUS_SESSVALID 256 | USBOTGSS_UTMI_OTG_STATUS_VBUSVALID 257 | USBOTGSS_UTMI_OTG_STATUS_POWERPRESENT); 258 val |= USBOTGSS_UTMI_OTG_STATUS_SESSEND 259 | USBOTGSS_UTMI_OTG_STATUS_IDDIG; 260 dwc3_omap_write_utmi_status(omap, val); 261 break; 262 263 default: 264 dev_dbg(omap->dev, "invalid state\n"); 265 } 266 } 267 268 static irqreturn_t dwc3_omap_interrupt(int irq, void *_omap) 269 { 270 struct dwc3_omap *omap = _omap; 271 u32 reg; 272 273 reg = dwc3_omap_read_irqmisc_status(omap); 274 275 if (reg & USBOTGSS_IRQMISC_DMADISABLECLR) { 276 dev_dbg(omap->dev, "DMA Disable was Cleared\n"); 277 omap->dma_status = false; 278 } 279 280 if (reg & USBOTGSS_IRQMISC_OEVT) 281 dev_dbg(omap->dev, "OTG Event\n"); 282 283 if (reg & USBOTGSS_IRQMISC_DRVVBUS_RISE) 284 dev_dbg(omap->dev, "DRVVBUS Rise\n"); 285 286 if (reg & USBOTGSS_IRQMISC_CHRGVBUS_RISE) 287 dev_dbg(omap->dev, "CHRGVBUS Rise\n"); 288 289 if (reg & USBOTGSS_IRQMISC_DISCHRGVBUS_RISE) 290 dev_dbg(omap->dev, "DISCHRGVBUS Rise\n"); 291 292 if (reg & USBOTGSS_IRQMISC_IDPULLUP_RISE) 293 dev_dbg(omap->dev, "IDPULLUP Rise\n"); 294 295 if (reg & USBOTGSS_IRQMISC_DRVVBUS_FALL) 296 dev_dbg(omap->dev, "DRVVBUS Fall\n"); 297 298 if (reg & USBOTGSS_IRQMISC_CHRGVBUS_FALL) 299 dev_dbg(omap->dev, "CHRGVBUS Fall\n"); 300 301 if (reg & USBOTGSS_IRQMISC_DISCHRGVBUS_FALL) 302 dev_dbg(omap->dev, "DISCHRGVBUS Fall\n"); 303 304 if (reg & USBOTGSS_IRQMISC_IDPULLUP_FALL) 305 dev_dbg(omap->dev, "IDPULLUP Fall\n"); 306 307 dwc3_omap_write_irqmisc_status(omap, reg); 308 309 reg = dwc3_omap_read_irq0_status(omap); 310 311 dwc3_omap_write_irq0_status(omap, reg); 312 313 return IRQ_HANDLED; 314 } 315 316 static int dwc3_omap_remove_core(struct device *dev, void *c) 317 { 318 struct platform_device *pdev = to_platform_device(dev); 319 320 of_device_unregister(pdev); 321 322 return 0; 323 } 324 325 static void dwc3_omap_enable_irqs(struct dwc3_omap *omap) 326 { 327 u32 reg; 328 329 /* enable all IRQs */ 330 reg = USBOTGSS_IRQO_COREIRQ_ST; 331 dwc3_omap_write_irq0_set(omap, reg); 332 333 reg = (USBOTGSS_IRQMISC_OEVT | 334 USBOTGSS_IRQMISC_DRVVBUS_RISE | 335 USBOTGSS_IRQMISC_CHRGVBUS_RISE | 336 USBOTGSS_IRQMISC_DISCHRGVBUS_RISE | 337 USBOTGSS_IRQMISC_IDPULLUP_RISE | 338 USBOTGSS_IRQMISC_DRVVBUS_FALL | 339 USBOTGSS_IRQMISC_CHRGVBUS_FALL | 340 USBOTGSS_IRQMISC_DISCHRGVBUS_FALL | 341 USBOTGSS_IRQMISC_IDPULLUP_FALL); 342 343 dwc3_omap_write_irqmisc_set(omap, reg); 344 } 345 346 static void dwc3_omap_disable_irqs(struct dwc3_omap *omap) 347 { 348 /* disable all IRQs */ 349 dwc3_omap_write_irqmisc_set(omap, 0x00); 350 dwc3_omap_write_irq0_set(omap, 0x00); 351 } 352 353 static u64 dwc3_omap_dma_mask = DMA_BIT_MASK(32); 354 355 static int dwc3_omap_id_notifier(struct notifier_block *nb, 356 unsigned long event, void *ptr) 357 { 358 struct dwc3_omap *omap = container_of(nb, struct dwc3_omap, id_nb); 359 360 if (event) 361 dwc3_omap_set_mailbox(omap, OMAP_DWC3_ID_GROUND); 362 else 363 dwc3_omap_set_mailbox(omap, OMAP_DWC3_ID_FLOAT); 364 365 return NOTIFY_DONE; 366 } 367 368 static int dwc3_omap_vbus_notifier(struct notifier_block *nb, 369 unsigned long event, void *ptr) 370 { 371 struct dwc3_omap *omap = container_of(nb, struct dwc3_omap, vbus_nb); 372 373 if (event) 374 dwc3_omap_set_mailbox(omap, OMAP_DWC3_VBUS_VALID); 375 else 376 dwc3_omap_set_mailbox(omap, OMAP_DWC3_VBUS_OFF); 377 378 return NOTIFY_DONE; 379 } 380 381 static void dwc3_omap_map_offset(struct dwc3_omap *omap) 382 { 383 struct device_node *node = omap->dev->of_node; 384 385 /* 386 * Differentiate between OMAP5 and AM437x. 387 * 388 * For OMAP5(ES2.0) and AM437x wrapper revision is same, even 389 * though there are changes in wrapper register offsets. 390 * 391 * Using dt compatible to differentiate AM437x. 392 */ 393 if (of_device_is_compatible(node, "ti,am437x-dwc3")) { 394 omap->irq_eoi_offset = USBOTGSS_EOI_OFFSET; 395 omap->irq0_offset = USBOTGSS_IRQ0_OFFSET; 396 omap->irqmisc_offset = USBOTGSS_IRQMISC_OFFSET; 397 omap->utmi_otg_offset = USBOTGSS_UTMI_OTG_OFFSET; 398 omap->debug_offset = USBOTGSS_DEBUG_OFFSET; 399 } 400 } 401 402 static void dwc3_omap_set_utmi_mode(struct dwc3_omap *omap) 403 { 404 u32 reg; 405 struct device_node *node = omap->dev->of_node; 406 int utmi_mode = 0; 407 408 reg = dwc3_omap_read_utmi_status(omap); 409 410 of_property_read_u32(node, "utmi-mode", &utmi_mode); 411 412 switch (utmi_mode) { 413 case DWC3_OMAP_UTMI_MODE_SW: 414 reg |= USBOTGSS_UTMI_OTG_STATUS_SW_MODE; 415 break; 416 case DWC3_OMAP_UTMI_MODE_HW: 417 reg &= ~USBOTGSS_UTMI_OTG_STATUS_SW_MODE; 418 break; 419 default: 420 dev_dbg(omap->dev, "UNKNOWN utmi mode %d\n", utmi_mode); 421 } 422 423 dwc3_omap_write_utmi_status(omap, reg); 424 } 425 426 static int dwc3_omap_extcon_register(struct dwc3_omap *omap) 427 { 428 int ret; 429 struct device_node *node = omap->dev->of_node; 430 struct extcon_dev *edev; 431 432 if (of_property_read_bool(node, "extcon")) { 433 edev = extcon_get_edev_by_phandle(omap->dev, 0); 434 if (IS_ERR(edev)) { 435 dev_vdbg(omap->dev, "couldn't get extcon device\n"); 436 return -EPROBE_DEFER; 437 } 438 439 omap->vbus_nb.notifier_call = dwc3_omap_vbus_notifier; 440 ret = extcon_register_interest(&omap->extcon_vbus_dev, 441 edev->name, "USB", 442 &omap->vbus_nb); 443 if (ret < 0) 444 dev_vdbg(omap->dev, "failed to register notifier for USB\n"); 445 446 omap->id_nb.notifier_call = dwc3_omap_id_notifier; 447 ret = extcon_register_interest(&omap->extcon_id_dev, 448 edev->name, "USB-HOST", 449 &omap->id_nb); 450 if (ret < 0) 451 dev_vdbg(omap->dev, "failed to register notifier for USB-HOST\n"); 452 453 if (extcon_get_cable_state(edev, "USB") == true) 454 dwc3_omap_set_mailbox(omap, OMAP_DWC3_VBUS_VALID); 455 if (extcon_get_cable_state(edev, "USB-HOST") == true) 456 dwc3_omap_set_mailbox(omap, OMAP_DWC3_ID_GROUND); 457 } 458 459 return 0; 460 } 461 462 static int dwc3_omap_probe(struct platform_device *pdev) 463 { 464 struct device_node *node = pdev->dev.of_node; 465 466 struct dwc3_omap *omap; 467 struct resource *res; 468 struct device *dev = &pdev->dev; 469 struct regulator *vbus_reg = NULL; 470 471 int ret; 472 int irq; 473 474 u32 reg; 475 476 void __iomem *base; 477 478 if (!node) { 479 dev_err(dev, "device node not found\n"); 480 return -EINVAL; 481 } 482 483 omap = devm_kzalloc(dev, sizeof(*omap), GFP_KERNEL); 484 if (!omap) 485 return -ENOMEM; 486 487 platform_set_drvdata(pdev, omap); 488 489 irq = platform_get_irq(pdev, 0); 490 if (irq < 0) { 491 dev_err(dev, "missing IRQ resource\n"); 492 return -EINVAL; 493 } 494 495 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 496 base = devm_ioremap_resource(dev, res); 497 if (IS_ERR(base)) 498 return PTR_ERR(base); 499 500 if (of_property_read_bool(node, "vbus-supply")) { 501 vbus_reg = devm_regulator_get(dev, "vbus"); 502 if (IS_ERR(vbus_reg)) { 503 dev_err(dev, "vbus init failed\n"); 504 return PTR_ERR(vbus_reg); 505 } 506 } 507 508 omap->dev = dev; 509 omap->irq = irq; 510 omap->base = base; 511 omap->vbus_reg = vbus_reg; 512 dev->dma_mask = &dwc3_omap_dma_mask; 513 514 pm_runtime_enable(dev); 515 ret = pm_runtime_get_sync(dev); 516 if (ret < 0) { 517 dev_err(dev, "get_sync failed with err %d\n", ret); 518 goto err0; 519 } 520 521 dwc3_omap_map_offset(omap); 522 dwc3_omap_set_utmi_mode(omap); 523 524 /* check the DMA Status */ 525 reg = dwc3_omap_readl(omap->base, USBOTGSS_SYSCONFIG); 526 omap->dma_status = !!(reg & USBOTGSS_SYSCONFIG_DMADISABLE); 527 528 ret = devm_request_irq(dev, omap->irq, dwc3_omap_interrupt, 0, 529 "dwc3-omap", omap); 530 if (ret) { 531 dev_err(dev, "failed to request IRQ #%d --> %d\n", 532 omap->irq, ret); 533 goto err1; 534 } 535 536 dwc3_omap_enable_irqs(omap); 537 538 ret = dwc3_omap_extcon_register(omap); 539 if (ret < 0) 540 goto err2; 541 542 ret = of_platform_populate(node, NULL, NULL, dev); 543 if (ret) { 544 dev_err(&pdev->dev, "failed to create dwc3 core\n"); 545 goto err3; 546 } 547 548 return 0; 549 550 err3: 551 if (omap->extcon_vbus_dev.edev) 552 extcon_unregister_interest(&omap->extcon_vbus_dev); 553 if (omap->extcon_id_dev.edev) 554 extcon_unregister_interest(&omap->extcon_id_dev); 555 556 err2: 557 dwc3_omap_disable_irqs(omap); 558 559 err1: 560 pm_runtime_put_sync(dev); 561 562 err0: 563 pm_runtime_disable(dev); 564 565 return ret; 566 } 567 568 static int dwc3_omap_remove(struct platform_device *pdev) 569 { 570 struct dwc3_omap *omap = platform_get_drvdata(pdev); 571 572 if (omap->extcon_vbus_dev.edev) 573 extcon_unregister_interest(&omap->extcon_vbus_dev); 574 if (omap->extcon_id_dev.edev) 575 extcon_unregister_interest(&omap->extcon_id_dev); 576 dwc3_omap_disable_irqs(omap); 577 device_for_each_child(&pdev->dev, NULL, dwc3_omap_remove_core); 578 pm_runtime_put_sync(&pdev->dev); 579 pm_runtime_disable(&pdev->dev); 580 581 return 0; 582 } 583 584 static const struct of_device_id of_dwc3_match[] = { 585 { 586 .compatible = "ti,dwc3" 587 }, 588 { 589 .compatible = "ti,am437x-dwc3" 590 }, 591 { }, 592 }; 593 MODULE_DEVICE_TABLE(of, of_dwc3_match); 594 595 #ifdef CONFIG_PM_SLEEP 596 static int dwc3_omap_prepare(struct device *dev) 597 { 598 struct dwc3_omap *omap = dev_get_drvdata(dev); 599 600 dwc3_omap_disable_irqs(omap); 601 602 return 0; 603 } 604 605 static void dwc3_omap_complete(struct device *dev) 606 { 607 struct dwc3_omap *omap = dev_get_drvdata(dev); 608 609 dwc3_omap_enable_irqs(omap); 610 } 611 612 static int dwc3_omap_suspend(struct device *dev) 613 { 614 struct dwc3_omap *omap = dev_get_drvdata(dev); 615 616 omap->utmi_otg_status = dwc3_omap_read_utmi_status(omap); 617 618 return 0; 619 } 620 621 static int dwc3_omap_resume(struct device *dev) 622 { 623 struct dwc3_omap *omap = dev_get_drvdata(dev); 624 625 dwc3_omap_write_utmi_status(omap, omap->utmi_otg_status); 626 627 pm_runtime_disable(dev); 628 pm_runtime_set_active(dev); 629 pm_runtime_enable(dev); 630 631 return 0; 632 } 633 634 static const struct dev_pm_ops dwc3_omap_dev_pm_ops = { 635 .prepare = dwc3_omap_prepare, 636 .complete = dwc3_omap_complete, 637 638 SET_SYSTEM_SLEEP_PM_OPS(dwc3_omap_suspend, dwc3_omap_resume) 639 }; 640 641 #define DEV_PM_OPS (&dwc3_omap_dev_pm_ops) 642 #else 643 #define DEV_PM_OPS NULL 644 #endif /* CONFIG_PM_SLEEP */ 645 646 static struct platform_driver dwc3_omap_driver = { 647 .probe = dwc3_omap_probe, 648 .remove = dwc3_omap_remove, 649 .driver = { 650 .name = "omap-dwc3", 651 .of_match_table = of_dwc3_match, 652 .pm = DEV_PM_OPS, 653 }, 654 }; 655 656 module_platform_driver(dwc3_omap_driver); 657 658 MODULE_ALIAS("platform:omap-dwc3"); 659 MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>"); 660 MODULE_LICENSE("GPL v2"); 661 MODULE_DESCRIPTION("DesignWare USB3 OMAP Glue Layer"); 662