1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * USB Glue for Amlogic G12A SoCs 4 * 5 * Copyright (c) 2019 BayLibre, SAS 6 * Author: Neil Armstrong <narmstrong@baylibre.com> 7 */ 8 9 /* 10 * The USB is organized with a glue around the DWC3 Controller IP as : 11 * - Control registers for each USB2 Ports 12 * - Control registers for the USB PHY layer 13 * - SuperSpeed PHY can be enabled only if port is used 14 * - Dynamic OTG switching with ID change interrupt 15 */ 16 17 #include <linux/module.h> 18 #include <linux/kernel.h> 19 #include <linux/platform_device.h> 20 #include <linux/clk.h> 21 #include <linux/of.h> 22 #include <linux/of_platform.h> 23 #include <linux/pm_runtime.h> 24 #include <linux/regmap.h> 25 #include <linux/bitfield.h> 26 #include <linux/bitops.h> 27 #include <linux/reset.h> 28 #include <linux/phy/phy.h> 29 #include <linux/usb/otg.h> 30 #include <linux/usb/role.h> 31 #include <linux/regulator/consumer.h> 32 33 /* USB2 Ports Control Registers */ 34 35 #define U2P_REG_SIZE 0x20 36 37 #define U2P_R0 0x0 38 #define U2P_R0_HOST_DEVICE BIT(0) 39 #define U2P_R0_POWER_OK BIT(1) 40 #define U2P_R0_HAST_MODE BIT(2) 41 #define U2P_R0_POWER_ON_RESET BIT(3) 42 #define U2P_R0_ID_PULLUP BIT(4) 43 #define U2P_R0_DRV_VBUS BIT(5) 44 45 #define U2P_R1 0x4 46 #define U2P_R1_PHY_READY BIT(0) 47 #define U2P_R1_ID_DIG BIT(1) 48 #define U2P_R1_OTG_SESSION_VALID BIT(2) 49 #define U2P_R1_VBUS_VALID BIT(3) 50 51 /* USB Glue Control Registers */ 52 53 #define USB_R0 0x80 54 #define USB_R0_P30_LANE0_TX2RX_LOOPBACK BIT(17) 55 #define USB_R0_P30_LANE0_EXT_PCLK_REQ BIT(18) 56 #define USB_R0_P30_PCS_RX_LOS_MASK_VAL_MASK GENMASK(28, 19) 57 #define USB_R0_U2D_SS_SCALEDOWN_MODE_MASK GENMASK(30, 29) 58 #define USB_R0_U2D_ACT BIT(31) 59 60 #define USB_R1 0x84 61 #define USB_R1_U3H_BIGENDIAN_GS BIT(0) 62 #define USB_R1_U3H_PME_ENABLE BIT(1) 63 #define USB_R1_U3H_HUB_PORT_OVERCURRENT_MASK GENMASK(4, 2) 64 #define USB_R1_U3H_HUB_PORT_PERM_ATTACH_MASK GENMASK(9, 7) 65 #define USB_R1_U3H_HOST_U2_PORT_DISABLE_MASK GENMASK(13, 12) 66 #define USB_R1_U3H_HOST_U3_PORT_DISABLE BIT(16) 67 #define USB_R1_U3H_HOST_PORT_POWER_CONTROL_PRESENT BIT(17) 68 #define USB_R1_U3H_HOST_MSI_ENABLE BIT(18) 69 #define USB_R1_U3H_FLADJ_30MHZ_REG_MASK GENMASK(24, 19) 70 #define USB_R1_P30_PCS_TX_SWING_FULL_MASK GENMASK(31, 25) 71 72 #define USB_R2 0x88 73 #define USB_R2_P30_PCS_TX_DEEMPH_3P5DB_MASK GENMASK(25, 20) 74 #define USB_R2_P30_PCS_TX_DEEMPH_6DB_MASK GENMASK(31, 26) 75 76 #define USB_R3 0x8c 77 #define USB_R3_P30_SSC_ENABLE BIT(0) 78 #define USB_R3_P30_SSC_RANGE_MASK GENMASK(3, 1) 79 #define USB_R3_P30_SSC_REF_CLK_SEL_MASK GENMASK(12, 4) 80 #define USB_R3_P30_REF_SSP_EN BIT(13) 81 82 #define USB_R4 0x90 83 #define USB_R4_P21_PORT_RESET_0 BIT(0) 84 #define USB_R4_P21_SLEEP_M0 BIT(1) 85 #define USB_R4_MEM_PD_MASK GENMASK(3, 2) 86 #define USB_R4_P21_ONLY BIT(4) 87 88 #define USB_R5 0x94 89 #define USB_R5_ID_DIG_SYNC BIT(0) 90 #define USB_R5_ID_DIG_REG BIT(1) 91 #define USB_R5_ID_DIG_CFG_MASK GENMASK(3, 2) 92 #define USB_R5_ID_DIG_EN_0 BIT(4) 93 #define USB_R5_ID_DIG_EN_1 BIT(5) 94 #define USB_R5_ID_DIG_CURR BIT(6) 95 #define USB_R5_ID_DIG_IRQ BIT(7) 96 #define USB_R5_ID_DIG_TH_MASK GENMASK(15, 8) 97 #define USB_R5_ID_DIG_CNT_MASK GENMASK(23, 16) 98 99 enum { 100 USB2_HOST_PHY = 0, 101 USB2_OTG_PHY, 102 USB3_HOST_PHY, 103 PHY_COUNT, 104 }; 105 106 static const char *phy_names[PHY_COUNT] = { 107 "usb2-phy0", "usb2-phy1", "usb3-phy0", 108 }; 109 110 struct dwc3_meson_g12a { 111 struct device *dev; 112 struct regmap *regmap; 113 struct clk *clk; 114 struct reset_control *reset; 115 struct phy *phys[PHY_COUNT]; 116 enum usb_dr_mode otg_mode; 117 enum phy_mode otg_phy_mode; 118 unsigned int usb2_ports; 119 unsigned int usb3_ports; 120 struct regulator *vbus; 121 struct usb_role_switch_desc switch_desc; 122 struct usb_role_switch *role_switch; 123 }; 124 125 static void dwc3_meson_g12a_usb2_set_mode(struct dwc3_meson_g12a *priv, 126 int i, enum phy_mode mode) 127 { 128 if (mode == PHY_MODE_USB_HOST) 129 regmap_update_bits(priv->regmap, U2P_R0 + (U2P_REG_SIZE * i), 130 U2P_R0_HOST_DEVICE, 131 U2P_R0_HOST_DEVICE); 132 else 133 regmap_update_bits(priv->regmap, U2P_R0 + (U2P_REG_SIZE * i), 134 U2P_R0_HOST_DEVICE, 0); 135 } 136 137 static int dwc3_meson_g12a_usb2_init(struct dwc3_meson_g12a *priv) 138 { 139 int i; 140 141 if (priv->otg_mode == USB_DR_MODE_PERIPHERAL) 142 priv->otg_phy_mode = PHY_MODE_USB_DEVICE; 143 else 144 priv->otg_phy_mode = PHY_MODE_USB_HOST; 145 146 for (i = 0 ; i < USB3_HOST_PHY ; ++i) { 147 if (!priv->phys[i]) 148 continue; 149 150 regmap_update_bits(priv->regmap, U2P_R0 + (U2P_REG_SIZE * i), 151 U2P_R0_POWER_ON_RESET, 152 U2P_R0_POWER_ON_RESET); 153 154 if (i == USB2_OTG_PHY) { 155 regmap_update_bits(priv->regmap, 156 U2P_R0 + (U2P_REG_SIZE * i), 157 U2P_R0_ID_PULLUP | U2P_R0_DRV_VBUS, 158 U2P_R0_ID_PULLUP | U2P_R0_DRV_VBUS); 159 160 dwc3_meson_g12a_usb2_set_mode(priv, i, 161 priv->otg_phy_mode); 162 } else 163 dwc3_meson_g12a_usb2_set_mode(priv, i, 164 PHY_MODE_USB_HOST); 165 166 regmap_update_bits(priv->regmap, U2P_R0 + (U2P_REG_SIZE * i), 167 U2P_R0_POWER_ON_RESET, 0); 168 } 169 170 return 0; 171 } 172 173 static void dwc3_meson_g12a_usb3_init(struct dwc3_meson_g12a *priv) 174 { 175 regmap_update_bits(priv->regmap, USB_R3, 176 USB_R3_P30_SSC_RANGE_MASK | 177 USB_R3_P30_REF_SSP_EN, 178 USB_R3_P30_SSC_ENABLE | 179 FIELD_PREP(USB_R3_P30_SSC_RANGE_MASK, 2) | 180 USB_R3_P30_REF_SSP_EN); 181 udelay(2); 182 183 regmap_update_bits(priv->regmap, USB_R2, 184 USB_R2_P30_PCS_TX_DEEMPH_3P5DB_MASK, 185 FIELD_PREP(USB_R2_P30_PCS_TX_DEEMPH_3P5DB_MASK, 0x15)); 186 187 regmap_update_bits(priv->regmap, USB_R2, 188 USB_R2_P30_PCS_TX_DEEMPH_6DB_MASK, 189 FIELD_PREP(USB_R2_P30_PCS_TX_DEEMPH_6DB_MASK, 0x20)); 190 191 udelay(2); 192 193 regmap_update_bits(priv->regmap, USB_R1, 194 USB_R1_U3H_HOST_PORT_POWER_CONTROL_PRESENT, 195 USB_R1_U3H_HOST_PORT_POWER_CONTROL_PRESENT); 196 197 regmap_update_bits(priv->regmap, USB_R1, 198 USB_R1_P30_PCS_TX_SWING_FULL_MASK, 199 FIELD_PREP(USB_R1_P30_PCS_TX_SWING_FULL_MASK, 127)); 200 } 201 202 static void dwc3_meson_g12a_usb_otg_apply_mode(struct dwc3_meson_g12a *priv) 203 { 204 if (priv->otg_phy_mode == PHY_MODE_USB_DEVICE) { 205 regmap_update_bits(priv->regmap, USB_R0, 206 USB_R0_U2D_ACT, USB_R0_U2D_ACT); 207 regmap_update_bits(priv->regmap, USB_R0, 208 USB_R0_U2D_SS_SCALEDOWN_MODE_MASK, 0); 209 regmap_update_bits(priv->regmap, USB_R4, 210 USB_R4_P21_SLEEP_M0, USB_R4_P21_SLEEP_M0); 211 } else { 212 regmap_update_bits(priv->regmap, USB_R0, 213 USB_R0_U2D_ACT, 0); 214 regmap_update_bits(priv->regmap, USB_R4, 215 USB_R4_P21_SLEEP_M0, 0); 216 } 217 } 218 219 static int dwc3_meson_g12a_usb_init(struct dwc3_meson_g12a *priv) 220 { 221 int ret; 222 223 ret = dwc3_meson_g12a_usb2_init(priv); 224 if (ret) 225 return ret; 226 227 regmap_update_bits(priv->regmap, USB_R1, 228 USB_R1_U3H_FLADJ_30MHZ_REG_MASK, 229 FIELD_PREP(USB_R1_U3H_FLADJ_30MHZ_REG_MASK, 0x20)); 230 231 regmap_update_bits(priv->regmap, USB_R5, 232 USB_R5_ID_DIG_EN_0, 233 USB_R5_ID_DIG_EN_0); 234 regmap_update_bits(priv->regmap, USB_R5, 235 USB_R5_ID_DIG_EN_1, 236 USB_R5_ID_DIG_EN_1); 237 regmap_update_bits(priv->regmap, USB_R5, 238 USB_R5_ID_DIG_TH_MASK, 239 FIELD_PREP(USB_R5_ID_DIG_TH_MASK, 0xff)); 240 241 /* If we have an actual SuperSpeed port, initialize it */ 242 if (priv->usb3_ports) 243 dwc3_meson_g12a_usb3_init(priv); 244 245 dwc3_meson_g12a_usb_otg_apply_mode(priv); 246 247 return 0; 248 } 249 250 static const struct regmap_config phy_meson_g12a_usb3_regmap_conf = { 251 .reg_bits = 8, 252 .val_bits = 32, 253 .reg_stride = 4, 254 .max_register = USB_R5, 255 }; 256 257 static int dwc3_meson_g12a_get_phys(struct dwc3_meson_g12a *priv) 258 { 259 int i; 260 261 for (i = 0 ; i < PHY_COUNT ; ++i) { 262 priv->phys[i] = devm_phy_optional_get(priv->dev, phy_names[i]); 263 if (!priv->phys[i]) 264 continue; 265 266 if (IS_ERR(priv->phys[i])) 267 return PTR_ERR(priv->phys[i]); 268 269 if (i == USB3_HOST_PHY) 270 priv->usb3_ports++; 271 else 272 priv->usb2_ports++; 273 } 274 275 dev_info(priv->dev, "USB2 ports: %d\n", priv->usb2_ports); 276 dev_info(priv->dev, "USB3 ports: %d\n", priv->usb3_ports); 277 278 return 0; 279 } 280 281 static enum phy_mode dwc3_meson_g12a_get_id(struct dwc3_meson_g12a *priv) 282 { 283 u32 reg; 284 285 regmap_read(priv->regmap, USB_R5, ®); 286 287 if (reg & (USB_R5_ID_DIG_SYNC | USB_R5_ID_DIG_REG)) 288 return PHY_MODE_USB_DEVICE; 289 290 return PHY_MODE_USB_HOST; 291 } 292 293 static int dwc3_meson_g12a_otg_mode_set(struct dwc3_meson_g12a *priv, 294 enum phy_mode mode) 295 { 296 int ret; 297 298 if (!priv->phys[USB2_OTG_PHY]) 299 return -EINVAL; 300 301 if (mode == PHY_MODE_USB_HOST) 302 dev_info(priv->dev, "switching to Host Mode\n"); 303 else 304 dev_info(priv->dev, "switching to Device Mode\n"); 305 306 if (priv->vbus) { 307 if (mode == PHY_MODE_USB_DEVICE) 308 ret = regulator_disable(priv->vbus); 309 else 310 ret = regulator_enable(priv->vbus); 311 if (ret) 312 return ret; 313 } 314 315 priv->otg_phy_mode = mode; 316 317 dwc3_meson_g12a_usb2_set_mode(priv, USB2_OTG_PHY, mode); 318 319 dwc3_meson_g12a_usb_otg_apply_mode(priv); 320 321 return 0; 322 } 323 324 static int dwc3_meson_g12a_role_set(struct device *dev, enum usb_role role) 325 { 326 struct dwc3_meson_g12a *priv = dev_get_drvdata(dev); 327 enum phy_mode mode; 328 329 if (role == USB_ROLE_NONE) 330 return 0; 331 332 mode = (role == USB_ROLE_HOST) ? PHY_MODE_USB_HOST 333 : PHY_MODE_USB_DEVICE; 334 335 if (mode == priv->otg_phy_mode) 336 return 0; 337 338 return dwc3_meson_g12a_otg_mode_set(priv, mode); 339 } 340 341 static enum usb_role dwc3_meson_g12a_role_get(struct device *dev) 342 { 343 struct dwc3_meson_g12a *priv = dev_get_drvdata(dev); 344 345 return priv->otg_phy_mode == PHY_MODE_USB_HOST ? 346 USB_ROLE_HOST : USB_ROLE_DEVICE; 347 } 348 349 static irqreturn_t dwc3_meson_g12a_irq_thread(int irq, void *data) 350 { 351 struct dwc3_meson_g12a *priv = data; 352 enum phy_mode otg_id; 353 354 otg_id = dwc3_meson_g12a_get_id(priv); 355 if (otg_id != priv->otg_phy_mode) { 356 if (dwc3_meson_g12a_otg_mode_set(priv, otg_id)) 357 dev_warn(priv->dev, "Failed to switch OTG mode\n"); 358 } 359 360 regmap_update_bits(priv->regmap, USB_R5, USB_R5_ID_DIG_IRQ, 0); 361 362 return IRQ_HANDLED; 363 } 364 365 static struct device *dwc3_meson_g12_find_child(struct device *dev, 366 const char *compatible) 367 { 368 struct platform_device *pdev; 369 struct device_node *np; 370 371 np = of_get_compatible_child(dev->of_node, compatible); 372 if (!np) 373 return NULL; 374 375 pdev = of_find_device_by_node(np); 376 of_node_put(np); 377 if (!pdev) 378 return NULL; 379 380 return &pdev->dev; 381 } 382 383 static int dwc3_meson_g12a_probe(struct platform_device *pdev) 384 { 385 struct dwc3_meson_g12a *priv; 386 struct device *dev = &pdev->dev; 387 struct device_node *np = dev->of_node; 388 void __iomem *base; 389 struct resource *res; 390 enum phy_mode otg_id; 391 int ret, i, irq; 392 393 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); 394 if (!priv) 395 return -ENOMEM; 396 397 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 398 base = devm_ioremap_resource(dev, res); 399 if (IS_ERR(base)) 400 return PTR_ERR(base); 401 402 priv->regmap = devm_regmap_init_mmio(dev, base, 403 &phy_meson_g12a_usb3_regmap_conf); 404 if (IS_ERR(priv->regmap)) 405 return PTR_ERR(priv->regmap); 406 407 priv->vbus = devm_regulator_get_optional(dev, "vbus"); 408 if (IS_ERR(priv->vbus)) { 409 if (PTR_ERR(priv->vbus) == -EPROBE_DEFER) 410 return PTR_ERR(priv->vbus); 411 priv->vbus = NULL; 412 } 413 414 priv->clk = devm_clk_get(dev, NULL); 415 if (IS_ERR(priv->clk)) 416 return PTR_ERR(priv->clk); 417 418 ret = clk_prepare_enable(priv->clk); 419 if (ret) 420 return ret; 421 422 devm_add_action_or_reset(dev, 423 (void(*)(void *))clk_disable_unprepare, 424 priv->clk); 425 426 platform_set_drvdata(pdev, priv); 427 priv->dev = dev; 428 429 priv->reset = devm_reset_control_get(dev, NULL); 430 if (IS_ERR(priv->reset)) { 431 ret = PTR_ERR(priv->reset); 432 dev_err(dev, "failed to get device reset, err=%d\n", ret); 433 return ret; 434 } 435 436 ret = reset_control_reset(priv->reset); 437 if (ret) 438 return ret; 439 440 ret = dwc3_meson_g12a_get_phys(priv); 441 if (ret) 442 return ret; 443 444 if (priv->vbus) { 445 ret = regulator_enable(priv->vbus); 446 if (ret) 447 return ret; 448 } 449 450 /* Get dr_mode */ 451 priv->otg_mode = usb_get_dr_mode(dev); 452 453 if (priv->otg_mode == USB_DR_MODE_OTG) { 454 /* Ack irq before registering */ 455 regmap_update_bits(priv->regmap, USB_R5, 456 USB_R5_ID_DIG_IRQ, 0); 457 458 irq = platform_get_irq(pdev, 0); 459 ret = devm_request_threaded_irq(&pdev->dev, irq, NULL, 460 dwc3_meson_g12a_irq_thread, 461 IRQF_ONESHOT, pdev->name, priv); 462 if (ret) 463 return ret; 464 } 465 466 dwc3_meson_g12a_usb_init(priv); 467 468 /* Init PHYs */ 469 for (i = 0 ; i < PHY_COUNT ; ++i) { 470 ret = phy_init(priv->phys[i]); 471 if (ret) 472 return ret; 473 } 474 475 /* Set PHY Power */ 476 for (i = 0 ; i < PHY_COUNT ; ++i) { 477 ret = phy_power_on(priv->phys[i]); 478 if (ret) 479 goto err_phys_exit; 480 } 481 482 ret = of_platform_populate(np, NULL, NULL, dev); 483 if (ret) { 484 clk_disable_unprepare(priv->clk); 485 goto err_phys_power; 486 } 487 488 /* Setup OTG mode corresponding to the ID pin */ 489 if (priv->otg_mode == USB_DR_MODE_OTG) { 490 otg_id = dwc3_meson_g12a_get_id(priv); 491 if (otg_id != priv->otg_phy_mode) { 492 if (dwc3_meson_g12a_otg_mode_set(priv, otg_id)) 493 dev_warn(dev, "Failed to switch OTG mode\n"); 494 } 495 } 496 497 /* Setup role switcher */ 498 priv->switch_desc.usb2_port = dwc3_meson_g12_find_child(dev, 499 "snps,dwc3"); 500 priv->switch_desc.udc = dwc3_meson_g12_find_child(dev, "snps,dwc2"); 501 priv->switch_desc.allow_userspace_control = true; 502 priv->switch_desc.set = dwc3_meson_g12a_role_set; 503 priv->switch_desc.get = dwc3_meson_g12a_role_get; 504 505 priv->role_switch = usb_role_switch_register(dev, &priv->switch_desc); 506 if (IS_ERR(priv->role_switch)) 507 dev_warn(dev, "Unable to register Role Switch\n"); 508 509 pm_runtime_set_active(dev); 510 pm_runtime_enable(dev); 511 pm_runtime_get_sync(dev); 512 513 return 0; 514 515 err_phys_power: 516 for (i = 0 ; i < PHY_COUNT ; ++i) 517 phy_power_off(priv->phys[i]); 518 519 err_phys_exit: 520 for (i = 0 ; i < PHY_COUNT ; ++i) 521 phy_exit(priv->phys[i]); 522 523 return ret; 524 } 525 526 static int dwc3_meson_g12a_remove(struct platform_device *pdev) 527 { 528 struct dwc3_meson_g12a *priv = platform_get_drvdata(pdev); 529 struct device *dev = &pdev->dev; 530 int i; 531 532 usb_role_switch_unregister(priv->role_switch); 533 534 of_platform_depopulate(dev); 535 536 for (i = 0 ; i < PHY_COUNT ; ++i) { 537 phy_power_off(priv->phys[i]); 538 phy_exit(priv->phys[i]); 539 } 540 541 pm_runtime_disable(dev); 542 pm_runtime_put_noidle(dev); 543 pm_runtime_set_suspended(dev); 544 545 return 0; 546 } 547 548 static int __maybe_unused dwc3_meson_g12a_runtime_suspend(struct device *dev) 549 { 550 struct dwc3_meson_g12a *priv = dev_get_drvdata(dev); 551 552 clk_disable(priv->clk); 553 554 return 0; 555 } 556 557 static int __maybe_unused dwc3_meson_g12a_runtime_resume(struct device *dev) 558 { 559 struct dwc3_meson_g12a *priv = dev_get_drvdata(dev); 560 561 return clk_enable(priv->clk); 562 } 563 564 static int __maybe_unused dwc3_meson_g12a_suspend(struct device *dev) 565 { 566 struct dwc3_meson_g12a *priv = dev_get_drvdata(dev); 567 int i; 568 569 for (i = 0 ; i < PHY_COUNT ; ++i) { 570 phy_power_off(priv->phys[i]); 571 phy_exit(priv->phys[i]); 572 } 573 574 reset_control_assert(priv->reset); 575 576 return 0; 577 } 578 579 static int __maybe_unused dwc3_meson_g12a_resume(struct device *dev) 580 { 581 struct dwc3_meson_g12a *priv = dev_get_drvdata(dev); 582 int i, ret; 583 584 reset_control_deassert(priv->reset); 585 586 dwc3_meson_g12a_usb_init(priv); 587 588 /* Init PHYs */ 589 for (i = 0 ; i < PHY_COUNT ; ++i) { 590 ret = phy_init(priv->phys[i]); 591 if (ret) 592 return ret; 593 } 594 595 /* Set PHY Power */ 596 for (i = 0 ; i < PHY_COUNT ; ++i) { 597 ret = phy_power_on(priv->phys[i]); 598 if (ret) 599 return ret; 600 } 601 602 return 0; 603 } 604 605 static const struct dev_pm_ops dwc3_meson_g12a_dev_pm_ops = { 606 SET_SYSTEM_SLEEP_PM_OPS(dwc3_meson_g12a_suspend, dwc3_meson_g12a_resume) 607 SET_RUNTIME_PM_OPS(dwc3_meson_g12a_runtime_suspend, 608 dwc3_meson_g12a_runtime_resume, NULL) 609 }; 610 611 static const struct of_device_id dwc3_meson_g12a_match[] = { 612 { .compatible = "amlogic,meson-g12a-usb-ctrl" }, 613 { /* Sentinel */ } 614 }; 615 MODULE_DEVICE_TABLE(of, dwc3_meson_g12a_match); 616 617 static struct platform_driver dwc3_meson_g12a_driver = { 618 .probe = dwc3_meson_g12a_probe, 619 .remove = dwc3_meson_g12a_remove, 620 .driver = { 621 .name = "dwc3-meson-g12a", 622 .of_match_table = dwc3_meson_g12a_match, 623 .pm = &dwc3_meson_g12a_dev_pm_ops, 624 }, 625 }; 626 627 module_platform_driver(dwc3_meson_g12a_driver); 628 MODULE_LICENSE("GPL v2"); 629 MODULE_DESCRIPTION("Amlogic Meson G12A USB Glue Layer"); 630 MODULE_AUTHOR("Neil Armstrong <narmstrong@baylibre.com>"); 631