1 // SPDX-License-Identifier: GPL-2.0 2 /** 3 * drd.c - DesignWare USB3 DRD Controller Dual-role support 4 * 5 * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com 6 * 7 * Authors: Roger Quadros <rogerq@ti.com> 8 */ 9 10 #include <linux/extcon.h> 11 #include <linux/of_graph.h> 12 #include <linux/platform_device.h> 13 14 #include "debug.h" 15 #include "core.h" 16 #include "gadget.h" 17 18 static void dwc3_otg_disable_events(struct dwc3 *dwc, u32 disable_mask) 19 { 20 u32 reg = dwc3_readl(dwc->regs, DWC3_OEVTEN); 21 22 reg &= ~(disable_mask); 23 dwc3_writel(dwc->regs, DWC3_OEVTEN, reg); 24 } 25 26 static void dwc3_otg_enable_events(struct dwc3 *dwc, u32 enable_mask) 27 { 28 u32 reg = dwc3_readl(dwc->regs, DWC3_OEVTEN); 29 30 reg |= (enable_mask); 31 dwc3_writel(dwc->regs, DWC3_OEVTEN, reg); 32 } 33 34 static void dwc3_otg_clear_events(struct dwc3 *dwc) 35 { 36 u32 reg = dwc3_readl(dwc->regs, DWC3_OEVT); 37 38 dwc3_writel(dwc->regs, DWC3_OEVTEN, reg); 39 } 40 41 #define DWC3_OTG_ALL_EVENTS (DWC3_OEVTEN_XHCIRUNSTPSETEN | \ 42 DWC3_OEVTEN_DEVRUNSTPSETEN | DWC3_OEVTEN_HIBENTRYEN | \ 43 DWC3_OEVTEN_CONIDSTSCHNGEN | DWC3_OEVTEN_HRRCONFNOTIFEN | \ 44 DWC3_OEVTEN_HRRINITNOTIFEN | DWC3_OEVTEN_ADEVIDLEEN | \ 45 DWC3_OEVTEN_ADEVBHOSTENDEN | DWC3_OEVTEN_ADEVHOSTEN | \ 46 DWC3_OEVTEN_ADEVHNPCHNGEN | DWC3_OEVTEN_ADEVSRPDETEN | \ 47 DWC3_OEVTEN_ADEVSESSENDDETEN | DWC3_OEVTEN_BDEVBHOSTENDEN | \ 48 DWC3_OEVTEN_BDEVHNPCHNGEN | DWC3_OEVTEN_BDEVSESSVLDDETEN | \ 49 DWC3_OEVTEN_BDEVVBUSCHNGEN) 50 51 static irqreturn_t dwc3_otg_thread_irq(int irq, void *_dwc) 52 { 53 struct dwc3 *dwc = _dwc; 54 55 spin_lock(&dwc->lock); 56 if (dwc->otg_restart_host) { 57 dwc3_otg_host_init(dwc); 58 dwc->otg_restart_host = 0; 59 } 60 61 spin_unlock(&dwc->lock); 62 63 dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_OTG); 64 65 return IRQ_HANDLED; 66 } 67 68 static irqreturn_t dwc3_otg_irq(int irq, void *_dwc) 69 { 70 u32 reg; 71 struct dwc3 *dwc = _dwc; 72 irqreturn_t ret = IRQ_NONE; 73 74 reg = dwc3_readl(dwc->regs, DWC3_OEVT); 75 if (reg) { 76 /* ignore non OTG events, we can't disable them in OEVTEN */ 77 if (!(reg & DWC3_OTG_ALL_EVENTS)) { 78 dwc3_writel(dwc->regs, DWC3_OEVT, reg); 79 return IRQ_NONE; 80 } 81 82 if (dwc->current_otg_role == DWC3_OTG_ROLE_HOST && 83 !(reg & DWC3_OEVT_DEVICEMODE)) 84 dwc->otg_restart_host = 1; 85 dwc3_writel(dwc->regs, DWC3_OEVT, reg); 86 ret = IRQ_WAKE_THREAD; 87 } 88 89 return ret; 90 } 91 92 static void dwc3_otgregs_init(struct dwc3 *dwc) 93 { 94 u32 reg; 95 96 /* 97 * Prevent host/device reset from resetting OTG core. 98 * If we don't do this then xhci_reset (USBCMD.HCRST) will reset 99 * the signal outputs sent to the PHY, the OTG FSM logic of the 100 * core and also the resets to the VBUS filters inside the core. 101 */ 102 reg = dwc3_readl(dwc->regs, DWC3_OCFG); 103 reg |= DWC3_OCFG_SFTRSTMASK; 104 dwc3_writel(dwc->regs, DWC3_OCFG, reg); 105 106 /* Disable hibernation for simplicity */ 107 reg = dwc3_readl(dwc->regs, DWC3_GCTL); 108 reg &= ~DWC3_GCTL_GBLHIBERNATIONEN; 109 dwc3_writel(dwc->regs, DWC3_GCTL, reg); 110 111 /* 112 * Initialize OTG registers as per 113 * Figure 11-4 OTG Driver Overall Programming Flow 114 */ 115 /* OCFG.SRPCap = 0, OCFG.HNPCap = 0 */ 116 reg = dwc3_readl(dwc->regs, DWC3_OCFG); 117 reg &= ~(DWC3_OCFG_SRPCAP | DWC3_OCFG_HNPCAP); 118 dwc3_writel(dwc->regs, DWC3_OCFG, reg); 119 /* OEVT = FFFF */ 120 dwc3_otg_clear_events(dwc); 121 /* OEVTEN = 0 */ 122 dwc3_otg_disable_events(dwc, DWC3_OTG_ALL_EVENTS); 123 /* OEVTEN.ConIDStsChngEn = 1. Instead we enable all events */ 124 dwc3_otg_enable_events(dwc, DWC3_OTG_ALL_EVENTS); 125 /* 126 * OCTL.PeriMode = 1, OCTL.DevSetHNPEn = 0, OCTL.HstSetHNPEn = 0, 127 * OCTL.HNPReq = 0 128 */ 129 reg = dwc3_readl(dwc->regs, DWC3_OCTL); 130 reg |= DWC3_OCTL_PERIMODE; 131 reg &= ~(DWC3_OCTL_DEVSETHNPEN | DWC3_OCTL_HSTSETHNPEN | 132 DWC3_OCTL_HNPREQ); 133 dwc3_writel(dwc->regs, DWC3_OCTL, reg); 134 } 135 136 static int dwc3_otg_get_irq(struct dwc3 *dwc) 137 { 138 struct platform_device *dwc3_pdev = to_platform_device(dwc->dev); 139 int irq; 140 141 irq = platform_get_irq_byname(dwc3_pdev, "otg"); 142 if (irq > 0) 143 goto out; 144 145 if (irq == -EPROBE_DEFER) 146 goto out; 147 148 irq = platform_get_irq_byname(dwc3_pdev, "dwc_usb3"); 149 if (irq > 0) 150 goto out; 151 152 if (irq == -EPROBE_DEFER) 153 goto out; 154 155 irq = platform_get_irq(dwc3_pdev, 0); 156 if (irq > 0) 157 goto out; 158 159 if (irq != -EPROBE_DEFER) 160 dev_err(dwc->dev, "missing OTG IRQ\n"); 161 162 if (!irq) 163 irq = -EINVAL; 164 165 out: 166 return irq; 167 } 168 169 void dwc3_otg_init(struct dwc3 *dwc) 170 { 171 u32 reg; 172 173 /* 174 * As per Figure 11-4 OTG Driver Overall Programming Flow, 175 * block "Initialize GCTL for OTG operation". 176 */ 177 /* GCTL.PrtCapDir=2'b11 */ 178 dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_OTG); 179 /* GUSB2PHYCFG0.SusPHY=0 */ 180 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0)); 181 reg &= ~DWC3_GUSB2PHYCFG_SUSPHY; 182 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg); 183 184 /* Initialize OTG registers */ 185 dwc3_otgregs_init(dwc); 186 } 187 188 void dwc3_otg_exit(struct dwc3 *dwc) 189 { 190 /* disable all OTG IRQs */ 191 dwc3_otg_disable_events(dwc, DWC3_OTG_ALL_EVENTS); 192 /* clear all events */ 193 dwc3_otg_clear_events(dwc); 194 } 195 196 /* should be called before Host controller driver is started */ 197 void dwc3_otg_host_init(struct dwc3 *dwc) 198 { 199 u32 reg; 200 201 /* As per Figure 11-10 A-Device Flow Diagram */ 202 /* OCFG.HNPCap = 0, OCFG.SRPCap = 0. Already 0 */ 203 204 /* 205 * OCTL.PeriMode=0, OCTL.TermSelDLPulse = 0, 206 * OCTL.DevSetHNPEn = 0, OCTL.HstSetHNPEn = 0 207 */ 208 reg = dwc3_readl(dwc->regs, DWC3_OCTL); 209 reg &= ~(DWC3_OCTL_PERIMODE | DWC3_OCTL_TERMSELIDPULSE | 210 DWC3_OCTL_DEVSETHNPEN | DWC3_OCTL_HSTSETHNPEN); 211 dwc3_writel(dwc->regs, DWC3_OCTL, reg); 212 213 /* 214 * OCFG.DisPrtPwrCutoff = 0/1 215 */ 216 reg = dwc3_readl(dwc->regs, DWC3_OCFG); 217 reg &= ~DWC3_OCFG_DISPWRCUTTOFF; 218 dwc3_writel(dwc->regs, DWC3_OCFG, reg); 219 220 /* 221 * OCFG.SRPCap = 1, OCFG.HNPCap = GHWPARAMS6.HNP_CAP 222 * We don't want SRP/HNP for simple dual-role so leave 223 * these disabled. 224 */ 225 226 /* 227 * OEVTEN.OTGADevHostEvntEn = 1 228 * OEVTEN.OTGADevSessEndDetEvntEn = 1 229 * We don't want HNP/role-swap so leave these disabled. 230 */ 231 232 /* GUSB2PHYCFG.ULPIAutoRes = 1/0, GUSB2PHYCFG.SusPHY = 1 */ 233 if (!dwc->dis_u2_susphy_quirk) { 234 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0)); 235 reg |= DWC3_GUSB2PHYCFG_SUSPHY; 236 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg); 237 } 238 239 /* Set Port Power to enable VBUS: OCTL.PrtPwrCtl = 1 */ 240 reg = dwc3_readl(dwc->regs, DWC3_OCTL); 241 reg |= DWC3_OCTL_PRTPWRCTL; 242 dwc3_writel(dwc->regs, DWC3_OCTL, reg); 243 } 244 245 /* should be called after Host controller driver is stopped */ 246 static void dwc3_otg_host_exit(struct dwc3 *dwc) 247 { 248 u32 reg; 249 250 /* 251 * Exit from A-device flow as per 252 * Figure 11-4 OTG Driver Overall Programming Flow 253 */ 254 255 /* 256 * OEVTEN.OTGADevBHostEndEvntEn=0, OEVTEN.OTGADevHNPChngEvntEn=0 257 * OEVTEN.OTGADevSessEndDetEvntEn=0, 258 * OEVTEN.OTGADevHostEvntEn = 0 259 * But we don't disable any OTG events 260 */ 261 262 /* OCTL.HstSetHNPEn = 0, OCTL.PrtPwrCtl=0 */ 263 reg = dwc3_readl(dwc->regs, DWC3_OCTL); 264 reg &= ~(DWC3_OCTL_HSTSETHNPEN | DWC3_OCTL_PRTPWRCTL); 265 dwc3_writel(dwc->regs, DWC3_OCTL, reg); 266 } 267 268 /* should be called before the gadget controller driver is started */ 269 static void dwc3_otg_device_init(struct dwc3 *dwc) 270 { 271 u32 reg; 272 273 /* As per Figure 11-20 B-Device Flow Diagram */ 274 275 /* 276 * OCFG.HNPCap = GHWPARAMS6.HNP_CAP, OCFG.SRPCap = 1 277 * but we keep them 0 for simple dual-role operation. 278 */ 279 reg = dwc3_readl(dwc->regs, DWC3_OCFG); 280 /* OCFG.OTGSftRstMsk = 0/1 */ 281 reg |= DWC3_OCFG_SFTRSTMASK; 282 dwc3_writel(dwc->regs, DWC3_OCFG, reg); 283 /* 284 * OCTL.PeriMode = 1 285 * OCTL.TermSelDLPulse = 0/1, OCTL.HNPReq = 0 286 * OCTL.DevSetHNPEn = 0, OCTL.HstSetHNPEn = 0 287 */ 288 reg = dwc3_readl(dwc->regs, DWC3_OCTL); 289 reg |= DWC3_OCTL_PERIMODE; 290 reg &= ~(DWC3_OCTL_TERMSELIDPULSE | DWC3_OCTL_HNPREQ | 291 DWC3_OCTL_DEVSETHNPEN | DWC3_OCTL_HSTSETHNPEN); 292 dwc3_writel(dwc->regs, DWC3_OCTL, reg); 293 /* OEVTEN.OTGBDevSesVldDetEvntEn = 1 */ 294 dwc3_otg_enable_events(dwc, DWC3_OEVTEN_BDEVSESSVLDDETEN); 295 /* GUSB2PHYCFG.ULPIAutoRes = 0, GUSB2PHYCFG0.SusPHY = 1 */ 296 if (!dwc->dis_u2_susphy_quirk) { 297 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0)); 298 reg |= DWC3_GUSB2PHYCFG_SUSPHY; 299 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg); 300 } 301 /* GCTL.GblHibernationEn = 0. Already 0. */ 302 } 303 304 /* should be called after the gadget controller driver is stopped */ 305 static void dwc3_otg_device_exit(struct dwc3 *dwc) 306 { 307 u32 reg; 308 309 /* 310 * Exit from B-device flow as per 311 * Figure 11-4 OTG Driver Overall Programming Flow 312 */ 313 314 /* 315 * OEVTEN.OTGBDevHNPChngEvntEn = 0 316 * OEVTEN.OTGBDevVBusChngEvntEn = 0 317 * OEVTEN.OTGBDevBHostEndEvntEn = 0 318 */ 319 dwc3_otg_disable_events(dwc, DWC3_OEVTEN_BDEVHNPCHNGEN | 320 DWC3_OEVTEN_BDEVVBUSCHNGEN | 321 DWC3_OEVTEN_BDEVBHOSTENDEN); 322 323 /* OCTL.DevSetHNPEn = 0, OCTL.HNPReq = 0, OCTL.PeriMode=1 */ 324 reg = dwc3_readl(dwc->regs, DWC3_OCTL); 325 reg &= ~(DWC3_OCTL_DEVSETHNPEN | DWC3_OCTL_HNPREQ); 326 reg |= DWC3_OCTL_PERIMODE; 327 dwc3_writel(dwc->regs, DWC3_OCTL, reg); 328 } 329 330 void dwc3_otg_update(struct dwc3 *dwc, bool ignore_idstatus) 331 { 332 int ret; 333 u32 reg; 334 int id; 335 unsigned long flags; 336 337 if (dwc->dr_mode != USB_DR_MODE_OTG) 338 return; 339 340 /* don't do anything if debug user changed role to not OTG */ 341 if (dwc->current_dr_role != DWC3_GCTL_PRTCAP_OTG) 342 return; 343 344 if (!ignore_idstatus) { 345 reg = dwc3_readl(dwc->regs, DWC3_OSTS); 346 id = !!(reg & DWC3_OSTS_CONIDSTS); 347 348 dwc->desired_otg_role = id ? DWC3_OTG_ROLE_DEVICE : 349 DWC3_OTG_ROLE_HOST; 350 } 351 352 if (dwc->desired_otg_role == dwc->current_otg_role) 353 return; 354 355 switch (dwc->current_otg_role) { 356 case DWC3_OTG_ROLE_HOST: 357 dwc3_host_exit(dwc); 358 spin_lock_irqsave(&dwc->lock, flags); 359 dwc3_otg_host_exit(dwc); 360 spin_unlock_irqrestore(&dwc->lock, flags); 361 break; 362 case DWC3_OTG_ROLE_DEVICE: 363 dwc3_gadget_exit(dwc); 364 spin_lock_irqsave(&dwc->lock, flags); 365 dwc3_event_buffers_cleanup(dwc); 366 dwc3_otg_device_exit(dwc); 367 spin_unlock_irqrestore(&dwc->lock, flags); 368 break; 369 default: 370 break; 371 } 372 373 spin_lock_irqsave(&dwc->lock, flags); 374 375 dwc->current_otg_role = dwc->desired_otg_role; 376 377 spin_unlock_irqrestore(&dwc->lock, flags); 378 379 switch (dwc->desired_otg_role) { 380 case DWC3_OTG_ROLE_HOST: 381 spin_lock_irqsave(&dwc->lock, flags); 382 dwc3_otgregs_init(dwc); 383 dwc3_otg_host_init(dwc); 384 spin_unlock_irqrestore(&dwc->lock, flags); 385 ret = dwc3_host_init(dwc); 386 if (ret) { 387 dev_err(dwc->dev, "failed to initialize host\n"); 388 } else { 389 if (dwc->usb2_phy) 390 otg_set_vbus(dwc->usb2_phy->otg, true); 391 if (dwc->usb2_generic_phy) 392 phy_set_mode(dwc->usb2_generic_phy, 393 PHY_MODE_USB_HOST); 394 } 395 break; 396 case DWC3_OTG_ROLE_DEVICE: 397 spin_lock_irqsave(&dwc->lock, flags); 398 dwc3_otgregs_init(dwc); 399 dwc3_otg_device_init(dwc); 400 dwc3_event_buffers_setup(dwc); 401 spin_unlock_irqrestore(&dwc->lock, flags); 402 403 if (dwc->usb2_phy) 404 otg_set_vbus(dwc->usb2_phy->otg, false); 405 if (dwc->usb2_generic_phy) 406 phy_set_mode(dwc->usb2_generic_phy, 407 PHY_MODE_USB_DEVICE); 408 ret = dwc3_gadget_init(dwc); 409 if (ret) 410 dev_err(dwc->dev, "failed to initialize peripheral\n"); 411 break; 412 default: 413 break; 414 } 415 } 416 417 static void dwc3_drd_update(struct dwc3 *dwc) 418 { 419 int id; 420 421 if (dwc->edev) { 422 id = extcon_get_state(dwc->edev, EXTCON_USB_HOST); 423 if (id < 0) 424 id = 0; 425 dwc3_set_mode(dwc, id ? 426 DWC3_GCTL_PRTCAP_HOST : 427 DWC3_GCTL_PRTCAP_DEVICE); 428 } 429 } 430 431 static int dwc3_drd_notifier(struct notifier_block *nb, 432 unsigned long event, void *ptr) 433 { 434 struct dwc3 *dwc = container_of(nb, struct dwc3, edev_nb); 435 436 dwc3_set_mode(dwc, event ? 437 DWC3_GCTL_PRTCAP_HOST : 438 DWC3_GCTL_PRTCAP_DEVICE); 439 440 return NOTIFY_DONE; 441 } 442 443 static struct extcon_dev *dwc3_get_extcon(struct dwc3 *dwc) 444 { 445 struct device *dev = dwc->dev; 446 struct device_node *np_phy, *np_conn; 447 struct extcon_dev *edev; 448 449 if (of_property_read_bool(dev->of_node, "extcon")) 450 return extcon_get_edev_by_phandle(dwc->dev, 0); 451 452 np_phy = of_parse_phandle(dev->of_node, "phys", 0); 453 np_conn = of_graph_get_remote_node(np_phy, -1, -1); 454 455 if (np_conn) 456 edev = extcon_find_edev_by_node(np_conn); 457 else 458 edev = NULL; 459 460 of_node_put(np_conn); 461 of_node_put(np_phy); 462 463 return edev; 464 } 465 466 int dwc3_drd_init(struct dwc3 *dwc) 467 { 468 int ret, irq; 469 470 dwc->edev = dwc3_get_extcon(dwc); 471 if (IS_ERR(dwc->edev)) 472 return PTR_ERR(dwc->edev); 473 474 if (dwc->edev) { 475 dwc->edev_nb.notifier_call = dwc3_drd_notifier; 476 ret = extcon_register_notifier(dwc->edev, EXTCON_USB_HOST, 477 &dwc->edev_nb); 478 if (ret < 0) { 479 dev_err(dwc->dev, "couldn't register cable notifier\n"); 480 return ret; 481 } 482 483 dwc3_drd_update(dwc); 484 } else { 485 dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_OTG); 486 dwc->current_dr_role = DWC3_GCTL_PRTCAP_OTG; 487 488 /* use OTG block to get ID event */ 489 irq = dwc3_otg_get_irq(dwc); 490 if (irq < 0) 491 return irq; 492 493 dwc->otg_irq = irq; 494 495 /* disable all OTG IRQs */ 496 dwc3_otg_disable_events(dwc, DWC3_OTG_ALL_EVENTS); 497 /* clear all events */ 498 dwc3_otg_clear_events(dwc); 499 500 ret = request_threaded_irq(dwc->otg_irq, dwc3_otg_irq, 501 dwc3_otg_thread_irq, 502 IRQF_SHARED, "dwc3-otg", dwc); 503 if (ret) { 504 dev_err(dwc->dev, "failed to request irq #%d --> %d\n", 505 dwc->otg_irq, ret); 506 ret = -ENODEV; 507 return ret; 508 } 509 510 dwc3_otg_init(dwc); 511 dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_OTG); 512 } 513 514 return 0; 515 } 516 517 void dwc3_drd_exit(struct dwc3 *dwc) 518 { 519 unsigned long flags; 520 521 if (dwc->edev) 522 extcon_unregister_notifier(dwc->edev, EXTCON_USB_HOST, 523 &dwc->edev_nb); 524 525 cancel_work_sync(&dwc->drd_work); 526 527 /* debug user might have changed role, clean based on current role */ 528 switch (dwc->current_dr_role) { 529 case DWC3_GCTL_PRTCAP_HOST: 530 dwc3_host_exit(dwc); 531 break; 532 case DWC3_GCTL_PRTCAP_DEVICE: 533 dwc3_gadget_exit(dwc); 534 dwc3_event_buffers_cleanup(dwc); 535 break; 536 case DWC3_GCTL_PRTCAP_OTG: 537 dwc3_otg_exit(dwc); 538 spin_lock_irqsave(&dwc->lock, flags); 539 dwc->desired_otg_role = DWC3_OTG_ROLE_IDLE; 540 spin_unlock_irqrestore(&dwc->lock, flags); 541 dwc3_otg_update(dwc, 1); 542 break; 543 default: 544 break; 545 } 546 547 if (!dwc->edev) 548 free_irq(dwc->otg_irq, dwc); 549 } 550