xref: /openbmc/linux/drivers/usb/dwc3/core.h (revision fb960bd2)
1 // SPDX-License-Identifier: GPL-2.0
2 /*
3  * core.h - DesignWare USB3 DRD Core Header
4  *
5  * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
6  *
7  * Authors: Felipe Balbi <balbi@ti.com>,
8  *	    Sebastian Andrzej Siewior <bigeasy@linutronix.de>
9  */
10 
11 #ifndef __DRIVERS_USB_DWC3_CORE_H
12 #define __DRIVERS_USB_DWC3_CORE_H
13 
14 #include <linux/device.h>
15 #include <linux/spinlock.h>
16 #include <linux/ioport.h>
17 #include <linux/list.h>
18 #include <linux/bitops.h>
19 #include <linux/dma-mapping.h>
20 #include <linux/mm.h>
21 #include <linux/debugfs.h>
22 #include <linux/wait.h>
23 #include <linux/workqueue.h>
24 
25 #include <linux/usb/ch9.h>
26 #include <linux/usb/gadget.h>
27 #include <linux/usb/otg.h>
28 #include <linux/ulpi/interface.h>
29 
30 #include <linux/phy/phy.h>
31 
32 #define DWC3_MSG_MAX	500
33 
34 /* Global constants */
35 #define DWC3_PULL_UP_TIMEOUT	500	/* ms */
36 #define DWC3_BOUNCE_SIZE	1024	/* size of a superspeed bulk */
37 #define DWC3_EP0_SETUP_SIZE	512
38 #define DWC3_ENDPOINTS_NUM	32
39 #define DWC3_XHCI_RESOURCES_NUM	2
40 
41 #define DWC3_SCRATCHBUF_SIZE	4096	/* each buffer is assumed to be 4KiB */
42 #define DWC3_EVENT_BUFFERS_SIZE	4096
43 #define DWC3_EVENT_TYPE_MASK	0xfe
44 
45 #define DWC3_EVENT_TYPE_DEV	0
46 #define DWC3_EVENT_TYPE_CARKIT	3
47 #define DWC3_EVENT_TYPE_I2C	4
48 
49 #define DWC3_DEVICE_EVENT_DISCONNECT		0
50 #define DWC3_DEVICE_EVENT_RESET			1
51 #define DWC3_DEVICE_EVENT_CONNECT_DONE		2
52 #define DWC3_DEVICE_EVENT_LINK_STATUS_CHANGE	3
53 #define DWC3_DEVICE_EVENT_WAKEUP		4
54 #define DWC3_DEVICE_EVENT_HIBER_REQ		5
55 #define DWC3_DEVICE_EVENT_EOPF			6
56 #define DWC3_DEVICE_EVENT_SOF			7
57 #define DWC3_DEVICE_EVENT_ERRATIC_ERROR		9
58 #define DWC3_DEVICE_EVENT_CMD_CMPL		10
59 #define DWC3_DEVICE_EVENT_OVERFLOW		11
60 
61 #define DWC3_GEVNTCOUNT_MASK	0xfffc
62 #define DWC3_GEVNTCOUNT_EHB	BIT(31)
63 #define DWC3_GSNPSID_MASK	0xffff0000
64 #define DWC3_GSNPSREV_MASK	0xffff
65 
66 /* DWC3 registers memory space boundries */
67 #define DWC3_XHCI_REGS_START		0x0
68 #define DWC3_XHCI_REGS_END		0x7fff
69 #define DWC3_GLOBALS_REGS_START		0xc100
70 #define DWC3_GLOBALS_REGS_END		0xc6ff
71 #define DWC3_DEVICE_REGS_START		0xc700
72 #define DWC3_DEVICE_REGS_END		0xcbff
73 #define DWC3_OTG_REGS_START		0xcc00
74 #define DWC3_OTG_REGS_END		0xccff
75 
76 /* Global Registers */
77 #define DWC3_GSBUSCFG0		0xc100
78 #define DWC3_GSBUSCFG1		0xc104
79 #define DWC3_GTXTHRCFG		0xc108
80 #define DWC3_GRXTHRCFG		0xc10c
81 #define DWC3_GCTL		0xc110
82 #define DWC3_GEVTEN		0xc114
83 #define DWC3_GSTS		0xc118
84 #define DWC3_GUCTL1		0xc11c
85 #define DWC3_GSNPSID		0xc120
86 #define DWC3_GGPIO		0xc124
87 #define DWC3_GUID		0xc128
88 #define DWC3_GUCTL		0xc12c
89 #define DWC3_GBUSERRADDR0	0xc130
90 #define DWC3_GBUSERRADDR1	0xc134
91 #define DWC3_GPRTBIMAP0		0xc138
92 #define DWC3_GPRTBIMAP1		0xc13c
93 #define DWC3_GHWPARAMS0		0xc140
94 #define DWC3_GHWPARAMS1		0xc144
95 #define DWC3_GHWPARAMS2		0xc148
96 #define DWC3_GHWPARAMS3		0xc14c
97 #define DWC3_GHWPARAMS4		0xc150
98 #define DWC3_GHWPARAMS5		0xc154
99 #define DWC3_GHWPARAMS6		0xc158
100 #define DWC3_GHWPARAMS7		0xc15c
101 #define DWC3_GDBGFIFOSPACE	0xc160
102 #define DWC3_GDBGLTSSM		0xc164
103 #define DWC3_GPRTBIMAP_HS0	0xc180
104 #define DWC3_GPRTBIMAP_HS1	0xc184
105 #define DWC3_GPRTBIMAP_FS0	0xc188
106 #define DWC3_GPRTBIMAP_FS1	0xc18c
107 #define DWC3_GUCTL2		0xc19c
108 
109 #define DWC3_VER_NUMBER		0xc1a0
110 #define DWC3_VER_TYPE		0xc1a4
111 
112 #define DWC3_GUSB2PHYCFG(n)	(0xc200 + ((n) * 0x04))
113 #define DWC3_GUSB2I2CCTL(n)	(0xc240 + ((n) * 0x04))
114 
115 #define DWC3_GUSB2PHYACC(n)	(0xc280 + ((n) * 0x04))
116 
117 #define DWC3_GUSB3PIPECTL(n)	(0xc2c0 + ((n) * 0x04))
118 
119 #define DWC3_GTXFIFOSIZ(n)	(0xc300 + ((n) * 0x04))
120 #define DWC3_GRXFIFOSIZ(n)	(0xc380 + ((n) * 0x04))
121 
122 #define DWC3_GEVNTADRLO(n)	(0xc400 + ((n) * 0x10))
123 #define DWC3_GEVNTADRHI(n)	(0xc404 + ((n) * 0x10))
124 #define DWC3_GEVNTSIZ(n)	(0xc408 + ((n) * 0x10))
125 #define DWC3_GEVNTCOUNT(n)	(0xc40c + ((n) * 0x10))
126 
127 #define DWC3_GHWPARAMS8		0xc600
128 #define DWC3_GFLADJ		0xc630
129 
130 /* Device Registers */
131 #define DWC3_DCFG		0xc700
132 #define DWC3_DCTL		0xc704
133 #define DWC3_DEVTEN		0xc708
134 #define DWC3_DSTS		0xc70c
135 #define DWC3_DGCMDPAR		0xc710
136 #define DWC3_DGCMD		0xc714
137 #define DWC3_DALEPENA		0xc720
138 
139 #define DWC3_DEP_BASE(n)	(0xc800 + ((n) * 0x10))
140 #define DWC3_DEPCMDPAR2		0x00
141 #define DWC3_DEPCMDPAR1		0x04
142 #define DWC3_DEPCMDPAR0		0x08
143 #define DWC3_DEPCMD		0x0c
144 
145 #define DWC3_DEV_IMOD(n)	(0xca00 + ((n) * 0x4))
146 
147 /* OTG Registers */
148 #define DWC3_OCFG		0xcc00
149 #define DWC3_OCTL		0xcc04
150 #define DWC3_OEVT		0xcc08
151 #define DWC3_OEVTEN		0xcc0C
152 #define DWC3_OSTS		0xcc10
153 
154 /* Bit fields */
155 
156 /* Global Debug Queue/FIFO Space Available Register */
157 #define DWC3_GDBGFIFOSPACE_NUM(n)	((n) & 0x1f)
158 #define DWC3_GDBGFIFOSPACE_TYPE(n)	(((n) << 5) & 0x1e0)
159 #define DWC3_GDBGFIFOSPACE_SPACE_AVAILABLE(n) (((n) >> 16) & 0xffff)
160 
161 #define DWC3_TXFIFOQ		1
162 #define DWC3_RXFIFOQ		3
163 #define DWC3_TXREQQ		5
164 #define DWC3_RXREQQ		7
165 #define DWC3_RXINFOQ		9
166 #define DWC3_DESCFETCHQ		13
167 #define DWC3_EVENTQ		15
168 
169 /* Global RX Threshold Configuration Register */
170 #define DWC3_GRXTHRCFG_MAXRXBURSTSIZE(n) (((n) & 0x1f) << 19)
171 #define DWC3_GRXTHRCFG_RXPKTCNT(n) (((n) & 0xf) << 24)
172 #define DWC3_GRXTHRCFG_PKTCNTSEL BIT(29)
173 
174 /* Global Configuration Register */
175 #define DWC3_GCTL_PWRDNSCALE(n)	((n) << 19)
176 #define DWC3_GCTL_U2RSTECN	BIT(16)
177 #define DWC3_GCTL_RAMCLKSEL(x)	(((x) & DWC3_GCTL_CLK_MASK) << 6)
178 #define DWC3_GCTL_CLK_BUS	(0)
179 #define DWC3_GCTL_CLK_PIPE	(1)
180 #define DWC3_GCTL_CLK_PIPEHALF	(2)
181 #define DWC3_GCTL_CLK_MASK	(3)
182 
183 #define DWC3_GCTL_PRTCAP(n)	(((n) & (3 << 12)) >> 12)
184 #define DWC3_GCTL_PRTCAPDIR(n)	((n) << 12)
185 #define DWC3_GCTL_PRTCAP_HOST	1
186 #define DWC3_GCTL_PRTCAP_DEVICE	2
187 #define DWC3_GCTL_PRTCAP_OTG	3
188 
189 #define DWC3_GCTL_CORESOFTRESET		BIT(11)
190 #define DWC3_GCTL_SOFITPSYNC		BIT(10)
191 #define DWC3_GCTL_SCALEDOWN(n)		((n) << 4)
192 #define DWC3_GCTL_SCALEDOWN_MASK	DWC3_GCTL_SCALEDOWN(3)
193 #define DWC3_GCTL_DISSCRAMBLE		BIT(3)
194 #define DWC3_GCTL_U2EXIT_LFPS		BIT(2)
195 #define DWC3_GCTL_GBLHIBERNATIONEN	BIT(1)
196 #define DWC3_GCTL_DSBLCLKGTNG		BIT(0)
197 
198 /* Global User Control 1 Register */
199 #define DWC3_GUCTL1_TX_IPGAP_LINECHECK_DIS	BIT(28)
200 #define DWC3_GUCTL1_DEV_L1_EXIT_BY_HW	BIT(24)
201 
202 /* Global USB2 PHY Configuration Register */
203 #define DWC3_GUSB2PHYCFG_PHYSOFTRST	BIT(31)
204 #define DWC3_GUSB2PHYCFG_U2_FREECLK_EXISTS	BIT(30)
205 #define DWC3_GUSB2PHYCFG_SUSPHY		BIT(6)
206 #define DWC3_GUSB2PHYCFG_ULPI_UTMI	BIT(4)
207 #define DWC3_GUSB2PHYCFG_ENBLSLPM	BIT(8)
208 #define DWC3_GUSB2PHYCFG_PHYIF(n)	(n << 3)
209 #define DWC3_GUSB2PHYCFG_PHYIF_MASK	DWC3_GUSB2PHYCFG_PHYIF(1)
210 #define DWC3_GUSB2PHYCFG_USBTRDTIM(n)	(n << 10)
211 #define DWC3_GUSB2PHYCFG_USBTRDTIM_MASK	DWC3_GUSB2PHYCFG_USBTRDTIM(0xf)
212 #define USBTRDTIM_UTMI_8_BIT		9
213 #define USBTRDTIM_UTMI_16_BIT		5
214 #define UTMI_PHYIF_16_BIT		1
215 #define UTMI_PHYIF_8_BIT		0
216 
217 /* Global USB2 PHY Vendor Control Register */
218 #define DWC3_GUSB2PHYACC_NEWREGREQ	BIT(25)
219 #define DWC3_GUSB2PHYACC_BUSY		BIT(23)
220 #define DWC3_GUSB2PHYACC_WRITE		BIT(22)
221 #define DWC3_GUSB2PHYACC_ADDR(n)	(n << 16)
222 #define DWC3_GUSB2PHYACC_EXTEND_ADDR(n)	(n << 8)
223 #define DWC3_GUSB2PHYACC_DATA(n)	(n & 0xff)
224 
225 /* Global USB3 PIPE Control Register */
226 #define DWC3_GUSB3PIPECTL_PHYSOFTRST	BIT(31)
227 #define DWC3_GUSB3PIPECTL_U2SSINP3OK	BIT(29)
228 #define DWC3_GUSB3PIPECTL_DISRXDETINP3	BIT(28)
229 #define DWC3_GUSB3PIPECTL_UX_EXIT_PX	BIT(27)
230 #define DWC3_GUSB3PIPECTL_REQP1P2P3	BIT(24)
231 #define DWC3_GUSB3PIPECTL_DEP1P2P3(n)	((n) << 19)
232 #define DWC3_GUSB3PIPECTL_DEP1P2P3_MASK	DWC3_GUSB3PIPECTL_DEP1P2P3(7)
233 #define DWC3_GUSB3PIPECTL_DEP1P2P3_EN	DWC3_GUSB3PIPECTL_DEP1P2P3(1)
234 #define DWC3_GUSB3PIPECTL_DEPOCHANGE	BIT(18)
235 #define DWC3_GUSB3PIPECTL_SUSPHY	BIT(17)
236 #define DWC3_GUSB3PIPECTL_LFPSFILT	BIT(9)
237 #define DWC3_GUSB3PIPECTL_RX_DETOPOLL	BIT(8)
238 #define DWC3_GUSB3PIPECTL_TX_DEEPH_MASK	DWC3_GUSB3PIPECTL_TX_DEEPH(3)
239 #define DWC3_GUSB3PIPECTL_TX_DEEPH(n)	((n) << 1)
240 
241 /* Global TX Fifo Size Register */
242 #define DWC3_GTXFIFOSIZ_TXFDEF(n)	((n) & 0xffff)
243 #define DWC3_GTXFIFOSIZ_TXFSTADDR(n)	((n) & 0xffff0000)
244 
245 /* Global Event Size Registers */
246 #define DWC3_GEVNTSIZ_INTMASK		BIT(31)
247 #define DWC3_GEVNTSIZ_SIZE(n)		((n) & 0xffff)
248 
249 /* Global HWPARAMS0 Register */
250 #define DWC3_GHWPARAMS0_MODE(n)		((n) & 0x3)
251 #define DWC3_GHWPARAMS0_MODE_GADGET	0
252 #define DWC3_GHWPARAMS0_MODE_HOST	1
253 #define DWC3_GHWPARAMS0_MODE_DRD	2
254 #define DWC3_GHWPARAMS0_MBUS_TYPE(n)	(((n) >> 3) & 0x7)
255 #define DWC3_GHWPARAMS0_SBUS_TYPE(n)	(((n) >> 6) & 0x3)
256 #define DWC3_GHWPARAMS0_MDWIDTH(n)	(((n) >> 8) & 0xff)
257 #define DWC3_GHWPARAMS0_SDWIDTH(n)	(((n) >> 16) & 0xff)
258 #define DWC3_GHWPARAMS0_AWIDTH(n)	(((n) >> 24) & 0xff)
259 
260 /* Global HWPARAMS1 Register */
261 #define DWC3_GHWPARAMS1_EN_PWROPT(n)	(((n) & (3 << 24)) >> 24)
262 #define DWC3_GHWPARAMS1_EN_PWROPT_NO	0
263 #define DWC3_GHWPARAMS1_EN_PWROPT_CLK	1
264 #define DWC3_GHWPARAMS1_EN_PWROPT_HIB	2
265 #define DWC3_GHWPARAMS1_PWROPT(n)	((n) << 24)
266 #define DWC3_GHWPARAMS1_PWROPT_MASK	DWC3_GHWPARAMS1_PWROPT(3)
267 
268 /* Global HWPARAMS3 Register */
269 #define DWC3_GHWPARAMS3_SSPHY_IFC(n)		((n) & 3)
270 #define DWC3_GHWPARAMS3_SSPHY_IFC_DIS		0
271 #define DWC3_GHWPARAMS3_SSPHY_IFC_GEN1		1
272 #define DWC3_GHWPARAMS3_SSPHY_IFC_GEN2		2 /* DWC_usb31 only */
273 #define DWC3_GHWPARAMS3_HSPHY_IFC(n)		(((n) & (3 << 2)) >> 2)
274 #define DWC3_GHWPARAMS3_HSPHY_IFC_DIS		0
275 #define DWC3_GHWPARAMS3_HSPHY_IFC_UTMI		1
276 #define DWC3_GHWPARAMS3_HSPHY_IFC_ULPI		2
277 #define DWC3_GHWPARAMS3_HSPHY_IFC_UTMI_ULPI	3
278 #define DWC3_GHWPARAMS3_FSPHY_IFC(n)		(((n) & (3 << 4)) >> 4)
279 #define DWC3_GHWPARAMS3_FSPHY_IFC_DIS		0
280 #define DWC3_GHWPARAMS3_FSPHY_IFC_ENA		1
281 
282 /* Global HWPARAMS4 Register */
283 #define DWC3_GHWPARAMS4_HIBER_SCRATCHBUFS(n)	(((n) & (0x0f << 13)) >> 13)
284 #define DWC3_MAX_HIBER_SCRATCHBUFS		15
285 
286 /* Global HWPARAMS6 Register */
287 #define DWC3_GHWPARAMS6_EN_FPGA			BIT(7)
288 
289 /* Global HWPARAMS7 Register */
290 #define DWC3_GHWPARAMS7_RAM1_DEPTH(n)	((n) & 0xffff)
291 #define DWC3_GHWPARAMS7_RAM2_DEPTH(n)	(((n) >> 16) & 0xffff)
292 
293 /* Global Frame Length Adjustment Register */
294 #define DWC3_GFLADJ_30MHZ_SDBND_SEL		BIT(7)
295 #define DWC3_GFLADJ_30MHZ_MASK			0x3f
296 
297 /* Global User Control Register 2 */
298 #define DWC3_GUCTL2_RST_ACTBITLATER		BIT(14)
299 
300 /* Device Configuration Register */
301 #define DWC3_DCFG_DEVADDR(addr)	((addr) << 3)
302 #define DWC3_DCFG_DEVADDR_MASK	DWC3_DCFG_DEVADDR(0x7f)
303 
304 #define DWC3_DCFG_SPEED_MASK	(7 << 0)
305 #define DWC3_DCFG_SUPERSPEED_PLUS (5 << 0)  /* DWC_usb31 only */
306 #define DWC3_DCFG_SUPERSPEED	(4 << 0)
307 #define DWC3_DCFG_HIGHSPEED	(0 << 0)
308 #define DWC3_DCFG_FULLSPEED	BIT(0)
309 #define DWC3_DCFG_LOWSPEED	(2 << 0)
310 
311 #define DWC3_DCFG_NUMP_SHIFT	17
312 #define DWC3_DCFG_NUMP(n)	(((n) >> DWC3_DCFG_NUMP_SHIFT) & 0x1f)
313 #define DWC3_DCFG_NUMP_MASK	(0x1f << DWC3_DCFG_NUMP_SHIFT)
314 #define DWC3_DCFG_LPM_CAP	BIT(22)
315 
316 /* Device Control Register */
317 #define DWC3_DCTL_RUN_STOP	BIT(31)
318 #define DWC3_DCTL_CSFTRST	BIT(30)
319 #define DWC3_DCTL_LSFTRST	BIT(29)
320 
321 #define DWC3_DCTL_HIRD_THRES_MASK	(0x1f << 24)
322 #define DWC3_DCTL_HIRD_THRES(n)	((n) << 24)
323 
324 #define DWC3_DCTL_APPL1RES	BIT(23)
325 
326 /* These apply for core versions 1.87a and earlier */
327 #define DWC3_DCTL_TRGTULST_MASK		(0x0f << 17)
328 #define DWC3_DCTL_TRGTULST(n)		((n) << 17)
329 #define DWC3_DCTL_TRGTULST_U2		(DWC3_DCTL_TRGTULST(2))
330 #define DWC3_DCTL_TRGTULST_U3		(DWC3_DCTL_TRGTULST(3))
331 #define DWC3_DCTL_TRGTULST_SS_DIS	(DWC3_DCTL_TRGTULST(4))
332 #define DWC3_DCTL_TRGTULST_RX_DET	(DWC3_DCTL_TRGTULST(5))
333 #define DWC3_DCTL_TRGTULST_SS_INACT	(DWC3_DCTL_TRGTULST(6))
334 
335 /* These apply for core versions 1.94a and later */
336 #define DWC3_DCTL_LPM_ERRATA_MASK	DWC3_DCTL_LPM_ERRATA(0xf)
337 #define DWC3_DCTL_LPM_ERRATA(n)		((n) << 20)
338 
339 #define DWC3_DCTL_KEEP_CONNECT		BIT(19)
340 #define DWC3_DCTL_L1_HIBER_EN		BIT(18)
341 #define DWC3_DCTL_CRS			BIT(17)
342 #define DWC3_DCTL_CSS			BIT(16)
343 
344 #define DWC3_DCTL_INITU2ENA		BIT(12)
345 #define DWC3_DCTL_ACCEPTU2ENA		BIT(11)
346 #define DWC3_DCTL_INITU1ENA		BIT(10)
347 #define DWC3_DCTL_ACCEPTU1ENA		BIT(9)
348 #define DWC3_DCTL_TSTCTRL_MASK		(0xf << 1)
349 
350 #define DWC3_DCTL_ULSTCHNGREQ_MASK	(0x0f << 5)
351 #define DWC3_DCTL_ULSTCHNGREQ(n) (((n) << 5) & DWC3_DCTL_ULSTCHNGREQ_MASK)
352 
353 #define DWC3_DCTL_ULSTCHNG_NO_ACTION	(DWC3_DCTL_ULSTCHNGREQ(0))
354 #define DWC3_DCTL_ULSTCHNG_SS_DISABLED	(DWC3_DCTL_ULSTCHNGREQ(4))
355 #define DWC3_DCTL_ULSTCHNG_RX_DETECT	(DWC3_DCTL_ULSTCHNGREQ(5))
356 #define DWC3_DCTL_ULSTCHNG_SS_INACTIVE	(DWC3_DCTL_ULSTCHNGREQ(6))
357 #define DWC3_DCTL_ULSTCHNG_RECOVERY	(DWC3_DCTL_ULSTCHNGREQ(8))
358 #define DWC3_DCTL_ULSTCHNG_COMPLIANCE	(DWC3_DCTL_ULSTCHNGREQ(10))
359 #define DWC3_DCTL_ULSTCHNG_LOOPBACK	(DWC3_DCTL_ULSTCHNGREQ(11))
360 
361 /* Device Event Enable Register */
362 #define DWC3_DEVTEN_VNDRDEVTSTRCVEDEN	BIT(12)
363 #define DWC3_DEVTEN_EVNTOVERFLOWEN	BIT(11)
364 #define DWC3_DEVTEN_CMDCMPLTEN		BIT(10)
365 #define DWC3_DEVTEN_ERRTICERREN		BIT(9)
366 #define DWC3_DEVTEN_SOFEN		BIT(7)
367 #define DWC3_DEVTEN_EOPFEN		BIT(6)
368 #define DWC3_DEVTEN_HIBERNATIONREQEVTEN	BIT(5)
369 #define DWC3_DEVTEN_WKUPEVTEN		BIT(4)
370 #define DWC3_DEVTEN_ULSTCNGEN		BIT(3)
371 #define DWC3_DEVTEN_CONNECTDONEEN	BIT(2)
372 #define DWC3_DEVTEN_USBRSTEN		BIT(1)
373 #define DWC3_DEVTEN_DISCONNEVTEN	BIT(0)
374 
375 /* Device Status Register */
376 #define DWC3_DSTS_DCNRD			BIT(29)
377 
378 /* This applies for core versions 1.87a and earlier */
379 #define DWC3_DSTS_PWRUPREQ		BIT(24)
380 
381 /* These apply for core versions 1.94a and later */
382 #define DWC3_DSTS_RSS			BIT(25)
383 #define DWC3_DSTS_SSS			BIT(24)
384 
385 #define DWC3_DSTS_COREIDLE		BIT(23)
386 #define DWC3_DSTS_DEVCTRLHLT		BIT(22)
387 
388 #define DWC3_DSTS_USBLNKST_MASK		(0x0f << 18)
389 #define DWC3_DSTS_USBLNKST(n)		(((n) & DWC3_DSTS_USBLNKST_MASK) >> 18)
390 
391 #define DWC3_DSTS_RXFIFOEMPTY		BIT(17)
392 
393 #define DWC3_DSTS_SOFFN_MASK		(0x3fff << 3)
394 #define DWC3_DSTS_SOFFN(n)		(((n) & DWC3_DSTS_SOFFN_MASK) >> 3)
395 
396 #define DWC3_DSTS_CONNECTSPD		(7 << 0)
397 
398 #define DWC3_DSTS_SUPERSPEED_PLUS	(5 << 0) /* DWC_usb31 only */
399 #define DWC3_DSTS_SUPERSPEED		(4 << 0)
400 #define DWC3_DSTS_HIGHSPEED		(0 << 0)
401 #define DWC3_DSTS_FULLSPEED		BIT(0)
402 #define DWC3_DSTS_LOWSPEED		(2 << 0)
403 
404 /* Device Generic Command Register */
405 #define DWC3_DGCMD_SET_LMP		0x01
406 #define DWC3_DGCMD_SET_PERIODIC_PAR	0x02
407 #define DWC3_DGCMD_XMIT_FUNCTION	0x03
408 
409 /* These apply for core versions 1.94a and later */
410 #define DWC3_DGCMD_SET_SCRATCHPAD_ADDR_LO	0x04
411 #define DWC3_DGCMD_SET_SCRATCHPAD_ADDR_HI	0x05
412 
413 #define DWC3_DGCMD_SELECTED_FIFO_FLUSH	0x09
414 #define DWC3_DGCMD_ALL_FIFO_FLUSH	0x0a
415 #define DWC3_DGCMD_SET_ENDPOINT_NRDY	0x0c
416 #define DWC3_DGCMD_RUN_SOC_BUS_LOOPBACK	0x10
417 
418 #define DWC3_DGCMD_STATUS(n)		(((n) >> 12) & 0x0F)
419 #define DWC3_DGCMD_CMDACT		BIT(10)
420 #define DWC3_DGCMD_CMDIOC		BIT(8)
421 
422 /* Device Generic Command Parameter Register */
423 #define DWC3_DGCMDPAR_FORCE_LINKPM_ACCEPT	BIT(0)
424 #define DWC3_DGCMDPAR_FIFO_NUM(n)		((n) << 0)
425 #define DWC3_DGCMDPAR_RX_FIFO			(0 << 5)
426 #define DWC3_DGCMDPAR_TX_FIFO			BIT(5)
427 #define DWC3_DGCMDPAR_LOOPBACK_DIS		(0 << 0)
428 #define DWC3_DGCMDPAR_LOOPBACK_ENA		BIT(0)
429 
430 /* Device Endpoint Command Register */
431 #define DWC3_DEPCMD_PARAM_SHIFT		16
432 #define DWC3_DEPCMD_PARAM(x)		((x) << DWC3_DEPCMD_PARAM_SHIFT)
433 #define DWC3_DEPCMD_GET_RSC_IDX(x)	(((x) >> DWC3_DEPCMD_PARAM_SHIFT) & 0x7f)
434 #define DWC3_DEPCMD_STATUS(x)		(((x) >> 12) & 0x0F)
435 #define DWC3_DEPCMD_HIPRI_FORCERM	BIT(11)
436 #define DWC3_DEPCMD_CLEARPENDIN		BIT(11)
437 #define DWC3_DEPCMD_CMDACT		BIT(10)
438 #define DWC3_DEPCMD_CMDIOC		BIT(8)
439 
440 #define DWC3_DEPCMD_DEPSTARTCFG		(0x09 << 0)
441 #define DWC3_DEPCMD_ENDTRANSFER		(0x08 << 0)
442 #define DWC3_DEPCMD_UPDATETRANSFER	(0x07 << 0)
443 #define DWC3_DEPCMD_STARTTRANSFER	(0x06 << 0)
444 #define DWC3_DEPCMD_CLEARSTALL		(0x05 << 0)
445 #define DWC3_DEPCMD_SETSTALL		(0x04 << 0)
446 /* This applies for core versions 1.90a and earlier */
447 #define DWC3_DEPCMD_GETSEQNUMBER	(0x03 << 0)
448 /* This applies for core versions 1.94a and later */
449 #define DWC3_DEPCMD_GETEPSTATE		(0x03 << 0)
450 #define DWC3_DEPCMD_SETTRANSFRESOURCE	(0x02 << 0)
451 #define DWC3_DEPCMD_SETEPCONFIG		(0x01 << 0)
452 
453 #define DWC3_DEPCMD_CMD(x)		((x) & 0xf)
454 
455 /* The EP number goes 0..31 so ep0 is always out and ep1 is always in */
456 #define DWC3_DALEPENA_EP(n)		BIT(n)
457 
458 #define DWC3_DEPCMD_TYPE_CONTROL	0
459 #define DWC3_DEPCMD_TYPE_ISOC		1
460 #define DWC3_DEPCMD_TYPE_BULK		2
461 #define DWC3_DEPCMD_TYPE_INTR		3
462 
463 #define DWC3_DEV_IMOD_COUNT_SHIFT	16
464 #define DWC3_DEV_IMOD_COUNT_MASK	(0xffff << 16)
465 #define DWC3_DEV_IMOD_INTERVAL_SHIFT	0
466 #define DWC3_DEV_IMOD_INTERVAL_MASK	(0xffff << 0)
467 
468 /* Structures */
469 
470 struct dwc3_trb;
471 
472 /**
473  * struct dwc3_event_buffer - Software event buffer representation
474  * @buf: _THE_ buffer
475  * @cache: The buffer cache used in the threaded interrupt
476  * @length: size of this buffer
477  * @lpos: event offset
478  * @count: cache of last read event count register
479  * @flags: flags related to this event buffer
480  * @dma: dma_addr_t
481  * @dwc: pointer to DWC controller
482  */
483 struct dwc3_event_buffer {
484 	void			*buf;
485 	void			*cache;
486 	unsigned		length;
487 	unsigned int		lpos;
488 	unsigned int		count;
489 	unsigned int		flags;
490 
491 #define DWC3_EVENT_PENDING	BIT(0)
492 
493 	dma_addr_t		dma;
494 
495 	struct dwc3		*dwc;
496 };
497 
498 #define DWC3_EP_FLAG_STALLED	BIT(0)
499 #define DWC3_EP_FLAG_WEDGED	BIT(1)
500 
501 #define DWC3_EP_DIRECTION_TX	true
502 #define DWC3_EP_DIRECTION_RX	false
503 
504 #define DWC3_TRB_NUM		256
505 
506 /**
507  * struct dwc3_ep - device side endpoint representation
508  * @endpoint: usb endpoint
509  * @pending_list: list of pending requests for this endpoint
510  * @started_list: list of started requests on this endpoint
511  * @wait_end_transfer: wait_queue_head_t for waiting on End Transfer complete
512  * @lock: spinlock for endpoint request queue traversal
513  * @regs: pointer to first endpoint register
514  * @trb_pool: array of transaction buffers
515  * @trb_pool_dma: dma address of @trb_pool
516  * @trb_enqueue: enqueue 'pointer' into TRB array
517  * @trb_dequeue: dequeue 'pointer' into TRB array
518  * @dwc: pointer to DWC controller
519  * @saved_state: ep state saved during hibernation
520  * @flags: endpoint flags (wedged, stalled, ...)
521  * @number: endpoint number (1 - 15)
522  * @type: set to bmAttributes & USB_ENDPOINT_XFERTYPE_MASK
523  * @resource_index: Resource transfer index
524  * @frame_number: set to the frame number we want this transfer to start (ISOC)
525  * @interval: the interval on which the ISOC transfer is started
526  * @allocated_requests: number of requests allocated
527  * @queued_requests: number of requests queued for transfer
528  * @name: a human readable name e.g. ep1out-bulk
529  * @direction: true for TX, false for RX
530  * @stream_capable: true when streams are enabled
531  */
532 struct dwc3_ep {
533 	struct usb_ep		endpoint;
534 	struct list_head	pending_list;
535 	struct list_head	started_list;
536 
537 	wait_queue_head_t	wait_end_transfer;
538 
539 	spinlock_t		lock;
540 	void __iomem		*regs;
541 
542 	struct dwc3_trb		*trb_pool;
543 	dma_addr_t		trb_pool_dma;
544 	struct dwc3		*dwc;
545 
546 	u32			saved_state;
547 	unsigned		flags;
548 #define DWC3_EP_ENABLED		BIT(0)
549 #define DWC3_EP_STALL		BIT(1)
550 #define DWC3_EP_WEDGE		BIT(2)
551 #define DWC3_EP_BUSY		BIT(4)
552 #define DWC3_EP_PENDING_REQUEST	BIT(5)
553 #define DWC3_EP_MISSED_ISOC	BIT(6)
554 #define DWC3_EP_END_TRANSFER_PENDING	BIT(7)
555 #define DWC3_EP_TRANSFER_STARTED BIT(8)
556 
557 	/* This last one is specific to EP0 */
558 #define DWC3_EP0_DIR_IN		BIT(31)
559 
560 	/*
561 	 * IMPORTANT: we *know* we have 256 TRBs in our @trb_pool, so we will
562 	 * use a u8 type here. If anybody decides to increase number of TRBs to
563 	 * anything larger than 256 - I can't see why people would want to do
564 	 * this though - then this type needs to be changed.
565 	 *
566 	 * By using u8 types we ensure that our % operator when incrementing
567 	 * enqueue and dequeue get optimized away by the compiler.
568 	 */
569 	u8			trb_enqueue;
570 	u8			trb_dequeue;
571 
572 	u8			number;
573 	u8			type;
574 	u8			resource_index;
575 	u32			allocated_requests;
576 	u32			queued_requests;
577 	u32			frame_number;
578 	u32			interval;
579 
580 	char			name[20];
581 
582 	unsigned		direction:1;
583 	unsigned		stream_capable:1;
584 };
585 
586 enum dwc3_phy {
587 	DWC3_PHY_UNKNOWN = 0,
588 	DWC3_PHY_USB3,
589 	DWC3_PHY_USB2,
590 };
591 
592 enum dwc3_ep0_next {
593 	DWC3_EP0_UNKNOWN = 0,
594 	DWC3_EP0_COMPLETE,
595 	DWC3_EP0_NRDY_DATA,
596 	DWC3_EP0_NRDY_STATUS,
597 };
598 
599 enum dwc3_ep0_state {
600 	EP0_UNCONNECTED		= 0,
601 	EP0_SETUP_PHASE,
602 	EP0_DATA_PHASE,
603 	EP0_STATUS_PHASE,
604 };
605 
606 enum dwc3_link_state {
607 	/* In SuperSpeed */
608 	DWC3_LINK_STATE_U0		= 0x00, /* in HS, means ON */
609 	DWC3_LINK_STATE_U1		= 0x01,
610 	DWC3_LINK_STATE_U2		= 0x02, /* in HS, means SLEEP */
611 	DWC3_LINK_STATE_U3		= 0x03, /* in HS, means SUSPEND */
612 	DWC3_LINK_STATE_SS_DIS		= 0x04,
613 	DWC3_LINK_STATE_RX_DET		= 0x05, /* in HS, means Early Suspend */
614 	DWC3_LINK_STATE_SS_INACT	= 0x06,
615 	DWC3_LINK_STATE_POLL		= 0x07,
616 	DWC3_LINK_STATE_RECOV		= 0x08,
617 	DWC3_LINK_STATE_HRESET		= 0x09,
618 	DWC3_LINK_STATE_CMPLY		= 0x0a,
619 	DWC3_LINK_STATE_LPBK		= 0x0b,
620 	DWC3_LINK_STATE_RESET		= 0x0e,
621 	DWC3_LINK_STATE_RESUME		= 0x0f,
622 	DWC3_LINK_STATE_MASK		= 0x0f,
623 };
624 
625 /* TRB Length, PCM and Status */
626 #define DWC3_TRB_SIZE_MASK	(0x00ffffff)
627 #define DWC3_TRB_SIZE_LENGTH(n)	((n) & DWC3_TRB_SIZE_MASK)
628 #define DWC3_TRB_SIZE_PCM1(n)	(((n) & 0x03) << 24)
629 #define DWC3_TRB_SIZE_TRBSTS(n)	(((n) & (0x0f << 28)) >> 28)
630 
631 #define DWC3_TRBSTS_OK			0
632 #define DWC3_TRBSTS_MISSED_ISOC		1
633 #define DWC3_TRBSTS_SETUP_PENDING	2
634 #define DWC3_TRB_STS_XFER_IN_PROG	4
635 
636 /* TRB Control */
637 #define DWC3_TRB_CTRL_HWO		BIT(0)
638 #define DWC3_TRB_CTRL_LST		BIT(1)
639 #define DWC3_TRB_CTRL_CHN		BIT(2)
640 #define DWC3_TRB_CTRL_CSP		BIT(3)
641 #define DWC3_TRB_CTRL_TRBCTL(n)		(((n) & 0x3f) << 4)
642 #define DWC3_TRB_CTRL_ISP_IMI		BIT(10)
643 #define DWC3_TRB_CTRL_IOC		BIT(11)
644 #define DWC3_TRB_CTRL_SID_SOFN(n)	(((n) & 0xffff) << 14)
645 
646 #define DWC3_TRBCTL_TYPE(n)		((n) & (0x3f << 4))
647 #define DWC3_TRBCTL_NORMAL		DWC3_TRB_CTRL_TRBCTL(1)
648 #define DWC3_TRBCTL_CONTROL_SETUP	DWC3_TRB_CTRL_TRBCTL(2)
649 #define DWC3_TRBCTL_CONTROL_STATUS2	DWC3_TRB_CTRL_TRBCTL(3)
650 #define DWC3_TRBCTL_CONTROL_STATUS3	DWC3_TRB_CTRL_TRBCTL(4)
651 #define DWC3_TRBCTL_CONTROL_DATA	DWC3_TRB_CTRL_TRBCTL(5)
652 #define DWC3_TRBCTL_ISOCHRONOUS_FIRST	DWC3_TRB_CTRL_TRBCTL(6)
653 #define DWC3_TRBCTL_ISOCHRONOUS		DWC3_TRB_CTRL_TRBCTL(7)
654 #define DWC3_TRBCTL_LINK_TRB		DWC3_TRB_CTRL_TRBCTL(8)
655 
656 /**
657  * struct dwc3_trb - transfer request block (hw format)
658  * @bpl: DW0-3
659  * @bph: DW4-7
660  * @size: DW8-B
661  * @ctrl: DWC-F
662  */
663 struct dwc3_trb {
664 	u32		bpl;
665 	u32		bph;
666 	u32		size;
667 	u32		ctrl;
668 } __packed;
669 
670 /**
671  * struct dwc3_hwparams - copy of HWPARAMS registers
672  * @hwparams0: GHWPARAMS0
673  * @hwparams1: GHWPARAMS1
674  * @hwparams2: GHWPARAMS2
675  * @hwparams3: GHWPARAMS3
676  * @hwparams4: GHWPARAMS4
677  * @hwparams5: GHWPARAMS5
678  * @hwparams6: GHWPARAMS6
679  * @hwparams7: GHWPARAMS7
680  * @hwparams8: GHWPARAMS8
681  */
682 struct dwc3_hwparams {
683 	u32	hwparams0;
684 	u32	hwparams1;
685 	u32	hwparams2;
686 	u32	hwparams3;
687 	u32	hwparams4;
688 	u32	hwparams5;
689 	u32	hwparams6;
690 	u32	hwparams7;
691 	u32	hwparams8;
692 };
693 
694 /* HWPARAMS0 */
695 #define DWC3_MODE(n)		((n) & 0x7)
696 
697 #define DWC3_MDWIDTH(n)		(((n) & 0xff00) >> 8)
698 
699 /* HWPARAMS1 */
700 #define DWC3_NUM_INT(n)		(((n) & (0x3f << 15)) >> 15)
701 
702 /* HWPARAMS3 */
703 #define DWC3_NUM_IN_EPS_MASK	(0x1f << 18)
704 #define DWC3_NUM_EPS_MASK	(0x3f << 12)
705 #define DWC3_NUM_EPS(p)		(((p)->hwparams3 &		\
706 			(DWC3_NUM_EPS_MASK)) >> 12)
707 #define DWC3_NUM_IN_EPS(p)	(((p)->hwparams3 &		\
708 			(DWC3_NUM_IN_EPS_MASK)) >> 18)
709 
710 /* HWPARAMS7 */
711 #define DWC3_RAM1_DEPTH(n)	((n) & 0xffff)
712 
713 /**
714  * struct dwc3_request - representation of a transfer request
715  * @request: struct usb_request to be transferred
716  * @list: a list_head used for request queueing
717  * @dep: struct dwc3_ep owning this request
718  * @sg: pointer to first incomplete sg
719  * @num_pending_sgs: counter to pending sgs
720  * @remaining: amount of data remaining
721  * @epnum: endpoint number to which this request refers
722  * @trb: pointer to struct dwc3_trb
723  * @trb_dma: DMA address of @trb
724  * @unaligned: true for OUT endpoints with length not divisible by maxp
725  * @direction: IN or OUT direction flag
726  * @mapped: true when request has been dma-mapped
727  * @started: request is started
728  * @zero: wants a ZLP
729  */
730 struct dwc3_request {
731 	struct usb_request	request;
732 	struct list_head	list;
733 	struct dwc3_ep		*dep;
734 	struct scatterlist	*sg;
735 
736 	unsigned		num_pending_sgs;
737 	unsigned		remaining;
738 	u8			epnum;
739 	struct dwc3_trb		*trb;
740 	dma_addr_t		trb_dma;
741 
742 	unsigned		unaligned:1;
743 	unsigned		direction:1;
744 	unsigned		mapped:1;
745 	unsigned		started:1;
746 	unsigned		zero:1;
747 };
748 
749 /*
750  * struct dwc3_scratchpad_array - hibernation scratchpad array
751  * (format defined by hw)
752  */
753 struct dwc3_scratchpad_array {
754 	__le64	dma_adr[DWC3_MAX_HIBER_SCRATCHBUFS];
755 };
756 
757 /**
758  * struct dwc3 - representation of our controller
759  * @drd_work: workqueue used for role swapping
760  * @ep0_trb: trb which is used for the ctrl_req
761  * @bounce: address of bounce buffer
762  * @scratchbuf: address of scratch buffer
763  * @setup_buf: used while precessing STD USB requests
764  * @ep0_trb_addr: dma address of @ep0_trb
765  * @bounce_addr: dma address of @bounce
766  * @ep0_usb_req: dummy req used while handling STD USB requests
767  * @scratch_addr: dma address of scratchbuf
768  * @ep0_in_setup: one control transfer is completed and enter setup phase
769  * @lock: for synchronizing
770  * @dev: pointer to our struct device
771  * @sysdev: pointer to the DMA-capable device
772  * @xhci: pointer to our xHCI child
773  * @xhci_resources: struct resources for our @xhci child
774  * @ev_buf: struct dwc3_event_buffer pointer
775  * @eps: endpoint array
776  * @gadget: device side representation of the peripheral controller
777  * @gadget_driver: pointer to the gadget driver
778  * @regs: base address for our registers
779  * @regs_size: address space size
780  * @fladj: frame length adjustment
781  * @irq_gadget: peripheral controller's IRQ number
782  * @nr_scratch: number of scratch buffers
783  * @u1u2: only used on revisions <1.83a for workaround
784  * @maximum_speed: maximum speed requested (mainly for testing purposes)
785  * @revision: revision register contents
786  * @dr_mode: requested mode of operation
787  * @current_dr_role: current role of operation when in dual-role mode
788  * @desired_dr_role: desired role of operation when in dual-role mode
789  * @edev: extcon handle
790  * @edev_nb: extcon notifier
791  * @hsphy_mode: UTMI phy mode, one of following:
792  *		- USBPHY_INTERFACE_MODE_UTMI
793  *		- USBPHY_INTERFACE_MODE_UTMIW
794  * @usb2_phy: pointer to USB2 PHY
795  * @usb3_phy: pointer to USB3 PHY
796  * @usb2_generic_phy: pointer to USB2 PHY
797  * @usb3_generic_phy: pointer to USB3 PHY
798  * @ulpi: pointer to ulpi interface
799  * @isoch_delay: wValue from Set Isochronous Delay request;
800  * @u2sel: parameter from Set SEL request.
801  * @u2pel: parameter from Set SEL request.
802  * @u1sel: parameter from Set SEL request.
803  * @u1pel: parameter from Set SEL request.
804  * @num_eps: number of endpoints
805  * @ep0_next_event: hold the next expected event
806  * @ep0state: state of endpoint zero
807  * @link_state: link state
808  * @speed: device speed (super, high, full, low)
809  * @hwparams: copy of hwparams registers
810  * @root: debugfs root folder pointer
811  * @regset: debugfs pointer to regdump file
812  * @test_mode: true when we're entering a USB test mode
813  * @test_mode_nr: test feature selector
814  * @lpm_nyet_threshold: LPM NYET response threshold
815  * @hird_threshold: HIRD threshold
816  * @hsphy_interface: "utmi" or "ulpi"
817  * @connected: true when we're connected to a host, false otherwise
818  * @delayed_status: true when gadget driver asks for delayed status
819  * @ep0_bounced: true when we used bounce buffer
820  * @ep0_expect_in: true when we expect a DATA IN transfer
821  * @has_hibernation: true when dwc3 was configured with Hibernation
822  * @sysdev_is_parent: true when dwc3 device has a parent driver
823  * @has_lpm_erratum: true when core was configured with LPM Erratum. Note that
824  *			there's now way for software to detect this in runtime.
825  * @is_utmi_l1_suspend: the core asserts output signal
826  * 	0	- utmi_sleep_n
827  * 	1	- utmi_l1_suspend_n
828  * @is_fpga: true when we are using the FPGA board
829  * @pending_events: true when we have pending IRQs to be handled
830  * @pullups_connected: true when Run/Stop bit is set
831  * @setup_packet_pending: true when there's a Setup Packet in FIFO. Workaround
832  * @three_stage_setup: set if we perform a three phase setup
833  * @usb3_lpm_capable: set if hadrware supports Link Power Management
834  * @disable_scramble_quirk: set if we enable the disable scramble quirk
835  * @u2exit_lfps_quirk: set if we enable u2exit lfps quirk
836  * @u2ss_inp3_quirk: set if we enable P3 OK for U2/SS Inactive quirk
837  * @req_p1p2p3_quirk: set if we enable request p1p2p3 quirk
838  * @del_p1p2p3_quirk: set if we enable delay p1p2p3 quirk
839  * @del_phy_power_chg_quirk: set if we enable delay phy power change quirk
840  * @lfps_filter_quirk: set if we enable LFPS filter quirk
841  * @rx_detect_poll_quirk: set if we enable rx_detect to polling lfps quirk
842  * @dis_u3_susphy_quirk: set if we disable usb3 suspend phy
843  * @dis_u2_susphy_quirk: set if we disable usb2 suspend phy
844  * @dis_enblslpm_quirk: set if we clear enblslpm in GUSB2PHYCFG,
845  *                      disabling the suspend signal to the PHY.
846  * @dis_rxdet_inp3_quirk: set if we disable Rx.Detect in P3
847  * @dis_u2_freeclk_exists_quirk : set if we clear u2_freeclk_exists
848  *			in GUSB2PHYCFG, specify that USB2 PHY doesn't
849  *			provide a free-running PHY clock.
850  * @dis_del_phy_power_chg_quirk: set if we disable delay phy power
851  *			change quirk.
852  * @dis_tx_ipgap_linecheck_quirk: set if we disable u2mac linestate
853  *			check during HS transmit.
854  * @tx_de_emphasis_quirk: set if we enable Tx de-emphasis quirk
855  * @tx_de_emphasis: Tx de-emphasis value
856  * 	0	- -6dB de-emphasis
857  * 	1	- -3.5dB de-emphasis
858  * 	2	- No de-emphasis
859  * 	3	- Reserved
860  * @imod_interval: set the interrupt moderation interval in 250ns
861  *                 increments or 0 to disable.
862  */
863 struct dwc3 {
864 	struct work_struct	drd_work;
865 	struct dwc3_trb		*ep0_trb;
866 	void			*bounce;
867 	void			*scratchbuf;
868 	u8			*setup_buf;
869 	dma_addr_t		ep0_trb_addr;
870 	dma_addr_t		bounce_addr;
871 	dma_addr_t		scratch_addr;
872 	struct dwc3_request	ep0_usb_req;
873 	struct completion	ep0_in_setup;
874 
875 	/* device lock */
876 	spinlock_t		lock;
877 
878 	struct device		*dev;
879 	struct device		*sysdev;
880 
881 	struct platform_device	*xhci;
882 	struct resource		xhci_resources[DWC3_XHCI_RESOURCES_NUM];
883 
884 	struct dwc3_event_buffer *ev_buf;
885 	struct dwc3_ep		*eps[DWC3_ENDPOINTS_NUM];
886 
887 	struct usb_gadget	gadget;
888 	struct usb_gadget_driver *gadget_driver;
889 
890 	struct usb_phy		*usb2_phy;
891 	struct usb_phy		*usb3_phy;
892 
893 	struct phy		*usb2_generic_phy;
894 	struct phy		*usb3_generic_phy;
895 
896 	struct ulpi		*ulpi;
897 
898 	void __iomem		*regs;
899 	size_t			regs_size;
900 
901 	enum usb_dr_mode	dr_mode;
902 	u32			current_dr_role;
903 	u32			desired_dr_role;
904 	struct extcon_dev	*edev;
905 	struct notifier_block	edev_nb;
906 	enum usb_phy_interface	hsphy_mode;
907 
908 	u32			fladj;
909 	u32			irq_gadget;
910 	u32			nr_scratch;
911 	u32			u1u2;
912 	u32			maximum_speed;
913 
914 	/*
915 	 * All 3.1 IP version constants are greater than the 3.0 IP
916 	 * version constants. This works for most version checks in
917 	 * dwc3. However, in the future, this may not apply as
918 	 * features may be developed on newer versions of the 3.0 IP
919 	 * that are not in the 3.1 IP.
920 	 */
921 	u32			revision;
922 
923 #define DWC3_REVISION_173A	0x5533173a
924 #define DWC3_REVISION_175A	0x5533175a
925 #define DWC3_REVISION_180A	0x5533180a
926 #define DWC3_REVISION_183A	0x5533183a
927 #define DWC3_REVISION_185A	0x5533185a
928 #define DWC3_REVISION_187A	0x5533187a
929 #define DWC3_REVISION_188A	0x5533188a
930 #define DWC3_REVISION_190A	0x5533190a
931 #define DWC3_REVISION_194A	0x5533194a
932 #define DWC3_REVISION_200A	0x5533200a
933 #define DWC3_REVISION_202A	0x5533202a
934 #define DWC3_REVISION_210A	0x5533210a
935 #define DWC3_REVISION_220A	0x5533220a
936 #define DWC3_REVISION_230A	0x5533230a
937 #define DWC3_REVISION_240A	0x5533240a
938 #define DWC3_REVISION_250A	0x5533250a
939 #define DWC3_REVISION_260A	0x5533260a
940 #define DWC3_REVISION_270A	0x5533270a
941 #define DWC3_REVISION_280A	0x5533280a
942 #define DWC3_REVISION_290A	0x5533290a
943 #define DWC3_REVISION_300A	0x5533300a
944 #define DWC3_REVISION_310A	0x5533310a
945 
946 /*
947  * NOTICE: we're using bit 31 as a "is usb 3.1" flag. This is really
948  * just so dwc31 revisions are always larger than dwc3.
949  */
950 #define DWC3_REVISION_IS_DWC31		0x80000000
951 #define DWC3_USB31_REVISION_110A	(0x3131302a | DWC3_REVISION_IS_DWC31)
952 #define DWC3_USB31_REVISION_120A	(0x3132302a | DWC3_REVISION_IS_DWC31)
953 
954 	enum dwc3_ep0_next	ep0_next_event;
955 	enum dwc3_ep0_state	ep0state;
956 	enum dwc3_link_state	link_state;
957 
958 	u16			isoch_delay;
959 	u16			u2sel;
960 	u16			u2pel;
961 	u8			u1sel;
962 	u8			u1pel;
963 
964 	u8			speed;
965 
966 	u8			num_eps;
967 
968 	struct dwc3_hwparams	hwparams;
969 	struct dentry		*root;
970 	struct debugfs_regset32	*regset;
971 
972 	u8			test_mode;
973 	u8			test_mode_nr;
974 	u8			lpm_nyet_threshold;
975 	u8			hird_threshold;
976 
977 	const char		*hsphy_interface;
978 
979 	unsigned		connected:1;
980 	unsigned		delayed_status:1;
981 	unsigned		ep0_bounced:1;
982 	unsigned		ep0_expect_in:1;
983 	unsigned		has_hibernation:1;
984 	unsigned		sysdev_is_parent:1;
985 	unsigned		has_lpm_erratum:1;
986 	unsigned		is_utmi_l1_suspend:1;
987 	unsigned		is_fpga:1;
988 	unsigned		pending_events:1;
989 	unsigned		pullups_connected:1;
990 	unsigned		setup_packet_pending:1;
991 	unsigned		three_stage_setup:1;
992 	unsigned		usb3_lpm_capable:1;
993 
994 	unsigned		disable_scramble_quirk:1;
995 	unsigned		u2exit_lfps_quirk:1;
996 	unsigned		u2ss_inp3_quirk:1;
997 	unsigned		req_p1p2p3_quirk:1;
998 	unsigned                del_p1p2p3_quirk:1;
999 	unsigned		del_phy_power_chg_quirk:1;
1000 	unsigned		lfps_filter_quirk:1;
1001 	unsigned		rx_detect_poll_quirk:1;
1002 	unsigned		dis_u3_susphy_quirk:1;
1003 	unsigned		dis_u2_susphy_quirk:1;
1004 	unsigned		dis_enblslpm_quirk:1;
1005 	unsigned		dis_rxdet_inp3_quirk:1;
1006 	unsigned		dis_u2_freeclk_exists_quirk:1;
1007 	unsigned		dis_del_phy_power_chg_quirk:1;
1008 	unsigned		dis_tx_ipgap_linecheck_quirk:1;
1009 
1010 	unsigned		tx_de_emphasis_quirk:1;
1011 	unsigned		tx_de_emphasis:2;
1012 
1013 	u16			imod_interval;
1014 };
1015 
1016 #define work_to_dwc(w)		(container_of((w), struct dwc3, drd_work))
1017 
1018 /* -------------------------------------------------------------------------- */
1019 
1020 struct dwc3_event_type {
1021 	u32	is_devspec:1;
1022 	u32	type:7;
1023 	u32	reserved8_31:24;
1024 } __packed;
1025 
1026 #define DWC3_DEPEVT_XFERCOMPLETE	0x01
1027 #define DWC3_DEPEVT_XFERINPROGRESS	0x02
1028 #define DWC3_DEPEVT_XFERNOTREADY	0x03
1029 #define DWC3_DEPEVT_RXTXFIFOEVT		0x04
1030 #define DWC3_DEPEVT_STREAMEVT		0x06
1031 #define DWC3_DEPEVT_EPCMDCMPLT		0x07
1032 
1033 /**
1034  * struct dwc3_event_depvt - Device Endpoint Events
1035  * @one_bit: indicates this is an endpoint event (not used)
1036  * @endpoint_number: number of the endpoint
1037  * @endpoint_event: The event we have:
1038  *	0x00	- Reserved
1039  *	0x01	- XferComplete
1040  *	0x02	- XferInProgress
1041  *	0x03	- XferNotReady
1042  *	0x04	- RxTxFifoEvt (IN->Underrun, OUT->Overrun)
1043  *	0x05	- Reserved
1044  *	0x06	- StreamEvt
1045  *	0x07	- EPCmdCmplt
1046  * @reserved11_10: Reserved, don't use.
1047  * @status: Indicates the status of the event. Refer to databook for
1048  *	more information.
1049  * @parameters: Parameters of the current event. Refer to databook for
1050  *	more information.
1051  */
1052 struct dwc3_event_depevt {
1053 	u32	one_bit:1;
1054 	u32	endpoint_number:5;
1055 	u32	endpoint_event:4;
1056 	u32	reserved11_10:2;
1057 	u32	status:4;
1058 
1059 /* Within XferNotReady */
1060 #define DEPEVT_STATUS_TRANSFER_ACTIVE	BIT(3)
1061 
1062 /* Within XferComplete */
1063 #define DEPEVT_STATUS_BUSERR	BIT(0)
1064 #define DEPEVT_STATUS_SHORT	BIT(1)
1065 #define DEPEVT_STATUS_IOC	BIT(2)
1066 #define DEPEVT_STATUS_LST	BIT(3)
1067 
1068 /* Stream event only */
1069 #define DEPEVT_STREAMEVT_FOUND		1
1070 #define DEPEVT_STREAMEVT_NOTFOUND	2
1071 
1072 /* Control-only Status */
1073 #define DEPEVT_STATUS_CONTROL_DATA	1
1074 #define DEPEVT_STATUS_CONTROL_STATUS	2
1075 #define DEPEVT_STATUS_CONTROL_PHASE(n)	((n) & 3)
1076 
1077 /* In response to Start Transfer */
1078 #define DEPEVT_TRANSFER_NO_RESOURCE	1
1079 #define DEPEVT_TRANSFER_BUS_EXPIRY	2
1080 
1081 	u32	parameters:16;
1082 
1083 /* For Command Complete Events */
1084 #define DEPEVT_PARAMETER_CMD(n)	(((n) & (0xf << 8)) >> 8)
1085 } __packed;
1086 
1087 /**
1088  * struct dwc3_event_devt - Device Events
1089  * @one_bit: indicates this is a non-endpoint event (not used)
1090  * @device_event: indicates it's a device event. Should read as 0x00
1091  * @type: indicates the type of device event.
1092  *	0	- DisconnEvt
1093  *	1	- USBRst
1094  *	2	- ConnectDone
1095  *	3	- ULStChng
1096  *	4	- WkUpEvt
1097  *	5	- Reserved
1098  *	6	- EOPF
1099  *	7	- SOF
1100  *	8	- Reserved
1101  *	9	- ErrticErr
1102  *	10	- CmdCmplt
1103  *	11	- EvntOverflow
1104  *	12	- VndrDevTstRcved
1105  * @reserved15_12: Reserved, not used
1106  * @event_info: Information about this event
1107  * @reserved31_25: Reserved, not used
1108  */
1109 struct dwc3_event_devt {
1110 	u32	one_bit:1;
1111 	u32	device_event:7;
1112 	u32	type:4;
1113 	u32	reserved15_12:4;
1114 	u32	event_info:9;
1115 	u32	reserved31_25:7;
1116 } __packed;
1117 
1118 /**
1119  * struct dwc3_event_gevt - Other Core Events
1120  * @one_bit: indicates this is a non-endpoint event (not used)
1121  * @device_event: indicates it's (0x03) Carkit or (0x04) I2C event.
1122  * @phy_port_number: self-explanatory
1123  * @reserved31_12: Reserved, not used.
1124  */
1125 struct dwc3_event_gevt {
1126 	u32	one_bit:1;
1127 	u32	device_event:7;
1128 	u32	phy_port_number:4;
1129 	u32	reserved31_12:20;
1130 } __packed;
1131 
1132 /**
1133  * union dwc3_event - representation of Event Buffer contents
1134  * @raw: raw 32-bit event
1135  * @type: the type of the event
1136  * @depevt: Device Endpoint Event
1137  * @devt: Device Event
1138  * @gevt: Global Event
1139  */
1140 union dwc3_event {
1141 	u32				raw;
1142 	struct dwc3_event_type		type;
1143 	struct dwc3_event_depevt	depevt;
1144 	struct dwc3_event_devt		devt;
1145 	struct dwc3_event_gevt		gevt;
1146 };
1147 
1148 /**
1149  * struct dwc3_gadget_ep_cmd_params - representation of endpoint command
1150  * parameters
1151  * @param2: third parameter
1152  * @param1: second parameter
1153  * @param0: first parameter
1154  */
1155 struct dwc3_gadget_ep_cmd_params {
1156 	u32	param2;
1157 	u32	param1;
1158 	u32	param0;
1159 };
1160 
1161 /*
1162  * DWC3 Features to be used as Driver Data
1163  */
1164 
1165 #define DWC3_HAS_PERIPHERAL		BIT(0)
1166 #define DWC3_HAS_XHCI			BIT(1)
1167 #define DWC3_HAS_OTG			BIT(3)
1168 
1169 /* prototypes */
1170 void dwc3_set_mode(struct dwc3 *dwc, u32 mode);
1171 u32 dwc3_core_fifo_space(struct dwc3_ep *dep, u8 type);
1172 
1173 /* check whether we are on the DWC_usb3 core */
1174 static inline bool dwc3_is_usb3(struct dwc3 *dwc)
1175 {
1176 	return !(dwc->revision & DWC3_REVISION_IS_DWC31);
1177 }
1178 
1179 /* check whether we are on the DWC_usb31 core */
1180 static inline bool dwc3_is_usb31(struct dwc3 *dwc)
1181 {
1182 	return !!(dwc->revision & DWC3_REVISION_IS_DWC31);
1183 }
1184 
1185 bool dwc3_has_imod(struct dwc3 *dwc);
1186 
1187 #if IS_ENABLED(CONFIG_USB_DWC3_HOST) || IS_ENABLED(CONFIG_USB_DWC3_DUAL_ROLE)
1188 int dwc3_host_init(struct dwc3 *dwc);
1189 void dwc3_host_exit(struct dwc3 *dwc);
1190 #else
1191 static inline int dwc3_host_init(struct dwc3 *dwc)
1192 { return 0; }
1193 static inline void dwc3_host_exit(struct dwc3 *dwc)
1194 { }
1195 #endif
1196 
1197 #if IS_ENABLED(CONFIG_USB_DWC3_GADGET) || IS_ENABLED(CONFIG_USB_DWC3_DUAL_ROLE)
1198 int dwc3_gadget_init(struct dwc3 *dwc);
1199 void dwc3_gadget_exit(struct dwc3 *dwc);
1200 int dwc3_gadget_set_test_mode(struct dwc3 *dwc, int mode);
1201 int dwc3_gadget_get_link_state(struct dwc3 *dwc);
1202 int dwc3_gadget_set_link_state(struct dwc3 *dwc, enum dwc3_link_state state);
1203 int dwc3_send_gadget_ep_cmd(struct dwc3_ep *dep, unsigned cmd,
1204 		struct dwc3_gadget_ep_cmd_params *params);
1205 int dwc3_send_gadget_generic_command(struct dwc3 *dwc, unsigned cmd, u32 param);
1206 #else
1207 static inline int dwc3_gadget_init(struct dwc3 *dwc)
1208 { return 0; }
1209 static inline void dwc3_gadget_exit(struct dwc3 *dwc)
1210 { }
1211 static inline int dwc3_gadget_set_test_mode(struct dwc3 *dwc, int mode)
1212 { return 0; }
1213 static inline int dwc3_gadget_get_link_state(struct dwc3 *dwc)
1214 { return 0; }
1215 static inline int dwc3_gadget_set_link_state(struct dwc3 *dwc,
1216 		enum dwc3_link_state state)
1217 { return 0; }
1218 
1219 static inline int dwc3_send_gadget_ep_cmd(struct dwc3_ep *dep, unsigned cmd,
1220 		struct dwc3_gadget_ep_cmd_params *params)
1221 { return 0; }
1222 static inline int dwc3_send_gadget_generic_command(struct dwc3 *dwc,
1223 		int cmd, u32 param)
1224 { return 0; }
1225 #endif
1226 
1227 #if IS_ENABLED(CONFIG_USB_DWC3_DUAL_ROLE)
1228 int dwc3_drd_init(struct dwc3 *dwc);
1229 void dwc3_drd_exit(struct dwc3 *dwc);
1230 #else
1231 static inline int dwc3_drd_init(struct dwc3 *dwc)
1232 { return 0; }
1233 static inline void dwc3_drd_exit(struct dwc3 *dwc)
1234 { }
1235 #endif
1236 
1237 /* power management interface */
1238 #if !IS_ENABLED(CONFIG_USB_DWC3_HOST)
1239 int dwc3_gadget_suspend(struct dwc3 *dwc);
1240 int dwc3_gadget_resume(struct dwc3 *dwc);
1241 void dwc3_gadget_process_pending_events(struct dwc3 *dwc);
1242 #else
1243 static inline int dwc3_gadget_suspend(struct dwc3 *dwc)
1244 {
1245 	return 0;
1246 }
1247 
1248 static inline int dwc3_gadget_resume(struct dwc3 *dwc)
1249 {
1250 	return 0;
1251 }
1252 
1253 static inline void dwc3_gadget_process_pending_events(struct dwc3 *dwc)
1254 {
1255 }
1256 #endif /* !IS_ENABLED(CONFIG_USB_DWC3_HOST) */
1257 
1258 #if IS_ENABLED(CONFIG_USB_DWC3_ULPI)
1259 int dwc3_ulpi_init(struct dwc3 *dwc);
1260 void dwc3_ulpi_exit(struct dwc3 *dwc);
1261 #else
1262 static inline int dwc3_ulpi_init(struct dwc3 *dwc)
1263 { return 0; }
1264 static inline void dwc3_ulpi_exit(struct dwc3 *dwc)
1265 { }
1266 #endif
1267 
1268 #endif /* __DRIVERS_USB_DWC3_CORE_H */
1269