1 /** 2 * core.h - DesignWare USB3 DRD Core Header 3 * 4 * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com 5 * 6 * Authors: Felipe Balbi <balbi@ti.com>, 7 * Sebastian Andrzej Siewior <bigeasy@linutronix.de> 8 * 9 * This program is free software: you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License version 2 of 11 * the License as published by the Free Software Foundation. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 */ 18 19 #ifndef __DRIVERS_USB_DWC3_CORE_H 20 #define __DRIVERS_USB_DWC3_CORE_H 21 22 #include <linux/device.h> 23 #include <linux/spinlock.h> 24 #include <linux/ioport.h> 25 #include <linux/list.h> 26 #include <linux/dma-mapping.h> 27 #include <linux/mm.h> 28 #include <linux/debugfs.h> 29 30 #include <linux/usb/ch9.h> 31 #include <linux/usb/gadget.h> 32 #include <linux/usb/otg.h> 33 #include <linux/ulpi/interface.h> 34 35 #include <linux/phy/phy.h> 36 37 #define DWC3_MSG_MAX 500 38 39 /* Global constants */ 40 #define DWC3_ZLP_BUF_SIZE 1024 /* size of a superspeed bulk */ 41 #define DWC3_EP0_BOUNCE_SIZE 512 42 #define DWC3_ENDPOINTS_NUM 32 43 #define DWC3_XHCI_RESOURCES_NUM 2 44 45 #define DWC3_SCRATCHBUF_SIZE 4096 /* each buffer is assumed to be 4KiB */ 46 #define DWC3_EVENT_SIZE 4 /* bytes */ 47 #define DWC3_EVENT_MAX_NUM 64 /* 2 events/endpoint */ 48 #define DWC3_EVENT_BUFFERS_SIZE (DWC3_EVENT_SIZE * DWC3_EVENT_MAX_NUM) 49 #define DWC3_EVENT_TYPE_MASK 0xfe 50 51 #define DWC3_EVENT_TYPE_DEV 0 52 #define DWC3_EVENT_TYPE_CARKIT 3 53 #define DWC3_EVENT_TYPE_I2C 4 54 55 #define DWC3_DEVICE_EVENT_DISCONNECT 0 56 #define DWC3_DEVICE_EVENT_RESET 1 57 #define DWC3_DEVICE_EVENT_CONNECT_DONE 2 58 #define DWC3_DEVICE_EVENT_LINK_STATUS_CHANGE 3 59 #define DWC3_DEVICE_EVENT_WAKEUP 4 60 #define DWC3_DEVICE_EVENT_HIBER_REQ 5 61 #define DWC3_DEVICE_EVENT_EOPF 6 62 #define DWC3_DEVICE_EVENT_SOF 7 63 #define DWC3_DEVICE_EVENT_ERRATIC_ERROR 9 64 #define DWC3_DEVICE_EVENT_CMD_CMPL 10 65 #define DWC3_DEVICE_EVENT_OVERFLOW 11 66 67 #define DWC3_GEVNTCOUNT_MASK 0xfffc 68 #define DWC3_GSNPSID_MASK 0xffff0000 69 #define DWC3_GSNPSREV_MASK 0xffff 70 71 /* DWC3 registers memory space boundries */ 72 #define DWC3_XHCI_REGS_START 0x0 73 #define DWC3_XHCI_REGS_END 0x7fff 74 #define DWC3_GLOBALS_REGS_START 0xc100 75 #define DWC3_GLOBALS_REGS_END 0xc6ff 76 #define DWC3_DEVICE_REGS_START 0xc700 77 #define DWC3_DEVICE_REGS_END 0xcbff 78 #define DWC3_OTG_REGS_START 0xcc00 79 #define DWC3_OTG_REGS_END 0xccff 80 81 /* Global Registers */ 82 #define DWC3_GSBUSCFG0 0xc100 83 #define DWC3_GSBUSCFG1 0xc104 84 #define DWC3_GTXTHRCFG 0xc108 85 #define DWC3_GRXTHRCFG 0xc10c 86 #define DWC3_GCTL 0xc110 87 #define DWC3_GEVTEN 0xc114 88 #define DWC3_GSTS 0xc118 89 #define DWC3_GUCTL1 0xc11c 90 #define DWC3_GSNPSID 0xc120 91 #define DWC3_GGPIO 0xc124 92 #define DWC3_GUID 0xc128 93 #define DWC3_GUCTL 0xc12c 94 #define DWC3_GBUSERRADDR0 0xc130 95 #define DWC3_GBUSERRADDR1 0xc134 96 #define DWC3_GPRTBIMAP0 0xc138 97 #define DWC3_GPRTBIMAP1 0xc13c 98 #define DWC3_GHWPARAMS0 0xc140 99 #define DWC3_GHWPARAMS1 0xc144 100 #define DWC3_GHWPARAMS2 0xc148 101 #define DWC3_GHWPARAMS3 0xc14c 102 #define DWC3_GHWPARAMS4 0xc150 103 #define DWC3_GHWPARAMS5 0xc154 104 #define DWC3_GHWPARAMS6 0xc158 105 #define DWC3_GHWPARAMS7 0xc15c 106 #define DWC3_GDBGFIFOSPACE 0xc160 107 #define DWC3_GDBGLTSSM 0xc164 108 #define DWC3_GPRTBIMAP_HS0 0xc180 109 #define DWC3_GPRTBIMAP_HS1 0xc184 110 #define DWC3_GPRTBIMAP_FS0 0xc188 111 #define DWC3_GPRTBIMAP_FS1 0xc18c 112 #define DWC3_GUCTL2 0xc19c 113 114 #define DWC3_VER_NUMBER 0xc1a0 115 #define DWC3_VER_TYPE 0xc1a4 116 117 #define DWC3_GUSB2PHYCFG(n) (0xc200 + (n * 0x04)) 118 #define DWC3_GUSB2I2CCTL(n) (0xc240 + (n * 0x04)) 119 120 #define DWC3_GUSB2PHYACC(n) (0xc280 + (n * 0x04)) 121 122 #define DWC3_GUSB3PIPECTL(n) (0xc2c0 + (n * 0x04)) 123 124 #define DWC3_GTXFIFOSIZ(n) (0xc300 + (n * 0x04)) 125 #define DWC3_GRXFIFOSIZ(n) (0xc380 + (n * 0x04)) 126 127 #define DWC3_GEVNTADRLO(n) (0xc400 + (n * 0x10)) 128 #define DWC3_GEVNTADRHI(n) (0xc404 + (n * 0x10)) 129 #define DWC3_GEVNTSIZ(n) (0xc408 + (n * 0x10)) 130 #define DWC3_GEVNTCOUNT(n) (0xc40c + (n * 0x10)) 131 132 #define DWC3_GHWPARAMS8 0xc600 133 #define DWC3_GFLADJ 0xc630 134 135 /* Device Registers */ 136 #define DWC3_DCFG 0xc700 137 #define DWC3_DCTL 0xc704 138 #define DWC3_DEVTEN 0xc708 139 #define DWC3_DSTS 0xc70c 140 #define DWC3_DGCMDPAR 0xc710 141 #define DWC3_DGCMD 0xc714 142 #define DWC3_DALEPENA 0xc720 143 144 #define DWC3_DEP_BASE(n) (0xc800 + (n * 0x10)) 145 #define DWC3_DEPCMDPAR2 0x00 146 #define DWC3_DEPCMDPAR1 0x04 147 #define DWC3_DEPCMDPAR0 0x08 148 #define DWC3_DEPCMD 0x0c 149 150 /* OTG Registers */ 151 #define DWC3_OCFG 0xcc00 152 #define DWC3_OCTL 0xcc04 153 #define DWC3_OEVT 0xcc08 154 #define DWC3_OEVTEN 0xcc0C 155 #define DWC3_OSTS 0xcc10 156 157 /* Bit fields */ 158 159 /* Global Debug Queue/FIFO Space Available Register */ 160 #define DWC3_GDBGFIFOSPACE_NUM(n) ((n) & 0x1f) 161 #define DWC3_GDBGFIFOSPACE_TYPE(n) (((n) << 5) & 0x1e0) 162 #define DWC3_GDBGFIFOSPACE_SPACE_AVAILABLE(n) (((n) >> 16) & 0xffff) 163 164 #define DWC3_TXFIFOQ 1 165 #define DWC3_RXFIFOQ 3 166 #define DWC3_TXREQQ 5 167 #define DWC3_RXREQQ 7 168 #define DWC3_RXINFOQ 9 169 #define DWC3_DESCFETCHQ 13 170 #define DWC3_EVENTQ 15 171 172 /* Global RX Threshold Configuration Register */ 173 #define DWC3_GRXTHRCFG_MAXRXBURSTSIZE(n) (((n) & 0x1f) << 19) 174 #define DWC3_GRXTHRCFG_RXPKTCNT(n) (((n) & 0xf) << 24) 175 #define DWC3_GRXTHRCFG_PKTCNTSEL (1 << 29) 176 177 /* Global Configuration Register */ 178 #define DWC3_GCTL_PWRDNSCALE(n) ((n) << 19) 179 #define DWC3_GCTL_U2RSTECN (1 << 16) 180 #define DWC3_GCTL_RAMCLKSEL(x) (((x) & DWC3_GCTL_CLK_MASK) << 6) 181 #define DWC3_GCTL_CLK_BUS (0) 182 #define DWC3_GCTL_CLK_PIPE (1) 183 #define DWC3_GCTL_CLK_PIPEHALF (2) 184 #define DWC3_GCTL_CLK_MASK (3) 185 186 #define DWC3_GCTL_PRTCAP(n) (((n) & (3 << 12)) >> 12) 187 #define DWC3_GCTL_PRTCAPDIR(n) ((n) << 12) 188 #define DWC3_GCTL_PRTCAP_HOST 1 189 #define DWC3_GCTL_PRTCAP_DEVICE 2 190 #define DWC3_GCTL_PRTCAP_OTG 3 191 192 #define DWC3_GCTL_CORESOFTRESET (1 << 11) 193 #define DWC3_GCTL_SOFITPSYNC (1 << 10) 194 #define DWC3_GCTL_SCALEDOWN(n) ((n) << 4) 195 #define DWC3_GCTL_SCALEDOWN_MASK DWC3_GCTL_SCALEDOWN(3) 196 #define DWC3_GCTL_DISSCRAMBLE (1 << 3) 197 #define DWC3_GCTL_U2EXIT_LFPS (1 << 2) 198 #define DWC3_GCTL_GBLHIBERNATIONEN (1 << 1) 199 #define DWC3_GCTL_DSBLCLKGTNG (1 << 0) 200 201 /* Global USB2 PHY Configuration Register */ 202 #define DWC3_GUSB2PHYCFG_PHYSOFTRST (1 << 31) 203 #define DWC3_GUSB2PHYCFG_U2_FREECLK_EXISTS (1 << 30) 204 #define DWC3_GUSB2PHYCFG_SUSPHY (1 << 6) 205 #define DWC3_GUSB2PHYCFG_ULPI_UTMI (1 << 4) 206 #define DWC3_GUSB2PHYCFG_ENBLSLPM (1 << 8) 207 #define DWC3_GUSB2PHYCFG_PHYIF(n) (n << 3) 208 #define DWC3_GUSB2PHYCFG_PHYIF_MASK DWC3_GUSB2PHYCFG_PHYIF(1) 209 #define DWC3_GUSB2PHYCFG_USBTRDTIM(n) (n << 10) 210 #define DWC3_GUSB2PHYCFG_USBTRDTIM_MASK DWC3_GUSB2PHYCFG_USBTRDTIM(0xf) 211 #define USBTRDTIM_UTMI_8_BIT 9 212 #define USBTRDTIM_UTMI_16_BIT 5 213 #define UTMI_PHYIF_16_BIT 1 214 #define UTMI_PHYIF_8_BIT 0 215 216 /* Global USB2 PHY Vendor Control Register */ 217 #define DWC3_GUSB2PHYACC_NEWREGREQ (1 << 25) 218 #define DWC3_GUSB2PHYACC_BUSY (1 << 23) 219 #define DWC3_GUSB2PHYACC_WRITE (1 << 22) 220 #define DWC3_GUSB2PHYACC_ADDR(n) (n << 16) 221 #define DWC3_GUSB2PHYACC_EXTEND_ADDR(n) (n << 8) 222 #define DWC3_GUSB2PHYACC_DATA(n) (n & 0xff) 223 224 /* Global USB3 PIPE Control Register */ 225 #define DWC3_GUSB3PIPECTL_PHYSOFTRST (1 << 31) 226 #define DWC3_GUSB3PIPECTL_U2SSINP3OK (1 << 29) 227 #define DWC3_GUSB3PIPECTL_DISRXDETINP3 (1 << 28) 228 #define DWC3_GUSB3PIPECTL_REQP1P2P3 (1 << 24) 229 #define DWC3_GUSB3PIPECTL_DEP1P2P3(n) ((n) << 19) 230 #define DWC3_GUSB3PIPECTL_DEP1P2P3_MASK DWC3_GUSB3PIPECTL_DEP1P2P3(7) 231 #define DWC3_GUSB3PIPECTL_DEP1P2P3_EN DWC3_GUSB3PIPECTL_DEP1P2P3(1) 232 #define DWC3_GUSB3PIPECTL_DEPOCHANGE (1 << 18) 233 #define DWC3_GUSB3PIPECTL_SUSPHY (1 << 17) 234 #define DWC3_GUSB3PIPECTL_LFPSFILT (1 << 9) 235 #define DWC3_GUSB3PIPECTL_RX_DETOPOLL (1 << 8) 236 #define DWC3_GUSB3PIPECTL_TX_DEEPH_MASK DWC3_GUSB3PIPECTL_TX_DEEPH(3) 237 #define DWC3_GUSB3PIPECTL_TX_DEEPH(n) ((n) << 1) 238 239 /* Global TX Fifo Size Register */ 240 #define DWC3_GTXFIFOSIZ_TXFDEF(n) ((n) & 0xffff) 241 #define DWC3_GTXFIFOSIZ_TXFSTADDR(n) ((n) & 0xffff0000) 242 243 /* Global Event Size Registers */ 244 #define DWC3_GEVNTSIZ_INTMASK (1 << 31) 245 #define DWC3_GEVNTSIZ_SIZE(n) ((n) & 0xffff) 246 247 /* Global HWPARAMS0 Register */ 248 #define DWC3_GHWPARAMS0_MODE(n) ((n) & 0x3) 249 #define DWC3_GHWPARAMS0_MODE_GADGET 0 250 #define DWC3_GHWPARAMS0_MODE_HOST 1 251 #define DWC3_GHWPARAMS0_MODE_DRD 2 252 #define DWC3_GHWPARAMS0_MBUS_TYPE(n) (((n) >> 3) & 0x7) 253 #define DWC3_GHWPARAMS0_SBUS_TYPE(n) (((n) >> 6) & 0x3) 254 #define DWC3_GHWPARAMS0_MDWIDTH(n) (((n) >> 8) & 0xff) 255 #define DWC3_GHWPARAMS0_SDWIDTH(n) (((n) >> 16) & 0xff) 256 #define DWC3_GHWPARAMS0_AWIDTH(n) (((n) >> 24) & 0xff) 257 258 /* Global HWPARAMS1 Register */ 259 #define DWC3_GHWPARAMS1_EN_PWROPT(n) (((n) & (3 << 24)) >> 24) 260 #define DWC3_GHWPARAMS1_EN_PWROPT_NO 0 261 #define DWC3_GHWPARAMS1_EN_PWROPT_CLK 1 262 #define DWC3_GHWPARAMS1_EN_PWROPT_HIB 2 263 #define DWC3_GHWPARAMS1_PWROPT(n) ((n) << 24) 264 #define DWC3_GHWPARAMS1_PWROPT_MASK DWC3_GHWPARAMS1_PWROPT(3) 265 266 /* Global HWPARAMS3 Register */ 267 #define DWC3_GHWPARAMS3_SSPHY_IFC(n) ((n) & 3) 268 #define DWC3_GHWPARAMS3_SSPHY_IFC_DIS 0 269 #define DWC3_GHWPARAMS3_SSPHY_IFC_GEN1 1 270 #define DWC3_GHWPARAMS3_SSPHY_IFC_GEN2 2 /* DWC_usb31 only */ 271 #define DWC3_GHWPARAMS3_HSPHY_IFC(n) (((n) & (3 << 2)) >> 2) 272 #define DWC3_GHWPARAMS3_HSPHY_IFC_DIS 0 273 #define DWC3_GHWPARAMS3_HSPHY_IFC_UTMI 1 274 #define DWC3_GHWPARAMS3_HSPHY_IFC_ULPI 2 275 #define DWC3_GHWPARAMS3_HSPHY_IFC_UTMI_ULPI 3 276 #define DWC3_GHWPARAMS3_FSPHY_IFC(n) (((n) & (3 << 4)) >> 4) 277 #define DWC3_GHWPARAMS3_FSPHY_IFC_DIS 0 278 #define DWC3_GHWPARAMS3_FSPHY_IFC_ENA 1 279 280 /* Global HWPARAMS4 Register */ 281 #define DWC3_GHWPARAMS4_HIBER_SCRATCHBUFS(n) (((n) & (0x0f << 13)) >> 13) 282 #define DWC3_MAX_HIBER_SCRATCHBUFS 15 283 284 /* Global HWPARAMS6 Register */ 285 #define DWC3_GHWPARAMS6_EN_FPGA (1 << 7) 286 287 /* Global HWPARAMS7 Register */ 288 #define DWC3_GHWPARAMS7_RAM1_DEPTH(n) ((n) & 0xffff) 289 #define DWC3_GHWPARAMS7_RAM2_DEPTH(n) (((n) >> 16) & 0xffff) 290 291 /* Global Frame Length Adjustment Register */ 292 #define DWC3_GFLADJ_30MHZ_SDBND_SEL (1 << 7) 293 #define DWC3_GFLADJ_30MHZ_MASK 0x3f 294 295 /* Global User Control Register 2 */ 296 #define DWC3_GUCTL2_RST_ACTBITLATER (1 << 14) 297 298 /* Device Configuration Register */ 299 #define DWC3_DCFG_DEVADDR(addr) ((addr) << 3) 300 #define DWC3_DCFG_DEVADDR_MASK DWC3_DCFG_DEVADDR(0x7f) 301 302 #define DWC3_DCFG_SPEED_MASK (7 << 0) 303 #define DWC3_DCFG_SUPERSPEED_PLUS (5 << 0) /* DWC_usb31 only */ 304 #define DWC3_DCFG_SUPERSPEED (4 << 0) 305 #define DWC3_DCFG_HIGHSPEED (0 << 0) 306 #define DWC3_DCFG_FULLSPEED2 (1 << 0) 307 #define DWC3_DCFG_LOWSPEED (2 << 0) 308 #define DWC3_DCFG_FULLSPEED1 (3 << 0) 309 310 #define DWC3_DCFG_NUMP_SHIFT 17 311 #define DWC3_DCFG_NUMP(n) (((n) >> DWC3_DCFG_NUMP_SHIFT) & 0x1f) 312 #define DWC3_DCFG_NUMP_MASK (0x1f << DWC3_DCFG_NUMP_SHIFT) 313 #define DWC3_DCFG_LPM_CAP (1 << 22) 314 315 /* Device Control Register */ 316 #define DWC3_DCTL_RUN_STOP (1 << 31) 317 #define DWC3_DCTL_CSFTRST (1 << 30) 318 #define DWC3_DCTL_LSFTRST (1 << 29) 319 320 #define DWC3_DCTL_HIRD_THRES_MASK (0x1f << 24) 321 #define DWC3_DCTL_HIRD_THRES(n) ((n) << 24) 322 323 #define DWC3_DCTL_APPL1RES (1 << 23) 324 325 /* These apply for core versions 1.87a and earlier */ 326 #define DWC3_DCTL_TRGTULST_MASK (0x0f << 17) 327 #define DWC3_DCTL_TRGTULST(n) ((n) << 17) 328 #define DWC3_DCTL_TRGTULST_U2 (DWC3_DCTL_TRGTULST(2)) 329 #define DWC3_DCTL_TRGTULST_U3 (DWC3_DCTL_TRGTULST(3)) 330 #define DWC3_DCTL_TRGTULST_SS_DIS (DWC3_DCTL_TRGTULST(4)) 331 #define DWC3_DCTL_TRGTULST_RX_DET (DWC3_DCTL_TRGTULST(5)) 332 #define DWC3_DCTL_TRGTULST_SS_INACT (DWC3_DCTL_TRGTULST(6)) 333 334 /* These apply for core versions 1.94a and later */ 335 #define DWC3_DCTL_LPM_ERRATA_MASK DWC3_DCTL_LPM_ERRATA(0xf) 336 #define DWC3_DCTL_LPM_ERRATA(n) ((n) << 20) 337 338 #define DWC3_DCTL_KEEP_CONNECT (1 << 19) 339 #define DWC3_DCTL_L1_HIBER_EN (1 << 18) 340 #define DWC3_DCTL_CRS (1 << 17) 341 #define DWC3_DCTL_CSS (1 << 16) 342 343 #define DWC3_DCTL_INITU2ENA (1 << 12) 344 #define DWC3_DCTL_ACCEPTU2ENA (1 << 11) 345 #define DWC3_DCTL_INITU1ENA (1 << 10) 346 #define DWC3_DCTL_ACCEPTU1ENA (1 << 9) 347 #define DWC3_DCTL_TSTCTRL_MASK (0xf << 1) 348 349 #define DWC3_DCTL_ULSTCHNGREQ_MASK (0x0f << 5) 350 #define DWC3_DCTL_ULSTCHNGREQ(n) (((n) << 5) & DWC3_DCTL_ULSTCHNGREQ_MASK) 351 352 #define DWC3_DCTL_ULSTCHNG_NO_ACTION (DWC3_DCTL_ULSTCHNGREQ(0)) 353 #define DWC3_DCTL_ULSTCHNG_SS_DISABLED (DWC3_DCTL_ULSTCHNGREQ(4)) 354 #define DWC3_DCTL_ULSTCHNG_RX_DETECT (DWC3_DCTL_ULSTCHNGREQ(5)) 355 #define DWC3_DCTL_ULSTCHNG_SS_INACTIVE (DWC3_DCTL_ULSTCHNGREQ(6)) 356 #define DWC3_DCTL_ULSTCHNG_RECOVERY (DWC3_DCTL_ULSTCHNGREQ(8)) 357 #define DWC3_DCTL_ULSTCHNG_COMPLIANCE (DWC3_DCTL_ULSTCHNGREQ(10)) 358 #define DWC3_DCTL_ULSTCHNG_LOOPBACK (DWC3_DCTL_ULSTCHNGREQ(11)) 359 360 /* Device Event Enable Register */ 361 #define DWC3_DEVTEN_VNDRDEVTSTRCVEDEN (1 << 12) 362 #define DWC3_DEVTEN_EVNTOVERFLOWEN (1 << 11) 363 #define DWC3_DEVTEN_CMDCMPLTEN (1 << 10) 364 #define DWC3_DEVTEN_ERRTICERREN (1 << 9) 365 #define DWC3_DEVTEN_SOFEN (1 << 7) 366 #define DWC3_DEVTEN_EOPFEN (1 << 6) 367 #define DWC3_DEVTEN_HIBERNATIONREQEVTEN (1 << 5) 368 #define DWC3_DEVTEN_WKUPEVTEN (1 << 4) 369 #define DWC3_DEVTEN_ULSTCNGEN (1 << 3) 370 #define DWC3_DEVTEN_CONNECTDONEEN (1 << 2) 371 #define DWC3_DEVTEN_USBRSTEN (1 << 1) 372 #define DWC3_DEVTEN_DISCONNEVTEN (1 << 0) 373 374 /* Device Status Register */ 375 #define DWC3_DSTS_DCNRD (1 << 29) 376 377 /* This applies for core versions 1.87a and earlier */ 378 #define DWC3_DSTS_PWRUPREQ (1 << 24) 379 380 /* These apply for core versions 1.94a and later */ 381 #define DWC3_DSTS_RSS (1 << 25) 382 #define DWC3_DSTS_SSS (1 << 24) 383 384 #define DWC3_DSTS_COREIDLE (1 << 23) 385 #define DWC3_DSTS_DEVCTRLHLT (1 << 22) 386 387 #define DWC3_DSTS_USBLNKST_MASK (0x0f << 18) 388 #define DWC3_DSTS_USBLNKST(n) (((n) & DWC3_DSTS_USBLNKST_MASK) >> 18) 389 390 #define DWC3_DSTS_RXFIFOEMPTY (1 << 17) 391 392 #define DWC3_DSTS_SOFFN_MASK (0x3fff << 3) 393 #define DWC3_DSTS_SOFFN(n) (((n) & DWC3_DSTS_SOFFN_MASK) >> 3) 394 395 #define DWC3_DSTS_CONNECTSPD (7 << 0) 396 397 #define DWC3_DSTS_SUPERSPEED_PLUS (5 << 0) /* DWC_usb31 only */ 398 #define DWC3_DSTS_SUPERSPEED (4 << 0) 399 #define DWC3_DSTS_HIGHSPEED (0 << 0) 400 #define DWC3_DSTS_FULLSPEED2 (1 << 0) 401 #define DWC3_DSTS_LOWSPEED (2 << 0) 402 #define DWC3_DSTS_FULLSPEED1 (3 << 0) 403 404 /* Device Generic Command Register */ 405 #define DWC3_DGCMD_SET_LMP 0x01 406 #define DWC3_DGCMD_SET_PERIODIC_PAR 0x02 407 #define DWC3_DGCMD_XMIT_FUNCTION 0x03 408 409 /* These apply for core versions 1.94a and later */ 410 #define DWC3_DGCMD_SET_SCRATCHPAD_ADDR_LO 0x04 411 #define DWC3_DGCMD_SET_SCRATCHPAD_ADDR_HI 0x05 412 413 #define DWC3_DGCMD_SELECTED_FIFO_FLUSH 0x09 414 #define DWC3_DGCMD_ALL_FIFO_FLUSH 0x0a 415 #define DWC3_DGCMD_SET_ENDPOINT_NRDY 0x0c 416 #define DWC3_DGCMD_RUN_SOC_BUS_LOOPBACK 0x10 417 418 #define DWC3_DGCMD_STATUS(n) (((n) >> 12) & 0x0F) 419 #define DWC3_DGCMD_CMDACT (1 << 10) 420 #define DWC3_DGCMD_CMDIOC (1 << 8) 421 422 /* Device Generic Command Parameter Register */ 423 #define DWC3_DGCMDPAR_FORCE_LINKPM_ACCEPT (1 << 0) 424 #define DWC3_DGCMDPAR_FIFO_NUM(n) ((n) << 0) 425 #define DWC3_DGCMDPAR_RX_FIFO (0 << 5) 426 #define DWC3_DGCMDPAR_TX_FIFO (1 << 5) 427 #define DWC3_DGCMDPAR_LOOPBACK_DIS (0 << 0) 428 #define DWC3_DGCMDPAR_LOOPBACK_ENA (1 << 0) 429 430 /* Device Endpoint Command Register */ 431 #define DWC3_DEPCMD_PARAM_SHIFT 16 432 #define DWC3_DEPCMD_PARAM(x) ((x) << DWC3_DEPCMD_PARAM_SHIFT) 433 #define DWC3_DEPCMD_GET_RSC_IDX(x) (((x) >> DWC3_DEPCMD_PARAM_SHIFT) & 0x7f) 434 #define DWC3_DEPCMD_STATUS(x) (((x) >> 12) & 0x0F) 435 #define DWC3_DEPCMD_HIPRI_FORCERM (1 << 11) 436 #define DWC3_DEPCMD_CLEARPENDIN (1 << 11) 437 #define DWC3_DEPCMD_CMDACT (1 << 10) 438 #define DWC3_DEPCMD_CMDIOC (1 << 8) 439 440 #define DWC3_DEPCMD_DEPSTARTCFG (0x09 << 0) 441 #define DWC3_DEPCMD_ENDTRANSFER (0x08 << 0) 442 #define DWC3_DEPCMD_UPDATETRANSFER (0x07 << 0) 443 #define DWC3_DEPCMD_STARTTRANSFER (0x06 << 0) 444 #define DWC3_DEPCMD_CLEARSTALL (0x05 << 0) 445 #define DWC3_DEPCMD_SETSTALL (0x04 << 0) 446 /* This applies for core versions 1.90a and earlier */ 447 #define DWC3_DEPCMD_GETSEQNUMBER (0x03 << 0) 448 /* This applies for core versions 1.94a and later */ 449 #define DWC3_DEPCMD_GETEPSTATE (0x03 << 0) 450 #define DWC3_DEPCMD_SETTRANSFRESOURCE (0x02 << 0) 451 #define DWC3_DEPCMD_SETEPCONFIG (0x01 << 0) 452 453 /* The EP number goes 0..31 so ep0 is always out and ep1 is always in */ 454 #define DWC3_DALEPENA_EP(n) (1 << n) 455 456 #define DWC3_DEPCMD_TYPE_CONTROL 0 457 #define DWC3_DEPCMD_TYPE_ISOC 1 458 #define DWC3_DEPCMD_TYPE_BULK 2 459 #define DWC3_DEPCMD_TYPE_INTR 3 460 461 /* Structures */ 462 463 struct dwc3_trb; 464 465 /** 466 * struct dwc3_event_buffer - Software event buffer representation 467 * @buf: _THE_ buffer 468 * @length: size of this buffer 469 * @lpos: event offset 470 * @count: cache of last read event count register 471 * @flags: flags related to this event buffer 472 * @dma: dma_addr_t 473 * @dwc: pointer to DWC controller 474 */ 475 struct dwc3_event_buffer { 476 void *buf; 477 unsigned length; 478 unsigned int lpos; 479 unsigned int count; 480 unsigned int flags; 481 482 #define DWC3_EVENT_PENDING BIT(0) 483 484 dma_addr_t dma; 485 486 struct dwc3 *dwc; 487 }; 488 489 #define DWC3_EP_FLAG_STALLED (1 << 0) 490 #define DWC3_EP_FLAG_WEDGED (1 << 1) 491 492 #define DWC3_EP_DIRECTION_TX true 493 #define DWC3_EP_DIRECTION_RX false 494 495 #define DWC3_TRB_NUM 256 496 497 /** 498 * struct dwc3_ep - device side endpoint representation 499 * @endpoint: usb endpoint 500 * @pending_list: list of pending requests for this endpoint 501 * @started_list: list of started requests on this endpoint 502 * @lock: spinlock for endpoint request queue traversal 503 * @regs: pointer to first endpoint register 504 * @trb_pool: array of transaction buffers 505 * @trb_pool_dma: dma address of @trb_pool 506 * @trb_enqueue: enqueue 'pointer' into TRB array 507 * @trb_dequeue: dequeue 'pointer' into TRB array 508 * @desc: usb_endpoint_descriptor pointer 509 * @dwc: pointer to DWC controller 510 * @saved_state: ep state saved during hibernation 511 * @flags: endpoint flags (wedged, stalled, ...) 512 * @number: endpoint number (1 - 15) 513 * @type: set to bmAttributes & USB_ENDPOINT_XFERTYPE_MASK 514 * @resource_index: Resource transfer index 515 * @interval: the interval on which the ISOC transfer is started 516 * @allocated_requests: number of requests allocated 517 * @queued_requests: number of requests queued for transfer 518 * @name: a human readable name e.g. ep1out-bulk 519 * @direction: true for TX, false for RX 520 * @stream_capable: true when streams are enabled 521 */ 522 struct dwc3_ep { 523 struct usb_ep endpoint; 524 struct list_head pending_list; 525 struct list_head started_list; 526 527 spinlock_t lock; 528 void __iomem *regs; 529 530 struct dwc3_trb *trb_pool; 531 dma_addr_t trb_pool_dma; 532 const struct usb_ss_ep_comp_descriptor *comp_desc; 533 struct dwc3 *dwc; 534 535 u32 saved_state; 536 unsigned flags; 537 #define DWC3_EP_ENABLED (1 << 0) 538 #define DWC3_EP_STALL (1 << 1) 539 #define DWC3_EP_WEDGE (1 << 2) 540 #define DWC3_EP_BUSY (1 << 4) 541 #define DWC3_EP_PENDING_REQUEST (1 << 5) 542 #define DWC3_EP_MISSED_ISOC (1 << 6) 543 544 /* This last one is specific to EP0 */ 545 #define DWC3_EP0_DIR_IN (1 << 31) 546 547 /* 548 * IMPORTANT: we *know* we have 256 TRBs in our @trb_pool, so we will 549 * use a u8 type here. If anybody decides to increase number of TRBs to 550 * anything larger than 256 - I can't see why people would want to do 551 * this though - then this type needs to be changed. 552 * 553 * By using u8 types we ensure that our % operator when incrementing 554 * enqueue and dequeue get optimized away by the compiler. 555 */ 556 u8 trb_enqueue; 557 u8 trb_dequeue; 558 559 u8 number; 560 u8 type; 561 u8 resource_index; 562 u32 allocated_requests; 563 u32 queued_requests; 564 u32 interval; 565 566 char name[20]; 567 568 unsigned direction:1; 569 unsigned stream_capable:1; 570 }; 571 572 enum dwc3_phy { 573 DWC3_PHY_UNKNOWN = 0, 574 DWC3_PHY_USB3, 575 DWC3_PHY_USB2, 576 }; 577 578 enum dwc3_ep0_next { 579 DWC3_EP0_UNKNOWN = 0, 580 DWC3_EP0_COMPLETE, 581 DWC3_EP0_NRDY_DATA, 582 DWC3_EP0_NRDY_STATUS, 583 }; 584 585 enum dwc3_ep0_state { 586 EP0_UNCONNECTED = 0, 587 EP0_SETUP_PHASE, 588 EP0_DATA_PHASE, 589 EP0_STATUS_PHASE, 590 }; 591 592 enum dwc3_link_state { 593 /* In SuperSpeed */ 594 DWC3_LINK_STATE_U0 = 0x00, /* in HS, means ON */ 595 DWC3_LINK_STATE_U1 = 0x01, 596 DWC3_LINK_STATE_U2 = 0x02, /* in HS, means SLEEP */ 597 DWC3_LINK_STATE_U3 = 0x03, /* in HS, means SUSPEND */ 598 DWC3_LINK_STATE_SS_DIS = 0x04, 599 DWC3_LINK_STATE_RX_DET = 0x05, /* in HS, means Early Suspend */ 600 DWC3_LINK_STATE_SS_INACT = 0x06, 601 DWC3_LINK_STATE_POLL = 0x07, 602 DWC3_LINK_STATE_RECOV = 0x08, 603 DWC3_LINK_STATE_HRESET = 0x09, 604 DWC3_LINK_STATE_CMPLY = 0x0a, 605 DWC3_LINK_STATE_LPBK = 0x0b, 606 DWC3_LINK_STATE_RESET = 0x0e, 607 DWC3_LINK_STATE_RESUME = 0x0f, 608 DWC3_LINK_STATE_MASK = 0x0f, 609 }; 610 611 /* TRB Length, PCM and Status */ 612 #define DWC3_TRB_SIZE_MASK (0x00ffffff) 613 #define DWC3_TRB_SIZE_LENGTH(n) ((n) & DWC3_TRB_SIZE_MASK) 614 #define DWC3_TRB_SIZE_PCM1(n) (((n) & 0x03) << 24) 615 #define DWC3_TRB_SIZE_TRBSTS(n) (((n) & (0x0f << 28)) >> 28) 616 617 #define DWC3_TRBSTS_OK 0 618 #define DWC3_TRBSTS_MISSED_ISOC 1 619 #define DWC3_TRBSTS_SETUP_PENDING 2 620 #define DWC3_TRB_STS_XFER_IN_PROG 4 621 622 /* TRB Control */ 623 #define DWC3_TRB_CTRL_HWO (1 << 0) 624 #define DWC3_TRB_CTRL_LST (1 << 1) 625 #define DWC3_TRB_CTRL_CHN (1 << 2) 626 #define DWC3_TRB_CTRL_CSP (1 << 3) 627 #define DWC3_TRB_CTRL_TRBCTL(n) (((n) & 0x3f) << 4) 628 #define DWC3_TRB_CTRL_ISP_IMI (1 << 10) 629 #define DWC3_TRB_CTRL_IOC (1 << 11) 630 #define DWC3_TRB_CTRL_SID_SOFN(n) (((n) & 0xffff) << 14) 631 632 #define DWC3_TRBCTL_TYPE(n) ((n) & (0x3f << 4)) 633 #define DWC3_TRBCTL_NORMAL DWC3_TRB_CTRL_TRBCTL(1) 634 #define DWC3_TRBCTL_CONTROL_SETUP DWC3_TRB_CTRL_TRBCTL(2) 635 #define DWC3_TRBCTL_CONTROL_STATUS2 DWC3_TRB_CTRL_TRBCTL(3) 636 #define DWC3_TRBCTL_CONTROL_STATUS3 DWC3_TRB_CTRL_TRBCTL(4) 637 #define DWC3_TRBCTL_CONTROL_DATA DWC3_TRB_CTRL_TRBCTL(5) 638 #define DWC3_TRBCTL_ISOCHRONOUS_FIRST DWC3_TRB_CTRL_TRBCTL(6) 639 #define DWC3_TRBCTL_ISOCHRONOUS DWC3_TRB_CTRL_TRBCTL(7) 640 #define DWC3_TRBCTL_LINK_TRB DWC3_TRB_CTRL_TRBCTL(8) 641 642 /** 643 * struct dwc3_trb - transfer request block (hw format) 644 * @bpl: DW0-3 645 * @bph: DW4-7 646 * @size: DW8-B 647 * @trl: DWC-F 648 */ 649 struct dwc3_trb { 650 u32 bpl; 651 u32 bph; 652 u32 size; 653 u32 ctrl; 654 } __packed; 655 656 /** 657 * dwc3_hwparams - copy of HWPARAMS registers 658 * @hwparams0 - GHWPARAMS0 659 * @hwparams1 - GHWPARAMS1 660 * @hwparams2 - GHWPARAMS2 661 * @hwparams3 - GHWPARAMS3 662 * @hwparams4 - GHWPARAMS4 663 * @hwparams5 - GHWPARAMS5 664 * @hwparams6 - GHWPARAMS6 665 * @hwparams7 - GHWPARAMS7 666 * @hwparams8 - GHWPARAMS8 667 */ 668 struct dwc3_hwparams { 669 u32 hwparams0; 670 u32 hwparams1; 671 u32 hwparams2; 672 u32 hwparams3; 673 u32 hwparams4; 674 u32 hwparams5; 675 u32 hwparams6; 676 u32 hwparams7; 677 u32 hwparams8; 678 }; 679 680 /* HWPARAMS0 */ 681 #define DWC3_MODE(n) ((n) & 0x7) 682 683 #define DWC3_MDWIDTH(n) (((n) & 0xff00) >> 8) 684 685 /* HWPARAMS1 */ 686 #define DWC3_NUM_INT(n) (((n) & (0x3f << 15)) >> 15) 687 688 /* HWPARAMS3 */ 689 #define DWC3_NUM_IN_EPS_MASK (0x1f << 18) 690 #define DWC3_NUM_EPS_MASK (0x3f << 12) 691 #define DWC3_NUM_EPS(p) (((p)->hwparams3 & \ 692 (DWC3_NUM_EPS_MASK)) >> 12) 693 #define DWC3_NUM_IN_EPS(p) (((p)->hwparams3 & \ 694 (DWC3_NUM_IN_EPS_MASK)) >> 18) 695 696 /* HWPARAMS7 */ 697 #define DWC3_RAM1_DEPTH(n) ((n) & 0xffff) 698 699 /** 700 * struct dwc3_request - representation of a transfer request 701 * @request: struct usb_request to be transferred 702 * @list: a list_head used for request queueing 703 * @dep: struct dwc3_ep owning this request 704 * @sg: pointer to first incomplete sg 705 * @num_pending_sgs: counter to pending sgs 706 * @first_trb_index: index to first trb used by this request 707 * @epnum: endpoint number to which this request refers 708 * @trb: pointer to struct dwc3_trb 709 * @trb_dma: DMA address of @trb 710 * @direction: IN or OUT direction flag 711 * @mapped: true when request has been dma-mapped 712 * @queued: true when request has been queued to HW 713 */ 714 struct dwc3_request { 715 struct usb_request request; 716 struct list_head list; 717 struct dwc3_ep *dep; 718 struct scatterlist *sg; 719 720 unsigned num_pending_sgs; 721 u8 first_trb_index; 722 u8 epnum; 723 struct dwc3_trb *trb; 724 dma_addr_t trb_dma; 725 726 unsigned direction:1; 727 unsigned mapped:1; 728 unsigned started:1; 729 }; 730 731 /* 732 * struct dwc3_scratchpad_array - hibernation scratchpad array 733 * (format defined by hw) 734 */ 735 struct dwc3_scratchpad_array { 736 __le64 dma_adr[DWC3_MAX_HIBER_SCRATCHBUFS]; 737 }; 738 739 /** 740 * struct dwc3 - representation of our controller 741 * @ctrl_req: usb control request which is used for ep0 742 * @ep0_trb: trb which is used for the ctrl_req 743 * @ep0_bounce: bounce buffer for ep0 744 * @zlp_buf: used when request->zero is set 745 * @setup_buf: used while precessing STD USB requests 746 * @ctrl_req_addr: dma address of ctrl_req 747 * @ep0_trb: dma address of ep0_trb 748 * @ep0_usb_req: dummy req used while handling STD USB requests 749 * @ep0_bounce_addr: dma address of ep0_bounce 750 * @scratch_addr: dma address of scratchbuf 751 * @lock: for synchronizing 752 * @dev: pointer to our struct device 753 * @xhci: pointer to our xHCI child 754 * @event_buffer_list: a list of event buffers 755 * @gadget: device side representation of the peripheral controller 756 * @gadget_driver: pointer to the gadget driver 757 * @regs: base address for our registers 758 * @regs_size: address space size 759 * @fladj: frame length adjustment 760 * @irq_gadget: peripheral controller's IRQ number 761 * @nr_scratch: number of scratch buffers 762 * @u1u2: only used on revisions <1.83a for workaround 763 * @maximum_speed: maximum speed requested (mainly for testing purposes) 764 * @revision: revision register contents 765 * @dr_mode: requested mode of operation 766 * @hsphy_mode: UTMI phy mode, one of following: 767 * - USBPHY_INTERFACE_MODE_UTMI 768 * - USBPHY_INTERFACE_MODE_UTMIW 769 * @usb2_phy: pointer to USB2 PHY 770 * @usb3_phy: pointer to USB3 PHY 771 * @usb2_generic_phy: pointer to USB2 PHY 772 * @usb3_generic_phy: pointer to USB3 PHY 773 * @ulpi: pointer to ulpi interface 774 * @dcfg: saved contents of DCFG register 775 * @gctl: saved contents of GCTL register 776 * @isoch_delay: wValue from Set Isochronous Delay request; 777 * @u2sel: parameter from Set SEL request. 778 * @u2pel: parameter from Set SEL request. 779 * @u1sel: parameter from Set SEL request. 780 * @u1pel: parameter from Set SEL request. 781 * @num_out_eps: number of out endpoints 782 * @num_in_eps: number of in endpoints 783 * @ep0_next_event: hold the next expected event 784 * @ep0state: state of endpoint zero 785 * @link_state: link state 786 * @speed: device speed (super, high, full, low) 787 * @mem: points to start of memory which is used for this struct. 788 * @hwparams: copy of hwparams registers 789 * @root: debugfs root folder pointer 790 * @regset: debugfs pointer to regdump file 791 * @test_mode: true when we're entering a USB test mode 792 * @test_mode_nr: test feature selector 793 * @lpm_nyet_threshold: LPM NYET response threshold 794 * @hird_threshold: HIRD threshold 795 * @hsphy_interface: "utmi" or "ulpi" 796 * @connected: true when we're connected to a host, false otherwise 797 * @delayed_status: true when gadget driver asks for delayed status 798 * @ep0_bounced: true when we used bounce buffer 799 * @ep0_expect_in: true when we expect a DATA IN transfer 800 * @has_hibernation: true when dwc3 was configured with Hibernation 801 * @has_lpm_erratum: true when core was configured with LPM Erratum. Note that 802 * there's now way for software to detect this in runtime. 803 * @is_utmi_l1_suspend: the core asserts output signal 804 * 0 - utmi_sleep_n 805 * 1 - utmi_l1_suspend_n 806 * @is_fpga: true when we are using the FPGA board 807 * @pending_events: true when we have pending IRQs to be handled 808 * @pullups_connected: true when Run/Stop bit is set 809 * @setup_packet_pending: true when there's a Setup Packet in FIFO. Workaround 810 * @start_config_issued: true when StartConfig command has been issued 811 * @three_stage_setup: set if we perform a three phase setup 812 * @usb3_lpm_capable: set if hadrware supports Link Power Management 813 * @disable_scramble_quirk: set if we enable the disable scramble quirk 814 * @u2exit_lfps_quirk: set if we enable u2exit lfps quirk 815 * @u2ss_inp3_quirk: set if we enable P3 OK for U2/SS Inactive quirk 816 * @req_p1p2p3_quirk: set if we enable request p1p2p3 quirk 817 * @del_p1p2p3_quirk: set if we enable delay p1p2p3 quirk 818 * @del_phy_power_chg_quirk: set if we enable delay phy power change quirk 819 * @lfps_filter_quirk: set if we enable LFPS filter quirk 820 * @rx_detect_poll_quirk: set if we enable rx_detect to polling lfps quirk 821 * @dis_u3_susphy_quirk: set if we disable usb3 suspend phy 822 * @dis_u2_susphy_quirk: set if we disable usb2 suspend phy 823 * @dis_enblslpm_quirk: set if we clear enblslpm in GUSB2PHYCFG, 824 * disabling the suspend signal to the PHY. 825 * @dis_u2_freeclk_exists_quirk : set if we clear u2_freeclk_exists 826 * in GUSB2PHYCFG, specify that USB2 PHY doesn't 827 * provide a free-running PHY clock. 828 * @dis_del_phy_power_chg_quirk: set if we disable delay phy power 829 * change quirk. 830 * @tx_de_emphasis_quirk: set if we enable Tx de-emphasis quirk 831 * @tx_de_emphasis: Tx de-emphasis value 832 * 0 - -6dB de-emphasis 833 * 1 - -3.5dB de-emphasis 834 * 2 - No de-emphasis 835 * 3 - Reserved 836 */ 837 struct dwc3 { 838 struct usb_ctrlrequest *ctrl_req; 839 struct dwc3_trb *ep0_trb; 840 void *ep0_bounce; 841 void *zlp_buf; 842 void *scratchbuf; 843 u8 *setup_buf; 844 dma_addr_t ctrl_req_addr; 845 dma_addr_t ep0_trb_addr; 846 dma_addr_t ep0_bounce_addr; 847 dma_addr_t scratch_addr; 848 struct dwc3_request ep0_usb_req; 849 850 /* device lock */ 851 spinlock_t lock; 852 853 struct device *dev; 854 855 struct platform_device *xhci; 856 struct resource xhci_resources[DWC3_XHCI_RESOURCES_NUM]; 857 858 struct dwc3_event_buffer *ev_buf; 859 struct dwc3_ep *eps[DWC3_ENDPOINTS_NUM]; 860 861 struct usb_gadget gadget; 862 struct usb_gadget_driver *gadget_driver; 863 864 struct usb_phy *usb2_phy; 865 struct usb_phy *usb3_phy; 866 867 struct phy *usb2_generic_phy; 868 struct phy *usb3_generic_phy; 869 870 struct ulpi *ulpi; 871 872 void __iomem *regs; 873 size_t regs_size; 874 875 enum usb_dr_mode dr_mode; 876 enum usb_phy_interface hsphy_mode; 877 878 u32 fladj; 879 u32 irq_gadget; 880 u32 nr_scratch; 881 u32 u1u2; 882 u32 maximum_speed; 883 884 /* 885 * All 3.1 IP version constants are greater than the 3.0 IP 886 * version constants. This works for most version checks in 887 * dwc3. However, in the future, this may not apply as 888 * features may be developed on newer versions of the 3.0 IP 889 * that are not in the 3.1 IP. 890 */ 891 u32 revision; 892 893 #define DWC3_REVISION_173A 0x5533173a 894 #define DWC3_REVISION_175A 0x5533175a 895 #define DWC3_REVISION_180A 0x5533180a 896 #define DWC3_REVISION_183A 0x5533183a 897 #define DWC3_REVISION_185A 0x5533185a 898 #define DWC3_REVISION_187A 0x5533187a 899 #define DWC3_REVISION_188A 0x5533188a 900 #define DWC3_REVISION_190A 0x5533190a 901 #define DWC3_REVISION_194A 0x5533194a 902 #define DWC3_REVISION_200A 0x5533200a 903 #define DWC3_REVISION_202A 0x5533202a 904 #define DWC3_REVISION_210A 0x5533210a 905 #define DWC3_REVISION_220A 0x5533220a 906 #define DWC3_REVISION_230A 0x5533230a 907 #define DWC3_REVISION_240A 0x5533240a 908 #define DWC3_REVISION_250A 0x5533250a 909 #define DWC3_REVISION_260A 0x5533260a 910 #define DWC3_REVISION_270A 0x5533270a 911 #define DWC3_REVISION_280A 0x5533280a 912 #define DWC3_REVISION_300A 0x5533300a 913 #define DWC3_REVISION_310A 0x5533310a 914 915 /* 916 * NOTICE: we're using bit 31 as a "is usb 3.1" flag. This is really 917 * just so dwc31 revisions are always larger than dwc3. 918 */ 919 #define DWC3_REVISION_IS_DWC31 0x80000000 920 #define DWC3_USB31_REVISION_110A (0x3131302a | DWC3_REVISION_IS_DWC31) 921 922 enum dwc3_ep0_next ep0_next_event; 923 enum dwc3_ep0_state ep0state; 924 enum dwc3_link_state link_state; 925 926 u16 isoch_delay; 927 u16 u2sel; 928 u16 u2pel; 929 u8 u1sel; 930 u8 u1pel; 931 932 u8 speed; 933 934 u8 num_out_eps; 935 u8 num_in_eps; 936 937 void *mem; 938 939 struct dwc3_hwparams hwparams; 940 struct dentry *root; 941 struct debugfs_regset32 *regset; 942 943 u8 test_mode; 944 u8 test_mode_nr; 945 u8 lpm_nyet_threshold; 946 u8 hird_threshold; 947 948 const char *hsphy_interface; 949 950 unsigned connected:1; 951 unsigned delayed_status:1; 952 unsigned ep0_bounced:1; 953 unsigned ep0_expect_in:1; 954 unsigned has_hibernation:1; 955 unsigned has_lpm_erratum:1; 956 unsigned is_utmi_l1_suspend:1; 957 unsigned is_fpga:1; 958 unsigned pending_events:1; 959 unsigned pullups_connected:1; 960 unsigned setup_packet_pending:1; 961 unsigned three_stage_setup:1; 962 unsigned usb3_lpm_capable:1; 963 964 unsigned disable_scramble_quirk:1; 965 unsigned u2exit_lfps_quirk:1; 966 unsigned u2ss_inp3_quirk:1; 967 unsigned req_p1p2p3_quirk:1; 968 unsigned del_p1p2p3_quirk:1; 969 unsigned del_phy_power_chg_quirk:1; 970 unsigned lfps_filter_quirk:1; 971 unsigned rx_detect_poll_quirk:1; 972 unsigned dis_u3_susphy_quirk:1; 973 unsigned dis_u2_susphy_quirk:1; 974 unsigned dis_enblslpm_quirk:1; 975 unsigned dis_rxdet_inp3_quirk:1; 976 unsigned dis_u2_freeclk_exists_quirk:1; 977 unsigned dis_del_phy_power_chg_quirk:1; 978 979 unsigned tx_de_emphasis_quirk:1; 980 unsigned tx_de_emphasis:2; 981 }; 982 983 /* -------------------------------------------------------------------------- */ 984 985 /* -------------------------------------------------------------------------- */ 986 987 struct dwc3_event_type { 988 u32 is_devspec:1; 989 u32 type:7; 990 u32 reserved8_31:24; 991 } __packed; 992 993 #define DWC3_DEPEVT_XFERCOMPLETE 0x01 994 #define DWC3_DEPEVT_XFERINPROGRESS 0x02 995 #define DWC3_DEPEVT_XFERNOTREADY 0x03 996 #define DWC3_DEPEVT_RXTXFIFOEVT 0x04 997 #define DWC3_DEPEVT_STREAMEVT 0x06 998 #define DWC3_DEPEVT_EPCMDCMPLT 0x07 999 1000 /** 1001 * struct dwc3_event_depvt - Device Endpoint Events 1002 * @one_bit: indicates this is an endpoint event (not used) 1003 * @endpoint_number: number of the endpoint 1004 * @endpoint_event: The event we have: 1005 * 0x00 - Reserved 1006 * 0x01 - XferComplete 1007 * 0x02 - XferInProgress 1008 * 0x03 - XferNotReady 1009 * 0x04 - RxTxFifoEvt (IN->Underrun, OUT->Overrun) 1010 * 0x05 - Reserved 1011 * 0x06 - StreamEvt 1012 * 0x07 - EPCmdCmplt 1013 * @reserved11_10: Reserved, don't use. 1014 * @status: Indicates the status of the event. Refer to databook for 1015 * more information. 1016 * @parameters: Parameters of the current event. Refer to databook for 1017 * more information. 1018 */ 1019 struct dwc3_event_depevt { 1020 u32 one_bit:1; 1021 u32 endpoint_number:5; 1022 u32 endpoint_event:4; 1023 u32 reserved11_10:2; 1024 u32 status:4; 1025 1026 /* Within XferNotReady */ 1027 #define DEPEVT_STATUS_TRANSFER_ACTIVE (1 << 3) 1028 1029 /* Within XferComplete */ 1030 #define DEPEVT_STATUS_BUSERR (1 << 0) 1031 #define DEPEVT_STATUS_SHORT (1 << 1) 1032 #define DEPEVT_STATUS_IOC (1 << 2) 1033 #define DEPEVT_STATUS_LST (1 << 3) 1034 1035 /* Stream event only */ 1036 #define DEPEVT_STREAMEVT_FOUND 1 1037 #define DEPEVT_STREAMEVT_NOTFOUND 2 1038 1039 /* Control-only Status */ 1040 #define DEPEVT_STATUS_CONTROL_DATA 1 1041 #define DEPEVT_STATUS_CONTROL_STATUS 2 1042 1043 /* In response to Start Transfer */ 1044 #define DEPEVT_TRANSFER_NO_RESOURCE 1 1045 #define DEPEVT_TRANSFER_BUS_EXPIRY 2 1046 1047 u32 parameters:16; 1048 } __packed; 1049 1050 /** 1051 * struct dwc3_event_devt - Device Events 1052 * @one_bit: indicates this is a non-endpoint event (not used) 1053 * @device_event: indicates it's a device event. Should read as 0x00 1054 * @type: indicates the type of device event. 1055 * 0 - DisconnEvt 1056 * 1 - USBRst 1057 * 2 - ConnectDone 1058 * 3 - ULStChng 1059 * 4 - WkUpEvt 1060 * 5 - Reserved 1061 * 6 - EOPF 1062 * 7 - SOF 1063 * 8 - Reserved 1064 * 9 - ErrticErr 1065 * 10 - CmdCmplt 1066 * 11 - EvntOverflow 1067 * 12 - VndrDevTstRcved 1068 * @reserved15_12: Reserved, not used 1069 * @event_info: Information about this event 1070 * @reserved31_25: Reserved, not used 1071 */ 1072 struct dwc3_event_devt { 1073 u32 one_bit:1; 1074 u32 device_event:7; 1075 u32 type:4; 1076 u32 reserved15_12:4; 1077 u32 event_info:9; 1078 u32 reserved31_25:7; 1079 } __packed; 1080 1081 /** 1082 * struct dwc3_event_gevt - Other Core Events 1083 * @one_bit: indicates this is a non-endpoint event (not used) 1084 * @device_event: indicates it's (0x03) Carkit or (0x04) I2C event. 1085 * @phy_port_number: self-explanatory 1086 * @reserved31_12: Reserved, not used. 1087 */ 1088 struct dwc3_event_gevt { 1089 u32 one_bit:1; 1090 u32 device_event:7; 1091 u32 phy_port_number:4; 1092 u32 reserved31_12:20; 1093 } __packed; 1094 1095 /** 1096 * union dwc3_event - representation of Event Buffer contents 1097 * @raw: raw 32-bit event 1098 * @type: the type of the event 1099 * @depevt: Device Endpoint Event 1100 * @devt: Device Event 1101 * @gevt: Global Event 1102 */ 1103 union dwc3_event { 1104 u32 raw; 1105 struct dwc3_event_type type; 1106 struct dwc3_event_depevt depevt; 1107 struct dwc3_event_devt devt; 1108 struct dwc3_event_gevt gevt; 1109 }; 1110 1111 /** 1112 * struct dwc3_gadget_ep_cmd_params - representation of endpoint command 1113 * parameters 1114 * @param2: third parameter 1115 * @param1: second parameter 1116 * @param0: first parameter 1117 */ 1118 struct dwc3_gadget_ep_cmd_params { 1119 u32 param2; 1120 u32 param1; 1121 u32 param0; 1122 }; 1123 1124 /* 1125 * DWC3 Features to be used as Driver Data 1126 */ 1127 1128 #define DWC3_HAS_PERIPHERAL BIT(0) 1129 #define DWC3_HAS_XHCI BIT(1) 1130 #define DWC3_HAS_OTG BIT(3) 1131 1132 /* prototypes */ 1133 void dwc3_set_mode(struct dwc3 *dwc, u32 mode); 1134 u32 dwc3_core_fifo_space(struct dwc3_ep *dep, u8 type); 1135 1136 /* check whether we are on the DWC_usb31 core */ 1137 static inline bool dwc3_is_usb31(struct dwc3 *dwc) 1138 { 1139 return !!(dwc->revision & DWC3_REVISION_IS_DWC31); 1140 } 1141 1142 #if IS_ENABLED(CONFIG_USB_DWC3_HOST) || IS_ENABLED(CONFIG_USB_DWC3_DUAL_ROLE) 1143 int dwc3_host_init(struct dwc3 *dwc); 1144 void dwc3_host_exit(struct dwc3 *dwc); 1145 #else 1146 static inline int dwc3_host_init(struct dwc3 *dwc) 1147 { return 0; } 1148 static inline void dwc3_host_exit(struct dwc3 *dwc) 1149 { } 1150 #endif 1151 1152 #if IS_ENABLED(CONFIG_USB_DWC3_GADGET) || IS_ENABLED(CONFIG_USB_DWC3_DUAL_ROLE) 1153 int dwc3_gadget_init(struct dwc3 *dwc); 1154 void dwc3_gadget_exit(struct dwc3 *dwc); 1155 int dwc3_gadget_set_test_mode(struct dwc3 *dwc, int mode); 1156 int dwc3_gadget_get_link_state(struct dwc3 *dwc); 1157 int dwc3_gadget_set_link_state(struct dwc3 *dwc, enum dwc3_link_state state); 1158 int dwc3_send_gadget_ep_cmd(struct dwc3_ep *dep, unsigned cmd, 1159 struct dwc3_gadget_ep_cmd_params *params); 1160 int dwc3_send_gadget_generic_command(struct dwc3 *dwc, unsigned cmd, u32 param); 1161 #else 1162 static inline int dwc3_gadget_init(struct dwc3 *dwc) 1163 { return 0; } 1164 static inline void dwc3_gadget_exit(struct dwc3 *dwc) 1165 { } 1166 static inline int dwc3_gadget_set_test_mode(struct dwc3 *dwc, int mode) 1167 { return 0; } 1168 static inline int dwc3_gadget_get_link_state(struct dwc3 *dwc) 1169 { return 0; } 1170 static inline int dwc3_gadget_set_link_state(struct dwc3 *dwc, 1171 enum dwc3_link_state state) 1172 { return 0; } 1173 1174 static inline int dwc3_send_gadget_ep_cmd(struct dwc3_ep *dep, unsigned cmd, 1175 struct dwc3_gadget_ep_cmd_params *params) 1176 { return 0; } 1177 static inline int dwc3_send_gadget_generic_command(struct dwc3 *dwc, 1178 int cmd, u32 param) 1179 { return 0; } 1180 #endif 1181 1182 /* power management interface */ 1183 #if !IS_ENABLED(CONFIG_USB_DWC3_HOST) 1184 int dwc3_gadget_suspend(struct dwc3 *dwc); 1185 int dwc3_gadget_resume(struct dwc3 *dwc); 1186 void dwc3_gadget_process_pending_events(struct dwc3 *dwc); 1187 #else 1188 static inline int dwc3_gadget_suspend(struct dwc3 *dwc) 1189 { 1190 return 0; 1191 } 1192 1193 static inline int dwc3_gadget_resume(struct dwc3 *dwc) 1194 { 1195 return 0; 1196 } 1197 1198 static inline void dwc3_gadget_process_pending_events(struct dwc3 *dwc) 1199 { 1200 } 1201 #endif /* !IS_ENABLED(CONFIG_USB_DWC3_HOST) */ 1202 1203 #if IS_ENABLED(CONFIG_USB_DWC3_ULPI) 1204 int dwc3_ulpi_init(struct dwc3 *dwc); 1205 void dwc3_ulpi_exit(struct dwc3 *dwc); 1206 #else 1207 static inline int dwc3_ulpi_init(struct dwc3 *dwc) 1208 { return 0; } 1209 static inline void dwc3_ulpi_exit(struct dwc3 *dwc) 1210 { } 1211 #endif 1212 1213 #endif /* __DRIVERS_USB_DWC3_CORE_H */ 1214