1 /** 2 * core.h - DesignWare USB3 DRD Core Header 3 * 4 * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com 5 * 6 * Authors: Felipe Balbi <balbi@ti.com>, 7 * Sebastian Andrzej Siewior <bigeasy@linutronix.de> 8 * 9 * This program is free software: you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License version 2 of 11 * the License as published by the Free Software Foundation. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 */ 18 19 #ifndef __DRIVERS_USB_DWC3_CORE_H 20 #define __DRIVERS_USB_DWC3_CORE_H 21 22 #include <linux/device.h> 23 #include <linux/spinlock.h> 24 #include <linux/ioport.h> 25 #include <linux/list.h> 26 #include <linux/dma-mapping.h> 27 #include <linux/mm.h> 28 #include <linux/debugfs.h> 29 30 #include <linux/usb/ch9.h> 31 #include <linux/usb/gadget.h> 32 #include <linux/usb/otg.h> 33 #include <linux/ulpi/interface.h> 34 35 #include <linux/phy/phy.h> 36 37 #define DWC3_MSG_MAX 500 38 39 /* Global constants */ 40 #define DWC3_ZLP_BUF_SIZE 1024 /* size of a superspeed bulk */ 41 #define DWC3_EP0_BOUNCE_SIZE 512 42 #define DWC3_ENDPOINTS_NUM 32 43 #define DWC3_XHCI_RESOURCES_NUM 2 44 45 #define DWC3_SCRATCHBUF_SIZE 4096 /* each buffer is assumed to be 4KiB */ 46 #define DWC3_EVENT_SIZE 4 /* bytes */ 47 #define DWC3_EVENT_MAX_NUM 64 /* 2 events/endpoint */ 48 #define DWC3_EVENT_BUFFERS_SIZE (DWC3_EVENT_SIZE * DWC3_EVENT_MAX_NUM) 49 #define DWC3_EVENT_TYPE_MASK 0xfe 50 51 #define DWC3_EVENT_TYPE_DEV 0 52 #define DWC3_EVENT_TYPE_CARKIT 3 53 #define DWC3_EVENT_TYPE_I2C 4 54 55 #define DWC3_DEVICE_EVENT_DISCONNECT 0 56 #define DWC3_DEVICE_EVENT_RESET 1 57 #define DWC3_DEVICE_EVENT_CONNECT_DONE 2 58 #define DWC3_DEVICE_EVENT_LINK_STATUS_CHANGE 3 59 #define DWC3_DEVICE_EVENT_WAKEUP 4 60 #define DWC3_DEVICE_EVENT_HIBER_REQ 5 61 #define DWC3_DEVICE_EVENT_EOPF 6 62 #define DWC3_DEVICE_EVENT_SOF 7 63 #define DWC3_DEVICE_EVENT_ERRATIC_ERROR 9 64 #define DWC3_DEVICE_EVENT_CMD_CMPL 10 65 #define DWC3_DEVICE_EVENT_OVERFLOW 11 66 67 #define DWC3_GEVNTCOUNT_MASK 0xfffc 68 #define DWC3_GSNPSID_MASK 0xffff0000 69 #define DWC3_GSNPSREV_MASK 0xffff 70 71 /* DWC3 registers memory space boundries */ 72 #define DWC3_XHCI_REGS_START 0x0 73 #define DWC3_XHCI_REGS_END 0x7fff 74 #define DWC3_GLOBALS_REGS_START 0xc100 75 #define DWC3_GLOBALS_REGS_END 0xc6ff 76 #define DWC3_DEVICE_REGS_START 0xc700 77 #define DWC3_DEVICE_REGS_END 0xcbff 78 #define DWC3_OTG_REGS_START 0xcc00 79 #define DWC3_OTG_REGS_END 0xccff 80 81 /* Global Registers */ 82 #define DWC3_GSBUSCFG0 0xc100 83 #define DWC3_GSBUSCFG1 0xc104 84 #define DWC3_GTXTHRCFG 0xc108 85 #define DWC3_GRXTHRCFG 0xc10c 86 #define DWC3_GCTL 0xc110 87 #define DWC3_GEVTEN 0xc114 88 #define DWC3_GSTS 0xc118 89 #define DWC3_GSNPSID 0xc120 90 #define DWC3_GGPIO 0xc124 91 #define DWC3_GUID 0xc128 92 #define DWC3_GUCTL 0xc12c 93 #define DWC3_GBUSERRADDR0 0xc130 94 #define DWC3_GBUSERRADDR1 0xc134 95 #define DWC3_GPRTBIMAP0 0xc138 96 #define DWC3_GPRTBIMAP1 0xc13c 97 #define DWC3_GHWPARAMS0 0xc140 98 #define DWC3_GHWPARAMS1 0xc144 99 #define DWC3_GHWPARAMS2 0xc148 100 #define DWC3_GHWPARAMS3 0xc14c 101 #define DWC3_GHWPARAMS4 0xc150 102 #define DWC3_GHWPARAMS5 0xc154 103 #define DWC3_GHWPARAMS6 0xc158 104 #define DWC3_GHWPARAMS7 0xc15c 105 #define DWC3_GDBGFIFOSPACE 0xc160 106 #define DWC3_GDBGLTSSM 0xc164 107 #define DWC3_GPRTBIMAP_HS0 0xc180 108 #define DWC3_GPRTBIMAP_HS1 0xc184 109 #define DWC3_GPRTBIMAP_FS0 0xc188 110 #define DWC3_GPRTBIMAP_FS1 0xc18c 111 112 #define DWC3_VER_NUMBER 0xc1a0 113 #define DWC3_VER_TYPE 0xc1a4 114 115 #define DWC3_GUSB2PHYCFG(n) (0xc200 + (n * 0x04)) 116 #define DWC3_GUSB2I2CCTL(n) (0xc240 + (n * 0x04)) 117 118 #define DWC3_GUSB2PHYACC(n) (0xc280 + (n * 0x04)) 119 120 #define DWC3_GUSB3PIPECTL(n) (0xc2c0 + (n * 0x04)) 121 122 #define DWC3_GTXFIFOSIZ(n) (0xc300 + (n * 0x04)) 123 #define DWC3_GRXFIFOSIZ(n) (0xc380 + (n * 0x04)) 124 125 #define DWC3_GEVNTADRLO(n) (0xc400 + (n * 0x10)) 126 #define DWC3_GEVNTADRHI(n) (0xc404 + (n * 0x10)) 127 #define DWC3_GEVNTSIZ(n) (0xc408 + (n * 0x10)) 128 #define DWC3_GEVNTCOUNT(n) (0xc40c + (n * 0x10)) 129 130 #define DWC3_GHWPARAMS8 0xc600 131 #define DWC3_GFLADJ 0xc630 132 133 /* Device Registers */ 134 #define DWC3_DCFG 0xc700 135 #define DWC3_DCTL 0xc704 136 #define DWC3_DEVTEN 0xc708 137 #define DWC3_DSTS 0xc70c 138 #define DWC3_DGCMDPAR 0xc710 139 #define DWC3_DGCMD 0xc714 140 #define DWC3_DALEPENA 0xc720 141 #define DWC3_DEPCMDPAR2(n) (0xc800 + (n * 0x10)) 142 #define DWC3_DEPCMDPAR1(n) (0xc804 + (n * 0x10)) 143 #define DWC3_DEPCMDPAR0(n) (0xc808 + (n * 0x10)) 144 #define DWC3_DEPCMD(n) (0xc80c + (n * 0x10)) 145 146 /* OTG Registers */ 147 #define DWC3_OCFG 0xcc00 148 #define DWC3_OCTL 0xcc04 149 #define DWC3_OEVT 0xcc08 150 #define DWC3_OEVTEN 0xcc0C 151 #define DWC3_OSTS 0xcc10 152 153 /* Bit fields */ 154 155 /* Global Configuration Register */ 156 #define DWC3_GCTL_PWRDNSCALE(n) ((n) << 19) 157 #define DWC3_GCTL_U2RSTECN (1 << 16) 158 #define DWC3_GCTL_RAMCLKSEL(x) (((x) & DWC3_GCTL_CLK_MASK) << 6) 159 #define DWC3_GCTL_CLK_BUS (0) 160 #define DWC3_GCTL_CLK_PIPE (1) 161 #define DWC3_GCTL_CLK_PIPEHALF (2) 162 #define DWC3_GCTL_CLK_MASK (3) 163 164 #define DWC3_GCTL_PRTCAP(n) (((n) & (3 << 12)) >> 12) 165 #define DWC3_GCTL_PRTCAPDIR(n) ((n) << 12) 166 #define DWC3_GCTL_PRTCAP_HOST 1 167 #define DWC3_GCTL_PRTCAP_DEVICE 2 168 #define DWC3_GCTL_PRTCAP_OTG 3 169 170 #define DWC3_GCTL_CORESOFTRESET (1 << 11) 171 #define DWC3_GCTL_SOFITPSYNC (1 << 10) 172 #define DWC3_GCTL_SCALEDOWN(n) ((n) << 4) 173 #define DWC3_GCTL_SCALEDOWN_MASK DWC3_GCTL_SCALEDOWN(3) 174 #define DWC3_GCTL_DISSCRAMBLE (1 << 3) 175 #define DWC3_GCTL_U2EXIT_LFPS (1 << 2) 176 #define DWC3_GCTL_GBLHIBERNATIONEN (1 << 1) 177 #define DWC3_GCTL_DSBLCLKGTNG (1 << 0) 178 179 /* Global USB2 PHY Configuration Register */ 180 #define DWC3_GUSB2PHYCFG_PHYSOFTRST (1 << 31) 181 #define DWC3_GUSB2PHYCFG_SUSPHY (1 << 6) 182 #define DWC3_GUSB2PHYCFG_ULPI_UTMI (1 << 4) 183 #define DWC3_GUSB2PHYCFG_ENBLSLPM (1 << 8) 184 185 /* Global USB2 PHY Vendor Control Register */ 186 #define DWC3_GUSB2PHYACC_NEWREGREQ (1 << 25) 187 #define DWC3_GUSB2PHYACC_BUSY (1 << 23) 188 #define DWC3_GUSB2PHYACC_WRITE (1 << 22) 189 #define DWC3_GUSB2PHYACC_ADDR(n) (n << 16) 190 #define DWC3_GUSB2PHYACC_EXTEND_ADDR(n) (n << 8) 191 #define DWC3_GUSB2PHYACC_DATA(n) (n & 0xff) 192 193 /* Global USB3 PIPE Control Register */ 194 #define DWC3_GUSB3PIPECTL_PHYSOFTRST (1 << 31) 195 #define DWC3_GUSB3PIPECTL_U2SSINP3OK (1 << 29) 196 #define DWC3_GUSB3PIPECTL_REQP1P2P3 (1 << 24) 197 #define DWC3_GUSB3PIPECTL_DEP1P2P3(n) ((n) << 19) 198 #define DWC3_GUSB3PIPECTL_DEP1P2P3_MASK DWC3_GUSB3PIPECTL_DEP1P2P3(7) 199 #define DWC3_GUSB3PIPECTL_DEP1P2P3_EN DWC3_GUSB3PIPECTL_DEP1P2P3(1) 200 #define DWC3_GUSB3PIPECTL_DEPOCHANGE (1 << 18) 201 #define DWC3_GUSB3PIPECTL_SUSPHY (1 << 17) 202 #define DWC3_GUSB3PIPECTL_LFPSFILT (1 << 9) 203 #define DWC3_GUSB3PIPECTL_RX_DETOPOLL (1 << 8) 204 #define DWC3_GUSB3PIPECTL_TX_DEEPH_MASK DWC3_GUSB3PIPECTL_TX_DEEPH(3) 205 #define DWC3_GUSB3PIPECTL_TX_DEEPH(n) ((n) << 1) 206 207 /* Global TX Fifo Size Register */ 208 #define DWC3_GTXFIFOSIZ_TXFDEF(n) ((n) & 0xffff) 209 #define DWC3_GTXFIFOSIZ_TXFSTADDR(n) ((n) & 0xffff0000) 210 211 /* Global Event Size Registers */ 212 #define DWC3_GEVNTSIZ_INTMASK (1 << 31) 213 #define DWC3_GEVNTSIZ_SIZE(n) ((n) & 0xffff) 214 215 /* Global HWPARAMS1 Register */ 216 #define DWC3_GHWPARAMS1_EN_PWROPT(n) (((n) & (3 << 24)) >> 24) 217 #define DWC3_GHWPARAMS1_EN_PWROPT_NO 0 218 #define DWC3_GHWPARAMS1_EN_PWROPT_CLK 1 219 #define DWC3_GHWPARAMS1_EN_PWROPT_HIB 2 220 #define DWC3_GHWPARAMS1_PWROPT(n) ((n) << 24) 221 #define DWC3_GHWPARAMS1_PWROPT_MASK DWC3_GHWPARAMS1_PWROPT(3) 222 223 /* Global HWPARAMS3 Register */ 224 #define DWC3_GHWPARAMS3_SSPHY_IFC(n) ((n) & 3) 225 #define DWC3_GHWPARAMS3_SSPHY_IFC_DIS 0 226 #define DWC3_GHWPARAMS3_SSPHY_IFC_GEN1 1 227 #define DWC3_GHWPARAMS3_SSPHY_IFC_GEN2 2 /* DWC_usb31 only */ 228 #define DWC3_GHWPARAMS3_HSPHY_IFC(n) (((n) & (3 << 2)) >> 2) 229 #define DWC3_GHWPARAMS3_HSPHY_IFC_DIS 0 230 #define DWC3_GHWPARAMS3_HSPHY_IFC_UTMI 1 231 #define DWC3_GHWPARAMS3_HSPHY_IFC_ULPI 2 232 #define DWC3_GHWPARAMS3_HSPHY_IFC_UTMI_ULPI 3 233 #define DWC3_GHWPARAMS3_FSPHY_IFC(n) (((n) & (3 << 4)) >> 4) 234 #define DWC3_GHWPARAMS3_FSPHY_IFC_DIS 0 235 #define DWC3_GHWPARAMS3_FSPHY_IFC_ENA 1 236 237 /* Global HWPARAMS4 Register */ 238 #define DWC3_GHWPARAMS4_HIBER_SCRATCHBUFS(n) (((n) & (0x0f << 13)) >> 13) 239 #define DWC3_MAX_HIBER_SCRATCHBUFS 15 240 241 /* Global HWPARAMS6 Register */ 242 #define DWC3_GHWPARAMS6_EN_FPGA (1 << 7) 243 244 /* Global Frame Length Adjustment Register */ 245 #define DWC3_GFLADJ_30MHZ_SDBND_SEL (1 << 7) 246 #define DWC3_GFLADJ_30MHZ_MASK 0x3f 247 248 /* Device Configuration Register */ 249 #define DWC3_DCFG_DEVADDR(addr) ((addr) << 3) 250 #define DWC3_DCFG_DEVADDR_MASK DWC3_DCFG_DEVADDR(0x7f) 251 252 #define DWC3_DCFG_SPEED_MASK (7 << 0) 253 #define DWC3_DCFG_SUPERSPEED_PLUS (5 << 0) /* DWC_usb31 only */ 254 #define DWC3_DCFG_SUPERSPEED (4 << 0) 255 #define DWC3_DCFG_HIGHSPEED (0 << 0) 256 #define DWC3_DCFG_FULLSPEED2 (1 << 0) 257 #define DWC3_DCFG_LOWSPEED (2 << 0) 258 #define DWC3_DCFG_FULLSPEED1 (3 << 0) 259 260 #define DWC3_DCFG_LPM_CAP (1 << 22) 261 262 /* Device Control Register */ 263 #define DWC3_DCTL_RUN_STOP (1 << 31) 264 #define DWC3_DCTL_CSFTRST (1 << 30) 265 #define DWC3_DCTL_LSFTRST (1 << 29) 266 267 #define DWC3_DCTL_HIRD_THRES_MASK (0x1f << 24) 268 #define DWC3_DCTL_HIRD_THRES(n) ((n) << 24) 269 270 #define DWC3_DCTL_APPL1RES (1 << 23) 271 272 /* These apply for core versions 1.87a and earlier */ 273 #define DWC3_DCTL_TRGTULST_MASK (0x0f << 17) 274 #define DWC3_DCTL_TRGTULST(n) ((n) << 17) 275 #define DWC3_DCTL_TRGTULST_U2 (DWC3_DCTL_TRGTULST(2)) 276 #define DWC3_DCTL_TRGTULST_U3 (DWC3_DCTL_TRGTULST(3)) 277 #define DWC3_DCTL_TRGTULST_SS_DIS (DWC3_DCTL_TRGTULST(4)) 278 #define DWC3_DCTL_TRGTULST_RX_DET (DWC3_DCTL_TRGTULST(5)) 279 #define DWC3_DCTL_TRGTULST_SS_INACT (DWC3_DCTL_TRGTULST(6)) 280 281 /* These apply for core versions 1.94a and later */ 282 #define DWC3_DCTL_LPM_ERRATA_MASK DWC3_DCTL_LPM_ERRATA(0xf) 283 #define DWC3_DCTL_LPM_ERRATA(n) ((n) << 20) 284 285 #define DWC3_DCTL_KEEP_CONNECT (1 << 19) 286 #define DWC3_DCTL_L1_HIBER_EN (1 << 18) 287 #define DWC3_DCTL_CRS (1 << 17) 288 #define DWC3_DCTL_CSS (1 << 16) 289 290 #define DWC3_DCTL_INITU2ENA (1 << 12) 291 #define DWC3_DCTL_ACCEPTU2ENA (1 << 11) 292 #define DWC3_DCTL_INITU1ENA (1 << 10) 293 #define DWC3_DCTL_ACCEPTU1ENA (1 << 9) 294 #define DWC3_DCTL_TSTCTRL_MASK (0xf << 1) 295 296 #define DWC3_DCTL_ULSTCHNGREQ_MASK (0x0f << 5) 297 #define DWC3_DCTL_ULSTCHNGREQ(n) (((n) << 5) & DWC3_DCTL_ULSTCHNGREQ_MASK) 298 299 #define DWC3_DCTL_ULSTCHNG_NO_ACTION (DWC3_DCTL_ULSTCHNGREQ(0)) 300 #define DWC3_DCTL_ULSTCHNG_SS_DISABLED (DWC3_DCTL_ULSTCHNGREQ(4)) 301 #define DWC3_DCTL_ULSTCHNG_RX_DETECT (DWC3_DCTL_ULSTCHNGREQ(5)) 302 #define DWC3_DCTL_ULSTCHNG_SS_INACTIVE (DWC3_DCTL_ULSTCHNGREQ(6)) 303 #define DWC3_DCTL_ULSTCHNG_RECOVERY (DWC3_DCTL_ULSTCHNGREQ(8)) 304 #define DWC3_DCTL_ULSTCHNG_COMPLIANCE (DWC3_DCTL_ULSTCHNGREQ(10)) 305 #define DWC3_DCTL_ULSTCHNG_LOOPBACK (DWC3_DCTL_ULSTCHNGREQ(11)) 306 307 /* Device Event Enable Register */ 308 #define DWC3_DEVTEN_VNDRDEVTSTRCVEDEN (1 << 12) 309 #define DWC3_DEVTEN_EVNTOVERFLOWEN (1 << 11) 310 #define DWC3_DEVTEN_CMDCMPLTEN (1 << 10) 311 #define DWC3_DEVTEN_ERRTICERREN (1 << 9) 312 #define DWC3_DEVTEN_SOFEN (1 << 7) 313 #define DWC3_DEVTEN_EOPFEN (1 << 6) 314 #define DWC3_DEVTEN_HIBERNATIONREQEVTEN (1 << 5) 315 #define DWC3_DEVTEN_WKUPEVTEN (1 << 4) 316 #define DWC3_DEVTEN_ULSTCNGEN (1 << 3) 317 #define DWC3_DEVTEN_CONNECTDONEEN (1 << 2) 318 #define DWC3_DEVTEN_USBRSTEN (1 << 1) 319 #define DWC3_DEVTEN_DISCONNEVTEN (1 << 0) 320 321 /* Device Status Register */ 322 #define DWC3_DSTS_DCNRD (1 << 29) 323 324 /* This applies for core versions 1.87a and earlier */ 325 #define DWC3_DSTS_PWRUPREQ (1 << 24) 326 327 /* These apply for core versions 1.94a and later */ 328 #define DWC3_DSTS_RSS (1 << 25) 329 #define DWC3_DSTS_SSS (1 << 24) 330 331 #define DWC3_DSTS_COREIDLE (1 << 23) 332 #define DWC3_DSTS_DEVCTRLHLT (1 << 22) 333 334 #define DWC3_DSTS_USBLNKST_MASK (0x0f << 18) 335 #define DWC3_DSTS_USBLNKST(n) (((n) & DWC3_DSTS_USBLNKST_MASK) >> 18) 336 337 #define DWC3_DSTS_RXFIFOEMPTY (1 << 17) 338 339 #define DWC3_DSTS_SOFFN_MASK (0x3fff << 3) 340 #define DWC3_DSTS_SOFFN(n) (((n) & DWC3_DSTS_SOFFN_MASK) >> 3) 341 342 #define DWC3_DSTS_CONNECTSPD (7 << 0) 343 344 #define DWC3_DSTS_SUPERSPEED_PLUS (5 << 0) /* DWC_usb31 only */ 345 #define DWC3_DSTS_SUPERSPEED (4 << 0) 346 #define DWC3_DSTS_HIGHSPEED (0 << 0) 347 #define DWC3_DSTS_FULLSPEED2 (1 << 0) 348 #define DWC3_DSTS_LOWSPEED (2 << 0) 349 #define DWC3_DSTS_FULLSPEED1 (3 << 0) 350 351 /* Device Generic Command Register */ 352 #define DWC3_DGCMD_SET_LMP 0x01 353 #define DWC3_DGCMD_SET_PERIODIC_PAR 0x02 354 #define DWC3_DGCMD_XMIT_FUNCTION 0x03 355 356 /* These apply for core versions 1.94a and later */ 357 #define DWC3_DGCMD_SET_SCRATCHPAD_ADDR_LO 0x04 358 #define DWC3_DGCMD_SET_SCRATCHPAD_ADDR_HI 0x05 359 360 #define DWC3_DGCMD_SELECTED_FIFO_FLUSH 0x09 361 #define DWC3_DGCMD_ALL_FIFO_FLUSH 0x0a 362 #define DWC3_DGCMD_SET_ENDPOINT_NRDY 0x0c 363 #define DWC3_DGCMD_RUN_SOC_BUS_LOOPBACK 0x10 364 365 #define DWC3_DGCMD_STATUS(n) (((n) >> 12) & 0x0F) 366 #define DWC3_DGCMD_CMDACT (1 << 10) 367 #define DWC3_DGCMD_CMDIOC (1 << 8) 368 369 /* Device Generic Command Parameter Register */ 370 #define DWC3_DGCMDPAR_FORCE_LINKPM_ACCEPT (1 << 0) 371 #define DWC3_DGCMDPAR_FIFO_NUM(n) ((n) << 0) 372 #define DWC3_DGCMDPAR_RX_FIFO (0 << 5) 373 #define DWC3_DGCMDPAR_TX_FIFO (1 << 5) 374 #define DWC3_DGCMDPAR_LOOPBACK_DIS (0 << 0) 375 #define DWC3_DGCMDPAR_LOOPBACK_ENA (1 << 0) 376 377 /* Device Endpoint Command Register */ 378 #define DWC3_DEPCMD_PARAM_SHIFT 16 379 #define DWC3_DEPCMD_PARAM(x) ((x) << DWC3_DEPCMD_PARAM_SHIFT) 380 #define DWC3_DEPCMD_GET_RSC_IDX(x) (((x) >> DWC3_DEPCMD_PARAM_SHIFT) & 0x7f) 381 #define DWC3_DEPCMD_STATUS(x) (((x) >> 12) & 0x0F) 382 #define DWC3_DEPCMD_HIPRI_FORCERM (1 << 11) 383 #define DWC3_DEPCMD_CMDACT (1 << 10) 384 #define DWC3_DEPCMD_CMDIOC (1 << 8) 385 386 #define DWC3_DEPCMD_DEPSTARTCFG (0x09 << 0) 387 #define DWC3_DEPCMD_ENDTRANSFER (0x08 << 0) 388 #define DWC3_DEPCMD_UPDATETRANSFER (0x07 << 0) 389 #define DWC3_DEPCMD_STARTTRANSFER (0x06 << 0) 390 #define DWC3_DEPCMD_CLEARSTALL (0x05 << 0) 391 #define DWC3_DEPCMD_SETSTALL (0x04 << 0) 392 /* This applies for core versions 1.90a and earlier */ 393 #define DWC3_DEPCMD_GETSEQNUMBER (0x03 << 0) 394 /* This applies for core versions 1.94a and later */ 395 #define DWC3_DEPCMD_GETEPSTATE (0x03 << 0) 396 #define DWC3_DEPCMD_SETTRANSFRESOURCE (0x02 << 0) 397 #define DWC3_DEPCMD_SETEPCONFIG (0x01 << 0) 398 399 /* The EP number goes 0..31 so ep0 is always out and ep1 is always in */ 400 #define DWC3_DALEPENA_EP(n) (1 << n) 401 402 #define DWC3_DEPCMD_TYPE_CONTROL 0 403 #define DWC3_DEPCMD_TYPE_ISOC 1 404 #define DWC3_DEPCMD_TYPE_BULK 2 405 #define DWC3_DEPCMD_TYPE_INTR 3 406 407 /* Structures */ 408 409 struct dwc3_trb; 410 411 /** 412 * struct dwc3_event_buffer - Software event buffer representation 413 * @buf: _THE_ buffer 414 * @length: size of this buffer 415 * @lpos: event offset 416 * @count: cache of last read event count register 417 * @flags: flags related to this event buffer 418 * @dma: dma_addr_t 419 * @dwc: pointer to DWC controller 420 */ 421 struct dwc3_event_buffer { 422 void *buf; 423 unsigned length; 424 unsigned int lpos; 425 unsigned int count; 426 unsigned int flags; 427 428 #define DWC3_EVENT_PENDING BIT(0) 429 430 dma_addr_t dma; 431 432 struct dwc3 *dwc; 433 }; 434 435 #define DWC3_EP_FLAG_STALLED (1 << 0) 436 #define DWC3_EP_FLAG_WEDGED (1 << 1) 437 438 #define DWC3_EP_DIRECTION_TX true 439 #define DWC3_EP_DIRECTION_RX false 440 441 #define DWC3_TRB_NUM 32 442 #define DWC3_TRB_MASK (DWC3_TRB_NUM - 1) 443 444 /** 445 * struct dwc3_ep - device side endpoint representation 446 * @endpoint: usb endpoint 447 * @request_list: list of requests for this endpoint 448 * @req_queued: list of requests on this ep which have TRBs setup 449 * @trb_pool: array of transaction buffers 450 * @trb_pool_dma: dma address of @trb_pool 451 * @free_slot: next slot which is going to be used 452 * @busy_slot: first slot which is owned by HW 453 * @desc: usb_endpoint_descriptor pointer 454 * @dwc: pointer to DWC controller 455 * @saved_state: ep state saved during hibernation 456 * @flags: endpoint flags (wedged, stalled, ...) 457 * @number: endpoint number (1 - 15) 458 * @type: set to bmAttributes & USB_ENDPOINT_XFERTYPE_MASK 459 * @resource_index: Resource transfer index 460 * @interval: the interval on which the ISOC transfer is started 461 * @name: a human readable name e.g. ep1out-bulk 462 * @direction: true for TX, false for RX 463 * @stream_capable: true when streams are enabled 464 */ 465 struct dwc3_ep { 466 struct usb_ep endpoint; 467 struct list_head request_list; 468 struct list_head req_queued; 469 470 struct dwc3_trb *trb_pool; 471 dma_addr_t trb_pool_dma; 472 u32 free_slot; 473 u32 busy_slot; 474 const struct usb_ss_ep_comp_descriptor *comp_desc; 475 struct dwc3 *dwc; 476 477 u32 saved_state; 478 unsigned flags; 479 #define DWC3_EP_ENABLED (1 << 0) 480 #define DWC3_EP_STALL (1 << 1) 481 #define DWC3_EP_WEDGE (1 << 2) 482 #define DWC3_EP_BUSY (1 << 4) 483 #define DWC3_EP_PENDING_REQUEST (1 << 5) 484 #define DWC3_EP_MISSED_ISOC (1 << 6) 485 486 /* This last one is specific to EP0 */ 487 #define DWC3_EP0_DIR_IN (1 << 31) 488 489 u8 number; 490 u8 type; 491 u8 resource_index; 492 u32 interval; 493 494 char name[20]; 495 496 unsigned direction:1; 497 unsigned stream_capable:1; 498 }; 499 500 enum dwc3_phy { 501 DWC3_PHY_UNKNOWN = 0, 502 DWC3_PHY_USB3, 503 DWC3_PHY_USB2, 504 }; 505 506 enum dwc3_ep0_next { 507 DWC3_EP0_UNKNOWN = 0, 508 DWC3_EP0_COMPLETE, 509 DWC3_EP0_NRDY_DATA, 510 DWC3_EP0_NRDY_STATUS, 511 }; 512 513 enum dwc3_ep0_state { 514 EP0_UNCONNECTED = 0, 515 EP0_SETUP_PHASE, 516 EP0_DATA_PHASE, 517 EP0_STATUS_PHASE, 518 }; 519 520 enum dwc3_link_state { 521 /* In SuperSpeed */ 522 DWC3_LINK_STATE_U0 = 0x00, /* in HS, means ON */ 523 DWC3_LINK_STATE_U1 = 0x01, 524 DWC3_LINK_STATE_U2 = 0x02, /* in HS, means SLEEP */ 525 DWC3_LINK_STATE_U3 = 0x03, /* in HS, means SUSPEND */ 526 DWC3_LINK_STATE_SS_DIS = 0x04, 527 DWC3_LINK_STATE_RX_DET = 0x05, /* in HS, means Early Suspend */ 528 DWC3_LINK_STATE_SS_INACT = 0x06, 529 DWC3_LINK_STATE_POLL = 0x07, 530 DWC3_LINK_STATE_RECOV = 0x08, 531 DWC3_LINK_STATE_HRESET = 0x09, 532 DWC3_LINK_STATE_CMPLY = 0x0a, 533 DWC3_LINK_STATE_LPBK = 0x0b, 534 DWC3_LINK_STATE_RESET = 0x0e, 535 DWC3_LINK_STATE_RESUME = 0x0f, 536 DWC3_LINK_STATE_MASK = 0x0f, 537 }; 538 539 /* TRB Length, PCM and Status */ 540 #define DWC3_TRB_SIZE_MASK (0x00ffffff) 541 #define DWC3_TRB_SIZE_LENGTH(n) ((n) & DWC3_TRB_SIZE_MASK) 542 #define DWC3_TRB_SIZE_PCM1(n) (((n) & 0x03) << 24) 543 #define DWC3_TRB_SIZE_TRBSTS(n) (((n) & (0x0f << 28)) >> 28) 544 545 #define DWC3_TRBSTS_OK 0 546 #define DWC3_TRBSTS_MISSED_ISOC 1 547 #define DWC3_TRBSTS_SETUP_PENDING 2 548 #define DWC3_TRB_STS_XFER_IN_PROG 4 549 550 /* TRB Control */ 551 #define DWC3_TRB_CTRL_HWO (1 << 0) 552 #define DWC3_TRB_CTRL_LST (1 << 1) 553 #define DWC3_TRB_CTRL_CHN (1 << 2) 554 #define DWC3_TRB_CTRL_CSP (1 << 3) 555 #define DWC3_TRB_CTRL_TRBCTL(n) (((n) & 0x3f) << 4) 556 #define DWC3_TRB_CTRL_ISP_IMI (1 << 10) 557 #define DWC3_TRB_CTRL_IOC (1 << 11) 558 #define DWC3_TRB_CTRL_SID_SOFN(n) (((n) & 0xffff) << 14) 559 560 #define DWC3_TRBCTL_NORMAL DWC3_TRB_CTRL_TRBCTL(1) 561 #define DWC3_TRBCTL_CONTROL_SETUP DWC3_TRB_CTRL_TRBCTL(2) 562 #define DWC3_TRBCTL_CONTROL_STATUS2 DWC3_TRB_CTRL_TRBCTL(3) 563 #define DWC3_TRBCTL_CONTROL_STATUS3 DWC3_TRB_CTRL_TRBCTL(4) 564 #define DWC3_TRBCTL_CONTROL_DATA DWC3_TRB_CTRL_TRBCTL(5) 565 #define DWC3_TRBCTL_ISOCHRONOUS_FIRST DWC3_TRB_CTRL_TRBCTL(6) 566 #define DWC3_TRBCTL_ISOCHRONOUS DWC3_TRB_CTRL_TRBCTL(7) 567 #define DWC3_TRBCTL_LINK_TRB DWC3_TRB_CTRL_TRBCTL(8) 568 569 /** 570 * struct dwc3_trb - transfer request block (hw format) 571 * @bpl: DW0-3 572 * @bph: DW4-7 573 * @size: DW8-B 574 * @trl: DWC-F 575 */ 576 struct dwc3_trb { 577 u32 bpl; 578 u32 bph; 579 u32 size; 580 u32 ctrl; 581 } __packed; 582 583 /** 584 * dwc3_hwparams - copy of HWPARAMS registers 585 * @hwparams0 - GHWPARAMS0 586 * @hwparams1 - GHWPARAMS1 587 * @hwparams2 - GHWPARAMS2 588 * @hwparams3 - GHWPARAMS3 589 * @hwparams4 - GHWPARAMS4 590 * @hwparams5 - GHWPARAMS5 591 * @hwparams6 - GHWPARAMS6 592 * @hwparams7 - GHWPARAMS7 593 * @hwparams8 - GHWPARAMS8 594 */ 595 struct dwc3_hwparams { 596 u32 hwparams0; 597 u32 hwparams1; 598 u32 hwparams2; 599 u32 hwparams3; 600 u32 hwparams4; 601 u32 hwparams5; 602 u32 hwparams6; 603 u32 hwparams7; 604 u32 hwparams8; 605 }; 606 607 /* HWPARAMS0 */ 608 #define DWC3_MODE(n) ((n) & 0x7) 609 610 #define DWC3_MDWIDTH(n) (((n) & 0xff00) >> 8) 611 612 /* HWPARAMS1 */ 613 #define DWC3_NUM_INT(n) (((n) & (0x3f << 15)) >> 15) 614 615 /* HWPARAMS3 */ 616 #define DWC3_NUM_IN_EPS_MASK (0x1f << 18) 617 #define DWC3_NUM_EPS_MASK (0x3f << 12) 618 #define DWC3_NUM_EPS(p) (((p)->hwparams3 & \ 619 (DWC3_NUM_EPS_MASK)) >> 12) 620 #define DWC3_NUM_IN_EPS(p) (((p)->hwparams3 & \ 621 (DWC3_NUM_IN_EPS_MASK)) >> 18) 622 623 /* HWPARAMS7 */ 624 #define DWC3_RAM1_DEPTH(n) ((n) & 0xffff) 625 626 struct dwc3_request { 627 struct usb_request request; 628 struct list_head list; 629 struct dwc3_ep *dep; 630 u32 start_slot; 631 632 u8 epnum; 633 struct dwc3_trb *trb; 634 dma_addr_t trb_dma; 635 636 unsigned direction:1; 637 unsigned mapped:1; 638 unsigned queued:1; 639 }; 640 641 /* 642 * struct dwc3_scratchpad_array - hibernation scratchpad array 643 * (format defined by hw) 644 */ 645 struct dwc3_scratchpad_array { 646 __le64 dma_adr[DWC3_MAX_HIBER_SCRATCHBUFS]; 647 }; 648 649 /** 650 * struct dwc3 - representation of our controller 651 * @ctrl_req: usb control request which is used for ep0 652 * @ep0_trb: trb which is used for the ctrl_req 653 * @ep0_bounce: bounce buffer for ep0 654 * @zlp_buf: used when request->zero is set 655 * @setup_buf: used while precessing STD USB requests 656 * @ctrl_req_addr: dma address of ctrl_req 657 * @ep0_trb: dma address of ep0_trb 658 * @ep0_usb_req: dummy req used while handling STD USB requests 659 * @ep0_bounce_addr: dma address of ep0_bounce 660 * @scratch_addr: dma address of scratchbuf 661 * @lock: for synchronizing 662 * @dev: pointer to our struct device 663 * @xhci: pointer to our xHCI child 664 * @event_buffer_list: a list of event buffers 665 * @gadget: device side representation of the peripheral controller 666 * @gadget_driver: pointer to the gadget driver 667 * @regs: base address for our registers 668 * @regs_size: address space size 669 * @nr_scratch: number of scratch buffers 670 * @num_event_buffers: calculated number of event buffers 671 * @u1u2: only used on revisions <1.83a for workaround 672 * @maximum_speed: maximum speed requested (mainly for testing purposes) 673 * @revision: revision register contents 674 * @dr_mode: requested mode of operation 675 * @usb2_phy: pointer to USB2 PHY 676 * @usb3_phy: pointer to USB3 PHY 677 * @usb2_generic_phy: pointer to USB2 PHY 678 * @usb3_generic_phy: pointer to USB3 PHY 679 * @ulpi: pointer to ulpi interface 680 * @dcfg: saved contents of DCFG register 681 * @gctl: saved contents of GCTL register 682 * @isoch_delay: wValue from Set Isochronous Delay request; 683 * @u2sel: parameter from Set SEL request. 684 * @u2pel: parameter from Set SEL request. 685 * @u1sel: parameter from Set SEL request. 686 * @u1pel: parameter from Set SEL request. 687 * @num_out_eps: number of out endpoints 688 * @num_in_eps: number of in endpoints 689 * @ep0_next_event: hold the next expected event 690 * @ep0state: state of endpoint zero 691 * @link_state: link state 692 * @speed: device speed (super, high, full, low) 693 * @mem: points to start of memory which is used for this struct. 694 * @hwparams: copy of hwparams registers 695 * @root: debugfs root folder pointer 696 * @regset: debugfs pointer to regdump file 697 * @test_mode: true when we're entering a USB test mode 698 * @test_mode_nr: test feature selector 699 * @lpm_nyet_threshold: LPM NYET response threshold 700 * @hird_threshold: HIRD threshold 701 * @hsphy_interface: "utmi" or "ulpi" 702 * @delayed_status: true when gadget driver asks for delayed status 703 * @ep0_bounced: true when we used bounce buffer 704 * @ep0_expect_in: true when we expect a DATA IN transfer 705 * @has_hibernation: true when dwc3 was configured with Hibernation 706 * @has_lpm_erratum: true when core was configured with LPM Erratum. Note that 707 * there's now way for software to detect this in runtime. 708 * @is_utmi_l1_suspend: the core asserts output signal 709 * 0 - utmi_sleep_n 710 * 1 - utmi_l1_suspend_n 711 * @is_fpga: true when we are using the FPGA board 712 * @needs_fifo_resize: not all users might want fifo resizing, flag it 713 * @pullups_connected: true when Run/Stop bit is set 714 * @resize_fifos: tells us it's ok to reconfigure our TxFIFO sizes. 715 * @setup_packet_pending: true when there's a Setup Packet in FIFO. Workaround 716 * @start_config_issued: true when StartConfig command has been issued 717 * @three_stage_setup: set if we perform a three phase setup 718 * @usb3_lpm_capable: set if hadrware supports Link Power Management 719 * @disable_scramble_quirk: set if we enable the disable scramble quirk 720 * @u2exit_lfps_quirk: set if we enable u2exit lfps quirk 721 * @u2ss_inp3_quirk: set if we enable P3 OK for U2/SS Inactive quirk 722 * @req_p1p2p3_quirk: set if we enable request p1p2p3 quirk 723 * @del_p1p2p3_quirk: set if we enable delay p1p2p3 quirk 724 * @del_phy_power_chg_quirk: set if we enable delay phy power change quirk 725 * @lfps_filter_quirk: set if we enable LFPS filter quirk 726 * @rx_detect_poll_quirk: set if we enable rx_detect to polling lfps quirk 727 * @dis_u3_susphy_quirk: set if we disable usb3 suspend phy 728 * @dis_u2_susphy_quirk: set if we disable usb2 suspend phy 729 * @dis_enblslpm_quirk: set if we clear enblslpm in GUSB2PHYCFG, 730 * disabling the suspend signal to the PHY. 731 * @tx_de_emphasis_quirk: set if we enable Tx de-emphasis quirk 732 * @tx_de_emphasis: Tx de-emphasis value 733 * 0 - -6dB de-emphasis 734 * 1 - -3.5dB de-emphasis 735 * 2 - No de-emphasis 736 * 3 - Reserved 737 */ 738 struct dwc3 { 739 struct usb_ctrlrequest *ctrl_req; 740 struct dwc3_trb *ep0_trb; 741 void *ep0_bounce; 742 void *zlp_buf; 743 void *scratchbuf; 744 u8 *setup_buf; 745 dma_addr_t ctrl_req_addr; 746 dma_addr_t ep0_trb_addr; 747 dma_addr_t ep0_bounce_addr; 748 dma_addr_t scratch_addr; 749 struct dwc3_request ep0_usb_req; 750 751 /* device lock */ 752 spinlock_t lock; 753 754 struct device *dev; 755 756 struct platform_device *xhci; 757 struct resource xhci_resources[DWC3_XHCI_RESOURCES_NUM]; 758 759 struct dwc3_event_buffer **ev_buffs; 760 struct dwc3_ep *eps[DWC3_ENDPOINTS_NUM]; 761 762 struct usb_gadget gadget; 763 struct usb_gadget_driver *gadget_driver; 764 765 struct usb_phy *usb2_phy; 766 struct usb_phy *usb3_phy; 767 768 struct phy *usb2_generic_phy; 769 struct phy *usb3_generic_phy; 770 771 struct ulpi *ulpi; 772 773 void __iomem *regs; 774 size_t regs_size; 775 776 enum usb_dr_mode dr_mode; 777 778 /* used for suspend/resume */ 779 u32 dcfg; 780 u32 gctl; 781 782 u32 nr_scratch; 783 u32 num_event_buffers; 784 u32 u1u2; 785 u32 maximum_speed; 786 787 /* 788 * All 3.1 IP version constants are greater than the 3.0 IP 789 * version constants. This works for most version checks in 790 * dwc3. However, in the future, this may not apply as 791 * features may be developed on newer versions of the 3.0 IP 792 * that are not in the 3.1 IP. 793 */ 794 u32 revision; 795 796 #define DWC3_REVISION_173A 0x5533173a 797 #define DWC3_REVISION_175A 0x5533175a 798 #define DWC3_REVISION_180A 0x5533180a 799 #define DWC3_REVISION_183A 0x5533183a 800 #define DWC3_REVISION_185A 0x5533185a 801 #define DWC3_REVISION_187A 0x5533187a 802 #define DWC3_REVISION_188A 0x5533188a 803 #define DWC3_REVISION_190A 0x5533190a 804 #define DWC3_REVISION_194A 0x5533194a 805 #define DWC3_REVISION_200A 0x5533200a 806 #define DWC3_REVISION_202A 0x5533202a 807 #define DWC3_REVISION_210A 0x5533210a 808 #define DWC3_REVISION_220A 0x5533220a 809 #define DWC3_REVISION_230A 0x5533230a 810 #define DWC3_REVISION_240A 0x5533240a 811 #define DWC3_REVISION_250A 0x5533250a 812 #define DWC3_REVISION_260A 0x5533260a 813 #define DWC3_REVISION_270A 0x5533270a 814 #define DWC3_REVISION_280A 0x5533280a 815 816 /* 817 * NOTICE: we're using bit 31 as a "is usb 3.1" flag. This is really 818 * just so dwc31 revisions are always larger than dwc3. 819 */ 820 #define DWC3_REVISION_IS_DWC31 0x80000000 821 #define DWC3_USB31_REVISION_110A (0x3131302a | DWC3_REVISION_IS_USB31) 822 823 enum dwc3_ep0_next ep0_next_event; 824 enum dwc3_ep0_state ep0state; 825 enum dwc3_link_state link_state; 826 827 u16 isoch_delay; 828 u16 u2sel; 829 u16 u2pel; 830 u8 u1sel; 831 u8 u1pel; 832 833 u8 speed; 834 835 u8 num_out_eps; 836 u8 num_in_eps; 837 838 void *mem; 839 840 struct dwc3_hwparams hwparams; 841 struct dentry *root; 842 struct debugfs_regset32 *regset; 843 844 u8 test_mode; 845 u8 test_mode_nr; 846 u8 lpm_nyet_threshold; 847 u8 hird_threshold; 848 849 const char *hsphy_interface; 850 851 unsigned delayed_status:1; 852 unsigned ep0_bounced:1; 853 unsigned ep0_expect_in:1; 854 unsigned has_hibernation:1; 855 unsigned has_lpm_erratum:1; 856 unsigned is_utmi_l1_suspend:1; 857 unsigned is_fpga:1; 858 unsigned needs_fifo_resize:1; 859 unsigned pullups_connected:1; 860 unsigned resize_fifos:1; 861 unsigned setup_packet_pending:1; 862 unsigned three_stage_setup:1; 863 unsigned usb3_lpm_capable:1; 864 865 unsigned disable_scramble_quirk:1; 866 unsigned u2exit_lfps_quirk:1; 867 unsigned u2ss_inp3_quirk:1; 868 unsigned req_p1p2p3_quirk:1; 869 unsigned del_p1p2p3_quirk:1; 870 unsigned del_phy_power_chg_quirk:1; 871 unsigned lfps_filter_quirk:1; 872 unsigned rx_detect_poll_quirk:1; 873 unsigned dis_u3_susphy_quirk:1; 874 unsigned dis_u2_susphy_quirk:1; 875 unsigned dis_enblslpm_quirk:1; 876 877 unsigned tx_de_emphasis_quirk:1; 878 unsigned tx_de_emphasis:2; 879 }; 880 881 /* -------------------------------------------------------------------------- */ 882 883 /* -------------------------------------------------------------------------- */ 884 885 struct dwc3_event_type { 886 u32 is_devspec:1; 887 u32 type:7; 888 u32 reserved8_31:24; 889 } __packed; 890 891 #define DWC3_DEPEVT_XFERCOMPLETE 0x01 892 #define DWC3_DEPEVT_XFERINPROGRESS 0x02 893 #define DWC3_DEPEVT_XFERNOTREADY 0x03 894 #define DWC3_DEPEVT_RXTXFIFOEVT 0x04 895 #define DWC3_DEPEVT_STREAMEVT 0x06 896 #define DWC3_DEPEVT_EPCMDCMPLT 0x07 897 898 /** 899 * struct dwc3_event_depvt - Device Endpoint Events 900 * @one_bit: indicates this is an endpoint event (not used) 901 * @endpoint_number: number of the endpoint 902 * @endpoint_event: The event we have: 903 * 0x00 - Reserved 904 * 0x01 - XferComplete 905 * 0x02 - XferInProgress 906 * 0x03 - XferNotReady 907 * 0x04 - RxTxFifoEvt (IN->Underrun, OUT->Overrun) 908 * 0x05 - Reserved 909 * 0x06 - StreamEvt 910 * 0x07 - EPCmdCmplt 911 * @reserved11_10: Reserved, don't use. 912 * @status: Indicates the status of the event. Refer to databook for 913 * more information. 914 * @parameters: Parameters of the current event. Refer to databook for 915 * more information. 916 */ 917 struct dwc3_event_depevt { 918 u32 one_bit:1; 919 u32 endpoint_number:5; 920 u32 endpoint_event:4; 921 u32 reserved11_10:2; 922 u32 status:4; 923 924 /* Within XferNotReady */ 925 #define DEPEVT_STATUS_TRANSFER_ACTIVE (1 << 3) 926 927 /* Within XferComplete */ 928 #define DEPEVT_STATUS_BUSERR (1 << 0) 929 #define DEPEVT_STATUS_SHORT (1 << 1) 930 #define DEPEVT_STATUS_IOC (1 << 2) 931 #define DEPEVT_STATUS_LST (1 << 3) 932 933 /* Stream event only */ 934 #define DEPEVT_STREAMEVT_FOUND 1 935 #define DEPEVT_STREAMEVT_NOTFOUND 2 936 937 /* Control-only Status */ 938 #define DEPEVT_STATUS_CONTROL_DATA 1 939 #define DEPEVT_STATUS_CONTROL_STATUS 2 940 941 u32 parameters:16; 942 } __packed; 943 944 /** 945 * struct dwc3_event_devt - Device Events 946 * @one_bit: indicates this is a non-endpoint event (not used) 947 * @device_event: indicates it's a device event. Should read as 0x00 948 * @type: indicates the type of device event. 949 * 0 - DisconnEvt 950 * 1 - USBRst 951 * 2 - ConnectDone 952 * 3 - ULStChng 953 * 4 - WkUpEvt 954 * 5 - Reserved 955 * 6 - EOPF 956 * 7 - SOF 957 * 8 - Reserved 958 * 9 - ErrticErr 959 * 10 - CmdCmplt 960 * 11 - EvntOverflow 961 * 12 - VndrDevTstRcved 962 * @reserved15_12: Reserved, not used 963 * @event_info: Information about this event 964 * @reserved31_25: Reserved, not used 965 */ 966 struct dwc3_event_devt { 967 u32 one_bit:1; 968 u32 device_event:7; 969 u32 type:4; 970 u32 reserved15_12:4; 971 u32 event_info:9; 972 u32 reserved31_25:7; 973 } __packed; 974 975 /** 976 * struct dwc3_event_gevt - Other Core Events 977 * @one_bit: indicates this is a non-endpoint event (not used) 978 * @device_event: indicates it's (0x03) Carkit or (0x04) I2C event. 979 * @phy_port_number: self-explanatory 980 * @reserved31_12: Reserved, not used. 981 */ 982 struct dwc3_event_gevt { 983 u32 one_bit:1; 984 u32 device_event:7; 985 u32 phy_port_number:4; 986 u32 reserved31_12:20; 987 } __packed; 988 989 /** 990 * union dwc3_event - representation of Event Buffer contents 991 * @raw: raw 32-bit event 992 * @type: the type of the event 993 * @depevt: Device Endpoint Event 994 * @devt: Device Event 995 * @gevt: Global Event 996 */ 997 union dwc3_event { 998 u32 raw; 999 struct dwc3_event_type type; 1000 struct dwc3_event_depevt depevt; 1001 struct dwc3_event_devt devt; 1002 struct dwc3_event_gevt gevt; 1003 }; 1004 1005 /** 1006 * struct dwc3_gadget_ep_cmd_params - representation of endpoint command 1007 * parameters 1008 * @param2: third parameter 1009 * @param1: second parameter 1010 * @param0: first parameter 1011 */ 1012 struct dwc3_gadget_ep_cmd_params { 1013 u32 param2; 1014 u32 param1; 1015 u32 param0; 1016 }; 1017 1018 /* 1019 * DWC3 Features to be used as Driver Data 1020 */ 1021 1022 #define DWC3_HAS_PERIPHERAL BIT(0) 1023 #define DWC3_HAS_XHCI BIT(1) 1024 #define DWC3_HAS_OTG BIT(3) 1025 1026 /* prototypes */ 1027 void dwc3_set_mode(struct dwc3 *dwc, u32 mode); 1028 int dwc3_gadget_resize_tx_fifos(struct dwc3 *dwc); 1029 1030 /* check whether we are on the DWC_usb31 core */ 1031 static inline bool dwc3_is_usb31(struct dwc3 *dwc) 1032 { 1033 return !!(dwc->revision & DWC3_REVISION_IS_DWC31); 1034 } 1035 1036 #if IS_ENABLED(CONFIG_USB_DWC3_HOST) || IS_ENABLED(CONFIG_USB_DWC3_DUAL_ROLE) 1037 int dwc3_host_init(struct dwc3 *dwc); 1038 void dwc3_host_exit(struct dwc3 *dwc); 1039 #else 1040 static inline int dwc3_host_init(struct dwc3 *dwc) 1041 { return 0; } 1042 static inline void dwc3_host_exit(struct dwc3 *dwc) 1043 { } 1044 #endif 1045 1046 #if IS_ENABLED(CONFIG_USB_DWC3_GADGET) || IS_ENABLED(CONFIG_USB_DWC3_DUAL_ROLE) 1047 int dwc3_gadget_init(struct dwc3 *dwc); 1048 void dwc3_gadget_exit(struct dwc3 *dwc); 1049 int dwc3_gadget_set_test_mode(struct dwc3 *dwc, int mode); 1050 int dwc3_gadget_get_link_state(struct dwc3 *dwc); 1051 int dwc3_gadget_set_link_state(struct dwc3 *dwc, enum dwc3_link_state state); 1052 int dwc3_send_gadget_ep_cmd(struct dwc3 *dwc, unsigned ep, 1053 unsigned cmd, struct dwc3_gadget_ep_cmd_params *params); 1054 int dwc3_send_gadget_generic_command(struct dwc3 *dwc, unsigned cmd, u32 param); 1055 #else 1056 static inline int dwc3_gadget_init(struct dwc3 *dwc) 1057 { return 0; } 1058 static inline void dwc3_gadget_exit(struct dwc3 *dwc) 1059 { } 1060 static inline int dwc3_gadget_set_test_mode(struct dwc3 *dwc, int mode) 1061 { return 0; } 1062 static inline int dwc3_gadget_get_link_state(struct dwc3 *dwc) 1063 { return 0; } 1064 static inline int dwc3_gadget_set_link_state(struct dwc3 *dwc, 1065 enum dwc3_link_state state) 1066 { return 0; } 1067 1068 static inline int dwc3_send_gadget_ep_cmd(struct dwc3 *dwc, unsigned ep, 1069 unsigned cmd, struct dwc3_gadget_ep_cmd_params *params) 1070 { return 0; } 1071 static inline int dwc3_send_gadget_generic_command(struct dwc3 *dwc, 1072 int cmd, u32 param) 1073 { return 0; } 1074 #endif 1075 1076 /* power management interface */ 1077 #if !IS_ENABLED(CONFIG_USB_DWC3_HOST) 1078 int dwc3_gadget_suspend(struct dwc3 *dwc); 1079 int dwc3_gadget_resume(struct dwc3 *dwc); 1080 #else 1081 static inline int dwc3_gadget_suspend(struct dwc3 *dwc) 1082 { 1083 return 0; 1084 } 1085 1086 static inline int dwc3_gadget_resume(struct dwc3 *dwc) 1087 { 1088 return 0; 1089 } 1090 #endif /* !IS_ENABLED(CONFIG_USB_DWC3_HOST) */ 1091 1092 #if IS_ENABLED(CONFIG_USB_DWC3_ULPI) 1093 int dwc3_ulpi_init(struct dwc3 *dwc); 1094 void dwc3_ulpi_exit(struct dwc3 *dwc); 1095 #else 1096 static inline int dwc3_ulpi_init(struct dwc3 *dwc) 1097 { return 0; } 1098 static inline void dwc3_ulpi_exit(struct dwc3 *dwc) 1099 { } 1100 #endif 1101 1102 #endif /* __DRIVERS_USB_DWC3_CORE_H */ 1103