1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * core.h - DesignWare USB3 DRD Core Header 4 * 5 * Copyright (C) 2010-2011 Texas Instruments Incorporated - https://www.ti.com 6 * 7 * Authors: Felipe Balbi <balbi@ti.com>, 8 * Sebastian Andrzej Siewior <bigeasy@linutronix.de> 9 */ 10 11 #ifndef __DRIVERS_USB_DWC3_CORE_H 12 #define __DRIVERS_USB_DWC3_CORE_H 13 14 #include <linux/device.h> 15 #include <linux/spinlock.h> 16 #include <linux/mutex.h> 17 #include <linux/ioport.h> 18 #include <linux/list.h> 19 #include <linux/bitops.h> 20 #include <linux/dma-mapping.h> 21 #include <linux/mm.h> 22 #include <linux/debugfs.h> 23 #include <linux/wait.h> 24 #include <linux/workqueue.h> 25 26 #include <linux/usb/ch9.h> 27 #include <linux/usb/gadget.h> 28 #include <linux/usb/otg.h> 29 #include <linux/usb/role.h> 30 #include <linux/ulpi/interface.h> 31 32 #include <linux/phy/phy.h> 33 34 #include <linux/power_supply.h> 35 36 #define DWC3_MSG_MAX 500 37 38 /* Global constants */ 39 #define DWC3_PULL_UP_TIMEOUT 500 /* ms */ 40 #define DWC3_BOUNCE_SIZE 1024 /* size of a superspeed bulk */ 41 #define DWC3_EP0_SETUP_SIZE 512 42 #define DWC3_ENDPOINTS_NUM 32 43 #define DWC3_XHCI_RESOURCES_NUM 2 44 #define DWC3_ISOC_MAX_RETRIES 5 45 46 #define DWC3_SCRATCHBUF_SIZE 4096 /* each buffer is assumed to be 4KiB */ 47 #define DWC3_EVENT_BUFFERS_SIZE 4096 48 #define DWC3_EVENT_TYPE_MASK 0xfe 49 50 #define DWC3_EVENT_TYPE_DEV 0 51 #define DWC3_EVENT_TYPE_CARKIT 3 52 #define DWC3_EVENT_TYPE_I2C 4 53 54 #define DWC3_DEVICE_EVENT_DISCONNECT 0 55 #define DWC3_DEVICE_EVENT_RESET 1 56 #define DWC3_DEVICE_EVENT_CONNECT_DONE 2 57 #define DWC3_DEVICE_EVENT_LINK_STATUS_CHANGE 3 58 #define DWC3_DEVICE_EVENT_WAKEUP 4 59 #define DWC3_DEVICE_EVENT_HIBER_REQ 5 60 #define DWC3_DEVICE_EVENT_SUSPEND 6 61 #define DWC3_DEVICE_EVENT_SOF 7 62 #define DWC3_DEVICE_EVENT_ERRATIC_ERROR 9 63 #define DWC3_DEVICE_EVENT_CMD_CMPL 10 64 #define DWC3_DEVICE_EVENT_OVERFLOW 11 65 66 /* Controller's role while using the OTG block */ 67 #define DWC3_OTG_ROLE_IDLE 0 68 #define DWC3_OTG_ROLE_HOST 1 69 #define DWC3_OTG_ROLE_DEVICE 2 70 71 #define DWC3_GEVNTCOUNT_MASK 0xfffc 72 #define DWC3_GEVNTCOUNT_EHB BIT(31) 73 #define DWC3_GSNPSID_MASK 0xffff0000 74 #define DWC3_GSNPSREV_MASK 0xffff 75 #define DWC3_GSNPS_ID(p) (((p) & DWC3_GSNPSID_MASK) >> 16) 76 77 /* DWC3 registers memory space boundries */ 78 #define DWC3_XHCI_REGS_START 0x0 79 #define DWC3_XHCI_REGS_END 0x7fff 80 #define DWC3_GLOBALS_REGS_START 0xc100 81 #define DWC3_GLOBALS_REGS_END 0xc6ff 82 #define DWC3_DEVICE_REGS_START 0xc700 83 #define DWC3_DEVICE_REGS_END 0xcbff 84 #define DWC3_OTG_REGS_START 0xcc00 85 #define DWC3_OTG_REGS_END 0xccff 86 87 /* Global Registers */ 88 #define DWC3_GSBUSCFG0 0xc100 89 #define DWC3_GSBUSCFG1 0xc104 90 #define DWC3_GTXTHRCFG 0xc108 91 #define DWC3_GRXTHRCFG 0xc10c 92 #define DWC3_GCTL 0xc110 93 #define DWC3_GEVTEN 0xc114 94 #define DWC3_GSTS 0xc118 95 #define DWC3_GUCTL1 0xc11c 96 #define DWC3_GSNPSID 0xc120 97 #define DWC3_GGPIO 0xc124 98 #define DWC3_GUID 0xc128 99 #define DWC3_GUCTL 0xc12c 100 #define DWC3_GBUSERRADDR0 0xc130 101 #define DWC3_GBUSERRADDR1 0xc134 102 #define DWC3_GPRTBIMAP0 0xc138 103 #define DWC3_GPRTBIMAP1 0xc13c 104 #define DWC3_GHWPARAMS0 0xc140 105 #define DWC3_GHWPARAMS1 0xc144 106 #define DWC3_GHWPARAMS2 0xc148 107 #define DWC3_GHWPARAMS3 0xc14c 108 #define DWC3_GHWPARAMS4 0xc150 109 #define DWC3_GHWPARAMS5 0xc154 110 #define DWC3_GHWPARAMS6 0xc158 111 #define DWC3_GHWPARAMS7 0xc15c 112 #define DWC3_GDBGFIFOSPACE 0xc160 113 #define DWC3_GDBGLTSSM 0xc164 114 #define DWC3_GDBGBMU 0xc16c 115 #define DWC3_GDBGLSPMUX 0xc170 116 #define DWC3_GDBGLSP 0xc174 117 #define DWC3_GDBGEPINFO0 0xc178 118 #define DWC3_GDBGEPINFO1 0xc17c 119 #define DWC3_GPRTBIMAP_HS0 0xc180 120 #define DWC3_GPRTBIMAP_HS1 0xc184 121 #define DWC3_GPRTBIMAP_FS0 0xc188 122 #define DWC3_GPRTBIMAP_FS1 0xc18c 123 #define DWC3_GUCTL2 0xc19c 124 125 #define DWC3_VER_NUMBER 0xc1a0 126 #define DWC3_VER_TYPE 0xc1a4 127 128 #define DWC3_GUSB2PHYCFG(n) (0xc200 + ((n) * 0x04)) 129 #define DWC3_GUSB2I2CCTL(n) (0xc240 + ((n) * 0x04)) 130 131 #define DWC3_GUSB2PHYACC(n) (0xc280 + ((n) * 0x04)) 132 133 #define DWC3_GUSB3PIPECTL(n) (0xc2c0 + ((n) * 0x04)) 134 135 #define DWC3_GTXFIFOSIZ(n) (0xc300 + ((n) * 0x04)) 136 #define DWC3_GRXFIFOSIZ(n) (0xc380 + ((n) * 0x04)) 137 138 #define DWC3_GEVNTADRLO(n) (0xc400 + ((n) * 0x10)) 139 #define DWC3_GEVNTADRHI(n) (0xc404 + ((n) * 0x10)) 140 #define DWC3_GEVNTSIZ(n) (0xc408 + ((n) * 0x10)) 141 #define DWC3_GEVNTCOUNT(n) (0xc40c + ((n) * 0x10)) 142 143 #define DWC3_GHWPARAMS8 0xc600 144 #define DWC3_GUCTL3 0xc60c 145 #define DWC3_GFLADJ 0xc630 146 #define DWC3_GHWPARAMS9 0xc680 147 148 /* Device Registers */ 149 #define DWC3_DCFG 0xc700 150 #define DWC3_DCTL 0xc704 151 #define DWC3_DEVTEN 0xc708 152 #define DWC3_DSTS 0xc70c 153 #define DWC3_DGCMDPAR 0xc710 154 #define DWC3_DGCMD 0xc714 155 #define DWC3_DALEPENA 0xc720 156 157 #define DWC3_DEP_BASE(n) (0xc800 + ((n) * 0x10)) 158 #define DWC3_DEPCMDPAR2 0x00 159 #define DWC3_DEPCMDPAR1 0x04 160 #define DWC3_DEPCMDPAR0 0x08 161 #define DWC3_DEPCMD 0x0c 162 163 #define DWC3_DEV_IMOD(n) (0xca00 + ((n) * 0x4)) 164 165 /* OTG Registers */ 166 #define DWC3_OCFG 0xcc00 167 #define DWC3_OCTL 0xcc04 168 #define DWC3_OEVT 0xcc08 169 #define DWC3_OEVTEN 0xcc0C 170 #define DWC3_OSTS 0xcc10 171 172 /* Bit fields */ 173 174 /* Global SoC Bus Configuration INCRx Register 0 */ 175 #define DWC3_GSBUSCFG0_INCR256BRSTENA (1 << 7) /* INCR256 burst */ 176 #define DWC3_GSBUSCFG0_INCR128BRSTENA (1 << 6) /* INCR128 burst */ 177 #define DWC3_GSBUSCFG0_INCR64BRSTENA (1 << 5) /* INCR64 burst */ 178 #define DWC3_GSBUSCFG0_INCR32BRSTENA (1 << 4) /* INCR32 burst */ 179 #define DWC3_GSBUSCFG0_INCR16BRSTENA (1 << 3) /* INCR16 burst */ 180 #define DWC3_GSBUSCFG0_INCR8BRSTENA (1 << 2) /* INCR8 burst */ 181 #define DWC3_GSBUSCFG0_INCR4BRSTENA (1 << 1) /* INCR4 burst */ 182 #define DWC3_GSBUSCFG0_INCRBRSTENA (1 << 0) /* undefined length enable */ 183 #define DWC3_GSBUSCFG0_INCRBRST_MASK 0xff 184 185 /* Global Debug LSP MUX Select */ 186 #define DWC3_GDBGLSPMUX_ENDBC BIT(15) /* Host only */ 187 #define DWC3_GDBGLSPMUX_HOSTSELECT(n) ((n) & 0x3fff) 188 #define DWC3_GDBGLSPMUX_DEVSELECT(n) (((n) & 0xf) << 4) 189 #define DWC3_GDBGLSPMUX_EPSELECT(n) ((n) & 0xf) 190 191 /* Global Debug Queue/FIFO Space Available Register */ 192 #define DWC3_GDBGFIFOSPACE_NUM(n) ((n) & 0x1f) 193 #define DWC3_GDBGFIFOSPACE_TYPE(n) (((n) << 5) & 0x1e0) 194 #define DWC3_GDBGFIFOSPACE_SPACE_AVAILABLE(n) (((n) >> 16) & 0xffff) 195 196 #define DWC3_TXFIFO 0 197 #define DWC3_RXFIFO 1 198 #define DWC3_TXREQQ 2 199 #define DWC3_RXREQQ 3 200 #define DWC3_RXINFOQ 4 201 #define DWC3_PSTATQ 5 202 #define DWC3_DESCFETCHQ 6 203 #define DWC3_EVENTQ 7 204 #define DWC3_AUXEVENTQ 8 205 206 /* Global RX Threshold Configuration Register */ 207 #define DWC3_GRXTHRCFG_MAXRXBURSTSIZE(n) (((n) & 0x1f) << 19) 208 #define DWC3_GRXTHRCFG_RXPKTCNT(n) (((n) & 0xf) << 24) 209 #define DWC3_GRXTHRCFG_PKTCNTSEL BIT(29) 210 211 /* Global RX Threshold Configuration Register for DWC_usb31 only */ 212 #define DWC31_GRXTHRCFG_MAXRXBURSTSIZE(n) (((n) & 0x1f) << 16) 213 #define DWC31_GRXTHRCFG_RXPKTCNT(n) (((n) & 0x1f) << 21) 214 #define DWC31_GRXTHRCFG_PKTCNTSEL BIT(26) 215 #define DWC31_RXTHRNUMPKTSEL_HS_PRD BIT(15) 216 #define DWC31_RXTHRNUMPKT_HS_PRD(n) (((n) & 0x3) << 13) 217 #define DWC31_RXTHRNUMPKTSEL_PRD BIT(10) 218 #define DWC31_RXTHRNUMPKT_PRD(n) (((n) & 0x1f) << 5) 219 #define DWC31_MAXRXBURSTSIZE_PRD(n) ((n) & 0x1f) 220 221 /* Global TX Threshold Configuration Register for DWC_usb31 only */ 222 #define DWC31_GTXTHRCFG_MAXTXBURSTSIZE(n) (((n) & 0x1f) << 16) 223 #define DWC31_GTXTHRCFG_TXPKTCNT(n) (((n) & 0x1f) << 21) 224 #define DWC31_GTXTHRCFG_PKTCNTSEL BIT(26) 225 #define DWC31_TXTHRNUMPKTSEL_HS_PRD BIT(15) 226 #define DWC31_TXTHRNUMPKT_HS_PRD(n) (((n) & 0x3) << 13) 227 #define DWC31_TXTHRNUMPKTSEL_PRD BIT(10) 228 #define DWC31_TXTHRNUMPKT_PRD(n) (((n) & 0x1f) << 5) 229 #define DWC31_MAXTXBURSTSIZE_PRD(n) ((n) & 0x1f) 230 231 /* Global Configuration Register */ 232 #define DWC3_GCTL_PWRDNSCALE(n) ((n) << 19) 233 #define DWC3_GCTL_U2RSTECN BIT(16) 234 #define DWC3_GCTL_RAMCLKSEL(x) (((x) & DWC3_GCTL_CLK_MASK) << 6) 235 #define DWC3_GCTL_CLK_BUS (0) 236 #define DWC3_GCTL_CLK_PIPE (1) 237 #define DWC3_GCTL_CLK_PIPEHALF (2) 238 #define DWC3_GCTL_CLK_MASK (3) 239 240 #define DWC3_GCTL_PRTCAP(n) (((n) & (3 << 12)) >> 12) 241 #define DWC3_GCTL_PRTCAPDIR(n) ((n) << 12) 242 #define DWC3_GCTL_PRTCAP_HOST 1 243 #define DWC3_GCTL_PRTCAP_DEVICE 2 244 #define DWC3_GCTL_PRTCAP_OTG 3 245 246 #define DWC3_GCTL_CORESOFTRESET BIT(11) 247 #define DWC3_GCTL_SOFITPSYNC BIT(10) 248 #define DWC3_GCTL_SCALEDOWN(n) ((n) << 4) 249 #define DWC3_GCTL_SCALEDOWN_MASK DWC3_GCTL_SCALEDOWN(3) 250 #define DWC3_GCTL_DISSCRAMBLE BIT(3) 251 #define DWC3_GCTL_U2EXIT_LFPS BIT(2) 252 #define DWC3_GCTL_GBLHIBERNATIONEN BIT(1) 253 #define DWC3_GCTL_DSBLCLKGTNG BIT(0) 254 255 /* Global User Control Register */ 256 #define DWC3_GUCTL_HSTINAUTORETRY BIT(14) 257 258 /* Global User Control 1 Register */ 259 #define DWC3_GUCTL1_PARKMODE_DISABLE_SS BIT(17) 260 #define DWC3_GUCTL1_TX_IPGAP_LINECHECK_DIS BIT(28) 261 #define DWC3_GUCTL1_DEV_L1_EXIT_BY_HW BIT(24) 262 263 /* Global Status Register */ 264 #define DWC3_GSTS_OTG_IP BIT(10) 265 #define DWC3_GSTS_BC_IP BIT(9) 266 #define DWC3_GSTS_ADP_IP BIT(8) 267 #define DWC3_GSTS_HOST_IP BIT(7) 268 #define DWC3_GSTS_DEVICE_IP BIT(6) 269 #define DWC3_GSTS_CSR_TIMEOUT BIT(5) 270 #define DWC3_GSTS_BUS_ERR_ADDR_VLD BIT(4) 271 #define DWC3_GSTS_CURMOD(n) ((n) & 0x3) 272 #define DWC3_GSTS_CURMOD_DEVICE 0 273 #define DWC3_GSTS_CURMOD_HOST 1 274 275 /* Global USB2 PHY Configuration Register */ 276 #define DWC3_GUSB2PHYCFG_PHYSOFTRST BIT(31) 277 #define DWC3_GUSB2PHYCFG_U2_FREECLK_EXISTS BIT(30) 278 #define DWC3_GUSB2PHYCFG_SUSPHY BIT(6) 279 #define DWC3_GUSB2PHYCFG_ULPI_UTMI BIT(4) 280 #define DWC3_GUSB2PHYCFG_ENBLSLPM BIT(8) 281 #define DWC3_GUSB2PHYCFG_PHYIF(n) (n << 3) 282 #define DWC3_GUSB2PHYCFG_PHYIF_MASK DWC3_GUSB2PHYCFG_PHYIF(1) 283 #define DWC3_GUSB2PHYCFG_USBTRDTIM(n) (n << 10) 284 #define DWC3_GUSB2PHYCFG_USBTRDTIM_MASK DWC3_GUSB2PHYCFG_USBTRDTIM(0xf) 285 #define USBTRDTIM_UTMI_8_BIT 9 286 #define USBTRDTIM_UTMI_16_BIT 5 287 #define UTMI_PHYIF_16_BIT 1 288 #define UTMI_PHYIF_8_BIT 0 289 290 /* Global USB2 PHY Vendor Control Register */ 291 #define DWC3_GUSB2PHYACC_NEWREGREQ BIT(25) 292 #define DWC3_GUSB2PHYACC_DONE BIT(24) 293 #define DWC3_GUSB2PHYACC_BUSY BIT(23) 294 #define DWC3_GUSB2PHYACC_WRITE BIT(22) 295 #define DWC3_GUSB2PHYACC_ADDR(n) (n << 16) 296 #define DWC3_GUSB2PHYACC_EXTEND_ADDR(n) (n << 8) 297 #define DWC3_GUSB2PHYACC_DATA(n) (n & 0xff) 298 299 /* Global USB3 PIPE Control Register */ 300 #define DWC3_GUSB3PIPECTL_PHYSOFTRST BIT(31) 301 #define DWC3_GUSB3PIPECTL_U2SSINP3OK BIT(29) 302 #define DWC3_GUSB3PIPECTL_DISRXDETINP3 BIT(28) 303 #define DWC3_GUSB3PIPECTL_UX_EXIT_PX BIT(27) 304 #define DWC3_GUSB3PIPECTL_REQP1P2P3 BIT(24) 305 #define DWC3_GUSB3PIPECTL_DEP1P2P3(n) ((n) << 19) 306 #define DWC3_GUSB3PIPECTL_DEP1P2P3_MASK DWC3_GUSB3PIPECTL_DEP1P2P3(7) 307 #define DWC3_GUSB3PIPECTL_DEP1P2P3_EN DWC3_GUSB3PIPECTL_DEP1P2P3(1) 308 #define DWC3_GUSB3PIPECTL_DEPOCHANGE BIT(18) 309 #define DWC3_GUSB3PIPECTL_SUSPHY BIT(17) 310 #define DWC3_GUSB3PIPECTL_LFPSFILT BIT(9) 311 #define DWC3_GUSB3PIPECTL_RX_DETOPOLL BIT(8) 312 #define DWC3_GUSB3PIPECTL_TX_DEEPH_MASK DWC3_GUSB3PIPECTL_TX_DEEPH(3) 313 #define DWC3_GUSB3PIPECTL_TX_DEEPH(n) ((n) << 1) 314 315 /* Global TX Fifo Size Register */ 316 #define DWC31_GTXFIFOSIZ_TXFRAMNUM BIT(15) /* DWC_usb31 only */ 317 #define DWC31_GTXFIFOSIZ_TXFDEP(n) ((n) & 0x7fff) /* DWC_usb31 only */ 318 #define DWC3_GTXFIFOSIZ_TXFDEP(n) ((n) & 0xffff) 319 #define DWC3_GTXFIFOSIZ_TXFSTADDR(n) ((n) & 0xffff0000) 320 321 /* Global RX Fifo Size Register */ 322 #define DWC31_GRXFIFOSIZ_RXFDEP(n) ((n) & 0x7fff) /* DWC_usb31 only */ 323 #define DWC3_GRXFIFOSIZ_RXFDEP(n) ((n) & 0xffff) 324 325 /* Global Event Size Registers */ 326 #define DWC3_GEVNTSIZ_INTMASK BIT(31) 327 #define DWC3_GEVNTSIZ_SIZE(n) ((n) & 0xffff) 328 329 /* Global HWPARAMS0 Register */ 330 #define DWC3_GHWPARAMS0_MODE(n) ((n) & 0x3) 331 #define DWC3_GHWPARAMS0_MODE_GADGET 0 332 #define DWC3_GHWPARAMS0_MODE_HOST 1 333 #define DWC3_GHWPARAMS0_MODE_DRD 2 334 #define DWC3_GHWPARAMS0_MBUS_TYPE(n) (((n) >> 3) & 0x7) 335 #define DWC3_GHWPARAMS0_SBUS_TYPE(n) (((n) >> 6) & 0x3) 336 #define DWC3_GHWPARAMS0_MDWIDTH(n) (((n) >> 8) & 0xff) 337 #define DWC3_GHWPARAMS0_SDWIDTH(n) (((n) >> 16) & 0xff) 338 #define DWC3_GHWPARAMS0_AWIDTH(n) (((n) >> 24) & 0xff) 339 340 /* Global HWPARAMS1 Register */ 341 #define DWC3_GHWPARAMS1_EN_PWROPT(n) (((n) & (3 << 24)) >> 24) 342 #define DWC3_GHWPARAMS1_EN_PWROPT_NO 0 343 #define DWC3_GHWPARAMS1_EN_PWROPT_CLK 1 344 #define DWC3_GHWPARAMS1_EN_PWROPT_HIB 2 345 #define DWC3_GHWPARAMS1_PWROPT(n) ((n) << 24) 346 #define DWC3_GHWPARAMS1_PWROPT_MASK DWC3_GHWPARAMS1_PWROPT(3) 347 #define DWC3_GHWPARAMS1_ENDBC BIT(31) 348 349 /* Global HWPARAMS3 Register */ 350 #define DWC3_GHWPARAMS3_SSPHY_IFC(n) ((n) & 3) 351 #define DWC3_GHWPARAMS3_SSPHY_IFC_DIS 0 352 #define DWC3_GHWPARAMS3_SSPHY_IFC_GEN1 1 353 #define DWC3_GHWPARAMS3_SSPHY_IFC_GEN2 2 /* DWC_usb31 only */ 354 #define DWC3_GHWPARAMS3_HSPHY_IFC(n) (((n) & (3 << 2)) >> 2) 355 #define DWC3_GHWPARAMS3_HSPHY_IFC_DIS 0 356 #define DWC3_GHWPARAMS3_HSPHY_IFC_UTMI 1 357 #define DWC3_GHWPARAMS3_HSPHY_IFC_ULPI 2 358 #define DWC3_GHWPARAMS3_HSPHY_IFC_UTMI_ULPI 3 359 #define DWC3_GHWPARAMS3_FSPHY_IFC(n) (((n) & (3 << 4)) >> 4) 360 #define DWC3_GHWPARAMS3_FSPHY_IFC_DIS 0 361 #define DWC3_GHWPARAMS3_FSPHY_IFC_ENA 1 362 363 /* Global HWPARAMS4 Register */ 364 #define DWC3_GHWPARAMS4_HIBER_SCRATCHBUFS(n) (((n) & (0x0f << 13)) >> 13) 365 #define DWC3_MAX_HIBER_SCRATCHBUFS 15 366 367 /* Global HWPARAMS6 Register */ 368 #define DWC3_GHWPARAMS6_BCSUPPORT BIT(14) 369 #define DWC3_GHWPARAMS6_OTG3SUPPORT BIT(13) 370 #define DWC3_GHWPARAMS6_ADPSUPPORT BIT(12) 371 #define DWC3_GHWPARAMS6_HNPSUPPORT BIT(11) 372 #define DWC3_GHWPARAMS6_SRPSUPPORT BIT(10) 373 #define DWC3_GHWPARAMS6_EN_FPGA BIT(7) 374 375 /* DWC_usb32 only */ 376 #define DWC3_GHWPARAMS6_MDWIDTH(n) ((n) & (0x3 << 8)) 377 378 /* Global HWPARAMS7 Register */ 379 #define DWC3_GHWPARAMS7_RAM1_DEPTH(n) ((n) & 0xffff) 380 #define DWC3_GHWPARAMS7_RAM2_DEPTH(n) (((n) >> 16) & 0xffff) 381 382 /* Global HWPARAMS9 Register */ 383 #define DWC3_GHWPARAMS9_DEV_TXF_FLUSH_BYPASS BIT(0) 384 385 /* Global Frame Length Adjustment Register */ 386 #define DWC3_GFLADJ_30MHZ_SDBND_SEL BIT(7) 387 #define DWC3_GFLADJ_30MHZ_MASK 0x3f 388 389 /* Global User Control Register 2 */ 390 #define DWC3_GUCTL2_RST_ACTBITLATER BIT(14) 391 392 /* Global User Control Register 3 */ 393 #define DWC3_GUCTL3_SPLITDISABLE BIT(14) 394 395 /* Device Configuration Register */ 396 #define DWC3_DCFG_NUMLANES(n) (((n) & 0x3) << 30) /* DWC_usb32 only */ 397 398 #define DWC3_DCFG_DEVADDR(addr) ((addr) << 3) 399 #define DWC3_DCFG_DEVADDR_MASK DWC3_DCFG_DEVADDR(0x7f) 400 401 #define DWC3_DCFG_SPEED_MASK (7 << 0) 402 #define DWC3_DCFG_SUPERSPEED_PLUS (5 << 0) /* DWC_usb31 only */ 403 #define DWC3_DCFG_SUPERSPEED (4 << 0) 404 #define DWC3_DCFG_HIGHSPEED (0 << 0) 405 #define DWC3_DCFG_FULLSPEED BIT(0) 406 407 #define DWC3_DCFG_NUMP_SHIFT 17 408 #define DWC3_DCFG_NUMP(n) (((n) >> DWC3_DCFG_NUMP_SHIFT) & 0x1f) 409 #define DWC3_DCFG_NUMP_MASK (0x1f << DWC3_DCFG_NUMP_SHIFT) 410 #define DWC3_DCFG_LPM_CAP BIT(22) 411 #define DWC3_DCFG_IGNSTRMPP BIT(23) 412 413 /* Device Control Register */ 414 #define DWC3_DCTL_RUN_STOP BIT(31) 415 #define DWC3_DCTL_CSFTRST BIT(30) 416 #define DWC3_DCTL_LSFTRST BIT(29) 417 418 #define DWC3_DCTL_HIRD_THRES_MASK (0x1f << 24) 419 #define DWC3_DCTL_HIRD_THRES(n) ((n) << 24) 420 421 #define DWC3_DCTL_APPL1RES BIT(23) 422 423 /* These apply for core versions 1.87a and earlier */ 424 #define DWC3_DCTL_TRGTULST_MASK (0x0f << 17) 425 #define DWC3_DCTL_TRGTULST(n) ((n) << 17) 426 #define DWC3_DCTL_TRGTULST_U2 (DWC3_DCTL_TRGTULST(2)) 427 #define DWC3_DCTL_TRGTULST_U3 (DWC3_DCTL_TRGTULST(3)) 428 #define DWC3_DCTL_TRGTULST_SS_DIS (DWC3_DCTL_TRGTULST(4)) 429 #define DWC3_DCTL_TRGTULST_RX_DET (DWC3_DCTL_TRGTULST(5)) 430 #define DWC3_DCTL_TRGTULST_SS_INACT (DWC3_DCTL_TRGTULST(6)) 431 432 /* These apply for core versions 1.94a and later */ 433 #define DWC3_DCTL_NYET_THRES(n) (((n) & 0xf) << 20) 434 435 #define DWC3_DCTL_KEEP_CONNECT BIT(19) 436 #define DWC3_DCTL_L1_HIBER_EN BIT(18) 437 #define DWC3_DCTL_CRS BIT(17) 438 #define DWC3_DCTL_CSS BIT(16) 439 440 #define DWC3_DCTL_INITU2ENA BIT(12) 441 #define DWC3_DCTL_ACCEPTU2ENA BIT(11) 442 #define DWC3_DCTL_INITU1ENA BIT(10) 443 #define DWC3_DCTL_ACCEPTU1ENA BIT(9) 444 #define DWC3_DCTL_TSTCTRL_MASK (0xf << 1) 445 446 #define DWC3_DCTL_ULSTCHNGREQ_MASK (0x0f << 5) 447 #define DWC3_DCTL_ULSTCHNGREQ(n) (((n) << 5) & DWC3_DCTL_ULSTCHNGREQ_MASK) 448 449 #define DWC3_DCTL_ULSTCHNG_NO_ACTION (DWC3_DCTL_ULSTCHNGREQ(0)) 450 #define DWC3_DCTL_ULSTCHNG_SS_DISABLED (DWC3_DCTL_ULSTCHNGREQ(4)) 451 #define DWC3_DCTL_ULSTCHNG_RX_DETECT (DWC3_DCTL_ULSTCHNGREQ(5)) 452 #define DWC3_DCTL_ULSTCHNG_SS_INACTIVE (DWC3_DCTL_ULSTCHNGREQ(6)) 453 #define DWC3_DCTL_ULSTCHNG_RECOVERY (DWC3_DCTL_ULSTCHNGREQ(8)) 454 #define DWC3_DCTL_ULSTCHNG_COMPLIANCE (DWC3_DCTL_ULSTCHNGREQ(10)) 455 #define DWC3_DCTL_ULSTCHNG_LOOPBACK (DWC3_DCTL_ULSTCHNGREQ(11)) 456 457 /* Device Event Enable Register */ 458 #define DWC3_DEVTEN_VNDRDEVTSTRCVEDEN BIT(12) 459 #define DWC3_DEVTEN_EVNTOVERFLOWEN BIT(11) 460 #define DWC3_DEVTEN_CMDCMPLTEN BIT(10) 461 #define DWC3_DEVTEN_ERRTICERREN BIT(9) 462 #define DWC3_DEVTEN_SOFEN BIT(7) 463 #define DWC3_DEVTEN_U3L2L1SUSPEN BIT(6) 464 #define DWC3_DEVTEN_HIBERNATIONREQEVTEN BIT(5) 465 #define DWC3_DEVTEN_WKUPEVTEN BIT(4) 466 #define DWC3_DEVTEN_ULSTCNGEN BIT(3) 467 #define DWC3_DEVTEN_CONNECTDONEEN BIT(2) 468 #define DWC3_DEVTEN_USBRSTEN BIT(1) 469 #define DWC3_DEVTEN_DISCONNEVTEN BIT(0) 470 471 #define DWC3_DSTS_CONNLANES(n) (((n) >> 30) & 0x3) /* DWC_usb32 only */ 472 473 /* Device Status Register */ 474 #define DWC3_DSTS_DCNRD BIT(29) 475 476 /* This applies for core versions 1.87a and earlier */ 477 #define DWC3_DSTS_PWRUPREQ BIT(24) 478 479 /* These apply for core versions 1.94a and later */ 480 #define DWC3_DSTS_RSS BIT(25) 481 #define DWC3_DSTS_SSS BIT(24) 482 483 #define DWC3_DSTS_COREIDLE BIT(23) 484 #define DWC3_DSTS_DEVCTRLHLT BIT(22) 485 486 #define DWC3_DSTS_USBLNKST_MASK (0x0f << 18) 487 #define DWC3_DSTS_USBLNKST(n) (((n) & DWC3_DSTS_USBLNKST_MASK) >> 18) 488 489 #define DWC3_DSTS_RXFIFOEMPTY BIT(17) 490 491 #define DWC3_DSTS_SOFFN_MASK (0x3fff << 3) 492 #define DWC3_DSTS_SOFFN(n) (((n) & DWC3_DSTS_SOFFN_MASK) >> 3) 493 494 #define DWC3_DSTS_CONNECTSPD (7 << 0) 495 496 #define DWC3_DSTS_SUPERSPEED_PLUS (5 << 0) /* DWC_usb31 only */ 497 #define DWC3_DSTS_SUPERSPEED (4 << 0) 498 #define DWC3_DSTS_HIGHSPEED (0 << 0) 499 #define DWC3_DSTS_FULLSPEED BIT(0) 500 501 /* Device Generic Command Register */ 502 #define DWC3_DGCMD_SET_LMP 0x01 503 #define DWC3_DGCMD_SET_PERIODIC_PAR 0x02 504 #define DWC3_DGCMD_XMIT_FUNCTION 0x03 505 506 /* These apply for core versions 1.94a and later */ 507 #define DWC3_DGCMD_SET_SCRATCHPAD_ADDR_LO 0x04 508 #define DWC3_DGCMD_SET_SCRATCHPAD_ADDR_HI 0x05 509 510 #define DWC3_DGCMD_SELECTED_FIFO_FLUSH 0x09 511 #define DWC3_DGCMD_ALL_FIFO_FLUSH 0x0a 512 #define DWC3_DGCMD_SET_ENDPOINT_NRDY 0x0c 513 #define DWC3_DGCMD_SET_ENDPOINT_PRIME 0x0d 514 #define DWC3_DGCMD_RUN_SOC_BUS_LOOPBACK 0x10 515 516 #define DWC3_DGCMD_STATUS(n) (((n) >> 12) & 0x0F) 517 #define DWC3_DGCMD_CMDACT BIT(10) 518 #define DWC3_DGCMD_CMDIOC BIT(8) 519 520 /* Device Generic Command Parameter Register */ 521 #define DWC3_DGCMDPAR_FORCE_LINKPM_ACCEPT BIT(0) 522 #define DWC3_DGCMDPAR_FIFO_NUM(n) ((n) << 0) 523 #define DWC3_DGCMDPAR_RX_FIFO (0 << 5) 524 #define DWC3_DGCMDPAR_TX_FIFO BIT(5) 525 #define DWC3_DGCMDPAR_LOOPBACK_DIS (0 << 0) 526 #define DWC3_DGCMDPAR_LOOPBACK_ENA BIT(0) 527 528 /* Device Endpoint Command Register */ 529 #define DWC3_DEPCMD_PARAM_SHIFT 16 530 #define DWC3_DEPCMD_PARAM(x) ((x) << DWC3_DEPCMD_PARAM_SHIFT) 531 #define DWC3_DEPCMD_GET_RSC_IDX(x) (((x) >> DWC3_DEPCMD_PARAM_SHIFT) & 0x7f) 532 #define DWC3_DEPCMD_STATUS(x) (((x) >> 12) & 0x0F) 533 #define DWC3_DEPCMD_HIPRI_FORCERM BIT(11) 534 #define DWC3_DEPCMD_CLEARPENDIN BIT(11) 535 #define DWC3_DEPCMD_CMDACT BIT(10) 536 #define DWC3_DEPCMD_CMDIOC BIT(8) 537 538 #define DWC3_DEPCMD_DEPSTARTCFG (0x09 << 0) 539 #define DWC3_DEPCMD_ENDTRANSFER (0x08 << 0) 540 #define DWC3_DEPCMD_UPDATETRANSFER (0x07 << 0) 541 #define DWC3_DEPCMD_STARTTRANSFER (0x06 << 0) 542 #define DWC3_DEPCMD_CLEARSTALL (0x05 << 0) 543 #define DWC3_DEPCMD_SETSTALL (0x04 << 0) 544 /* This applies for core versions 1.90a and earlier */ 545 #define DWC3_DEPCMD_GETSEQNUMBER (0x03 << 0) 546 /* This applies for core versions 1.94a and later */ 547 #define DWC3_DEPCMD_GETEPSTATE (0x03 << 0) 548 #define DWC3_DEPCMD_SETTRANSFRESOURCE (0x02 << 0) 549 #define DWC3_DEPCMD_SETEPCONFIG (0x01 << 0) 550 551 #define DWC3_DEPCMD_CMD(x) ((x) & 0xf) 552 553 /* The EP number goes 0..31 so ep0 is always out and ep1 is always in */ 554 #define DWC3_DALEPENA_EP(n) BIT(n) 555 556 #define DWC3_DEPCMD_TYPE_CONTROL 0 557 #define DWC3_DEPCMD_TYPE_ISOC 1 558 #define DWC3_DEPCMD_TYPE_BULK 2 559 #define DWC3_DEPCMD_TYPE_INTR 3 560 561 #define DWC3_DEV_IMOD_COUNT_SHIFT 16 562 #define DWC3_DEV_IMOD_COUNT_MASK (0xffff << 16) 563 #define DWC3_DEV_IMOD_INTERVAL_SHIFT 0 564 #define DWC3_DEV_IMOD_INTERVAL_MASK (0xffff << 0) 565 566 /* OTG Configuration Register */ 567 #define DWC3_OCFG_DISPWRCUTTOFF BIT(5) 568 #define DWC3_OCFG_HIBDISMASK BIT(4) 569 #define DWC3_OCFG_SFTRSTMASK BIT(3) 570 #define DWC3_OCFG_OTGVERSION BIT(2) 571 #define DWC3_OCFG_HNPCAP BIT(1) 572 #define DWC3_OCFG_SRPCAP BIT(0) 573 574 /* OTG CTL Register */ 575 #define DWC3_OCTL_OTG3GOERR BIT(7) 576 #define DWC3_OCTL_PERIMODE BIT(6) 577 #define DWC3_OCTL_PRTPWRCTL BIT(5) 578 #define DWC3_OCTL_HNPREQ BIT(4) 579 #define DWC3_OCTL_SESREQ BIT(3) 580 #define DWC3_OCTL_TERMSELIDPULSE BIT(2) 581 #define DWC3_OCTL_DEVSETHNPEN BIT(1) 582 #define DWC3_OCTL_HSTSETHNPEN BIT(0) 583 584 /* OTG Event Register */ 585 #define DWC3_OEVT_DEVICEMODE BIT(31) 586 #define DWC3_OEVT_XHCIRUNSTPSET BIT(27) 587 #define DWC3_OEVT_DEVRUNSTPSET BIT(26) 588 #define DWC3_OEVT_HIBENTRY BIT(25) 589 #define DWC3_OEVT_CONIDSTSCHNG BIT(24) 590 #define DWC3_OEVT_HRRCONFNOTIF BIT(23) 591 #define DWC3_OEVT_HRRINITNOTIF BIT(22) 592 #define DWC3_OEVT_ADEVIDLE BIT(21) 593 #define DWC3_OEVT_ADEVBHOSTEND BIT(20) 594 #define DWC3_OEVT_ADEVHOST BIT(19) 595 #define DWC3_OEVT_ADEVHNPCHNG BIT(18) 596 #define DWC3_OEVT_ADEVSRPDET BIT(17) 597 #define DWC3_OEVT_ADEVSESSENDDET BIT(16) 598 #define DWC3_OEVT_BDEVBHOSTEND BIT(11) 599 #define DWC3_OEVT_BDEVHNPCHNG BIT(10) 600 #define DWC3_OEVT_BDEVSESSVLDDET BIT(9) 601 #define DWC3_OEVT_BDEVVBUSCHNG BIT(8) 602 #define DWC3_OEVT_BSESSVLD BIT(3) 603 #define DWC3_OEVT_HSTNEGSTS BIT(2) 604 #define DWC3_OEVT_SESREQSTS BIT(1) 605 #define DWC3_OEVT_ERROR BIT(0) 606 607 /* OTG Event Enable Register */ 608 #define DWC3_OEVTEN_XHCIRUNSTPSETEN BIT(27) 609 #define DWC3_OEVTEN_DEVRUNSTPSETEN BIT(26) 610 #define DWC3_OEVTEN_HIBENTRYEN BIT(25) 611 #define DWC3_OEVTEN_CONIDSTSCHNGEN BIT(24) 612 #define DWC3_OEVTEN_HRRCONFNOTIFEN BIT(23) 613 #define DWC3_OEVTEN_HRRINITNOTIFEN BIT(22) 614 #define DWC3_OEVTEN_ADEVIDLEEN BIT(21) 615 #define DWC3_OEVTEN_ADEVBHOSTENDEN BIT(20) 616 #define DWC3_OEVTEN_ADEVHOSTEN BIT(19) 617 #define DWC3_OEVTEN_ADEVHNPCHNGEN BIT(18) 618 #define DWC3_OEVTEN_ADEVSRPDETEN BIT(17) 619 #define DWC3_OEVTEN_ADEVSESSENDDETEN BIT(16) 620 #define DWC3_OEVTEN_BDEVBHOSTENDEN BIT(11) 621 #define DWC3_OEVTEN_BDEVHNPCHNGEN BIT(10) 622 #define DWC3_OEVTEN_BDEVSESSVLDDETEN BIT(9) 623 #define DWC3_OEVTEN_BDEVVBUSCHNGEN BIT(8) 624 625 /* OTG Status Register */ 626 #define DWC3_OSTS_DEVRUNSTP BIT(13) 627 #define DWC3_OSTS_XHCIRUNSTP BIT(12) 628 #define DWC3_OSTS_PERIPHERALSTATE BIT(4) 629 #define DWC3_OSTS_XHCIPRTPOWER BIT(3) 630 #define DWC3_OSTS_BSESVLD BIT(2) 631 #define DWC3_OSTS_VBUSVLD BIT(1) 632 #define DWC3_OSTS_CONIDSTS BIT(0) 633 634 /* Structures */ 635 636 struct dwc3_trb; 637 638 /** 639 * struct dwc3_event_buffer - Software event buffer representation 640 * @buf: _THE_ buffer 641 * @cache: The buffer cache used in the threaded interrupt 642 * @length: size of this buffer 643 * @lpos: event offset 644 * @count: cache of last read event count register 645 * @flags: flags related to this event buffer 646 * @dma: dma_addr_t 647 * @dwc: pointer to DWC controller 648 */ 649 struct dwc3_event_buffer { 650 void *buf; 651 void *cache; 652 unsigned int length; 653 unsigned int lpos; 654 unsigned int count; 655 unsigned int flags; 656 657 #define DWC3_EVENT_PENDING BIT(0) 658 659 dma_addr_t dma; 660 661 struct dwc3 *dwc; 662 }; 663 664 #define DWC3_EP_FLAG_STALLED BIT(0) 665 #define DWC3_EP_FLAG_WEDGED BIT(1) 666 667 #define DWC3_EP_DIRECTION_TX true 668 #define DWC3_EP_DIRECTION_RX false 669 670 #define DWC3_TRB_NUM 256 671 672 /** 673 * struct dwc3_ep - device side endpoint representation 674 * @endpoint: usb endpoint 675 * @cancelled_list: list of cancelled requests for this endpoint 676 * @pending_list: list of pending requests for this endpoint 677 * @started_list: list of started requests on this endpoint 678 * @regs: pointer to first endpoint register 679 * @trb_pool: array of transaction buffers 680 * @trb_pool_dma: dma address of @trb_pool 681 * @trb_enqueue: enqueue 'pointer' into TRB array 682 * @trb_dequeue: dequeue 'pointer' into TRB array 683 * @dwc: pointer to DWC controller 684 * @saved_state: ep state saved during hibernation 685 * @flags: endpoint flags (wedged, stalled, ...) 686 * @number: endpoint number (1 - 15) 687 * @type: set to bmAttributes & USB_ENDPOINT_XFERTYPE_MASK 688 * @resource_index: Resource transfer index 689 * @frame_number: set to the frame number we want this transfer to start (ISOC) 690 * @interval: the interval on which the ISOC transfer is started 691 * @name: a human readable name e.g. ep1out-bulk 692 * @direction: true for TX, false for RX 693 * @stream_capable: true when streams are enabled 694 * @combo_num: the test combination BIT[15:14] of the frame number to test 695 * isochronous START TRANSFER command failure workaround 696 * @start_cmd_status: the status of testing START TRANSFER command with 697 * combo_num = 'b00 698 */ 699 struct dwc3_ep { 700 struct usb_ep endpoint; 701 struct list_head cancelled_list; 702 struct list_head pending_list; 703 struct list_head started_list; 704 705 void __iomem *regs; 706 707 struct dwc3_trb *trb_pool; 708 dma_addr_t trb_pool_dma; 709 struct dwc3 *dwc; 710 711 u32 saved_state; 712 unsigned int flags; 713 #define DWC3_EP_ENABLED BIT(0) 714 #define DWC3_EP_STALL BIT(1) 715 #define DWC3_EP_WEDGE BIT(2) 716 #define DWC3_EP_TRANSFER_STARTED BIT(3) 717 #define DWC3_EP_END_TRANSFER_PENDING BIT(4) 718 #define DWC3_EP_PENDING_REQUEST BIT(5) 719 #define DWC3_EP_DELAY_START BIT(6) 720 #define DWC3_EP_WAIT_TRANSFER_COMPLETE BIT(7) 721 #define DWC3_EP_IGNORE_NEXT_NOSTREAM BIT(8) 722 #define DWC3_EP_FORCE_RESTART_STREAM BIT(9) 723 #define DWC3_EP_FIRST_STREAM_PRIMED BIT(10) 724 #define DWC3_EP_PENDING_CLEAR_STALL BIT(11) 725 726 /* This last one is specific to EP0 */ 727 #define DWC3_EP0_DIR_IN BIT(31) 728 729 /* 730 * IMPORTANT: we *know* we have 256 TRBs in our @trb_pool, so we will 731 * use a u8 type here. If anybody decides to increase number of TRBs to 732 * anything larger than 256 - I can't see why people would want to do 733 * this though - then this type needs to be changed. 734 * 735 * By using u8 types we ensure that our % operator when incrementing 736 * enqueue and dequeue get optimized away by the compiler. 737 */ 738 u8 trb_enqueue; 739 u8 trb_dequeue; 740 741 u8 number; 742 u8 type; 743 u8 resource_index; 744 u32 frame_number; 745 u32 interval; 746 747 char name[20]; 748 749 unsigned direction:1; 750 unsigned stream_capable:1; 751 752 /* For isochronous START TRANSFER workaround only */ 753 u8 combo_num; 754 int start_cmd_status; 755 }; 756 757 enum dwc3_phy { 758 DWC3_PHY_UNKNOWN = 0, 759 DWC3_PHY_USB3, 760 DWC3_PHY_USB2, 761 }; 762 763 enum dwc3_ep0_next { 764 DWC3_EP0_UNKNOWN = 0, 765 DWC3_EP0_COMPLETE, 766 DWC3_EP0_NRDY_DATA, 767 DWC3_EP0_NRDY_STATUS, 768 }; 769 770 enum dwc3_ep0_state { 771 EP0_UNCONNECTED = 0, 772 EP0_SETUP_PHASE, 773 EP0_DATA_PHASE, 774 EP0_STATUS_PHASE, 775 }; 776 777 enum dwc3_link_state { 778 /* In SuperSpeed */ 779 DWC3_LINK_STATE_U0 = 0x00, /* in HS, means ON */ 780 DWC3_LINK_STATE_U1 = 0x01, 781 DWC3_LINK_STATE_U2 = 0x02, /* in HS, means SLEEP */ 782 DWC3_LINK_STATE_U3 = 0x03, /* in HS, means SUSPEND */ 783 DWC3_LINK_STATE_SS_DIS = 0x04, 784 DWC3_LINK_STATE_RX_DET = 0x05, /* in HS, means Early Suspend */ 785 DWC3_LINK_STATE_SS_INACT = 0x06, 786 DWC3_LINK_STATE_POLL = 0x07, 787 DWC3_LINK_STATE_RECOV = 0x08, 788 DWC3_LINK_STATE_HRESET = 0x09, 789 DWC3_LINK_STATE_CMPLY = 0x0a, 790 DWC3_LINK_STATE_LPBK = 0x0b, 791 DWC3_LINK_STATE_RESET = 0x0e, 792 DWC3_LINK_STATE_RESUME = 0x0f, 793 DWC3_LINK_STATE_MASK = 0x0f, 794 }; 795 796 /* TRB Length, PCM and Status */ 797 #define DWC3_TRB_SIZE_MASK (0x00ffffff) 798 #define DWC3_TRB_SIZE_LENGTH(n) ((n) & DWC3_TRB_SIZE_MASK) 799 #define DWC3_TRB_SIZE_PCM1(n) (((n) & 0x03) << 24) 800 #define DWC3_TRB_SIZE_TRBSTS(n) (((n) & (0x0f << 28)) >> 28) 801 802 #define DWC3_TRBSTS_OK 0 803 #define DWC3_TRBSTS_MISSED_ISOC 1 804 #define DWC3_TRBSTS_SETUP_PENDING 2 805 #define DWC3_TRB_STS_XFER_IN_PROG 4 806 807 /* TRB Control */ 808 #define DWC3_TRB_CTRL_HWO BIT(0) 809 #define DWC3_TRB_CTRL_LST BIT(1) 810 #define DWC3_TRB_CTRL_CHN BIT(2) 811 #define DWC3_TRB_CTRL_CSP BIT(3) 812 #define DWC3_TRB_CTRL_TRBCTL(n) (((n) & 0x3f) << 4) 813 #define DWC3_TRB_CTRL_ISP_IMI BIT(10) 814 #define DWC3_TRB_CTRL_IOC BIT(11) 815 #define DWC3_TRB_CTRL_SID_SOFN(n) (((n) & 0xffff) << 14) 816 #define DWC3_TRB_CTRL_GET_SID_SOFN(n) (((n) & (0xffff << 14)) >> 14) 817 818 #define DWC3_TRBCTL_TYPE(n) ((n) & (0x3f << 4)) 819 #define DWC3_TRBCTL_NORMAL DWC3_TRB_CTRL_TRBCTL(1) 820 #define DWC3_TRBCTL_CONTROL_SETUP DWC3_TRB_CTRL_TRBCTL(2) 821 #define DWC3_TRBCTL_CONTROL_STATUS2 DWC3_TRB_CTRL_TRBCTL(3) 822 #define DWC3_TRBCTL_CONTROL_STATUS3 DWC3_TRB_CTRL_TRBCTL(4) 823 #define DWC3_TRBCTL_CONTROL_DATA DWC3_TRB_CTRL_TRBCTL(5) 824 #define DWC3_TRBCTL_ISOCHRONOUS_FIRST DWC3_TRB_CTRL_TRBCTL(6) 825 #define DWC3_TRBCTL_ISOCHRONOUS DWC3_TRB_CTRL_TRBCTL(7) 826 #define DWC3_TRBCTL_LINK_TRB DWC3_TRB_CTRL_TRBCTL(8) 827 828 /** 829 * struct dwc3_trb - transfer request block (hw format) 830 * @bpl: DW0-3 831 * @bph: DW4-7 832 * @size: DW8-B 833 * @ctrl: DWC-F 834 */ 835 struct dwc3_trb { 836 u32 bpl; 837 u32 bph; 838 u32 size; 839 u32 ctrl; 840 } __packed; 841 842 /** 843 * struct dwc3_hwparams - copy of HWPARAMS registers 844 * @hwparams0: GHWPARAMS0 845 * @hwparams1: GHWPARAMS1 846 * @hwparams2: GHWPARAMS2 847 * @hwparams3: GHWPARAMS3 848 * @hwparams4: GHWPARAMS4 849 * @hwparams5: GHWPARAMS5 850 * @hwparams6: GHWPARAMS6 851 * @hwparams7: GHWPARAMS7 852 * @hwparams8: GHWPARAMS8 853 * @hwparams9: GHWPARAMS9 854 */ 855 struct dwc3_hwparams { 856 u32 hwparams0; 857 u32 hwparams1; 858 u32 hwparams2; 859 u32 hwparams3; 860 u32 hwparams4; 861 u32 hwparams5; 862 u32 hwparams6; 863 u32 hwparams7; 864 u32 hwparams8; 865 u32 hwparams9; 866 }; 867 868 /* HWPARAMS0 */ 869 #define DWC3_MODE(n) ((n) & 0x7) 870 871 /* HWPARAMS1 */ 872 #define DWC3_NUM_INT(n) (((n) & (0x3f << 15)) >> 15) 873 874 /* HWPARAMS3 */ 875 #define DWC3_NUM_IN_EPS_MASK (0x1f << 18) 876 #define DWC3_NUM_EPS_MASK (0x3f << 12) 877 #define DWC3_NUM_EPS(p) (((p)->hwparams3 & \ 878 (DWC3_NUM_EPS_MASK)) >> 12) 879 #define DWC3_NUM_IN_EPS(p) (((p)->hwparams3 & \ 880 (DWC3_NUM_IN_EPS_MASK)) >> 18) 881 882 /* HWPARAMS7 */ 883 #define DWC3_RAM1_DEPTH(n) ((n) & 0xffff) 884 885 /** 886 * struct dwc3_request - representation of a transfer request 887 * @request: struct usb_request to be transferred 888 * @list: a list_head used for request queueing 889 * @dep: struct dwc3_ep owning this request 890 * @sg: pointer to first incomplete sg 891 * @start_sg: pointer to the sg which should be queued next 892 * @num_pending_sgs: counter to pending sgs 893 * @num_queued_sgs: counter to the number of sgs which already got queued 894 * @remaining: amount of data remaining 895 * @status: internal dwc3 request status tracking 896 * @epnum: endpoint number to which this request refers 897 * @trb: pointer to struct dwc3_trb 898 * @trb_dma: DMA address of @trb 899 * @num_trbs: number of TRBs used by this request 900 * @needs_extra_trb: true when request needs one extra TRB (either due to ZLP 901 * or unaligned OUT) 902 * @direction: IN or OUT direction flag 903 * @mapped: true when request has been dma-mapped 904 */ 905 struct dwc3_request { 906 struct usb_request request; 907 struct list_head list; 908 struct dwc3_ep *dep; 909 struct scatterlist *sg; 910 struct scatterlist *start_sg; 911 912 unsigned int num_pending_sgs; 913 unsigned int num_queued_sgs; 914 unsigned int remaining; 915 916 unsigned int status; 917 #define DWC3_REQUEST_STATUS_QUEUED 0 918 #define DWC3_REQUEST_STATUS_STARTED 1 919 #define DWC3_REQUEST_STATUS_DISCONNECTED 2 920 #define DWC3_REQUEST_STATUS_DEQUEUED 3 921 #define DWC3_REQUEST_STATUS_STALLED 4 922 #define DWC3_REQUEST_STATUS_COMPLETED 5 923 #define DWC3_REQUEST_STATUS_UNKNOWN -1 924 925 u8 epnum; 926 struct dwc3_trb *trb; 927 dma_addr_t trb_dma; 928 929 unsigned int num_trbs; 930 931 unsigned int needs_extra_trb:1; 932 unsigned int direction:1; 933 unsigned int mapped:1; 934 }; 935 936 /* 937 * struct dwc3_scratchpad_array - hibernation scratchpad array 938 * (format defined by hw) 939 */ 940 struct dwc3_scratchpad_array { 941 __le64 dma_adr[DWC3_MAX_HIBER_SCRATCHBUFS]; 942 }; 943 944 /** 945 * struct dwc3 - representation of our controller 946 * @drd_work: workqueue used for role swapping 947 * @ep0_trb: trb which is used for the ctrl_req 948 * @bounce: address of bounce buffer 949 * @scratchbuf: address of scratch buffer 950 * @setup_buf: used while precessing STD USB requests 951 * @ep0_trb_addr: dma address of @ep0_trb 952 * @bounce_addr: dma address of @bounce 953 * @ep0_usb_req: dummy req used while handling STD USB requests 954 * @scratch_addr: dma address of scratchbuf 955 * @ep0_in_setup: one control transfer is completed and enter setup phase 956 * @lock: for synchronizing 957 * @mutex: for mode switching 958 * @dev: pointer to our struct device 959 * @sysdev: pointer to the DMA-capable device 960 * @xhci: pointer to our xHCI child 961 * @xhci_resources: struct resources for our @xhci child 962 * @ev_buf: struct dwc3_event_buffer pointer 963 * @eps: endpoint array 964 * @gadget: device side representation of the peripheral controller 965 * @gadget_driver: pointer to the gadget driver 966 * @clks: array of clocks 967 * @num_clks: number of clocks 968 * @reset: reset control 969 * @regs: base address for our registers 970 * @regs_size: address space size 971 * @fladj: frame length adjustment 972 * @irq_gadget: peripheral controller's IRQ number 973 * @otg_irq: IRQ number for OTG IRQs 974 * @current_otg_role: current role of operation while using the OTG block 975 * @desired_otg_role: desired role of operation while using the OTG block 976 * @otg_restart_host: flag that OTG controller needs to restart host 977 * @nr_scratch: number of scratch buffers 978 * @u1u2: only used on revisions <1.83a for workaround 979 * @maximum_speed: maximum speed requested (mainly for testing purposes) 980 * @max_ssp_rate: SuperSpeed Plus maximum signaling rate and lane count 981 * @gadget_max_speed: maximum gadget speed requested 982 * @gadget_ssp_rate: Gadget driver's maximum supported SuperSpeed Plus signaling 983 * rate and lane count. 984 * @ip: controller's ID 985 * @revision: controller's version of an IP 986 * @version_type: VERSIONTYPE register contents, a sub release of a revision 987 * @dr_mode: requested mode of operation 988 * @current_dr_role: current role of operation when in dual-role mode 989 * @desired_dr_role: desired role of operation when in dual-role mode 990 * @edev: extcon handle 991 * @edev_nb: extcon notifier 992 * @hsphy_mode: UTMI phy mode, one of following: 993 * - USBPHY_INTERFACE_MODE_UTMI 994 * - USBPHY_INTERFACE_MODE_UTMIW 995 * @role_sw: usb_role_switch handle 996 * @role_switch_default_mode: default operation mode of controller while 997 * usb role is USB_ROLE_NONE. 998 * @usb_psy: pointer to power supply interface. 999 * @usb2_phy: pointer to USB2 PHY 1000 * @usb3_phy: pointer to USB3 PHY 1001 * @usb2_generic_phy: pointer to USB2 PHY 1002 * @usb3_generic_phy: pointer to USB3 PHY 1003 * @phys_ready: flag to indicate that PHYs are ready 1004 * @ulpi: pointer to ulpi interface 1005 * @ulpi_ready: flag to indicate that ULPI is initialized 1006 * @u2sel: parameter from Set SEL request. 1007 * @u2pel: parameter from Set SEL request. 1008 * @u1sel: parameter from Set SEL request. 1009 * @u1pel: parameter from Set SEL request. 1010 * @num_eps: number of endpoints 1011 * @ep0_next_event: hold the next expected event 1012 * @ep0state: state of endpoint zero 1013 * @link_state: link state 1014 * @speed: device speed (super, high, full, low) 1015 * @hwparams: copy of hwparams registers 1016 * @root: debugfs root folder pointer 1017 * @regset: debugfs pointer to regdump file 1018 * @dbg_lsp_select: current debug lsp mux register selection 1019 * @test_mode: true when we're entering a USB test mode 1020 * @test_mode_nr: test feature selector 1021 * @lpm_nyet_threshold: LPM NYET response threshold 1022 * @hird_threshold: HIRD threshold 1023 * @rx_thr_num_pkt_prd: periodic ESS receive packet count 1024 * @rx_max_burst_prd: max periodic ESS receive burst size 1025 * @tx_thr_num_pkt_prd: periodic ESS transmit packet count 1026 * @tx_max_burst_prd: max periodic ESS transmit burst size 1027 * @hsphy_interface: "utmi" or "ulpi" 1028 * @connected: true when we're connected to a host, false otherwise 1029 * @delayed_status: true when gadget driver asks for delayed status 1030 * @ep0_bounced: true when we used bounce buffer 1031 * @ep0_expect_in: true when we expect a DATA IN transfer 1032 * @has_hibernation: true when dwc3 was configured with Hibernation 1033 * @sysdev_is_parent: true when dwc3 device has a parent driver 1034 * @has_lpm_erratum: true when core was configured with LPM Erratum. Note that 1035 * there's now way for software to detect this in runtime. 1036 * @is_utmi_l1_suspend: the core asserts output signal 1037 * 0 - utmi_sleep_n 1038 * 1 - utmi_l1_suspend_n 1039 * @is_fpga: true when we are using the FPGA board 1040 * @pending_events: true when we have pending IRQs to be handled 1041 * @pullups_connected: true when Run/Stop bit is set 1042 * @setup_packet_pending: true when there's a Setup Packet in FIFO. Workaround 1043 * @three_stage_setup: set if we perform a three phase setup 1044 * @dis_start_transfer_quirk: set if start_transfer failure SW workaround is 1045 * not needed for DWC_usb31 version 1.70a-ea06 and below 1046 * @usb3_lpm_capable: set if hadrware supports Link Power Management 1047 * @usb2_lpm_disable: set to disable usb2 lpm for host 1048 * @usb2_gadget_lpm_disable: set to disable usb2 lpm for gadget 1049 * @disable_scramble_quirk: set if we enable the disable scramble quirk 1050 * @u2exit_lfps_quirk: set if we enable u2exit lfps quirk 1051 * @u2ss_inp3_quirk: set if we enable P3 OK for U2/SS Inactive quirk 1052 * @req_p1p2p3_quirk: set if we enable request p1p2p3 quirk 1053 * @del_p1p2p3_quirk: set if we enable delay p1p2p3 quirk 1054 * @del_phy_power_chg_quirk: set if we enable delay phy power change quirk 1055 * @lfps_filter_quirk: set if we enable LFPS filter quirk 1056 * @rx_detect_poll_quirk: set if we enable rx_detect to polling lfps quirk 1057 * @dis_u3_susphy_quirk: set if we disable usb3 suspend phy 1058 * @dis_u2_susphy_quirk: set if we disable usb2 suspend phy 1059 * @dis_enblslpm_quirk: set if we clear enblslpm in GUSB2PHYCFG, 1060 * disabling the suspend signal to the PHY. 1061 * @dis_u1_entry_quirk: set if link entering into U1 state needs to be disabled. 1062 * @dis_u2_entry_quirk: set if link entering into U2 state needs to be disabled. 1063 * @dis_rxdet_inp3_quirk: set if we disable Rx.Detect in P3 1064 * @dis_u2_freeclk_exists_quirk : set if we clear u2_freeclk_exists 1065 * in GUSB2PHYCFG, specify that USB2 PHY doesn't 1066 * provide a free-running PHY clock. 1067 * @dis_del_phy_power_chg_quirk: set if we disable delay phy power 1068 * change quirk. 1069 * @dis_tx_ipgap_linecheck_quirk: set if we disable u2mac linestate 1070 * check during HS transmit. 1071 * @parkmode_disable_ss_quirk: set if we need to disable all SuperSpeed 1072 * instances in park mode. 1073 * @tx_de_emphasis_quirk: set if we enable Tx de-emphasis quirk 1074 * @tx_de_emphasis: Tx de-emphasis value 1075 * 0 - -6dB de-emphasis 1076 * 1 - -3.5dB de-emphasis 1077 * 2 - No de-emphasis 1078 * 3 - Reserved 1079 * @dis_metastability_quirk: set to disable metastability quirk. 1080 * @dis_split_quirk: set to disable split boundary. 1081 * @imod_interval: set the interrupt moderation interval in 250ns 1082 * increments or 0 to disable. 1083 */ 1084 struct dwc3 { 1085 struct work_struct drd_work; 1086 struct dwc3_trb *ep0_trb; 1087 void *bounce; 1088 void *scratchbuf; 1089 u8 *setup_buf; 1090 dma_addr_t ep0_trb_addr; 1091 dma_addr_t bounce_addr; 1092 dma_addr_t scratch_addr; 1093 struct dwc3_request ep0_usb_req; 1094 struct completion ep0_in_setup; 1095 1096 /* device lock */ 1097 spinlock_t lock; 1098 1099 /* mode switching lock */ 1100 struct mutex mutex; 1101 1102 struct device *dev; 1103 struct device *sysdev; 1104 1105 struct platform_device *xhci; 1106 struct resource xhci_resources[DWC3_XHCI_RESOURCES_NUM]; 1107 1108 struct dwc3_event_buffer *ev_buf; 1109 struct dwc3_ep *eps[DWC3_ENDPOINTS_NUM]; 1110 1111 struct usb_gadget *gadget; 1112 struct usb_gadget_driver *gadget_driver; 1113 1114 struct clk_bulk_data *clks; 1115 int num_clks; 1116 1117 struct reset_control *reset; 1118 1119 struct usb_phy *usb2_phy; 1120 struct usb_phy *usb3_phy; 1121 1122 struct phy *usb2_generic_phy; 1123 struct phy *usb3_generic_phy; 1124 1125 bool phys_ready; 1126 1127 struct ulpi *ulpi; 1128 bool ulpi_ready; 1129 1130 void __iomem *regs; 1131 size_t regs_size; 1132 1133 enum usb_dr_mode dr_mode; 1134 u32 current_dr_role; 1135 u32 desired_dr_role; 1136 struct extcon_dev *edev; 1137 struct notifier_block edev_nb; 1138 enum usb_phy_interface hsphy_mode; 1139 struct usb_role_switch *role_sw; 1140 enum usb_dr_mode role_switch_default_mode; 1141 1142 struct power_supply *usb_psy; 1143 1144 u32 fladj; 1145 u32 irq_gadget; 1146 u32 otg_irq; 1147 u32 current_otg_role; 1148 u32 desired_otg_role; 1149 bool otg_restart_host; 1150 u32 nr_scratch; 1151 u32 u1u2; 1152 u32 maximum_speed; 1153 u32 gadget_max_speed; 1154 enum usb_ssp_rate max_ssp_rate; 1155 enum usb_ssp_rate gadget_ssp_rate; 1156 1157 u32 ip; 1158 1159 #define DWC3_IP 0x5533 1160 #define DWC31_IP 0x3331 1161 #define DWC32_IP 0x3332 1162 1163 u32 revision; 1164 1165 #define DWC3_REVISION_ANY 0x0 1166 #define DWC3_REVISION_173A 0x5533173a 1167 #define DWC3_REVISION_175A 0x5533175a 1168 #define DWC3_REVISION_180A 0x5533180a 1169 #define DWC3_REVISION_183A 0x5533183a 1170 #define DWC3_REVISION_185A 0x5533185a 1171 #define DWC3_REVISION_187A 0x5533187a 1172 #define DWC3_REVISION_188A 0x5533188a 1173 #define DWC3_REVISION_190A 0x5533190a 1174 #define DWC3_REVISION_194A 0x5533194a 1175 #define DWC3_REVISION_200A 0x5533200a 1176 #define DWC3_REVISION_202A 0x5533202a 1177 #define DWC3_REVISION_210A 0x5533210a 1178 #define DWC3_REVISION_220A 0x5533220a 1179 #define DWC3_REVISION_230A 0x5533230a 1180 #define DWC3_REVISION_240A 0x5533240a 1181 #define DWC3_REVISION_250A 0x5533250a 1182 #define DWC3_REVISION_260A 0x5533260a 1183 #define DWC3_REVISION_270A 0x5533270a 1184 #define DWC3_REVISION_280A 0x5533280a 1185 #define DWC3_REVISION_290A 0x5533290a 1186 #define DWC3_REVISION_300A 0x5533300a 1187 #define DWC3_REVISION_310A 0x5533310a 1188 #define DWC3_REVISION_330A 0x5533330a 1189 1190 #define DWC31_REVISION_ANY 0x0 1191 #define DWC31_REVISION_110A 0x3131302a 1192 #define DWC31_REVISION_120A 0x3132302a 1193 #define DWC31_REVISION_160A 0x3136302a 1194 #define DWC31_REVISION_170A 0x3137302a 1195 #define DWC31_REVISION_180A 0x3138302a 1196 #define DWC31_REVISION_190A 0x3139302a 1197 1198 #define DWC32_REVISION_ANY 0x0 1199 #define DWC32_REVISION_100A 0x3130302a 1200 1201 u32 version_type; 1202 1203 #define DWC31_VERSIONTYPE_ANY 0x0 1204 #define DWC31_VERSIONTYPE_EA01 0x65613031 1205 #define DWC31_VERSIONTYPE_EA02 0x65613032 1206 #define DWC31_VERSIONTYPE_EA03 0x65613033 1207 #define DWC31_VERSIONTYPE_EA04 0x65613034 1208 #define DWC31_VERSIONTYPE_EA05 0x65613035 1209 #define DWC31_VERSIONTYPE_EA06 0x65613036 1210 1211 enum dwc3_ep0_next ep0_next_event; 1212 enum dwc3_ep0_state ep0state; 1213 enum dwc3_link_state link_state; 1214 1215 u16 u2sel; 1216 u16 u2pel; 1217 u8 u1sel; 1218 u8 u1pel; 1219 1220 u8 speed; 1221 1222 u8 num_eps; 1223 1224 struct dwc3_hwparams hwparams; 1225 struct dentry *root; 1226 struct debugfs_regset32 *regset; 1227 1228 u32 dbg_lsp_select; 1229 1230 u8 test_mode; 1231 u8 test_mode_nr; 1232 u8 lpm_nyet_threshold; 1233 u8 hird_threshold; 1234 u8 rx_thr_num_pkt_prd; 1235 u8 rx_max_burst_prd; 1236 u8 tx_thr_num_pkt_prd; 1237 u8 tx_max_burst_prd; 1238 1239 const char *hsphy_interface; 1240 1241 unsigned connected:1; 1242 unsigned delayed_status:1; 1243 unsigned ep0_bounced:1; 1244 unsigned ep0_expect_in:1; 1245 unsigned has_hibernation:1; 1246 unsigned sysdev_is_parent:1; 1247 unsigned has_lpm_erratum:1; 1248 unsigned is_utmi_l1_suspend:1; 1249 unsigned is_fpga:1; 1250 unsigned pending_events:1; 1251 unsigned pullups_connected:1; 1252 unsigned setup_packet_pending:1; 1253 unsigned three_stage_setup:1; 1254 unsigned dis_start_transfer_quirk:1; 1255 unsigned usb3_lpm_capable:1; 1256 unsigned usb2_lpm_disable:1; 1257 unsigned usb2_gadget_lpm_disable:1; 1258 1259 unsigned disable_scramble_quirk:1; 1260 unsigned u2exit_lfps_quirk:1; 1261 unsigned u2ss_inp3_quirk:1; 1262 unsigned req_p1p2p3_quirk:1; 1263 unsigned del_p1p2p3_quirk:1; 1264 unsigned del_phy_power_chg_quirk:1; 1265 unsigned lfps_filter_quirk:1; 1266 unsigned rx_detect_poll_quirk:1; 1267 unsigned dis_u3_susphy_quirk:1; 1268 unsigned dis_u2_susphy_quirk:1; 1269 unsigned dis_enblslpm_quirk:1; 1270 unsigned dis_u1_entry_quirk:1; 1271 unsigned dis_u2_entry_quirk:1; 1272 unsigned dis_rxdet_inp3_quirk:1; 1273 unsigned dis_u2_freeclk_exists_quirk:1; 1274 unsigned dis_del_phy_power_chg_quirk:1; 1275 unsigned dis_tx_ipgap_linecheck_quirk:1; 1276 unsigned parkmode_disable_ss_quirk:1; 1277 1278 unsigned tx_de_emphasis_quirk:1; 1279 unsigned tx_de_emphasis:2; 1280 1281 unsigned dis_metastability_quirk:1; 1282 1283 unsigned dis_split_quirk:1; 1284 1285 u16 imod_interval; 1286 }; 1287 1288 #define INCRX_BURST_MODE 0 1289 #define INCRX_UNDEF_LENGTH_BURST_MODE 1 1290 1291 #define work_to_dwc(w) (container_of((w), struct dwc3, drd_work)) 1292 1293 /* -------------------------------------------------------------------------- */ 1294 1295 struct dwc3_event_type { 1296 u32 is_devspec:1; 1297 u32 type:7; 1298 u32 reserved8_31:24; 1299 } __packed; 1300 1301 #define DWC3_DEPEVT_XFERCOMPLETE 0x01 1302 #define DWC3_DEPEVT_XFERINPROGRESS 0x02 1303 #define DWC3_DEPEVT_XFERNOTREADY 0x03 1304 #define DWC3_DEPEVT_RXTXFIFOEVT 0x04 1305 #define DWC3_DEPEVT_STREAMEVT 0x06 1306 #define DWC3_DEPEVT_EPCMDCMPLT 0x07 1307 1308 /** 1309 * struct dwc3_event_depevt - Device Endpoint Events 1310 * @one_bit: indicates this is an endpoint event (not used) 1311 * @endpoint_number: number of the endpoint 1312 * @endpoint_event: The event we have: 1313 * 0x00 - Reserved 1314 * 0x01 - XferComplete 1315 * 0x02 - XferInProgress 1316 * 0x03 - XferNotReady 1317 * 0x04 - RxTxFifoEvt (IN->Underrun, OUT->Overrun) 1318 * 0x05 - Reserved 1319 * 0x06 - StreamEvt 1320 * 0x07 - EPCmdCmplt 1321 * @reserved11_10: Reserved, don't use. 1322 * @status: Indicates the status of the event. Refer to databook for 1323 * more information. 1324 * @parameters: Parameters of the current event. Refer to databook for 1325 * more information. 1326 */ 1327 struct dwc3_event_depevt { 1328 u32 one_bit:1; 1329 u32 endpoint_number:5; 1330 u32 endpoint_event:4; 1331 u32 reserved11_10:2; 1332 u32 status:4; 1333 1334 /* Within XferNotReady */ 1335 #define DEPEVT_STATUS_TRANSFER_ACTIVE BIT(3) 1336 1337 /* Within XferComplete or XferInProgress */ 1338 #define DEPEVT_STATUS_BUSERR BIT(0) 1339 #define DEPEVT_STATUS_SHORT BIT(1) 1340 #define DEPEVT_STATUS_IOC BIT(2) 1341 #define DEPEVT_STATUS_LST BIT(3) /* XferComplete */ 1342 #define DEPEVT_STATUS_MISSED_ISOC BIT(3) /* XferInProgress */ 1343 1344 /* Stream event only */ 1345 #define DEPEVT_STREAMEVT_FOUND 1 1346 #define DEPEVT_STREAMEVT_NOTFOUND 2 1347 1348 /* Stream event parameter */ 1349 #define DEPEVT_STREAM_PRIME 0xfffe 1350 #define DEPEVT_STREAM_NOSTREAM 0x0 1351 1352 /* Control-only Status */ 1353 #define DEPEVT_STATUS_CONTROL_DATA 1 1354 #define DEPEVT_STATUS_CONTROL_STATUS 2 1355 #define DEPEVT_STATUS_CONTROL_PHASE(n) ((n) & 3) 1356 1357 /* In response to Start Transfer */ 1358 #define DEPEVT_TRANSFER_NO_RESOURCE 1 1359 #define DEPEVT_TRANSFER_BUS_EXPIRY 2 1360 1361 u32 parameters:16; 1362 1363 /* For Command Complete Events */ 1364 #define DEPEVT_PARAMETER_CMD(n) (((n) & (0xf << 8)) >> 8) 1365 } __packed; 1366 1367 /** 1368 * struct dwc3_event_devt - Device Events 1369 * @one_bit: indicates this is a non-endpoint event (not used) 1370 * @device_event: indicates it's a device event. Should read as 0x00 1371 * @type: indicates the type of device event. 1372 * 0 - DisconnEvt 1373 * 1 - USBRst 1374 * 2 - ConnectDone 1375 * 3 - ULStChng 1376 * 4 - WkUpEvt 1377 * 5 - Reserved 1378 * 6 - Suspend (EOPF on revisions 2.10a and prior) 1379 * 7 - SOF 1380 * 8 - Reserved 1381 * 9 - ErrticErr 1382 * 10 - CmdCmplt 1383 * 11 - EvntOverflow 1384 * 12 - VndrDevTstRcved 1385 * @reserved15_12: Reserved, not used 1386 * @event_info: Information about this event 1387 * @reserved31_25: Reserved, not used 1388 */ 1389 struct dwc3_event_devt { 1390 u32 one_bit:1; 1391 u32 device_event:7; 1392 u32 type:4; 1393 u32 reserved15_12:4; 1394 u32 event_info:9; 1395 u32 reserved31_25:7; 1396 } __packed; 1397 1398 /** 1399 * struct dwc3_event_gevt - Other Core Events 1400 * @one_bit: indicates this is a non-endpoint event (not used) 1401 * @device_event: indicates it's (0x03) Carkit or (0x04) I2C event. 1402 * @phy_port_number: self-explanatory 1403 * @reserved31_12: Reserved, not used. 1404 */ 1405 struct dwc3_event_gevt { 1406 u32 one_bit:1; 1407 u32 device_event:7; 1408 u32 phy_port_number:4; 1409 u32 reserved31_12:20; 1410 } __packed; 1411 1412 /** 1413 * union dwc3_event - representation of Event Buffer contents 1414 * @raw: raw 32-bit event 1415 * @type: the type of the event 1416 * @depevt: Device Endpoint Event 1417 * @devt: Device Event 1418 * @gevt: Global Event 1419 */ 1420 union dwc3_event { 1421 u32 raw; 1422 struct dwc3_event_type type; 1423 struct dwc3_event_depevt depevt; 1424 struct dwc3_event_devt devt; 1425 struct dwc3_event_gevt gevt; 1426 }; 1427 1428 /** 1429 * struct dwc3_gadget_ep_cmd_params - representation of endpoint command 1430 * parameters 1431 * @param2: third parameter 1432 * @param1: second parameter 1433 * @param0: first parameter 1434 */ 1435 struct dwc3_gadget_ep_cmd_params { 1436 u32 param2; 1437 u32 param1; 1438 u32 param0; 1439 }; 1440 1441 /* 1442 * DWC3 Features to be used as Driver Data 1443 */ 1444 1445 #define DWC3_HAS_PERIPHERAL BIT(0) 1446 #define DWC3_HAS_XHCI BIT(1) 1447 #define DWC3_HAS_OTG BIT(3) 1448 1449 /* prototypes */ 1450 void dwc3_set_prtcap(struct dwc3 *dwc, u32 mode); 1451 void dwc3_set_mode(struct dwc3 *dwc, u32 mode); 1452 u32 dwc3_core_fifo_space(struct dwc3_ep *dep, u8 type); 1453 1454 #define DWC3_IP_IS(_ip) \ 1455 (dwc->ip == _ip##_IP) 1456 1457 #define DWC3_VER_IS(_ip, _ver) \ 1458 (DWC3_IP_IS(_ip) && dwc->revision == _ip##_REVISION_##_ver) 1459 1460 #define DWC3_VER_IS_PRIOR(_ip, _ver) \ 1461 (DWC3_IP_IS(_ip) && dwc->revision < _ip##_REVISION_##_ver) 1462 1463 #define DWC3_VER_IS_WITHIN(_ip, _from, _to) \ 1464 (DWC3_IP_IS(_ip) && \ 1465 dwc->revision >= _ip##_REVISION_##_from && \ 1466 (!(_ip##_REVISION_##_to) || \ 1467 dwc->revision <= _ip##_REVISION_##_to)) 1468 1469 #define DWC3_VER_TYPE_IS_WITHIN(_ip, _ver, _from, _to) \ 1470 (DWC3_VER_IS(_ip, _ver) && \ 1471 dwc->version_type >= _ip##_VERSIONTYPE_##_from && \ 1472 (!(_ip##_VERSIONTYPE_##_to) || \ 1473 dwc->version_type <= _ip##_VERSIONTYPE_##_to)) 1474 1475 /** 1476 * dwc3_mdwidth - get MDWIDTH value in bits 1477 * @dwc: pointer to our context structure 1478 * 1479 * Return MDWIDTH configuration value in bits. 1480 */ 1481 static inline u32 dwc3_mdwidth(struct dwc3 *dwc) 1482 { 1483 u32 mdwidth; 1484 1485 mdwidth = DWC3_GHWPARAMS0_MDWIDTH(dwc->hwparams.hwparams0); 1486 if (DWC3_IP_IS(DWC32)) 1487 mdwidth += DWC3_GHWPARAMS6_MDWIDTH(dwc->hwparams.hwparams6); 1488 1489 return mdwidth; 1490 } 1491 1492 bool dwc3_has_imod(struct dwc3 *dwc); 1493 1494 int dwc3_event_buffers_setup(struct dwc3 *dwc); 1495 void dwc3_event_buffers_cleanup(struct dwc3 *dwc); 1496 1497 #if IS_ENABLED(CONFIG_USB_DWC3_HOST) || IS_ENABLED(CONFIG_USB_DWC3_DUAL_ROLE) 1498 int dwc3_host_init(struct dwc3 *dwc); 1499 void dwc3_host_exit(struct dwc3 *dwc); 1500 #else 1501 static inline int dwc3_host_init(struct dwc3 *dwc) 1502 { return 0; } 1503 static inline void dwc3_host_exit(struct dwc3 *dwc) 1504 { } 1505 #endif 1506 1507 #if IS_ENABLED(CONFIG_USB_DWC3_GADGET) || IS_ENABLED(CONFIG_USB_DWC3_DUAL_ROLE) 1508 int dwc3_gadget_init(struct dwc3 *dwc); 1509 void dwc3_gadget_exit(struct dwc3 *dwc); 1510 int dwc3_gadget_set_test_mode(struct dwc3 *dwc, int mode); 1511 int dwc3_gadget_get_link_state(struct dwc3 *dwc); 1512 int dwc3_gadget_set_link_state(struct dwc3 *dwc, enum dwc3_link_state state); 1513 int dwc3_send_gadget_ep_cmd(struct dwc3_ep *dep, unsigned int cmd, 1514 struct dwc3_gadget_ep_cmd_params *params); 1515 int dwc3_send_gadget_generic_command(struct dwc3 *dwc, unsigned int cmd, 1516 u32 param); 1517 #else 1518 static inline int dwc3_gadget_init(struct dwc3 *dwc) 1519 { return 0; } 1520 static inline void dwc3_gadget_exit(struct dwc3 *dwc) 1521 { } 1522 static inline int dwc3_gadget_set_test_mode(struct dwc3 *dwc, int mode) 1523 { return 0; } 1524 static inline int dwc3_gadget_get_link_state(struct dwc3 *dwc) 1525 { return 0; } 1526 static inline int dwc3_gadget_set_link_state(struct dwc3 *dwc, 1527 enum dwc3_link_state state) 1528 { return 0; } 1529 1530 static inline int dwc3_send_gadget_ep_cmd(struct dwc3_ep *dep, unsigned int cmd, 1531 struct dwc3_gadget_ep_cmd_params *params) 1532 { return 0; } 1533 static inline int dwc3_send_gadget_generic_command(struct dwc3 *dwc, 1534 int cmd, u32 param) 1535 { return 0; } 1536 #endif 1537 1538 #if IS_ENABLED(CONFIG_USB_DWC3_DUAL_ROLE) 1539 int dwc3_drd_init(struct dwc3 *dwc); 1540 void dwc3_drd_exit(struct dwc3 *dwc); 1541 void dwc3_otg_init(struct dwc3 *dwc); 1542 void dwc3_otg_exit(struct dwc3 *dwc); 1543 void dwc3_otg_update(struct dwc3 *dwc, bool ignore_idstatus); 1544 void dwc3_otg_host_init(struct dwc3 *dwc); 1545 #else 1546 static inline int dwc3_drd_init(struct dwc3 *dwc) 1547 { return 0; } 1548 static inline void dwc3_drd_exit(struct dwc3 *dwc) 1549 { } 1550 static inline void dwc3_otg_init(struct dwc3 *dwc) 1551 { } 1552 static inline void dwc3_otg_exit(struct dwc3 *dwc) 1553 { } 1554 static inline void dwc3_otg_update(struct dwc3 *dwc, bool ignore_idstatus) 1555 { } 1556 static inline void dwc3_otg_host_init(struct dwc3 *dwc) 1557 { } 1558 #endif 1559 1560 /* power management interface */ 1561 #if !IS_ENABLED(CONFIG_USB_DWC3_HOST) 1562 int dwc3_gadget_suspend(struct dwc3 *dwc); 1563 int dwc3_gadget_resume(struct dwc3 *dwc); 1564 void dwc3_gadget_process_pending_events(struct dwc3 *dwc); 1565 #else 1566 static inline int dwc3_gadget_suspend(struct dwc3 *dwc) 1567 { 1568 return 0; 1569 } 1570 1571 static inline int dwc3_gadget_resume(struct dwc3 *dwc) 1572 { 1573 return 0; 1574 } 1575 1576 static inline void dwc3_gadget_process_pending_events(struct dwc3 *dwc) 1577 { 1578 } 1579 #endif /* !IS_ENABLED(CONFIG_USB_DWC3_HOST) */ 1580 1581 #if IS_ENABLED(CONFIG_USB_DWC3_ULPI) 1582 int dwc3_ulpi_init(struct dwc3 *dwc); 1583 void dwc3_ulpi_exit(struct dwc3 *dwc); 1584 #else 1585 static inline int dwc3_ulpi_init(struct dwc3 *dwc) 1586 { return 0; } 1587 static inline void dwc3_ulpi_exit(struct dwc3 *dwc) 1588 { } 1589 #endif 1590 1591 #endif /* __DRIVERS_USB_DWC3_CORE_H */ 1592