xref: /openbmc/linux/drivers/usb/dwc3/core.h (revision ae3473231e77a3f1909d48cd144cebe5e1d049b3)
1 /**
2  * core.h - DesignWare USB3 DRD Core Header
3  *
4  * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
5  *
6  * Authors: Felipe Balbi <balbi@ti.com>,
7  *	    Sebastian Andrzej Siewior <bigeasy@linutronix.de>
8  *
9  * This program is free software: you can redistribute it and/or modify
10  * it under the terms of the GNU General Public License version 2  of
11  * the License as published by the Free Software Foundation.
12  *
13  * This program is distributed in the hope that it will be useful,
14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
16  * GNU General Public License for more details.
17  */
18 
19 #ifndef __DRIVERS_USB_DWC3_CORE_H
20 #define __DRIVERS_USB_DWC3_CORE_H
21 
22 #include <linux/device.h>
23 #include <linux/spinlock.h>
24 #include <linux/ioport.h>
25 #include <linux/list.h>
26 #include <linux/dma-mapping.h>
27 #include <linux/mm.h>
28 #include <linux/debugfs.h>
29 #include <linux/wait.h>
30 
31 #include <linux/usb/ch9.h>
32 #include <linux/usb/gadget.h>
33 #include <linux/usb/otg.h>
34 #include <linux/ulpi/interface.h>
35 
36 #include <linux/phy/phy.h>
37 
38 #define DWC3_MSG_MAX	500
39 
40 /* Global constants */
41 #define DWC3_PULL_UP_TIMEOUT	500	/* ms */
42 #define DWC3_ZLP_BUF_SIZE	1024	/* size of a superspeed bulk */
43 #define DWC3_EP0_BOUNCE_SIZE	512
44 #define DWC3_ENDPOINTS_NUM	32
45 #define DWC3_XHCI_RESOURCES_NUM	2
46 
47 #define DWC3_SCRATCHBUF_SIZE	4096	/* each buffer is assumed to be 4KiB */
48 #define DWC3_EVENT_SIZE		4	/* bytes */
49 #define DWC3_EVENT_MAX_NUM	64	/* 2 events/endpoint */
50 #define DWC3_EVENT_BUFFERS_SIZE	(DWC3_EVENT_SIZE * DWC3_EVENT_MAX_NUM)
51 #define DWC3_EVENT_TYPE_MASK	0xfe
52 
53 #define DWC3_EVENT_TYPE_DEV	0
54 #define DWC3_EVENT_TYPE_CARKIT	3
55 #define DWC3_EVENT_TYPE_I2C	4
56 
57 #define DWC3_DEVICE_EVENT_DISCONNECT		0
58 #define DWC3_DEVICE_EVENT_RESET			1
59 #define DWC3_DEVICE_EVENT_CONNECT_DONE		2
60 #define DWC3_DEVICE_EVENT_LINK_STATUS_CHANGE	3
61 #define DWC3_DEVICE_EVENT_WAKEUP		4
62 #define DWC3_DEVICE_EVENT_HIBER_REQ		5
63 #define DWC3_DEVICE_EVENT_EOPF			6
64 #define DWC3_DEVICE_EVENT_SOF			7
65 #define DWC3_DEVICE_EVENT_ERRATIC_ERROR		9
66 #define DWC3_DEVICE_EVENT_CMD_CMPL		10
67 #define DWC3_DEVICE_EVENT_OVERFLOW		11
68 
69 #define DWC3_GEVNTCOUNT_MASK	0xfffc
70 #define DWC3_GEVNTCOUNT_EHB	(1 << 31)
71 #define DWC3_GSNPSID_MASK	0xffff0000
72 #define DWC3_GSNPSREV_MASK	0xffff
73 
74 /* DWC3 registers memory space boundries */
75 #define DWC3_XHCI_REGS_START		0x0
76 #define DWC3_XHCI_REGS_END		0x7fff
77 #define DWC3_GLOBALS_REGS_START		0xc100
78 #define DWC3_GLOBALS_REGS_END		0xc6ff
79 #define DWC3_DEVICE_REGS_START		0xc700
80 #define DWC3_DEVICE_REGS_END		0xcbff
81 #define DWC3_OTG_REGS_START		0xcc00
82 #define DWC3_OTG_REGS_END		0xccff
83 
84 /* Global Registers */
85 #define DWC3_GSBUSCFG0		0xc100
86 #define DWC3_GSBUSCFG1		0xc104
87 #define DWC3_GTXTHRCFG		0xc108
88 #define DWC3_GRXTHRCFG		0xc10c
89 #define DWC3_GCTL		0xc110
90 #define DWC3_GEVTEN		0xc114
91 #define DWC3_GSTS		0xc118
92 #define DWC3_GUCTL1		0xc11c
93 #define DWC3_GSNPSID		0xc120
94 #define DWC3_GGPIO		0xc124
95 #define DWC3_GUID		0xc128
96 #define DWC3_GUCTL		0xc12c
97 #define DWC3_GBUSERRADDR0	0xc130
98 #define DWC3_GBUSERRADDR1	0xc134
99 #define DWC3_GPRTBIMAP0		0xc138
100 #define DWC3_GPRTBIMAP1		0xc13c
101 #define DWC3_GHWPARAMS0		0xc140
102 #define DWC3_GHWPARAMS1		0xc144
103 #define DWC3_GHWPARAMS2		0xc148
104 #define DWC3_GHWPARAMS3		0xc14c
105 #define DWC3_GHWPARAMS4		0xc150
106 #define DWC3_GHWPARAMS5		0xc154
107 #define DWC3_GHWPARAMS6		0xc158
108 #define DWC3_GHWPARAMS7		0xc15c
109 #define DWC3_GDBGFIFOSPACE	0xc160
110 #define DWC3_GDBGLTSSM		0xc164
111 #define DWC3_GPRTBIMAP_HS0	0xc180
112 #define DWC3_GPRTBIMAP_HS1	0xc184
113 #define DWC3_GPRTBIMAP_FS0	0xc188
114 #define DWC3_GPRTBIMAP_FS1	0xc18c
115 #define DWC3_GUCTL2		0xc19c
116 
117 #define DWC3_VER_NUMBER		0xc1a0
118 #define DWC3_VER_TYPE		0xc1a4
119 
120 #define DWC3_GUSB2PHYCFG(n)	(0xc200 + (n * 0x04))
121 #define DWC3_GUSB2I2CCTL(n)	(0xc240 + (n * 0x04))
122 
123 #define DWC3_GUSB2PHYACC(n)	(0xc280 + (n * 0x04))
124 
125 #define DWC3_GUSB3PIPECTL(n)	(0xc2c0 + (n * 0x04))
126 
127 #define DWC3_GTXFIFOSIZ(n)	(0xc300 + (n * 0x04))
128 #define DWC3_GRXFIFOSIZ(n)	(0xc380 + (n * 0x04))
129 
130 #define DWC3_GEVNTADRLO(n)	(0xc400 + (n * 0x10))
131 #define DWC3_GEVNTADRHI(n)	(0xc404 + (n * 0x10))
132 #define DWC3_GEVNTSIZ(n)	(0xc408 + (n * 0x10))
133 #define DWC3_GEVNTCOUNT(n)	(0xc40c + (n * 0x10))
134 
135 #define DWC3_GHWPARAMS8		0xc600
136 #define DWC3_GFLADJ		0xc630
137 
138 /* Device Registers */
139 #define DWC3_DCFG		0xc700
140 #define DWC3_DCTL		0xc704
141 #define DWC3_DEVTEN		0xc708
142 #define DWC3_DSTS		0xc70c
143 #define DWC3_DGCMDPAR		0xc710
144 #define DWC3_DGCMD		0xc714
145 #define DWC3_DALEPENA		0xc720
146 
147 #define DWC3_DEP_BASE(n)	(0xc800 + (n * 0x10))
148 #define DWC3_DEPCMDPAR2		0x00
149 #define DWC3_DEPCMDPAR1		0x04
150 #define DWC3_DEPCMDPAR0		0x08
151 #define DWC3_DEPCMD		0x0c
152 
153 #define DWC3_DEV_IMOD(n)	(0xca00 + (n * 0x4))
154 
155 /* OTG Registers */
156 #define DWC3_OCFG		0xcc00
157 #define DWC3_OCTL		0xcc04
158 #define DWC3_OEVT		0xcc08
159 #define DWC3_OEVTEN		0xcc0C
160 #define DWC3_OSTS		0xcc10
161 
162 /* Bit fields */
163 
164 /* Global Debug Queue/FIFO Space Available Register */
165 #define DWC3_GDBGFIFOSPACE_NUM(n)	((n) & 0x1f)
166 #define DWC3_GDBGFIFOSPACE_TYPE(n)	(((n) << 5) & 0x1e0)
167 #define DWC3_GDBGFIFOSPACE_SPACE_AVAILABLE(n) (((n) >> 16) & 0xffff)
168 
169 #define DWC3_TXFIFOQ		1
170 #define DWC3_RXFIFOQ		3
171 #define DWC3_TXREQQ		5
172 #define DWC3_RXREQQ		7
173 #define DWC3_RXINFOQ		9
174 #define DWC3_DESCFETCHQ		13
175 #define DWC3_EVENTQ		15
176 
177 /* Global RX Threshold Configuration Register */
178 #define DWC3_GRXTHRCFG_MAXRXBURSTSIZE(n) (((n) & 0x1f) << 19)
179 #define DWC3_GRXTHRCFG_RXPKTCNT(n) (((n) & 0xf) << 24)
180 #define DWC3_GRXTHRCFG_PKTCNTSEL (1 << 29)
181 
182 /* Global Configuration Register */
183 #define DWC3_GCTL_PWRDNSCALE(n)	((n) << 19)
184 #define DWC3_GCTL_U2RSTECN	(1 << 16)
185 #define DWC3_GCTL_RAMCLKSEL(x)	(((x) & DWC3_GCTL_CLK_MASK) << 6)
186 #define DWC3_GCTL_CLK_BUS	(0)
187 #define DWC3_GCTL_CLK_PIPE	(1)
188 #define DWC3_GCTL_CLK_PIPEHALF	(2)
189 #define DWC3_GCTL_CLK_MASK	(3)
190 
191 #define DWC3_GCTL_PRTCAP(n)	(((n) & (3 << 12)) >> 12)
192 #define DWC3_GCTL_PRTCAPDIR(n)	((n) << 12)
193 #define DWC3_GCTL_PRTCAP_HOST	1
194 #define DWC3_GCTL_PRTCAP_DEVICE	2
195 #define DWC3_GCTL_PRTCAP_OTG	3
196 
197 #define DWC3_GCTL_CORESOFTRESET		(1 << 11)
198 #define DWC3_GCTL_SOFITPSYNC		(1 << 10)
199 #define DWC3_GCTL_SCALEDOWN(n)		((n) << 4)
200 #define DWC3_GCTL_SCALEDOWN_MASK	DWC3_GCTL_SCALEDOWN(3)
201 #define DWC3_GCTL_DISSCRAMBLE		(1 << 3)
202 #define DWC3_GCTL_U2EXIT_LFPS		(1 << 2)
203 #define DWC3_GCTL_GBLHIBERNATIONEN	(1 << 1)
204 #define DWC3_GCTL_DSBLCLKGTNG		(1 << 0)
205 
206 /* Global User Control 1 Register */
207 #define DWC3_GUCTL1_DEV_L1_EXIT_BY_HW	(1 << 24)
208 
209 /* Global USB2 PHY Configuration Register */
210 #define DWC3_GUSB2PHYCFG_PHYSOFTRST	(1 << 31)
211 #define DWC3_GUSB2PHYCFG_U2_FREECLK_EXISTS	(1 << 30)
212 #define DWC3_GUSB2PHYCFG_SUSPHY		(1 << 6)
213 #define DWC3_GUSB2PHYCFG_ULPI_UTMI	(1 << 4)
214 #define DWC3_GUSB2PHYCFG_ENBLSLPM	(1 << 8)
215 #define DWC3_GUSB2PHYCFG_PHYIF(n)	(n << 3)
216 #define DWC3_GUSB2PHYCFG_PHYIF_MASK	DWC3_GUSB2PHYCFG_PHYIF(1)
217 #define DWC3_GUSB2PHYCFG_USBTRDTIM(n)	(n << 10)
218 #define DWC3_GUSB2PHYCFG_USBTRDTIM_MASK	DWC3_GUSB2PHYCFG_USBTRDTIM(0xf)
219 #define USBTRDTIM_UTMI_8_BIT		9
220 #define USBTRDTIM_UTMI_16_BIT		5
221 #define UTMI_PHYIF_16_BIT		1
222 #define UTMI_PHYIF_8_BIT		0
223 
224 /* Global USB2 PHY Vendor Control Register */
225 #define DWC3_GUSB2PHYACC_NEWREGREQ	(1 << 25)
226 #define DWC3_GUSB2PHYACC_BUSY		(1 << 23)
227 #define DWC3_GUSB2PHYACC_WRITE		(1 << 22)
228 #define DWC3_GUSB2PHYACC_ADDR(n)	(n << 16)
229 #define DWC3_GUSB2PHYACC_EXTEND_ADDR(n)	(n << 8)
230 #define DWC3_GUSB2PHYACC_DATA(n)	(n & 0xff)
231 
232 /* Global USB3 PIPE Control Register */
233 #define DWC3_GUSB3PIPECTL_PHYSOFTRST	(1 << 31)
234 #define DWC3_GUSB3PIPECTL_U2SSINP3OK	(1 << 29)
235 #define DWC3_GUSB3PIPECTL_DISRXDETINP3	(1 << 28)
236 #define DWC3_GUSB3PIPECTL_REQP1P2P3	(1 << 24)
237 #define DWC3_GUSB3PIPECTL_DEP1P2P3(n)	((n) << 19)
238 #define DWC3_GUSB3PIPECTL_DEP1P2P3_MASK	DWC3_GUSB3PIPECTL_DEP1P2P3(7)
239 #define DWC3_GUSB3PIPECTL_DEP1P2P3_EN	DWC3_GUSB3PIPECTL_DEP1P2P3(1)
240 #define DWC3_GUSB3PIPECTL_DEPOCHANGE	(1 << 18)
241 #define DWC3_GUSB3PIPECTL_SUSPHY	(1 << 17)
242 #define DWC3_GUSB3PIPECTL_LFPSFILT	(1 << 9)
243 #define DWC3_GUSB3PIPECTL_RX_DETOPOLL	(1 << 8)
244 #define DWC3_GUSB3PIPECTL_TX_DEEPH_MASK	DWC3_GUSB3PIPECTL_TX_DEEPH(3)
245 #define DWC3_GUSB3PIPECTL_TX_DEEPH(n)	((n) << 1)
246 
247 /* Global TX Fifo Size Register */
248 #define DWC3_GTXFIFOSIZ_TXFDEF(n)	((n) & 0xffff)
249 #define DWC3_GTXFIFOSIZ_TXFSTADDR(n)	((n) & 0xffff0000)
250 
251 /* Global Event Size Registers */
252 #define DWC3_GEVNTSIZ_INTMASK		(1 << 31)
253 #define DWC3_GEVNTSIZ_SIZE(n)		((n) & 0xffff)
254 
255 /* Global HWPARAMS0 Register */
256 #define DWC3_GHWPARAMS0_MODE(n)		((n) & 0x3)
257 #define DWC3_GHWPARAMS0_MODE_GADGET	0
258 #define DWC3_GHWPARAMS0_MODE_HOST	1
259 #define DWC3_GHWPARAMS0_MODE_DRD	2
260 #define DWC3_GHWPARAMS0_MBUS_TYPE(n)	(((n) >> 3) & 0x7)
261 #define DWC3_GHWPARAMS0_SBUS_TYPE(n)	(((n) >> 6) & 0x3)
262 #define DWC3_GHWPARAMS0_MDWIDTH(n)	(((n) >> 8) & 0xff)
263 #define DWC3_GHWPARAMS0_SDWIDTH(n)	(((n) >> 16) & 0xff)
264 #define DWC3_GHWPARAMS0_AWIDTH(n)	(((n) >> 24) & 0xff)
265 
266 /* Global HWPARAMS1 Register */
267 #define DWC3_GHWPARAMS1_EN_PWROPT(n)	(((n) & (3 << 24)) >> 24)
268 #define DWC3_GHWPARAMS1_EN_PWROPT_NO	0
269 #define DWC3_GHWPARAMS1_EN_PWROPT_CLK	1
270 #define DWC3_GHWPARAMS1_EN_PWROPT_HIB	2
271 #define DWC3_GHWPARAMS1_PWROPT(n)	((n) << 24)
272 #define DWC3_GHWPARAMS1_PWROPT_MASK	DWC3_GHWPARAMS1_PWROPT(3)
273 
274 /* Global HWPARAMS3 Register */
275 #define DWC3_GHWPARAMS3_SSPHY_IFC(n)		((n) & 3)
276 #define DWC3_GHWPARAMS3_SSPHY_IFC_DIS		0
277 #define DWC3_GHWPARAMS3_SSPHY_IFC_GEN1		1
278 #define DWC3_GHWPARAMS3_SSPHY_IFC_GEN2		2 /* DWC_usb31 only */
279 #define DWC3_GHWPARAMS3_HSPHY_IFC(n)		(((n) & (3 << 2)) >> 2)
280 #define DWC3_GHWPARAMS3_HSPHY_IFC_DIS		0
281 #define DWC3_GHWPARAMS3_HSPHY_IFC_UTMI		1
282 #define DWC3_GHWPARAMS3_HSPHY_IFC_ULPI		2
283 #define DWC3_GHWPARAMS3_HSPHY_IFC_UTMI_ULPI	3
284 #define DWC3_GHWPARAMS3_FSPHY_IFC(n)		(((n) & (3 << 4)) >> 4)
285 #define DWC3_GHWPARAMS3_FSPHY_IFC_DIS		0
286 #define DWC3_GHWPARAMS3_FSPHY_IFC_ENA		1
287 
288 /* Global HWPARAMS4 Register */
289 #define DWC3_GHWPARAMS4_HIBER_SCRATCHBUFS(n)	(((n) & (0x0f << 13)) >> 13)
290 #define DWC3_MAX_HIBER_SCRATCHBUFS		15
291 
292 /* Global HWPARAMS6 Register */
293 #define DWC3_GHWPARAMS6_EN_FPGA			(1 << 7)
294 
295 /* Global HWPARAMS7 Register */
296 #define DWC3_GHWPARAMS7_RAM1_DEPTH(n)	((n) & 0xffff)
297 #define DWC3_GHWPARAMS7_RAM2_DEPTH(n)	(((n) >> 16) & 0xffff)
298 
299 /* Global Frame Length Adjustment Register */
300 #define DWC3_GFLADJ_30MHZ_SDBND_SEL		(1 << 7)
301 #define DWC3_GFLADJ_30MHZ_MASK			0x3f
302 
303 /* Global User Control Register 2 */
304 #define DWC3_GUCTL2_RST_ACTBITLATER		(1 << 14)
305 
306 /* Device Configuration Register */
307 #define DWC3_DCFG_DEVADDR(addr)	((addr) << 3)
308 #define DWC3_DCFG_DEVADDR_MASK	DWC3_DCFG_DEVADDR(0x7f)
309 
310 #define DWC3_DCFG_SPEED_MASK	(7 << 0)
311 #define DWC3_DCFG_SUPERSPEED_PLUS (5 << 0)  /* DWC_usb31 only */
312 #define DWC3_DCFG_SUPERSPEED	(4 << 0)
313 #define DWC3_DCFG_HIGHSPEED	(0 << 0)
314 #define DWC3_DCFG_FULLSPEED2	(1 << 0)
315 #define DWC3_DCFG_LOWSPEED	(2 << 0)
316 #define DWC3_DCFG_FULLSPEED1	(3 << 0)
317 
318 #define DWC3_DCFG_NUMP_SHIFT	17
319 #define DWC3_DCFG_NUMP(n)	(((n) >> DWC3_DCFG_NUMP_SHIFT) & 0x1f)
320 #define DWC3_DCFG_NUMP_MASK	(0x1f << DWC3_DCFG_NUMP_SHIFT)
321 #define DWC3_DCFG_LPM_CAP	(1 << 22)
322 
323 /* Device Control Register */
324 #define DWC3_DCTL_RUN_STOP	(1 << 31)
325 #define DWC3_DCTL_CSFTRST	(1 << 30)
326 #define DWC3_DCTL_LSFTRST	(1 << 29)
327 
328 #define DWC3_DCTL_HIRD_THRES_MASK	(0x1f << 24)
329 #define DWC3_DCTL_HIRD_THRES(n)	((n) << 24)
330 
331 #define DWC3_DCTL_APPL1RES	(1 << 23)
332 
333 /* These apply for core versions 1.87a and earlier */
334 #define DWC3_DCTL_TRGTULST_MASK		(0x0f << 17)
335 #define DWC3_DCTL_TRGTULST(n)		((n) << 17)
336 #define DWC3_DCTL_TRGTULST_U2		(DWC3_DCTL_TRGTULST(2))
337 #define DWC3_DCTL_TRGTULST_U3		(DWC3_DCTL_TRGTULST(3))
338 #define DWC3_DCTL_TRGTULST_SS_DIS	(DWC3_DCTL_TRGTULST(4))
339 #define DWC3_DCTL_TRGTULST_RX_DET	(DWC3_DCTL_TRGTULST(5))
340 #define DWC3_DCTL_TRGTULST_SS_INACT	(DWC3_DCTL_TRGTULST(6))
341 
342 /* These apply for core versions 1.94a and later */
343 #define DWC3_DCTL_LPM_ERRATA_MASK	DWC3_DCTL_LPM_ERRATA(0xf)
344 #define DWC3_DCTL_LPM_ERRATA(n)		((n) << 20)
345 
346 #define DWC3_DCTL_KEEP_CONNECT		(1 << 19)
347 #define DWC3_DCTL_L1_HIBER_EN		(1 << 18)
348 #define DWC3_DCTL_CRS			(1 << 17)
349 #define DWC3_DCTL_CSS			(1 << 16)
350 
351 #define DWC3_DCTL_INITU2ENA		(1 << 12)
352 #define DWC3_DCTL_ACCEPTU2ENA		(1 << 11)
353 #define DWC3_DCTL_INITU1ENA		(1 << 10)
354 #define DWC3_DCTL_ACCEPTU1ENA		(1 << 9)
355 #define DWC3_DCTL_TSTCTRL_MASK		(0xf << 1)
356 
357 #define DWC3_DCTL_ULSTCHNGREQ_MASK	(0x0f << 5)
358 #define DWC3_DCTL_ULSTCHNGREQ(n) (((n) << 5) & DWC3_DCTL_ULSTCHNGREQ_MASK)
359 
360 #define DWC3_DCTL_ULSTCHNG_NO_ACTION	(DWC3_DCTL_ULSTCHNGREQ(0))
361 #define DWC3_DCTL_ULSTCHNG_SS_DISABLED	(DWC3_DCTL_ULSTCHNGREQ(4))
362 #define DWC3_DCTL_ULSTCHNG_RX_DETECT	(DWC3_DCTL_ULSTCHNGREQ(5))
363 #define DWC3_DCTL_ULSTCHNG_SS_INACTIVE	(DWC3_DCTL_ULSTCHNGREQ(6))
364 #define DWC3_DCTL_ULSTCHNG_RECOVERY	(DWC3_DCTL_ULSTCHNGREQ(8))
365 #define DWC3_DCTL_ULSTCHNG_COMPLIANCE	(DWC3_DCTL_ULSTCHNGREQ(10))
366 #define DWC3_DCTL_ULSTCHNG_LOOPBACK	(DWC3_DCTL_ULSTCHNGREQ(11))
367 
368 /* Device Event Enable Register */
369 #define DWC3_DEVTEN_VNDRDEVTSTRCVEDEN	(1 << 12)
370 #define DWC3_DEVTEN_EVNTOVERFLOWEN	(1 << 11)
371 #define DWC3_DEVTEN_CMDCMPLTEN		(1 << 10)
372 #define DWC3_DEVTEN_ERRTICERREN		(1 << 9)
373 #define DWC3_DEVTEN_SOFEN		(1 << 7)
374 #define DWC3_DEVTEN_EOPFEN		(1 << 6)
375 #define DWC3_DEVTEN_HIBERNATIONREQEVTEN	(1 << 5)
376 #define DWC3_DEVTEN_WKUPEVTEN		(1 << 4)
377 #define DWC3_DEVTEN_ULSTCNGEN		(1 << 3)
378 #define DWC3_DEVTEN_CONNECTDONEEN	(1 << 2)
379 #define DWC3_DEVTEN_USBRSTEN		(1 << 1)
380 #define DWC3_DEVTEN_DISCONNEVTEN	(1 << 0)
381 
382 /* Device Status Register */
383 #define DWC3_DSTS_DCNRD			(1 << 29)
384 
385 /* This applies for core versions 1.87a and earlier */
386 #define DWC3_DSTS_PWRUPREQ		(1 << 24)
387 
388 /* These apply for core versions 1.94a and later */
389 #define DWC3_DSTS_RSS			(1 << 25)
390 #define DWC3_DSTS_SSS			(1 << 24)
391 
392 #define DWC3_DSTS_COREIDLE		(1 << 23)
393 #define DWC3_DSTS_DEVCTRLHLT		(1 << 22)
394 
395 #define DWC3_DSTS_USBLNKST_MASK		(0x0f << 18)
396 #define DWC3_DSTS_USBLNKST(n)		(((n) & DWC3_DSTS_USBLNKST_MASK) >> 18)
397 
398 #define DWC3_DSTS_RXFIFOEMPTY		(1 << 17)
399 
400 #define DWC3_DSTS_SOFFN_MASK		(0x3fff << 3)
401 #define DWC3_DSTS_SOFFN(n)		(((n) & DWC3_DSTS_SOFFN_MASK) >> 3)
402 
403 #define DWC3_DSTS_CONNECTSPD		(7 << 0)
404 
405 #define DWC3_DSTS_SUPERSPEED_PLUS	(5 << 0) /* DWC_usb31 only */
406 #define DWC3_DSTS_SUPERSPEED		(4 << 0)
407 #define DWC3_DSTS_HIGHSPEED		(0 << 0)
408 #define DWC3_DSTS_FULLSPEED2		(1 << 0)
409 #define DWC3_DSTS_LOWSPEED		(2 << 0)
410 #define DWC3_DSTS_FULLSPEED1		(3 << 0)
411 
412 /* Device Generic Command Register */
413 #define DWC3_DGCMD_SET_LMP		0x01
414 #define DWC3_DGCMD_SET_PERIODIC_PAR	0x02
415 #define DWC3_DGCMD_XMIT_FUNCTION	0x03
416 
417 /* These apply for core versions 1.94a and later */
418 #define DWC3_DGCMD_SET_SCRATCHPAD_ADDR_LO	0x04
419 #define DWC3_DGCMD_SET_SCRATCHPAD_ADDR_HI	0x05
420 
421 #define DWC3_DGCMD_SELECTED_FIFO_FLUSH	0x09
422 #define DWC3_DGCMD_ALL_FIFO_FLUSH	0x0a
423 #define DWC3_DGCMD_SET_ENDPOINT_NRDY	0x0c
424 #define DWC3_DGCMD_RUN_SOC_BUS_LOOPBACK	0x10
425 
426 #define DWC3_DGCMD_STATUS(n)		(((n) >> 12) & 0x0F)
427 #define DWC3_DGCMD_CMDACT		(1 << 10)
428 #define DWC3_DGCMD_CMDIOC		(1 << 8)
429 
430 /* Device Generic Command Parameter Register */
431 #define DWC3_DGCMDPAR_FORCE_LINKPM_ACCEPT	(1 << 0)
432 #define DWC3_DGCMDPAR_FIFO_NUM(n)		((n) << 0)
433 #define DWC3_DGCMDPAR_RX_FIFO			(0 << 5)
434 #define DWC3_DGCMDPAR_TX_FIFO			(1 << 5)
435 #define DWC3_DGCMDPAR_LOOPBACK_DIS		(0 << 0)
436 #define DWC3_DGCMDPAR_LOOPBACK_ENA		(1 << 0)
437 
438 /* Device Endpoint Command Register */
439 #define DWC3_DEPCMD_PARAM_SHIFT		16
440 #define DWC3_DEPCMD_PARAM(x)		((x) << DWC3_DEPCMD_PARAM_SHIFT)
441 #define DWC3_DEPCMD_GET_RSC_IDX(x)	(((x) >> DWC3_DEPCMD_PARAM_SHIFT) & 0x7f)
442 #define DWC3_DEPCMD_STATUS(x)		(((x) >> 12) & 0x0F)
443 #define DWC3_DEPCMD_HIPRI_FORCERM	(1 << 11)
444 #define DWC3_DEPCMD_CLEARPENDIN		(1 << 11)
445 #define DWC3_DEPCMD_CMDACT		(1 << 10)
446 #define DWC3_DEPCMD_CMDIOC		(1 << 8)
447 
448 #define DWC3_DEPCMD_DEPSTARTCFG		(0x09 << 0)
449 #define DWC3_DEPCMD_ENDTRANSFER		(0x08 << 0)
450 #define DWC3_DEPCMD_UPDATETRANSFER	(0x07 << 0)
451 #define DWC3_DEPCMD_STARTTRANSFER	(0x06 << 0)
452 #define DWC3_DEPCMD_CLEARSTALL		(0x05 << 0)
453 #define DWC3_DEPCMD_SETSTALL		(0x04 << 0)
454 /* This applies for core versions 1.90a and earlier */
455 #define DWC3_DEPCMD_GETSEQNUMBER	(0x03 << 0)
456 /* This applies for core versions 1.94a and later */
457 #define DWC3_DEPCMD_GETEPSTATE		(0x03 << 0)
458 #define DWC3_DEPCMD_SETTRANSFRESOURCE	(0x02 << 0)
459 #define DWC3_DEPCMD_SETEPCONFIG		(0x01 << 0)
460 
461 #define DWC3_DEPCMD_CMD(x)		((x) & 0xf)
462 
463 /* The EP number goes 0..31 so ep0 is always out and ep1 is always in */
464 #define DWC3_DALEPENA_EP(n)		(1 << n)
465 
466 #define DWC3_DEPCMD_TYPE_CONTROL	0
467 #define DWC3_DEPCMD_TYPE_ISOC		1
468 #define DWC3_DEPCMD_TYPE_BULK		2
469 #define DWC3_DEPCMD_TYPE_INTR		3
470 
471 #define DWC3_DEV_IMOD_COUNT_SHIFT	16
472 #define DWC3_DEV_IMOD_COUNT_MASK	(0xffff << 16)
473 #define DWC3_DEV_IMOD_INTERVAL_SHIFT	0
474 #define DWC3_DEV_IMOD_INTERVAL_MASK	(0xffff << 0)
475 
476 /* Structures */
477 
478 struct dwc3_trb;
479 
480 /**
481  * struct dwc3_event_buffer - Software event buffer representation
482  * @buf: _THE_ buffer
483  * @cache: The buffer cache used in the threaded interrupt
484  * @length: size of this buffer
485  * @lpos: event offset
486  * @count: cache of last read event count register
487  * @flags: flags related to this event buffer
488  * @dma: dma_addr_t
489  * @dwc: pointer to DWC controller
490  */
491 struct dwc3_event_buffer {
492 	void			*buf;
493 	void			*cache;
494 	unsigned		length;
495 	unsigned int		lpos;
496 	unsigned int		count;
497 	unsigned int		flags;
498 
499 #define DWC3_EVENT_PENDING	BIT(0)
500 
501 	dma_addr_t		dma;
502 
503 	struct dwc3		*dwc;
504 };
505 
506 #define DWC3_EP_FLAG_STALLED	(1 << 0)
507 #define DWC3_EP_FLAG_WEDGED	(1 << 1)
508 
509 #define DWC3_EP_DIRECTION_TX	true
510 #define DWC3_EP_DIRECTION_RX	false
511 
512 #define DWC3_TRB_NUM		256
513 
514 /**
515  * struct dwc3_ep - device side endpoint representation
516  * @endpoint: usb endpoint
517  * @pending_list: list of pending requests for this endpoint
518  * @started_list: list of started requests on this endpoint
519  * @wait_end_transfer: wait_queue_head_t for waiting on End Transfer complete
520  * @lock: spinlock for endpoint request queue traversal
521  * @regs: pointer to first endpoint register
522  * @trb_pool: array of transaction buffers
523  * @trb_pool_dma: dma address of @trb_pool
524  * @trb_enqueue: enqueue 'pointer' into TRB array
525  * @trb_dequeue: dequeue 'pointer' into TRB array
526  * @desc: usb_endpoint_descriptor pointer
527  * @dwc: pointer to DWC controller
528  * @saved_state: ep state saved during hibernation
529  * @flags: endpoint flags (wedged, stalled, ...)
530  * @number: endpoint number (1 - 15)
531  * @type: set to bmAttributes & USB_ENDPOINT_XFERTYPE_MASK
532  * @resource_index: Resource transfer index
533  * @interval: the interval on which the ISOC transfer is started
534  * @allocated_requests: number of requests allocated
535  * @queued_requests: number of requests queued for transfer
536  * @name: a human readable name e.g. ep1out-bulk
537  * @direction: true for TX, false for RX
538  * @stream_capable: true when streams are enabled
539  */
540 struct dwc3_ep {
541 	struct usb_ep		endpoint;
542 	struct list_head	pending_list;
543 	struct list_head	started_list;
544 
545 	wait_queue_head_t	wait_end_transfer;
546 
547 	spinlock_t		lock;
548 	void __iomem		*regs;
549 
550 	struct dwc3_trb		*trb_pool;
551 	dma_addr_t		trb_pool_dma;
552 	struct dwc3		*dwc;
553 
554 	u32			saved_state;
555 	unsigned		flags;
556 #define DWC3_EP_ENABLED		(1 << 0)
557 #define DWC3_EP_STALL		(1 << 1)
558 #define DWC3_EP_WEDGE		(1 << 2)
559 #define DWC3_EP_BUSY		(1 << 4)
560 #define DWC3_EP_PENDING_REQUEST	(1 << 5)
561 #define DWC3_EP_MISSED_ISOC	(1 << 6)
562 #define DWC3_EP_END_TRANSFER_PENDING	(1 << 7)
563 #define DWC3_EP_TRANSFER_STARTED (1 << 8)
564 
565 	/* This last one is specific to EP0 */
566 #define DWC3_EP0_DIR_IN		(1 << 31)
567 
568 	/*
569 	 * IMPORTANT: we *know* we have 256 TRBs in our @trb_pool, so we will
570 	 * use a u8 type here. If anybody decides to increase number of TRBs to
571 	 * anything larger than 256 - I can't see why people would want to do
572 	 * this though - then this type needs to be changed.
573 	 *
574 	 * By using u8 types we ensure that our % operator when incrementing
575 	 * enqueue and dequeue get optimized away by the compiler.
576 	 */
577 	u8			trb_enqueue;
578 	u8			trb_dequeue;
579 
580 	u8			number;
581 	u8			type;
582 	u8			resource_index;
583 	u32			allocated_requests;
584 	u32			queued_requests;
585 	u32			interval;
586 
587 	char			name[20];
588 
589 	unsigned		direction:1;
590 	unsigned		stream_capable:1;
591 };
592 
593 enum dwc3_phy {
594 	DWC3_PHY_UNKNOWN = 0,
595 	DWC3_PHY_USB3,
596 	DWC3_PHY_USB2,
597 };
598 
599 enum dwc3_ep0_next {
600 	DWC3_EP0_UNKNOWN = 0,
601 	DWC3_EP0_COMPLETE,
602 	DWC3_EP0_NRDY_DATA,
603 	DWC3_EP0_NRDY_STATUS,
604 };
605 
606 enum dwc3_ep0_state {
607 	EP0_UNCONNECTED		= 0,
608 	EP0_SETUP_PHASE,
609 	EP0_DATA_PHASE,
610 	EP0_STATUS_PHASE,
611 };
612 
613 enum dwc3_link_state {
614 	/* In SuperSpeed */
615 	DWC3_LINK_STATE_U0		= 0x00, /* in HS, means ON */
616 	DWC3_LINK_STATE_U1		= 0x01,
617 	DWC3_LINK_STATE_U2		= 0x02, /* in HS, means SLEEP */
618 	DWC3_LINK_STATE_U3		= 0x03, /* in HS, means SUSPEND */
619 	DWC3_LINK_STATE_SS_DIS		= 0x04,
620 	DWC3_LINK_STATE_RX_DET		= 0x05, /* in HS, means Early Suspend */
621 	DWC3_LINK_STATE_SS_INACT	= 0x06,
622 	DWC3_LINK_STATE_POLL		= 0x07,
623 	DWC3_LINK_STATE_RECOV		= 0x08,
624 	DWC3_LINK_STATE_HRESET		= 0x09,
625 	DWC3_LINK_STATE_CMPLY		= 0x0a,
626 	DWC3_LINK_STATE_LPBK		= 0x0b,
627 	DWC3_LINK_STATE_RESET		= 0x0e,
628 	DWC3_LINK_STATE_RESUME		= 0x0f,
629 	DWC3_LINK_STATE_MASK		= 0x0f,
630 };
631 
632 /* TRB Length, PCM and Status */
633 #define DWC3_TRB_SIZE_MASK	(0x00ffffff)
634 #define DWC3_TRB_SIZE_LENGTH(n)	((n) & DWC3_TRB_SIZE_MASK)
635 #define DWC3_TRB_SIZE_PCM1(n)	(((n) & 0x03) << 24)
636 #define DWC3_TRB_SIZE_TRBSTS(n)	(((n) & (0x0f << 28)) >> 28)
637 
638 #define DWC3_TRBSTS_OK			0
639 #define DWC3_TRBSTS_MISSED_ISOC		1
640 #define DWC3_TRBSTS_SETUP_PENDING	2
641 #define DWC3_TRB_STS_XFER_IN_PROG	4
642 
643 /* TRB Control */
644 #define DWC3_TRB_CTRL_HWO		(1 << 0)
645 #define DWC3_TRB_CTRL_LST		(1 << 1)
646 #define DWC3_TRB_CTRL_CHN		(1 << 2)
647 #define DWC3_TRB_CTRL_CSP		(1 << 3)
648 #define DWC3_TRB_CTRL_TRBCTL(n)		(((n) & 0x3f) << 4)
649 #define DWC3_TRB_CTRL_ISP_IMI		(1 << 10)
650 #define DWC3_TRB_CTRL_IOC		(1 << 11)
651 #define DWC3_TRB_CTRL_SID_SOFN(n)	(((n) & 0xffff) << 14)
652 
653 #define DWC3_TRBCTL_TYPE(n)		((n) & (0x3f << 4))
654 #define DWC3_TRBCTL_NORMAL		DWC3_TRB_CTRL_TRBCTL(1)
655 #define DWC3_TRBCTL_CONTROL_SETUP	DWC3_TRB_CTRL_TRBCTL(2)
656 #define DWC3_TRBCTL_CONTROL_STATUS2	DWC3_TRB_CTRL_TRBCTL(3)
657 #define DWC3_TRBCTL_CONTROL_STATUS3	DWC3_TRB_CTRL_TRBCTL(4)
658 #define DWC3_TRBCTL_CONTROL_DATA	DWC3_TRB_CTRL_TRBCTL(5)
659 #define DWC3_TRBCTL_ISOCHRONOUS_FIRST	DWC3_TRB_CTRL_TRBCTL(6)
660 #define DWC3_TRBCTL_ISOCHRONOUS		DWC3_TRB_CTRL_TRBCTL(7)
661 #define DWC3_TRBCTL_LINK_TRB		DWC3_TRB_CTRL_TRBCTL(8)
662 
663 /**
664  * struct dwc3_trb - transfer request block (hw format)
665  * @bpl: DW0-3
666  * @bph: DW4-7
667  * @size: DW8-B
668  * @trl: DWC-F
669  */
670 struct dwc3_trb {
671 	u32		bpl;
672 	u32		bph;
673 	u32		size;
674 	u32		ctrl;
675 } __packed;
676 
677 /**
678  * dwc3_hwparams - copy of HWPARAMS registers
679  * @hwparams0 - GHWPARAMS0
680  * @hwparams1 - GHWPARAMS1
681  * @hwparams2 - GHWPARAMS2
682  * @hwparams3 - GHWPARAMS3
683  * @hwparams4 - GHWPARAMS4
684  * @hwparams5 - GHWPARAMS5
685  * @hwparams6 - GHWPARAMS6
686  * @hwparams7 - GHWPARAMS7
687  * @hwparams8 - GHWPARAMS8
688  */
689 struct dwc3_hwparams {
690 	u32	hwparams0;
691 	u32	hwparams1;
692 	u32	hwparams2;
693 	u32	hwparams3;
694 	u32	hwparams4;
695 	u32	hwparams5;
696 	u32	hwparams6;
697 	u32	hwparams7;
698 	u32	hwparams8;
699 };
700 
701 /* HWPARAMS0 */
702 #define DWC3_MODE(n)		((n) & 0x7)
703 
704 #define DWC3_MDWIDTH(n)		(((n) & 0xff00) >> 8)
705 
706 /* HWPARAMS1 */
707 #define DWC3_NUM_INT(n)		(((n) & (0x3f << 15)) >> 15)
708 
709 /* HWPARAMS3 */
710 #define DWC3_NUM_IN_EPS_MASK	(0x1f << 18)
711 #define DWC3_NUM_EPS_MASK	(0x3f << 12)
712 #define DWC3_NUM_EPS(p)		(((p)->hwparams3 &		\
713 			(DWC3_NUM_EPS_MASK)) >> 12)
714 #define DWC3_NUM_IN_EPS(p)	(((p)->hwparams3 &		\
715 			(DWC3_NUM_IN_EPS_MASK)) >> 18)
716 
717 /* HWPARAMS7 */
718 #define DWC3_RAM1_DEPTH(n)	((n) & 0xffff)
719 
720 /**
721  * struct dwc3_request - representation of a transfer request
722  * @request: struct usb_request to be transferred
723  * @list: a list_head used for request queueing
724  * @dep: struct dwc3_ep owning this request
725  * @sg: pointer to first incomplete sg
726  * @num_pending_sgs: counter to pending sgs
727  * @remaining: amount of data remaining
728  * @epnum: endpoint number to which this request refers
729  * @trb: pointer to struct dwc3_trb
730  * @trb_dma: DMA address of @trb
731  * @direction: IN or OUT direction flag
732  * @mapped: true when request has been dma-mapped
733  * @queued: true when request has been queued to HW
734  */
735 struct dwc3_request {
736 	struct usb_request	request;
737 	struct list_head	list;
738 	struct dwc3_ep		*dep;
739 	struct scatterlist	*sg;
740 
741 	unsigned		num_pending_sgs;
742 	unsigned		remaining;
743 	u8			epnum;
744 	struct dwc3_trb		*trb;
745 	dma_addr_t		trb_dma;
746 
747 	unsigned		direction:1;
748 	unsigned		mapped:1;
749 	unsigned		started:1;
750 };
751 
752 /*
753  * struct dwc3_scratchpad_array - hibernation scratchpad array
754  * (format defined by hw)
755  */
756 struct dwc3_scratchpad_array {
757 	__le64	dma_adr[DWC3_MAX_HIBER_SCRATCHBUFS];
758 };
759 
760 /**
761  * struct dwc3 - representation of our controller
762  * @ctrl_req: usb control request which is used for ep0
763  * @ep0_trb: trb which is used for the ctrl_req
764  * @ep0_bounce: bounce buffer for ep0
765  * @zlp_buf: used when request->zero is set
766  * @setup_buf: used while precessing STD USB requests
767  * @ctrl_req_addr: dma address of ctrl_req
768  * @ep0_trb: dma address of ep0_trb
769  * @ep0_usb_req: dummy req used while handling STD USB requests
770  * @ep0_bounce_addr: dma address of ep0_bounce
771  * @scratch_addr: dma address of scratchbuf
772  * @ep0_in_setup: one control transfer is completed and enter setup phase
773  * @lock: for synchronizing
774  * @dev: pointer to our struct device
775  * @xhci: pointer to our xHCI child
776  * @event_buffer_list: a list of event buffers
777  * @gadget: device side representation of the peripheral controller
778  * @gadget_driver: pointer to the gadget driver
779  * @regs: base address for our registers
780  * @regs_size: address space size
781  * @fladj: frame length adjustment
782  * @irq_gadget: peripheral controller's IRQ number
783  * @nr_scratch: number of scratch buffers
784  * @u1u2: only used on revisions <1.83a for workaround
785  * @maximum_speed: maximum speed requested (mainly for testing purposes)
786  * @revision: revision register contents
787  * @dr_mode: requested mode of operation
788  * @hsphy_mode: UTMI phy mode, one of following:
789  *		- USBPHY_INTERFACE_MODE_UTMI
790  *		- USBPHY_INTERFACE_MODE_UTMIW
791  * @usb2_phy: pointer to USB2 PHY
792  * @usb3_phy: pointer to USB3 PHY
793  * @usb2_generic_phy: pointer to USB2 PHY
794  * @usb3_generic_phy: pointer to USB3 PHY
795  * @ulpi: pointer to ulpi interface
796  * @dcfg: saved contents of DCFG register
797  * @gctl: saved contents of GCTL register
798  * @isoch_delay: wValue from Set Isochronous Delay request;
799  * @u2sel: parameter from Set SEL request.
800  * @u2pel: parameter from Set SEL request.
801  * @u1sel: parameter from Set SEL request.
802  * @u1pel: parameter from Set SEL request.
803  * @num_out_eps: number of out endpoints
804  * @num_in_eps: number of in endpoints
805  * @ep0_next_event: hold the next expected event
806  * @ep0state: state of endpoint zero
807  * @link_state: link state
808  * @speed: device speed (super, high, full, low)
809  * @hwparams: copy of hwparams registers
810  * @root: debugfs root folder pointer
811  * @regset: debugfs pointer to regdump file
812  * @test_mode: true when we're entering a USB test mode
813  * @test_mode_nr: test feature selector
814  * @lpm_nyet_threshold: LPM NYET response threshold
815  * @hird_threshold: HIRD threshold
816  * @hsphy_interface: "utmi" or "ulpi"
817  * @connected: true when we're connected to a host, false otherwise
818  * @delayed_status: true when gadget driver asks for delayed status
819  * @ep0_bounced: true when we used bounce buffer
820  * @ep0_expect_in: true when we expect a DATA IN transfer
821  * @has_hibernation: true when dwc3 was configured with Hibernation
822  * @sysdev_is_parent: true when dwc3 device has a parent driver
823  * @has_lpm_erratum: true when core was configured with LPM Erratum. Note that
824  *			there's now way for software to detect this in runtime.
825  * @is_utmi_l1_suspend: the core asserts output signal
826  * 	0	- utmi_sleep_n
827  * 	1	- utmi_l1_suspend_n
828  * @is_fpga: true when we are using the FPGA board
829  * @pending_events: true when we have pending IRQs to be handled
830  * @pullups_connected: true when Run/Stop bit is set
831  * @setup_packet_pending: true when there's a Setup Packet in FIFO. Workaround
832  * @start_config_issued: true when StartConfig command has been issued
833  * @three_stage_setup: set if we perform a three phase setup
834  * @usb3_lpm_capable: set if hadrware supports Link Power Management
835  * @disable_scramble_quirk: set if we enable the disable scramble quirk
836  * @u2exit_lfps_quirk: set if we enable u2exit lfps quirk
837  * @u2ss_inp3_quirk: set if we enable P3 OK for U2/SS Inactive quirk
838  * @req_p1p2p3_quirk: set if we enable request p1p2p3 quirk
839  * @del_p1p2p3_quirk: set if we enable delay p1p2p3 quirk
840  * @del_phy_power_chg_quirk: set if we enable delay phy power change quirk
841  * @lfps_filter_quirk: set if we enable LFPS filter quirk
842  * @rx_detect_poll_quirk: set if we enable rx_detect to polling lfps quirk
843  * @dis_u3_susphy_quirk: set if we disable usb3 suspend phy
844  * @dis_u2_susphy_quirk: set if we disable usb2 suspend phy
845  * @dis_enblslpm_quirk: set if we clear enblslpm in GUSB2PHYCFG,
846  *                      disabling the suspend signal to the PHY.
847  * @dis_u2_freeclk_exists_quirk : set if we clear u2_freeclk_exists
848  *			in GUSB2PHYCFG, specify that USB2 PHY doesn't
849  *			provide a free-running PHY clock.
850  * @dis_del_phy_power_chg_quirk: set if we disable delay phy power
851  *			change quirk.
852  * @tx_de_emphasis_quirk: set if we enable Tx de-emphasis quirk
853  * @tx_de_emphasis: Tx de-emphasis value
854  * 	0	- -6dB de-emphasis
855  * 	1	- -3.5dB de-emphasis
856  * 	2	- No de-emphasis
857  * 	3	- Reserved
858  * @imod_interval: set the interrupt moderation interval in 250ns
859  *                 increments or 0 to disable.
860  */
861 struct dwc3 {
862 	struct usb_ctrlrequest	*ctrl_req;
863 	struct dwc3_trb		*ep0_trb;
864 	void			*ep0_bounce;
865 	void			*zlp_buf;
866 	void			*scratchbuf;
867 	u8			*setup_buf;
868 	dma_addr_t		ctrl_req_addr;
869 	dma_addr_t		ep0_trb_addr;
870 	dma_addr_t		ep0_bounce_addr;
871 	dma_addr_t		scratch_addr;
872 	struct dwc3_request	ep0_usb_req;
873 	struct completion	ep0_in_setup;
874 
875 	/* device lock */
876 	spinlock_t		lock;
877 
878 	struct device		*dev;
879 	struct device		*sysdev;
880 
881 	struct platform_device	*xhci;
882 	struct resource		xhci_resources[DWC3_XHCI_RESOURCES_NUM];
883 
884 	struct dwc3_event_buffer *ev_buf;
885 	struct dwc3_ep		*eps[DWC3_ENDPOINTS_NUM];
886 
887 	struct usb_gadget	gadget;
888 	struct usb_gadget_driver *gadget_driver;
889 
890 	struct usb_phy		*usb2_phy;
891 	struct usb_phy		*usb3_phy;
892 
893 	struct phy		*usb2_generic_phy;
894 	struct phy		*usb3_generic_phy;
895 
896 	struct ulpi		*ulpi;
897 
898 	void __iomem		*regs;
899 	size_t			regs_size;
900 
901 	enum usb_dr_mode	dr_mode;
902 	enum usb_phy_interface	hsphy_mode;
903 
904 	u32			fladj;
905 	u32			irq_gadget;
906 	u32			nr_scratch;
907 	u32			u1u2;
908 	u32			maximum_speed;
909 
910 	/*
911 	 * All 3.1 IP version constants are greater than the 3.0 IP
912 	 * version constants. This works for most version checks in
913 	 * dwc3. However, in the future, this may not apply as
914 	 * features may be developed on newer versions of the 3.0 IP
915 	 * that are not in the 3.1 IP.
916 	 */
917 	u32			revision;
918 
919 #define DWC3_REVISION_173A	0x5533173a
920 #define DWC3_REVISION_175A	0x5533175a
921 #define DWC3_REVISION_180A	0x5533180a
922 #define DWC3_REVISION_183A	0x5533183a
923 #define DWC3_REVISION_185A	0x5533185a
924 #define DWC3_REVISION_187A	0x5533187a
925 #define DWC3_REVISION_188A	0x5533188a
926 #define DWC3_REVISION_190A	0x5533190a
927 #define DWC3_REVISION_194A	0x5533194a
928 #define DWC3_REVISION_200A	0x5533200a
929 #define DWC3_REVISION_202A	0x5533202a
930 #define DWC3_REVISION_210A	0x5533210a
931 #define DWC3_REVISION_220A	0x5533220a
932 #define DWC3_REVISION_230A	0x5533230a
933 #define DWC3_REVISION_240A	0x5533240a
934 #define DWC3_REVISION_250A	0x5533250a
935 #define DWC3_REVISION_260A	0x5533260a
936 #define DWC3_REVISION_270A	0x5533270a
937 #define DWC3_REVISION_280A	0x5533280a
938 #define DWC3_REVISION_290A	0x5533290a
939 #define DWC3_REVISION_300A	0x5533300a
940 #define DWC3_REVISION_310A	0x5533310a
941 
942 /*
943  * NOTICE: we're using bit 31 as a "is usb 3.1" flag. This is really
944  * just so dwc31 revisions are always larger than dwc3.
945  */
946 #define DWC3_REVISION_IS_DWC31		0x80000000
947 #define DWC3_USB31_REVISION_110A	(0x3131302a | DWC3_REVISION_IS_DWC31)
948 #define DWC3_USB31_REVISION_120A	(0x3132302a | DWC3_REVISION_IS_DWC31)
949 
950 	enum dwc3_ep0_next	ep0_next_event;
951 	enum dwc3_ep0_state	ep0state;
952 	enum dwc3_link_state	link_state;
953 
954 	u16			isoch_delay;
955 	u16			u2sel;
956 	u16			u2pel;
957 	u8			u1sel;
958 	u8			u1pel;
959 
960 	u8			speed;
961 
962 	u8			num_out_eps;
963 	u8			num_in_eps;
964 
965 	struct dwc3_hwparams	hwparams;
966 	struct dentry		*root;
967 	struct debugfs_regset32	*regset;
968 
969 	u8			test_mode;
970 	u8			test_mode_nr;
971 	u8			lpm_nyet_threshold;
972 	u8			hird_threshold;
973 
974 	const char		*hsphy_interface;
975 
976 	unsigned		connected:1;
977 	unsigned		delayed_status:1;
978 	unsigned		ep0_bounced:1;
979 	unsigned		ep0_expect_in:1;
980 	unsigned		has_hibernation:1;
981 	unsigned		sysdev_is_parent:1;
982 	unsigned		has_lpm_erratum:1;
983 	unsigned		is_utmi_l1_suspend:1;
984 	unsigned		is_fpga:1;
985 	unsigned		pending_events:1;
986 	unsigned		pullups_connected:1;
987 	unsigned		setup_packet_pending:1;
988 	unsigned		three_stage_setup:1;
989 	unsigned		usb3_lpm_capable:1;
990 
991 	unsigned		disable_scramble_quirk:1;
992 	unsigned		u2exit_lfps_quirk:1;
993 	unsigned		u2ss_inp3_quirk:1;
994 	unsigned		req_p1p2p3_quirk:1;
995 	unsigned                del_p1p2p3_quirk:1;
996 	unsigned		del_phy_power_chg_quirk:1;
997 	unsigned		lfps_filter_quirk:1;
998 	unsigned		rx_detect_poll_quirk:1;
999 	unsigned		dis_u3_susphy_quirk:1;
1000 	unsigned		dis_u2_susphy_quirk:1;
1001 	unsigned		dis_enblslpm_quirk:1;
1002 	unsigned		dis_rxdet_inp3_quirk:1;
1003 	unsigned		dis_u2_freeclk_exists_quirk:1;
1004 	unsigned		dis_del_phy_power_chg_quirk:1;
1005 
1006 	unsigned		tx_de_emphasis_quirk:1;
1007 	unsigned		tx_de_emphasis:2;
1008 
1009 	u16			imod_interval;
1010 };
1011 
1012 /* -------------------------------------------------------------------------- */
1013 
1014 /* -------------------------------------------------------------------------- */
1015 
1016 struct dwc3_event_type {
1017 	u32	is_devspec:1;
1018 	u32	type:7;
1019 	u32	reserved8_31:24;
1020 } __packed;
1021 
1022 #define DWC3_DEPEVT_XFERCOMPLETE	0x01
1023 #define DWC3_DEPEVT_XFERINPROGRESS	0x02
1024 #define DWC3_DEPEVT_XFERNOTREADY	0x03
1025 #define DWC3_DEPEVT_RXTXFIFOEVT		0x04
1026 #define DWC3_DEPEVT_STREAMEVT		0x06
1027 #define DWC3_DEPEVT_EPCMDCMPLT		0x07
1028 
1029 /**
1030  * struct dwc3_event_depvt - Device Endpoint Events
1031  * @one_bit: indicates this is an endpoint event (not used)
1032  * @endpoint_number: number of the endpoint
1033  * @endpoint_event: The event we have:
1034  *	0x00	- Reserved
1035  *	0x01	- XferComplete
1036  *	0x02	- XferInProgress
1037  *	0x03	- XferNotReady
1038  *	0x04	- RxTxFifoEvt (IN->Underrun, OUT->Overrun)
1039  *	0x05	- Reserved
1040  *	0x06	- StreamEvt
1041  *	0x07	- EPCmdCmplt
1042  * @reserved11_10: Reserved, don't use.
1043  * @status: Indicates the status of the event. Refer to databook for
1044  *	more information.
1045  * @parameters: Parameters of the current event. Refer to databook for
1046  *	more information.
1047  */
1048 struct dwc3_event_depevt {
1049 	u32	one_bit:1;
1050 	u32	endpoint_number:5;
1051 	u32	endpoint_event:4;
1052 	u32	reserved11_10:2;
1053 	u32	status:4;
1054 
1055 /* Within XferNotReady */
1056 #define DEPEVT_STATUS_TRANSFER_ACTIVE	(1 << 3)
1057 
1058 /* Within XferComplete */
1059 #define DEPEVT_STATUS_BUSERR	(1 << 0)
1060 #define DEPEVT_STATUS_SHORT	(1 << 1)
1061 #define DEPEVT_STATUS_IOC	(1 << 2)
1062 #define DEPEVT_STATUS_LST	(1 << 3)
1063 
1064 /* Stream event only */
1065 #define DEPEVT_STREAMEVT_FOUND		1
1066 #define DEPEVT_STREAMEVT_NOTFOUND	2
1067 
1068 /* Control-only Status */
1069 #define DEPEVT_STATUS_CONTROL_DATA	1
1070 #define DEPEVT_STATUS_CONTROL_STATUS	2
1071 #define DEPEVT_STATUS_CONTROL_PHASE(n)	((n) & 3)
1072 
1073 /* In response to Start Transfer */
1074 #define DEPEVT_TRANSFER_NO_RESOURCE	1
1075 #define DEPEVT_TRANSFER_BUS_EXPIRY	2
1076 
1077 	u32	parameters:16;
1078 
1079 /* For Command Complete Events */
1080 #define DEPEVT_PARAMETER_CMD(n)	(((n) & (0xf << 8)) >> 8)
1081 } __packed;
1082 
1083 /**
1084  * struct dwc3_event_devt - Device Events
1085  * @one_bit: indicates this is a non-endpoint event (not used)
1086  * @device_event: indicates it's a device event. Should read as 0x00
1087  * @type: indicates the type of device event.
1088  *	0	- DisconnEvt
1089  *	1	- USBRst
1090  *	2	- ConnectDone
1091  *	3	- ULStChng
1092  *	4	- WkUpEvt
1093  *	5	- Reserved
1094  *	6	- EOPF
1095  *	7	- SOF
1096  *	8	- Reserved
1097  *	9	- ErrticErr
1098  *	10	- CmdCmplt
1099  *	11	- EvntOverflow
1100  *	12	- VndrDevTstRcved
1101  * @reserved15_12: Reserved, not used
1102  * @event_info: Information about this event
1103  * @reserved31_25: Reserved, not used
1104  */
1105 struct dwc3_event_devt {
1106 	u32	one_bit:1;
1107 	u32	device_event:7;
1108 	u32	type:4;
1109 	u32	reserved15_12:4;
1110 	u32	event_info:9;
1111 	u32	reserved31_25:7;
1112 } __packed;
1113 
1114 /**
1115  * struct dwc3_event_gevt - Other Core Events
1116  * @one_bit: indicates this is a non-endpoint event (not used)
1117  * @device_event: indicates it's (0x03) Carkit or (0x04) I2C event.
1118  * @phy_port_number: self-explanatory
1119  * @reserved31_12: Reserved, not used.
1120  */
1121 struct dwc3_event_gevt {
1122 	u32	one_bit:1;
1123 	u32	device_event:7;
1124 	u32	phy_port_number:4;
1125 	u32	reserved31_12:20;
1126 } __packed;
1127 
1128 /**
1129  * union dwc3_event - representation of Event Buffer contents
1130  * @raw: raw 32-bit event
1131  * @type: the type of the event
1132  * @depevt: Device Endpoint Event
1133  * @devt: Device Event
1134  * @gevt: Global Event
1135  */
1136 union dwc3_event {
1137 	u32				raw;
1138 	struct dwc3_event_type		type;
1139 	struct dwc3_event_depevt	depevt;
1140 	struct dwc3_event_devt		devt;
1141 	struct dwc3_event_gevt		gevt;
1142 };
1143 
1144 /**
1145  * struct dwc3_gadget_ep_cmd_params - representation of endpoint command
1146  * parameters
1147  * @param2: third parameter
1148  * @param1: second parameter
1149  * @param0: first parameter
1150  */
1151 struct dwc3_gadget_ep_cmd_params {
1152 	u32	param2;
1153 	u32	param1;
1154 	u32	param0;
1155 };
1156 
1157 /*
1158  * DWC3 Features to be used as Driver Data
1159  */
1160 
1161 #define DWC3_HAS_PERIPHERAL		BIT(0)
1162 #define DWC3_HAS_XHCI			BIT(1)
1163 #define DWC3_HAS_OTG			BIT(3)
1164 
1165 /* prototypes */
1166 void dwc3_set_mode(struct dwc3 *dwc, u32 mode);
1167 u32 dwc3_core_fifo_space(struct dwc3_ep *dep, u8 type);
1168 
1169 /* check whether we are on the DWC_usb3 core */
1170 static inline bool dwc3_is_usb3(struct dwc3 *dwc)
1171 {
1172 	return !(dwc->revision & DWC3_REVISION_IS_DWC31);
1173 }
1174 
1175 /* check whether we are on the DWC_usb31 core */
1176 static inline bool dwc3_is_usb31(struct dwc3 *dwc)
1177 {
1178 	return !!(dwc->revision & DWC3_REVISION_IS_DWC31);
1179 }
1180 
1181 bool dwc3_has_imod(struct dwc3 *dwc);
1182 
1183 #if IS_ENABLED(CONFIG_USB_DWC3_HOST) || IS_ENABLED(CONFIG_USB_DWC3_DUAL_ROLE)
1184 int dwc3_host_init(struct dwc3 *dwc);
1185 void dwc3_host_exit(struct dwc3 *dwc);
1186 #else
1187 static inline int dwc3_host_init(struct dwc3 *dwc)
1188 { return 0; }
1189 static inline void dwc3_host_exit(struct dwc3 *dwc)
1190 { }
1191 #endif
1192 
1193 #if IS_ENABLED(CONFIG_USB_DWC3_GADGET) || IS_ENABLED(CONFIG_USB_DWC3_DUAL_ROLE)
1194 int dwc3_gadget_init(struct dwc3 *dwc);
1195 void dwc3_gadget_exit(struct dwc3 *dwc);
1196 int dwc3_gadget_set_test_mode(struct dwc3 *dwc, int mode);
1197 int dwc3_gadget_get_link_state(struct dwc3 *dwc);
1198 int dwc3_gadget_set_link_state(struct dwc3 *dwc, enum dwc3_link_state state);
1199 int dwc3_send_gadget_ep_cmd(struct dwc3_ep *dep, unsigned cmd,
1200 		struct dwc3_gadget_ep_cmd_params *params);
1201 int dwc3_send_gadget_generic_command(struct dwc3 *dwc, unsigned cmd, u32 param);
1202 #else
1203 static inline int dwc3_gadget_init(struct dwc3 *dwc)
1204 { return 0; }
1205 static inline void dwc3_gadget_exit(struct dwc3 *dwc)
1206 { }
1207 static inline int dwc3_gadget_set_test_mode(struct dwc3 *dwc, int mode)
1208 { return 0; }
1209 static inline int dwc3_gadget_get_link_state(struct dwc3 *dwc)
1210 { return 0; }
1211 static inline int dwc3_gadget_set_link_state(struct dwc3 *dwc,
1212 		enum dwc3_link_state state)
1213 { return 0; }
1214 
1215 static inline int dwc3_send_gadget_ep_cmd(struct dwc3_ep *dep, unsigned cmd,
1216 		struct dwc3_gadget_ep_cmd_params *params)
1217 { return 0; }
1218 static inline int dwc3_send_gadget_generic_command(struct dwc3 *dwc,
1219 		int cmd, u32 param)
1220 { return 0; }
1221 #endif
1222 
1223 /* power management interface */
1224 #if !IS_ENABLED(CONFIG_USB_DWC3_HOST)
1225 int dwc3_gadget_suspend(struct dwc3 *dwc);
1226 int dwc3_gadget_resume(struct dwc3 *dwc);
1227 void dwc3_gadget_process_pending_events(struct dwc3 *dwc);
1228 #else
1229 static inline int dwc3_gadget_suspend(struct dwc3 *dwc)
1230 {
1231 	return 0;
1232 }
1233 
1234 static inline int dwc3_gadget_resume(struct dwc3 *dwc)
1235 {
1236 	return 0;
1237 }
1238 
1239 static inline void dwc3_gadget_process_pending_events(struct dwc3 *dwc)
1240 {
1241 }
1242 #endif /* !IS_ENABLED(CONFIG_USB_DWC3_HOST) */
1243 
1244 #if IS_ENABLED(CONFIG_USB_DWC3_ULPI)
1245 int dwc3_ulpi_init(struct dwc3 *dwc);
1246 void dwc3_ulpi_exit(struct dwc3 *dwc);
1247 #else
1248 static inline int dwc3_ulpi_init(struct dwc3 *dwc)
1249 { return 0; }
1250 static inline void dwc3_ulpi_exit(struct dwc3 *dwc)
1251 { }
1252 #endif
1253 
1254 #endif /* __DRIVERS_USB_DWC3_CORE_H */
1255