1 /** 2 * core.h - DesignWare USB3 DRD Core Header 3 * 4 * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com 5 * 6 * Authors: Felipe Balbi <balbi@ti.com>, 7 * Sebastian Andrzej Siewior <bigeasy@linutronix.de> 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions, and the following disclaimer, 14 * without modification. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. The names of the above-listed copyright holders may not be used 19 * to endorse or promote products derived from this software without 20 * specific prior written permission. 21 * 22 * ALTERNATIVELY, this software may be distributed under the terms of the 23 * GNU General Public License ("GPL") version 2, as published by the Free 24 * Software Foundation. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS 27 * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 28 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR 30 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 31 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 32 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 33 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF 34 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING 35 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 36 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 #ifndef __DRIVERS_USB_DWC3_CORE_H 40 #define __DRIVERS_USB_DWC3_CORE_H 41 42 #include <linux/device.h> 43 #include <linux/spinlock.h> 44 #include <linux/ioport.h> 45 #include <linux/list.h> 46 #include <linux/dma-mapping.h> 47 #include <linux/mm.h> 48 #include <linux/debugfs.h> 49 50 #include <linux/usb/ch9.h> 51 #include <linux/usb/gadget.h> 52 53 /* Global constants */ 54 #define DWC3_EP0_BOUNCE_SIZE 512 55 #define DWC3_ENDPOINTS_NUM 32 56 #define DWC3_XHCI_RESOURCES_NUM 2 57 58 #define DWC3_EVENT_SIZE 4 /* bytes */ 59 #define DWC3_EVENT_MAX_NUM 64 /* 2 events/endpoint */ 60 #define DWC3_EVENT_BUFFERS_SIZE (DWC3_EVENT_SIZE * DWC3_EVENT_MAX_NUM) 61 #define DWC3_EVENT_TYPE_MASK 0xfe 62 63 #define DWC3_EVENT_TYPE_DEV 0 64 #define DWC3_EVENT_TYPE_CARKIT 3 65 #define DWC3_EVENT_TYPE_I2C 4 66 67 #define DWC3_DEVICE_EVENT_DISCONNECT 0 68 #define DWC3_DEVICE_EVENT_RESET 1 69 #define DWC3_DEVICE_EVENT_CONNECT_DONE 2 70 #define DWC3_DEVICE_EVENT_LINK_STATUS_CHANGE 3 71 #define DWC3_DEVICE_EVENT_WAKEUP 4 72 #define DWC3_DEVICE_EVENT_HIBER_REQ 5 73 #define DWC3_DEVICE_EVENT_EOPF 6 74 #define DWC3_DEVICE_EVENT_SOF 7 75 #define DWC3_DEVICE_EVENT_ERRATIC_ERROR 9 76 #define DWC3_DEVICE_EVENT_CMD_CMPL 10 77 #define DWC3_DEVICE_EVENT_OVERFLOW 11 78 79 #define DWC3_GEVNTCOUNT_MASK 0xfffc 80 #define DWC3_GSNPSID_MASK 0xffff0000 81 #define DWC3_GSNPSREV_MASK 0xffff 82 83 /* DWC3 registers memory space boundries */ 84 #define DWC3_XHCI_REGS_START 0x0 85 #define DWC3_XHCI_REGS_END 0x7fff 86 #define DWC3_GLOBALS_REGS_START 0xc100 87 #define DWC3_GLOBALS_REGS_END 0xc6ff 88 #define DWC3_DEVICE_REGS_START 0xc700 89 #define DWC3_DEVICE_REGS_END 0xcbff 90 #define DWC3_OTG_REGS_START 0xcc00 91 #define DWC3_OTG_REGS_END 0xccff 92 93 /* Global Registers */ 94 #define DWC3_GSBUSCFG0 0xc100 95 #define DWC3_GSBUSCFG1 0xc104 96 #define DWC3_GTXTHRCFG 0xc108 97 #define DWC3_GRXTHRCFG 0xc10c 98 #define DWC3_GCTL 0xc110 99 #define DWC3_GEVTEN 0xc114 100 #define DWC3_GSTS 0xc118 101 #define DWC3_GSNPSID 0xc120 102 #define DWC3_GGPIO 0xc124 103 #define DWC3_GUID 0xc128 104 #define DWC3_GUCTL 0xc12c 105 #define DWC3_GBUSERRADDR0 0xc130 106 #define DWC3_GBUSERRADDR1 0xc134 107 #define DWC3_GPRTBIMAP0 0xc138 108 #define DWC3_GPRTBIMAP1 0xc13c 109 #define DWC3_GHWPARAMS0 0xc140 110 #define DWC3_GHWPARAMS1 0xc144 111 #define DWC3_GHWPARAMS2 0xc148 112 #define DWC3_GHWPARAMS3 0xc14c 113 #define DWC3_GHWPARAMS4 0xc150 114 #define DWC3_GHWPARAMS5 0xc154 115 #define DWC3_GHWPARAMS6 0xc158 116 #define DWC3_GHWPARAMS7 0xc15c 117 #define DWC3_GDBGFIFOSPACE 0xc160 118 #define DWC3_GDBGLTSSM 0xc164 119 #define DWC3_GPRTBIMAP_HS0 0xc180 120 #define DWC3_GPRTBIMAP_HS1 0xc184 121 #define DWC3_GPRTBIMAP_FS0 0xc188 122 #define DWC3_GPRTBIMAP_FS1 0xc18c 123 124 #define DWC3_GUSB2PHYCFG(n) (0xc200 + (n * 0x04)) 125 #define DWC3_GUSB2I2CCTL(n) (0xc240 + (n * 0x04)) 126 127 #define DWC3_GUSB2PHYACC(n) (0xc280 + (n * 0x04)) 128 129 #define DWC3_GUSB3PIPECTL(n) (0xc2c0 + (n * 0x04)) 130 131 #define DWC3_GTXFIFOSIZ(n) (0xc300 + (n * 0x04)) 132 #define DWC3_GRXFIFOSIZ(n) (0xc380 + (n * 0x04)) 133 134 #define DWC3_GEVNTADRLO(n) (0xc400 + (n * 0x10)) 135 #define DWC3_GEVNTADRHI(n) (0xc404 + (n * 0x10)) 136 #define DWC3_GEVNTSIZ(n) (0xc408 + (n * 0x10)) 137 #define DWC3_GEVNTCOUNT(n) (0xc40c + (n * 0x10)) 138 139 #define DWC3_GHWPARAMS8 0xc600 140 141 /* Device Registers */ 142 #define DWC3_DCFG 0xc700 143 #define DWC3_DCTL 0xc704 144 #define DWC3_DEVTEN 0xc708 145 #define DWC3_DSTS 0xc70c 146 #define DWC3_DGCMDPAR 0xc710 147 #define DWC3_DGCMD 0xc714 148 #define DWC3_DALEPENA 0xc720 149 #define DWC3_DEPCMDPAR2(n) (0xc800 + (n * 0x10)) 150 #define DWC3_DEPCMDPAR1(n) (0xc804 + (n * 0x10)) 151 #define DWC3_DEPCMDPAR0(n) (0xc808 + (n * 0x10)) 152 #define DWC3_DEPCMD(n) (0xc80c + (n * 0x10)) 153 154 /* OTG Registers */ 155 #define DWC3_OCFG 0xcc00 156 #define DWC3_OCTL 0xcc04 157 #define DWC3_OEVTEN 0xcc08 158 #define DWC3_OSTS 0xcc0C 159 160 /* Bit fields */ 161 162 /* Global Configuration Register */ 163 #define DWC3_GCTL_PWRDNSCALE(n) ((n) << 19) 164 #define DWC3_GCTL_U2RSTECN (1 << 16) 165 #define DWC3_GCTL_RAMCLKSEL(x) (((x) & DWC3_GCTL_CLK_MASK) << 6) 166 #define DWC3_GCTL_CLK_BUS (0) 167 #define DWC3_GCTL_CLK_PIPE (1) 168 #define DWC3_GCTL_CLK_PIPEHALF (2) 169 #define DWC3_GCTL_CLK_MASK (3) 170 171 #define DWC3_GCTL_PRTCAP(n) (((n) & (3 << 12)) >> 12) 172 #define DWC3_GCTL_PRTCAPDIR(n) ((n) << 12) 173 #define DWC3_GCTL_PRTCAP_HOST 1 174 #define DWC3_GCTL_PRTCAP_DEVICE 2 175 #define DWC3_GCTL_PRTCAP_OTG 3 176 177 #define DWC3_GCTL_CORESOFTRESET (1 << 11) 178 #define DWC3_GCTL_SCALEDOWN(n) ((n) << 4) 179 #define DWC3_GCTL_SCALEDOWN_MASK DWC3_GCTL_SCALEDOWN(3) 180 #define DWC3_GCTL_DISSCRAMBLE (1 << 3) 181 #define DWC3_GCTL_GBLHIBERNATIONEN (1 << 1) 182 #define DWC3_GCTL_DSBLCLKGTNG (1 << 0) 183 184 /* Global USB2 PHY Configuration Register */ 185 #define DWC3_GUSB2PHYCFG_PHYSOFTRST (1 << 31) 186 #define DWC3_GUSB2PHYCFG_SUSPHY (1 << 6) 187 188 /* Global USB3 PIPE Control Register */ 189 #define DWC3_GUSB3PIPECTL_PHYSOFTRST (1 << 31) 190 #define DWC3_GUSB3PIPECTL_SUSPHY (1 << 17) 191 192 /* Global TX Fifo Size Register */ 193 #define DWC3_GTXFIFOSIZ_TXFDEF(n) ((n) & 0xffff) 194 #define DWC3_GTXFIFOSIZ_TXFSTADDR(n) ((n) & 0xffff0000) 195 196 /* Global HWPARAMS1 Register */ 197 #define DWC3_GHWPARAMS1_EN_PWROPT(n) (((n) & (3 << 24)) >> 24) 198 #define DWC3_GHWPARAMS1_EN_PWROPT_NO 0 199 #define DWC3_GHWPARAMS1_EN_PWROPT_CLK 1 200 #define DWC3_GHWPARAMS1_EN_PWROPT_HIB 2 201 #define DWC3_GHWPARAMS1_PWROPT(n) ((n) << 24) 202 #define DWC3_GHWPARAMS1_PWROPT_MASK DWC3_GHWPARAMS1_PWROPT(3) 203 204 /* Global HWPARAMS4 Register */ 205 #define DWC3_GHWPARAMS4_HIBER_SCRATCHBUFS(n) (((n) & (0x0f << 13)) >> 13) 206 #define DWC3_MAX_HIBER_SCRATCHBUFS 15 207 208 /* Device Configuration Register */ 209 #define DWC3_DCFG_LPM_CAP (1 << 22) 210 #define DWC3_DCFG_DEVADDR(addr) ((addr) << 3) 211 #define DWC3_DCFG_DEVADDR_MASK DWC3_DCFG_DEVADDR(0x7f) 212 213 #define DWC3_DCFG_SPEED_MASK (7 << 0) 214 #define DWC3_DCFG_SUPERSPEED (4 << 0) 215 #define DWC3_DCFG_HIGHSPEED (0 << 0) 216 #define DWC3_DCFG_FULLSPEED2 (1 << 0) 217 #define DWC3_DCFG_LOWSPEED (2 << 0) 218 #define DWC3_DCFG_FULLSPEED1 (3 << 0) 219 220 #define DWC3_DCFG_LPM_CAP (1 << 22) 221 222 /* Device Control Register */ 223 #define DWC3_DCTL_RUN_STOP (1 << 31) 224 #define DWC3_DCTL_CSFTRST (1 << 30) 225 #define DWC3_DCTL_LSFTRST (1 << 29) 226 227 #define DWC3_DCTL_HIRD_THRES_MASK (0x1f << 24) 228 #define DWC3_DCTL_HIRD_THRES(n) ((n) << 24) 229 230 #define DWC3_DCTL_APPL1RES (1 << 23) 231 232 /* These apply for core versions 1.87a and earlier */ 233 #define DWC3_DCTL_TRGTULST_MASK (0x0f << 17) 234 #define DWC3_DCTL_TRGTULST(n) ((n) << 17) 235 #define DWC3_DCTL_TRGTULST_U2 (DWC3_DCTL_TRGTULST(2)) 236 #define DWC3_DCTL_TRGTULST_U3 (DWC3_DCTL_TRGTULST(3)) 237 #define DWC3_DCTL_TRGTULST_SS_DIS (DWC3_DCTL_TRGTULST(4)) 238 #define DWC3_DCTL_TRGTULST_RX_DET (DWC3_DCTL_TRGTULST(5)) 239 #define DWC3_DCTL_TRGTULST_SS_INACT (DWC3_DCTL_TRGTULST(6)) 240 241 /* These apply for core versions 1.94a and later */ 242 #define DWC3_DCTL_KEEP_CONNECT (1 << 19) 243 #define DWC3_DCTL_L1_HIBER_EN (1 << 18) 244 #define DWC3_DCTL_CRS (1 << 17) 245 #define DWC3_DCTL_CSS (1 << 16) 246 247 #define DWC3_DCTL_INITU2ENA (1 << 12) 248 #define DWC3_DCTL_ACCEPTU2ENA (1 << 11) 249 #define DWC3_DCTL_INITU1ENA (1 << 10) 250 #define DWC3_DCTL_ACCEPTU1ENA (1 << 9) 251 #define DWC3_DCTL_TSTCTRL_MASK (0xf << 1) 252 253 #define DWC3_DCTL_ULSTCHNGREQ_MASK (0x0f << 5) 254 #define DWC3_DCTL_ULSTCHNGREQ(n) (((n) << 5) & DWC3_DCTL_ULSTCHNGREQ_MASK) 255 256 #define DWC3_DCTL_ULSTCHNG_NO_ACTION (DWC3_DCTL_ULSTCHNGREQ(0)) 257 #define DWC3_DCTL_ULSTCHNG_SS_DISABLED (DWC3_DCTL_ULSTCHNGREQ(4)) 258 #define DWC3_DCTL_ULSTCHNG_RX_DETECT (DWC3_DCTL_ULSTCHNGREQ(5)) 259 #define DWC3_DCTL_ULSTCHNG_SS_INACTIVE (DWC3_DCTL_ULSTCHNGREQ(6)) 260 #define DWC3_DCTL_ULSTCHNG_RECOVERY (DWC3_DCTL_ULSTCHNGREQ(8)) 261 #define DWC3_DCTL_ULSTCHNG_COMPLIANCE (DWC3_DCTL_ULSTCHNGREQ(10)) 262 #define DWC3_DCTL_ULSTCHNG_LOOPBACK (DWC3_DCTL_ULSTCHNGREQ(11)) 263 264 /* Device Event Enable Register */ 265 #define DWC3_DEVTEN_VNDRDEVTSTRCVEDEN (1 << 12) 266 #define DWC3_DEVTEN_EVNTOVERFLOWEN (1 << 11) 267 #define DWC3_DEVTEN_CMDCMPLTEN (1 << 10) 268 #define DWC3_DEVTEN_ERRTICERREN (1 << 9) 269 #define DWC3_DEVTEN_SOFEN (1 << 7) 270 #define DWC3_DEVTEN_EOPFEN (1 << 6) 271 #define DWC3_DEVTEN_HIBERNATIONREQEVTEN (1 << 5) 272 #define DWC3_DEVTEN_WKUPEVTEN (1 << 4) 273 #define DWC3_DEVTEN_ULSTCNGEN (1 << 3) 274 #define DWC3_DEVTEN_CONNECTDONEEN (1 << 2) 275 #define DWC3_DEVTEN_USBRSTEN (1 << 1) 276 #define DWC3_DEVTEN_DISCONNEVTEN (1 << 0) 277 278 /* Device Status Register */ 279 #define DWC3_DSTS_DCNRD (1 << 29) 280 281 /* This applies for core versions 1.87a and earlier */ 282 #define DWC3_DSTS_PWRUPREQ (1 << 24) 283 284 /* These apply for core versions 1.94a and later */ 285 #define DWC3_DSTS_RSS (1 << 25) 286 #define DWC3_DSTS_SSS (1 << 24) 287 288 #define DWC3_DSTS_COREIDLE (1 << 23) 289 #define DWC3_DSTS_DEVCTRLHLT (1 << 22) 290 291 #define DWC3_DSTS_USBLNKST_MASK (0x0f << 18) 292 #define DWC3_DSTS_USBLNKST(n) (((n) & DWC3_DSTS_USBLNKST_MASK) >> 18) 293 294 #define DWC3_DSTS_RXFIFOEMPTY (1 << 17) 295 296 #define DWC3_DSTS_SOFFN_MASK (0x3fff << 3) 297 #define DWC3_DSTS_SOFFN(n) (((n) & DWC3_DSTS_SOFFN_MASK) >> 3) 298 299 #define DWC3_DSTS_CONNECTSPD (7 << 0) 300 301 #define DWC3_DSTS_SUPERSPEED (4 << 0) 302 #define DWC3_DSTS_HIGHSPEED (0 << 0) 303 #define DWC3_DSTS_FULLSPEED2 (1 << 0) 304 #define DWC3_DSTS_LOWSPEED (2 << 0) 305 #define DWC3_DSTS_FULLSPEED1 (3 << 0) 306 307 /* Device Generic Command Register */ 308 #define DWC3_DGCMD_SET_LMP 0x01 309 #define DWC3_DGCMD_SET_PERIODIC_PAR 0x02 310 #define DWC3_DGCMD_XMIT_FUNCTION 0x03 311 312 /* These apply for core versions 1.94a and later */ 313 #define DWC3_DGCMD_SET_SCRATCHPAD_ADDR_LO 0x04 314 #define DWC3_DGCMD_SET_SCRATCHPAD_ADDR_HI 0x05 315 316 #define DWC3_DGCMD_SELECTED_FIFO_FLUSH 0x09 317 #define DWC3_DGCMD_ALL_FIFO_FLUSH 0x0a 318 #define DWC3_DGCMD_SET_ENDPOINT_NRDY 0x0c 319 #define DWC3_DGCMD_RUN_SOC_BUS_LOOPBACK 0x10 320 321 #define DWC3_DGCMD_STATUS(n) (((n) >> 15) & 1) 322 #define DWC3_DGCMD_CMDACT (1 << 10) 323 #define DWC3_DGCMD_CMDIOC (1 << 8) 324 325 /* Device Generic Command Parameter Register */ 326 #define DWC3_DGCMDPAR_FORCE_LINKPM_ACCEPT (1 << 0) 327 #define DWC3_DGCMDPAR_FIFO_NUM(n) ((n) << 0) 328 #define DWC3_DGCMDPAR_RX_FIFO (0 << 5) 329 #define DWC3_DGCMDPAR_TX_FIFO (1 << 5) 330 #define DWC3_DGCMDPAR_LOOPBACK_DIS (0 << 0) 331 #define DWC3_DGCMDPAR_LOOPBACK_ENA (1 << 0) 332 333 /* Device Endpoint Command Register */ 334 #define DWC3_DEPCMD_PARAM_SHIFT 16 335 #define DWC3_DEPCMD_PARAM(x) ((x) << DWC3_DEPCMD_PARAM_SHIFT) 336 #define DWC3_DEPCMD_GET_RSC_IDX(x) (((x) >> DWC3_DEPCMD_PARAM_SHIFT) & 0x7f) 337 #define DWC3_DEPCMD_STATUS(x) (((x) >> 15) & 1) 338 #define DWC3_DEPCMD_HIPRI_FORCERM (1 << 11) 339 #define DWC3_DEPCMD_CMDACT (1 << 10) 340 #define DWC3_DEPCMD_CMDIOC (1 << 8) 341 342 #define DWC3_DEPCMD_DEPSTARTCFG (0x09 << 0) 343 #define DWC3_DEPCMD_ENDTRANSFER (0x08 << 0) 344 #define DWC3_DEPCMD_UPDATETRANSFER (0x07 << 0) 345 #define DWC3_DEPCMD_STARTTRANSFER (0x06 << 0) 346 #define DWC3_DEPCMD_CLEARSTALL (0x05 << 0) 347 #define DWC3_DEPCMD_SETSTALL (0x04 << 0) 348 /* This applies for core versions 1.90a and earlier */ 349 #define DWC3_DEPCMD_GETSEQNUMBER (0x03 << 0) 350 /* This applies for core versions 1.94a and later */ 351 #define DWC3_DEPCMD_GETEPSTATE (0x03 << 0) 352 #define DWC3_DEPCMD_SETTRANSFRESOURCE (0x02 << 0) 353 #define DWC3_DEPCMD_SETEPCONFIG (0x01 << 0) 354 355 /* The EP number goes 0..31 so ep0 is always out and ep1 is always in */ 356 #define DWC3_DALEPENA_EP(n) (1 << n) 357 358 #define DWC3_DEPCMD_TYPE_CONTROL 0 359 #define DWC3_DEPCMD_TYPE_ISOC 1 360 #define DWC3_DEPCMD_TYPE_BULK 2 361 #define DWC3_DEPCMD_TYPE_INTR 3 362 363 /* Structures */ 364 365 struct dwc3_trb; 366 367 /** 368 * struct dwc3_event_buffer - Software event buffer representation 369 * @list: a list of event buffers 370 * @buf: _THE_ buffer 371 * @length: size of this buffer 372 * @dma: dma_addr_t 373 * @dwc: pointer to DWC controller 374 */ 375 struct dwc3_event_buffer { 376 void *buf; 377 unsigned length; 378 unsigned int lpos; 379 380 dma_addr_t dma; 381 382 struct dwc3 *dwc; 383 }; 384 385 #define DWC3_EP_FLAG_STALLED (1 << 0) 386 #define DWC3_EP_FLAG_WEDGED (1 << 1) 387 388 #define DWC3_EP_DIRECTION_TX true 389 #define DWC3_EP_DIRECTION_RX false 390 391 #define DWC3_TRB_NUM 32 392 #define DWC3_TRB_MASK (DWC3_TRB_NUM - 1) 393 394 /** 395 * struct dwc3_ep - device side endpoint representation 396 * @endpoint: usb endpoint 397 * @request_list: list of requests for this endpoint 398 * @req_queued: list of requests on this ep which have TRBs setup 399 * @trb_pool: array of transaction buffers 400 * @trb_pool_dma: dma address of @trb_pool 401 * @free_slot: next slot which is going to be used 402 * @busy_slot: first slot which is owned by HW 403 * @desc: usb_endpoint_descriptor pointer 404 * @dwc: pointer to DWC controller 405 * @flags: endpoint flags (wedged, stalled, ...) 406 * @current_trb: index of current used trb 407 * @number: endpoint number (1 - 15) 408 * @type: set to bmAttributes & USB_ENDPOINT_XFERTYPE_MASK 409 * @resource_index: Resource transfer index 410 * @interval: the intervall on which the ISOC transfer is started 411 * @name: a human readable name e.g. ep1out-bulk 412 * @direction: true for TX, false for RX 413 * @stream_capable: true when streams are enabled 414 */ 415 struct dwc3_ep { 416 struct usb_ep endpoint; 417 struct list_head request_list; 418 struct list_head req_queued; 419 420 struct dwc3_trb *trb_pool; 421 dma_addr_t trb_pool_dma; 422 u32 free_slot; 423 u32 busy_slot; 424 const struct usb_ss_ep_comp_descriptor *comp_desc; 425 struct dwc3 *dwc; 426 427 unsigned flags; 428 #define DWC3_EP_ENABLED (1 << 0) 429 #define DWC3_EP_STALL (1 << 1) 430 #define DWC3_EP_WEDGE (1 << 2) 431 #define DWC3_EP_BUSY (1 << 4) 432 #define DWC3_EP_PENDING_REQUEST (1 << 5) 433 #define DWC3_EP_MISSED_ISOC (1 << 6) 434 435 /* This last one is specific to EP0 */ 436 #define DWC3_EP0_DIR_IN (1 << 31) 437 438 unsigned current_trb; 439 440 u8 number; 441 u8 type; 442 u8 resource_index; 443 u32 interval; 444 445 char name[20]; 446 447 unsigned direction:1; 448 unsigned stream_capable:1; 449 }; 450 451 enum dwc3_phy { 452 DWC3_PHY_UNKNOWN = 0, 453 DWC3_PHY_USB3, 454 DWC3_PHY_USB2, 455 }; 456 457 enum dwc3_ep0_next { 458 DWC3_EP0_UNKNOWN = 0, 459 DWC3_EP0_COMPLETE, 460 DWC3_EP0_NRDY_DATA, 461 DWC3_EP0_NRDY_STATUS, 462 }; 463 464 enum dwc3_ep0_state { 465 EP0_UNCONNECTED = 0, 466 EP0_SETUP_PHASE, 467 EP0_DATA_PHASE, 468 EP0_STATUS_PHASE, 469 }; 470 471 enum dwc3_link_state { 472 /* In SuperSpeed */ 473 DWC3_LINK_STATE_U0 = 0x00, /* in HS, means ON */ 474 DWC3_LINK_STATE_U1 = 0x01, 475 DWC3_LINK_STATE_U2 = 0x02, /* in HS, means SLEEP */ 476 DWC3_LINK_STATE_U3 = 0x03, /* in HS, means SUSPEND */ 477 DWC3_LINK_STATE_SS_DIS = 0x04, 478 DWC3_LINK_STATE_RX_DET = 0x05, /* in HS, means Early Suspend */ 479 DWC3_LINK_STATE_SS_INACT = 0x06, 480 DWC3_LINK_STATE_POLL = 0x07, 481 DWC3_LINK_STATE_RECOV = 0x08, 482 DWC3_LINK_STATE_HRESET = 0x09, 483 DWC3_LINK_STATE_CMPLY = 0x0a, 484 DWC3_LINK_STATE_LPBK = 0x0b, 485 DWC3_LINK_STATE_RESET = 0x0e, 486 DWC3_LINK_STATE_RESUME = 0x0f, 487 DWC3_LINK_STATE_MASK = 0x0f, 488 }; 489 490 enum dwc3_device_state { 491 DWC3_DEFAULT_STATE, 492 DWC3_ADDRESS_STATE, 493 DWC3_CONFIGURED_STATE, 494 }; 495 496 /* TRB Length, PCM and Status */ 497 #define DWC3_TRB_SIZE_MASK (0x00ffffff) 498 #define DWC3_TRB_SIZE_LENGTH(n) ((n) & DWC3_TRB_SIZE_MASK) 499 #define DWC3_TRB_SIZE_PCM1(n) (((n) & 0x03) << 24) 500 #define DWC3_TRB_SIZE_TRBSTS(n) (((n) & (0x0f << 28)) >> 28) 501 502 #define DWC3_TRBSTS_OK 0 503 #define DWC3_TRBSTS_MISSED_ISOC 1 504 #define DWC3_TRBSTS_SETUP_PENDING 2 505 #define DWC3_TRB_STS_XFER_IN_PROG 4 506 507 /* TRB Control */ 508 #define DWC3_TRB_CTRL_HWO (1 << 0) 509 #define DWC3_TRB_CTRL_LST (1 << 1) 510 #define DWC3_TRB_CTRL_CHN (1 << 2) 511 #define DWC3_TRB_CTRL_CSP (1 << 3) 512 #define DWC3_TRB_CTRL_TRBCTL(n) (((n) & 0x3f) << 4) 513 #define DWC3_TRB_CTRL_ISP_IMI (1 << 10) 514 #define DWC3_TRB_CTRL_IOC (1 << 11) 515 #define DWC3_TRB_CTRL_SID_SOFN(n) (((n) & 0xffff) << 14) 516 517 #define DWC3_TRBCTL_NORMAL DWC3_TRB_CTRL_TRBCTL(1) 518 #define DWC3_TRBCTL_CONTROL_SETUP DWC3_TRB_CTRL_TRBCTL(2) 519 #define DWC3_TRBCTL_CONTROL_STATUS2 DWC3_TRB_CTRL_TRBCTL(3) 520 #define DWC3_TRBCTL_CONTROL_STATUS3 DWC3_TRB_CTRL_TRBCTL(4) 521 #define DWC3_TRBCTL_CONTROL_DATA DWC3_TRB_CTRL_TRBCTL(5) 522 #define DWC3_TRBCTL_ISOCHRONOUS_FIRST DWC3_TRB_CTRL_TRBCTL(6) 523 #define DWC3_TRBCTL_ISOCHRONOUS DWC3_TRB_CTRL_TRBCTL(7) 524 #define DWC3_TRBCTL_LINK_TRB DWC3_TRB_CTRL_TRBCTL(8) 525 526 /** 527 * struct dwc3_trb - transfer request block (hw format) 528 * @bpl: DW0-3 529 * @bph: DW4-7 530 * @size: DW8-B 531 * @trl: DWC-F 532 */ 533 struct dwc3_trb { 534 u32 bpl; 535 u32 bph; 536 u32 size; 537 u32 ctrl; 538 } __packed; 539 540 /** 541 * dwc3_hwparams - copy of HWPARAMS registers 542 * @hwparams0 - GHWPARAMS0 543 * @hwparams1 - GHWPARAMS1 544 * @hwparams2 - GHWPARAMS2 545 * @hwparams3 - GHWPARAMS3 546 * @hwparams4 - GHWPARAMS4 547 * @hwparams5 - GHWPARAMS5 548 * @hwparams6 - GHWPARAMS6 549 * @hwparams7 - GHWPARAMS7 550 * @hwparams8 - GHWPARAMS8 551 */ 552 struct dwc3_hwparams { 553 u32 hwparams0; 554 u32 hwparams1; 555 u32 hwparams2; 556 u32 hwparams3; 557 u32 hwparams4; 558 u32 hwparams5; 559 u32 hwparams6; 560 u32 hwparams7; 561 u32 hwparams8; 562 }; 563 564 /* HWPARAMS0 */ 565 #define DWC3_MODE(n) ((n) & 0x7) 566 567 #define DWC3_MODE_DEVICE 0 568 #define DWC3_MODE_HOST 1 569 #define DWC3_MODE_DRD 2 570 #define DWC3_MODE_HUB 3 571 572 #define DWC3_MDWIDTH(n) (((n) & 0xff00) >> 8) 573 574 /* HWPARAMS1 */ 575 #define DWC3_NUM_INT(n) (((n) & (0x3f << 15)) >> 15) 576 577 /* HWPARAMS7 */ 578 #define DWC3_RAM1_DEPTH(n) ((n) & 0xffff) 579 580 struct dwc3_request { 581 struct usb_request request; 582 struct list_head list; 583 struct dwc3_ep *dep; 584 u32 start_slot; 585 586 u8 epnum; 587 struct dwc3_trb *trb; 588 dma_addr_t trb_dma; 589 590 unsigned direction:1; 591 unsigned mapped:1; 592 unsigned queued:1; 593 }; 594 595 /* 596 * struct dwc3_scratchpad_array - hibernation scratchpad array 597 * (format defined by hw) 598 */ 599 struct dwc3_scratchpad_array { 600 __le64 dma_adr[DWC3_MAX_HIBER_SCRATCHBUFS]; 601 }; 602 603 /** 604 * struct dwc3 - representation of our controller 605 * @ctrl_req: usb control request which is used for ep0 606 * @ep0_trb: trb which is used for the ctrl_req 607 * @ep0_bounce: bounce buffer for ep0 608 * @setup_buf: used while precessing STD USB requests 609 * @ctrl_req_addr: dma address of ctrl_req 610 * @ep0_trb: dma address of ep0_trb 611 * @ep0_usb_req: dummy req used while handling STD USB requests 612 * @ep0_bounce_addr: dma address of ep0_bounce 613 * @lock: for synchronizing 614 * @dev: pointer to our struct device 615 * @xhci: pointer to our xHCI child 616 * @event_buffer_list: a list of event buffers 617 * @gadget: device side representation of the peripheral controller 618 * @gadget_driver: pointer to the gadget driver 619 * @regs: base address for our registers 620 * @regs_size: address space size 621 * @irq: IRQ number 622 * @num_event_buffers: calculated number of event buffers 623 * @u1u2: only used on revisions <1.83a for workaround 624 * @maximum_speed: maximum speed requested (mainly for testing purposes) 625 * @revision: revision register contents 626 * @mode: mode of operation 627 * @usb2_phy: pointer to USB2 PHY 628 * @usb3_phy: pointer to USB3 PHY 629 * @is_selfpowered: true when we are selfpowered 630 * @three_stage_setup: set if we perform a three phase setup 631 * @ep0_bounced: true when we used bounce buffer 632 * @ep0_expect_in: true when we expect a DATA IN transfer 633 * @start_config_issued: true when StartConfig command has been issued 634 * @setup_packet_pending: true when there's a Setup Packet in FIFO. Workaround 635 * @needs_fifo_resize: not all users might want fifo resizing, flag it 636 * @resize_fifos: tells us it's ok to reconfigure our TxFIFO sizes. 637 * @isoch_delay: wValue from Set Isochronous Delay request; 638 * @u2sel: parameter from Set SEL request. 639 * @u2pel: parameter from Set SEL request. 640 * @u1sel: parameter from Set SEL request. 641 * @u1pel: parameter from Set SEL request. 642 * @ep0_next_event: hold the next expected event 643 * @ep0state: state of endpoint zero 644 * @link_state: link state 645 * @speed: device speed (super, high, full, low) 646 * @mem: points to start of memory which is used for this struct. 647 * @hwparams: copy of hwparams registers 648 * @root: debugfs root folder pointer 649 */ 650 struct dwc3 { 651 struct usb_ctrlrequest *ctrl_req; 652 struct dwc3_trb *ep0_trb; 653 void *ep0_bounce; 654 u8 *setup_buf; 655 dma_addr_t ctrl_req_addr; 656 dma_addr_t ep0_trb_addr; 657 dma_addr_t ep0_bounce_addr; 658 struct dwc3_request ep0_usb_req; 659 /* device lock */ 660 spinlock_t lock; 661 struct device *dev; 662 663 struct platform_device *xhci; 664 struct resource xhci_resources[DWC3_XHCI_RESOURCES_NUM]; 665 666 struct dwc3_event_buffer **ev_buffs; 667 struct dwc3_ep *eps[DWC3_ENDPOINTS_NUM]; 668 669 struct usb_gadget gadget; 670 struct usb_gadget_driver *gadget_driver; 671 672 struct usb_phy *usb2_phy; 673 struct usb_phy *usb3_phy; 674 675 void __iomem *regs; 676 size_t regs_size; 677 678 u32 num_event_buffers; 679 u32 u1u2; 680 u32 maximum_speed; 681 u32 revision; 682 u32 mode; 683 684 #define DWC3_REVISION_173A 0x5533173a 685 #define DWC3_REVISION_175A 0x5533175a 686 #define DWC3_REVISION_180A 0x5533180a 687 #define DWC3_REVISION_183A 0x5533183a 688 #define DWC3_REVISION_185A 0x5533185a 689 #define DWC3_REVISION_187A 0x5533187a 690 #define DWC3_REVISION_188A 0x5533188a 691 #define DWC3_REVISION_190A 0x5533190a 692 #define DWC3_REVISION_194A 0x5533194a 693 #define DWC3_REVISION_200A 0x5533200a 694 #define DWC3_REVISION_202A 0x5533202a 695 #define DWC3_REVISION_210A 0x5533210a 696 #define DWC3_REVISION_220A 0x5533220a 697 698 unsigned is_selfpowered:1; 699 unsigned three_stage_setup:1; 700 unsigned ep0_bounced:1; 701 unsigned ep0_expect_in:1; 702 unsigned start_config_issued:1; 703 unsigned setup_packet_pending:1; 704 unsigned delayed_status:1; 705 unsigned needs_fifo_resize:1; 706 unsigned resize_fifos:1; 707 708 enum dwc3_ep0_next ep0_next_event; 709 enum dwc3_ep0_state ep0state; 710 enum dwc3_link_state link_state; 711 enum dwc3_device_state dev_state; 712 713 u16 isoch_delay; 714 u16 u2sel; 715 u16 u2pel; 716 u8 u1sel; 717 u8 u1pel; 718 719 u8 speed; 720 721 void *mem; 722 723 struct dwc3_hwparams hwparams; 724 struct dentry *root; 725 struct debugfs_regset32 *regset; 726 727 u8 test_mode; 728 u8 test_mode_nr; 729 }; 730 731 /* -------------------------------------------------------------------------- */ 732 733 /* -------------------------------------------------------------------------- */ 734 735 struct dwc3_event_type { 736 u32 is_devspec:1; 737 u32 type:6; 738 u32 reserved8_31:25; 739 } __packed; 740 741 #define DWC3_DEPEVT_XFERCOMPLETE 0x01 742 #define DWC3_DEPEVT_XFERINPROGRESS 0x02 743 #define DWC3_DEPEVT_XFERNOTREADY 0x03 744 #define DWC3_DEPEVT_RXTXFIFOEVT 0x04 745 #define DWC3_DEPEVT_STREAMEVT 0x06 746 #define DWC3_DEPEVT_EPCMDCMPLT 0x07 747 748 /** 749 * struct dwc3_event_depvt - Device Endpoint Events 750 * @one_bit: indicates this is an endpoint event (not used) 751 * @endpoint_number: number of the endpoint 752 * @endpoint_event: The event we have: 753 * 0x00 - Reserved 754 * 0x01 - XferComplete 755 * 0x02 - XferInProgress 756 * 0x03 - XferNotReady 757 * 0x04 - RxTxFifoEvt (IN->Underrun, OUT->Overrun) 758 * 0x05 - Reserved 759 * 0x06 - StreamEvt 760 * 0x07 - EPCmdCmplt 761 * @reserved11_10: Reserved, don't use. 762 * @status: Indicates the status of the event. Refer to databook for 763 * more information. 764 * @parameters: Parameters of the current event. Refer to databook for 765 * more information. 766 */ 767 struct dwc3_event_depevt { 768 u32 one_bit:1; 769 u32 endpoint_number:5; 770 u32 endpoint_event:4; 771 u32 reserved11_10:2; 772 u32 status:4; 773 774 /* Within XferNotReady */ 775 #define DEPEVT_STATUS_TRANSFER_ACTIVE (1 << 3) 776 777 /* Within XferComplete */ 778 #define DEPEVT_STATUS_BUSERR (1 << 0) 779 #define DEPEVT_STATUS_SHORT (1 << 1) 780 #define DEPEVT_STATUS_IOC (1 << 2) 781 #define DEPEVT_STATUS_LST (1 << 3) 782 783 /* Stream event only */ 784 #define DEPEVT_STREAMEVT_FOUND 1 785 #define DEPEVT_STREAMEVT_NOTFOUND 2 786 787 /* Control-only Status */ 788 #define DEPEVT_STATUS_CONTROL_DATA 1 789 #define DEPEVT_STATUS_CONTROL_STATUS 2 790 791 u32 parameters:16; 792 } __packed; 793 794 /** 795 * struct dwc3_event_devt - Device Events 796 * @one_bit: indicates this is a non-endpoint event (not used) 797 * @device_event: indicates it's a device event. Should read as 0x00 798 * @type: indicates the type of device event. 799 * 0 - DisconnEvt 800 * 1 - USBRst 801 * 2 - ConnectDone 802 * 3 - ULStChng 803 * 4 - WkUpEvt 804 * 5 - Reserved 805 * 6 - EOPF 806 * 7 - SOF 807 * 8 - Reserved 808 * 9 - ErrticErr 809 * 10 - CmdCmplt 810 * 11 - EvntOverflow 811 * 12 - VndrDevTstRcved 812 * @reserved15_12: Reserved, not used 813 * @event_info: Information about this event 814 * @reserved31_24: Reserved, not used 815 */ 816 struct dwc3_event_devt { 817 u32 one_bit:1; 818 u32 device_event:7; 819 u32 type:4; 820 u32 reserved15_12:4; 821 u32 event_info:8; 822 u32 reserved31_24:8; 823 } __packed; 824 825 /** 826 * struct dwc3_event_gevt - Other Core Events 827 * @one_bit: indicates this is a non-endpoint event (not used) 828 * @device_event: indicates it's (0x03) Carkit or (0x04) I2C event. 829 * @phy_port_number: self-explanatory 830 * @reserved31_12: Reserved, not used. 831 */ 832 struct dwc3_event_gevt { 833 u32 one_bit:1; 834 u32 device_event:7; 835 u32 phy_port_number:4; 836 u32 reserved31_12:20; 837 } __packed; 838 839 /** 840 * union dwc3_event - representation of Event Buffer contents 841 * @raw: raw 32-bit event 842 * @type: the type of the event 843 * @depevt: Device Endpoint Event 844 * @devt: Device Event 845 * @gevt: Global Event 846 */ 847 union dwc3_event { 848 u32 raw; 849 struct dwc3_event_type type; 850 struct dwc3_event_depevt depevt; 851 struct dwc3_event_devt devt; 852 struct dwc3_event_gevt gevt; 853 }; 854 855 /* 856 * DWC3 Features to be used as Driver Data 857 */ 858 859 #define DWC3_HAS_PERIPHERAL BIT(0) 860 #define DWC3_HAS_XHCI BIT(1) 861 #define DWC3_HAS_OTG BIT(3) 862 863 /* prototypes */ 864 void dwc3_set_mode(struct dwc3 *dwc, u32 mode); 865 int dwc3_gadget_resize_tx_fifos(struct dwc3 *dwc); 866 867 #if IS_ENABLED(CONFIG_USB_DWC3_HOST) || IS_ENABLED(CONFIG_USB_DWC3_DUAL_ROLE) 868 int dwc3_host_init(struct dwc3 *dwc); 869 void dwc3_host_exit(struct dwc3 *dwc); 870 #else 871 static inline int dwc3_host_init(struct dwc3 *dwc) 872 { return 0; } 873 static inline void dwc3_host_exit(struct dwc3 *dwc) 874 { } 875 #endif 876 877 #if IS_ENABLED(CONFIG_USB_DWC3_GADGET) || IS_ENABLED(CONFIG_USB_DWC3_DUAL_ROLE) 878 int dwc3_gadget_init(struct dwc3 *dwc); 879 void dwc3_gadget_exit(struct dwc3 *dwc); 880 #else 881 static inline int dwc3_gadget_init(struct dwc3 *dwc) 882 { return 0; } 883 static inline void dwc3_gadget_exit(struct dwc3 *dwc) 884 { } 885 #endif 886 887 #endif /* __DRIVERS_USB_DWC3_CORE_H */ 888