1 /** 2 * core.h - DesignWare USB3 DRD Core Header 3 * 4 * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com 5 * 6 * Authors: Felipe Balbi <balbi@ti.com>, 7 * Sebastian Andrzej Siewior <bigeasy@linutronix.de> 8 * 9 * This program is free software: you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License version 2 of 11 * the License as published by the Free Software Foundation. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 */ 18 19 #ifndef __DRIVERS_USB_DWC3_CORE_H 20 #define __DRIVERS_USB_DWC3_CORE_H 21 22 #include <linux/device.h> 23 #include <linux/spinlock.h> 24 #include <linux/ioport.h> 25 #include <linux/list.h> 26 #include <linux/dma-mapping.h> 27 #include <linux/mm.h> 28 #include <linux/debugfs.h> 29 30 #include <linux/usb/ch9.h> 31 #include <linux/usb/gadget.h> 32 #include <linux/usb/otg.h> 33 #include <linux/ulpi/interface.h> 34 35 #include <linux/phy/phy.h> 36 37 #define DWC3_MSG_MAX 500 38 39 /* Global constants */ 40 #define DWC3_ZLP_BUF_SIZE 1024 /* size of a superspeed bulk */ 41 #define DWC3_EP0_BOUNCE_SIZE 512 42 #define DWC3_ENDPOINTS_NUM 32 43 #define DWC3_XHCI_RESOURCES_NUM 2 44 45 #define DWC3_SCRATCHBUF_SIZE 4096 /* each buffer is assumed to be 4KiB */ 46 #define DWC3_EVENT_SIZE 4 /* bytes */ 47 #define DWC3_EVENT_MAX_NUM 64 /* 2 events/endpoint */ 48 #define DWC3_EVENT_BUFFERS_SIZE (DWC3_EVENT_SIZE * DWC3_EVENT_MAX_NUM) 49 #define DWC3_EVENT_TYPE_MASK 0xfe 50 51 #define DWC3_EVENT_TYPE_DEV 0 52 #define DWC3_EVENT_TYPE_CARKIT 3 53 #define DWC3_EVENT_TYPE_I2C 4 54 55 #define DWC3_DEVICE_EVENT_DISCONNECT 0 56 #define DWC3_DEVICE_EVENT_RESET 1 57 #define DWC3_DEVICE_EVENT_CONNECT_DONE 2 58 #define DWC3_DEVICE_EVENT_LINK_STATUS_CHANGE 3 59 #define DWC3_DEVICE_EVENT_WAKEUP 4 60 #define DWC3_DEVICE_EVENT_HIBER_REQ 5 61 #define DWC3_DEVICE_EVENT_EOPF 6 62 #define DWC3_DEVICE_EVENT_SOF 7 63 #define DWC3_DEVICE_EVENT_ERRATIC_ERROR 9 64 #define DWC3_DEVICE_EVENT_CMD_CMPL 10 65 #define DWC3_DEVICE_EVENT_OVERFLOW 11 66 67 #define DWC3_GEVNTCOUNT_MASK 0xfffc 68 #define DWC3_GSNPSID_MASK 0xffff0000 69 #define DWC3_GSNPSREV_MASK 0xffff 70 71 /* DWC3 registers memory space boundries */ 72 #define DWC3_XHCI_REGS_START 0x0 73 #define DWC3_XHCI_REGS_END 0x7fff 74 #define DWC3_GLOBALS_REGS_START 0xc100 75 #define DWC3_GLOBALS_REGS_END 0xc6ff 76 #define DWC3_DEVICE_REGS_START 0xc700 77 #define DWC3_DEVICE_REGS_END 0xcbff 78 #define DWC3_OTG_REGS_START 0xcc00 79 #define DWC3_OTG_REGS_END 0xccff 80 81 /* Global Registers */ 82 #define DWC3_GSBUSCFG0 0xc100 83 #define DWC3_GSBUSCFG1 0xc104 84 #define DWC3_GTXTHRCFG 0xc108 85 #define DWC3_GRXTHRCFG 0xc10c 86 #define DWC3_GCTL 0xc110 87 #define DWC3_GEVTEN 0xc114 88 #define DWC3_GSTS 0xc118 89 #define DWC3_GSNPSID 0xc120 90 #define DWC3_GGPIO 0xc124 91 #define DWC3_GUID 0xc128 92 #define DWC3_GUCTL 0xc12c 93 #define DWC3_GBUSERRADDR0 0xc130 94 #define DWC3_GBUSERRADDR1 0xc134 95 #define DWC3_GPRTBIMAP0 0xc138 96 #define DWC3_GPRTBIMAP1 0xc13c 97 #define DWC3_GHWPARAMS0 0xc140 98 #define DWC3_GHWPARAMS1 0xc144 99 #define DWC3_GHWPARAMS2 0xc148 100 #define DWC3_GHWPARAMS3 0xc14c 101 #define DWC3_GHWPARAMS4 0xc150 102 #define DWC3_GHWPARAMS5 0xc154 103 #define DWC3_GHWPARAMS6 0xc158 104 #define DWC3_GHWPARAMS7 0xc15c 105 #define DWC3_GDBGFIFOSPACE 0xc160 106 #define DWC3_GDBGLTSSM 0xc164 107 #define DWC3_GPRTBIMAP_HS0 0xc180 108 #define DWC3_GPRTBIMAP_HS1 0xc184 109 #define DWC3_GPRTBIMAP_FS0 0xc188 110 #define DWC3_GPRTBIMAP_FS1 0xc18c 111 112 #define DWC3_VER_NUMBER 0xc1a0 113 #define DWC3_VER_TYPE 0xc1a4 114 115 #define DWC3_GUSB2PHYCFG(n) (0xc200 + (n * 0x04)) 116 #define DWC3_GUSB2I2CCTL(n) (0xc240 + (n * 0x04)) 117 118 #define DWC3_GUSB2PHYACC(n) (0xc280 + (n * 0x04)) 119 120 #define DWC3_GUSB3PIPECTL(n) (0xc2c0 + (n * 0x04)) 121 122 #define DWC3_GTXFIFOSIZ(n) (0xc300 + (n * 0x04)) 123 #define DWC3_GRXFIFOSIZ(n) (0xc380 + (n * 0x04)) 124 125 #define DWC3_GEVNTADRLO(n) (0xc400 + (n * 0x10)) 126 #define DWC3_GEVNTADRHI(n) (0xc404 + (n * 0x10)) 127 #define DWC3_GEVNTSIZ(n) (0xc408 + (n * 0x10)) 128 #define DWC3_GEVNTCOUNT(n) (0xc40c + (n * 0x10)) 129 130 #define DWC3_GHWPARAMS8 0xc600 131 #define DWC3_GFLADJ 0xc630 132 133 /* Device Registers */ 134 #define DWC3_DCFG 0xc700 135 #define DWC3_DCTL 0xc704 136 #define DWC3_DEVTEN 0xc708 137 #define DWC3_DSTS 0xc70c 138 #define DWC3_DGCMDPAR 0xc710 139 #define DWC3_DGCMD 0xc714 140 #define DWC3_DALEPENA 0xc720 141 #define DWC3_DEPCMDPAR2(n) (0xc800 + (n * 0x10)) 142 #define DWC3_DEPCMDPAR1(n) (0xc804 + (n * 0x10)) 143 #define DWC3_DEPCMDPAR0(n) (0xc808 + (n * 0x10)) 144 #define DWC3_DEPCMD(n) (0xc80c + (n * 0x10)) 145 146 /* OTG Registers */ 147 #define DWC3_OCFG 0xcc00 148 #define DWC3_OCTL 0xcc04 149 #define DWC3_OEVT 0xcc08 150 #define DWC3_OEVTEN 0xcc0C 151 #define DWC3_OSTS 0xcc10 152 153 /* Bit fields */ 154 155 /* Global Debug Queue/FIFO Space Available Register */ 156 #define DWC3_GDBGFIFOSPACE_NUM(n) ((n) & 0x1f) 157 #define DWC3_GDBGFIFOSPACE_TYPE(n) (((n) << 5) & 0x1e0) 158 #define DWC3_GDBGFIFOSPACE_SPACE_AVAILABLE(n) (((n) >> 16) & 0xffff) 159 160 #define DWC3_TXFIFOQ 1 161 #define DWC3_RXFIFOQ 3 162 #define DWC3_TXREQQ 5 163 #define DWC3_RXREQQ 7 164 #define DWC3_RXINFOQ 9 165 #define DWC3_DESCFETCHQ 13 166 #define DWC3_EVENTQ 15 167 168 /* Global RX Threshold Configuration Register */ 169 #define DWC3_GRXTHRCFG_MAXRXBURSTSIZE(n) (((n) & 0x1f) << 19) 170 #define DWC3_GRXTHRCFG_RXPKTCNT(n) (((n) & 0xf) << 24) 171 #define DWC3_GRXTHRCFG_PKTCNTSEL (1 << 29) 172 173 /* Global Configuration Register */ 174 #define DWC3_GCTL_PWRDNSCALE(n) ((n) << 19) 175 #define DWC3_GCTL_U2RSTECN (1 << 16) 176 #define DWC3_GCTL_RAMCLKSEL(x) (((x) & DWC3_GCTL_CLK_MASK) << 6) 177 #define DWC3_GCTL_CLK_BUS (0) 178 #define DWC3_GCTL_CLK_PIPE (1) 179 #define DWC3_GCTL_CLK_PIPEHALF (2) 180 #define DWC3_GCTL_CLK_MASK (3) 181 182 #define DWC3_GCTL_PRTCAP(n) (((n) & (3 << 12)) >> 12) 183 #define DWC3_GCTL_PRTCAPDIR(n) ((n) << 12) 184 #define DWC3_GCTL_PRTCAP_HOST 1 185 #define DWC3_GCTL_PRTCAP_DEVICE 2 186 #define DWC3_GCTL_PRTCAP_OTG 3 187 188 #define DWC3_GCTL_CORESOFTRESET (1 << 11) 189 #define DWC3_GCTL_SOFITPSYNC (1 << 10) 190 #define DWC3_GCTL_SCALEDOWN(n) ((n) << 4) 191 #define DWC3_GCTL_SCALEDOWN_MASK DWC3_GCTL_SCALEDOWN(3) 192 #define DWC3_GCTL_DISSCRAMBLE (1 << 3) 193 #define DWC3_GCTL_U2EXIT_LFPS (1 << 2) 194 #define DWC3_GCTL_GBLHIBERNATIONEN (1 << 1) 195 #define DWC3_GCTL_DSBLCLKGTNG (1 << 0) 196 197 /* Global USB2 PHY Configuration Register */ 198 #define DWC3_GUSB2PHYCFG_PHYSOFTRST (1 << 31) 199 #define DWC3_GUSB2PHYCFG_SUSPHY (1 << 6) 200 #define DWC3_GUSB2PHYCFG_ULPI_UTMI (1 << 4) 201 #define DWC3_GUSB2PHYCFG_ENBLSLPM (1 << 8) 202 203 /* Global USB2 PHY Vendor Control Register */ 204 #define DWC3_GUSB2PHYACC_NEWREGREQ (1 << 25) 205 #define DWC3_GUSB2PHYACC_BUSY (1 << 23) 206 #define DWC3_GUSB2PHYACC_WRITE (1 << 22) 207 #define DWC3_GUSB2PHYACC_ADDR(n) (n << 16) 208 #define DWC3_GUSB2PHYACC_EXTEND_ADDR(n) (n << 8) 209 #define DWC3_GUSB2PHYACC_DATA(n) (n & 0xff) 210 211 /* Global USB3 PIPE Control Register */ 212 #define DWC3_GUSB3PIPECTL_PHYSOFTRST (1 << 31) 213 #define DWC3_GUSB3PIPECTL_U2SSINP3OK (1 << 29) 214 #define DWC3_GUSB3PIPECTL_DISRXDETINP3 (1 << 28) 215 #define DWC3_GUSB3PIPECTL_REQP1P2P3 (1 << 24) 216 #define DWC3_GUSB3PIPECTL_DEP1P2P3(n) ((n) << 19) 217 #define DWC3_GUSB3PIPECTL_DEP1P2P3_MASK DWC3_GUSB3PIPECTL_DEP1P2P3(7) 218 #define DWC3_GUSB3PIPECTL_DEP1P2P3_EN DWC3_GUSB3PIPECTL_DEP1P2P3(1) 219 #define DWC3_GUSB3PIPECTL_DEPOCHANGE (1 << 18) 220 #define DWC3_GUSB3PIPECTL_SUSPHY (1 << 17) 221 #define DWC3_GUSB3PIPECTL_LFPSFILT (1 << 9) 222 #define DWC3_GUSB3PIPECTL_RX_DETOPOLL (1 << 8) 223 #define DWC3_GUSB3PIPECTL_TX_DEEPH_MASK DWC3_GUSB3PIPECTL_TX_DEEPH(3) 224 #define DWC3_GUSB3PIPECTL_TX_DEEPH(n) ((n) << 1) 225 226 /* Global TX Fifo Size Register */ 227 #define DWC3_GTXFIFOSIZ_TXFDEF(n) ((n) & 0xffff) 228 #define DWC3_GTXFIFOSIZ_TXFSTADDR(n) ((n) & 0xffff0000) 229 230 /* Global Event Size Registers */ 231 #define DWC3_GEVNTSIZ_INTMASK (1 << 31) 232 #define DWC3_GEVNTSIZ_SIZE(n) ((n) & 0xffff) 233 234 /* Global HWPARAMS1 Register */ 235 #define DWC3_GHWPARAMS1_EN_PWROPT(n) (((n) & (3 << 24)) >> 24) 236 #define DWC3_GHWPARAMS1_EN_PWROPT_NO 0 237 #define DWC3_GHWPARAMS1_EN_PWROPT_CLK 1 238 #define DWC3_GHWPARAMS1_EN_PWROPT_HIB 2 239 #define DWC3_GHWPARAMS1_PWROPT(n) ((n) << 24) 240 #define DWC3_GHWPARAMS1_PWROPT_MASK DWC3_GHWPARAMS1_PWROPT(3) 241 242 /* Global HWPARAMS3 Register */ 243 #define DWC3_GHWPARAMS3_SSPHY_IFC(n) ((n) & 3) 244 #define DWC3_GHWPARAMS3_SSPHY_IFC_DIS 0 245 #define DWC3_GHWPARAMS3_SSPHY_IFC_GEN1 1 246 #define DWC3_GHWPARAMS3_SSPHY_IFC_GEN2 2 /* DWC_usb31 only */ 247 #define DWC3_GHWPARAMS3_HSPHY_IFC(n) (((n) & (3 << 2)) >> 2) 248 #define DWC3_GHWPARAMS3_HSPHY_IFC_DIS 0 249 #define DWC3_GHWPARAMS3_HSPHY_IFC_UTMI 1 250 #define DWC3_GHWPARAMS3_HSPHY_IFC_ULPI 2 251 #define DWC3_GHWPARAMS3_HSPHY_IFC_UTMI_ULPI 3 252 #define DWC3_GHWPARAMS3_FSPHY_IFC(n) (((n) & (3 << 4)) >> 4) 253 #define DWC3_GHWPARAMS3_FSPHY_IFC_DIS 0 254 #define DWC3_GHWPARAMS3_FSPHY_IFC_ENA 1 255 256 /* Global HWPARAMS4 Register */ 257 #define DWC3_GHWPARAMS4_HIBER_SCRATCHBUFS(n) (((n) & (0x0f << 13)) >> 13) 258 #define DWC3_MAX_HIBER_SCRATCHBUFS 15 259 260 /* Global HWPARAMS6 Register */ 261 #define DWC3_GHWPARAMS6_EN_FPGA (1 << 7) 262 263 /* Global Frame Length Adjustment Register */ 264 #define DWC3_GFLADJ_30MHZ_SDBND_SEL (1 << 7) 265 #define DWC3_GFLADJ_30MHZ_MASK 0x3f 266 267 /* Device Configuration Register */ 268 #define DWC3_DCFG_DEVADDR(addr) ((addr) << 3) 269 #define DWC3_DCFG_DEVADDR_MASK DWC3_DCFG_DEVADDR(0x7f) 270 271 #define DWC3_DCFG_SPEED_MASK (7 << 0) 272 #define DWC3_DCFG_SUPERSPEED_PLUS (5 << 0) /* DWC_usb31 only */ 273 #define DWC3_DCFG_SUPERSPEED (4 << 0) 274 #define DWC3_DCFG_HIGHSPEED (0 << 0) 275 #define DWC3_DCFG_FULLSPEED2 (1 << 0) 276 #define DWC3_DCFG_LOWSPEED (2 << 0) 277 #define DWC3_DCFG_FULLSPEED1 (3 << 0) 278 279 #define DWC3_DCFG_NUMP_SHIFT 17 280 #define DWC3_DCFG_NUMP(n) (((n) >> DWC3_DCFG_NUMP_SHIFT) & 0x1f) 281 #define DWC3_DCFG_NUMP_MASK (0x1f << DWC3_DCFG_NUMP_SHIFT) 282 #define DWC3_DCFG_LPM_CAP (1 << 22) 283 284 /* Device Control Register */ 285 #define DWC3_DCTL_RUN_STOP (1 << 31) 286 #define DWC3_DCTL_CSFTRST (1 << 30) 287 #define DWC3_DCTL_LSFTRST (1 << 29) 288 289 #define DWC3_DCTL_HIRD_THRES_MASK (0x1f << 24) 290 #define DWC3_DCTL_HIRD_THRES(n) ((n) << 24) 291 292 #define DWC3_DCTL_APPL1RES (1 << 23) 293 294 /* These apply for core versions 1.87a and earlier */ 295 #define DWC3_DCTL_TRGTULST_MASK (0x0f << 17) 296 #define DWC3_DCTL_TRGTULST(n) ((n) << 17) 297 #define DWC3_DCTL_TRGTULST_U2 (DWC3_DCTL_TRGTULST(2)) 298 #define DWC3_DCTL_TRGTULST_U3 (DWC3_DCTL_TRGTULST(3)) 299 #define DWC3_DCTL_TRGTULST_SS_DIS (DWC3_DCTL_TRGTULST(4)) 300 #define DWC3_DCTL_TRGTULST_RX_DET (DWC3_DCTL_TRGTULST(5)) 301 #define DWC3_DCTL_TRGTULST_SS_INACT (DWC3_DCTL_TRGTULST(6)) 302 303 /* These apply for core versions 1.94a and later */ 304 #define DWC3_DCTL_LPM_ERRATA_MASK DWC3_DCTL_LPM_ERRATA(0xf) 305 #define DWC3_DCTL_LPM_ERRATA(n) ((n) << 20) 306 307 #define DWC3_DCTL_KEEP_CONNECT (1 << 19) 308 #define DWC3_DCTL_L1_HIBER_EN (1 << 18) 309 #define DWC3_DCTL_CRS (1 << 17) 310 #define DWC3_DCTL_CSS (1 << 16) 311 312 #define DWC3_DCTL_INITU2ENA (1 << 12) 313 #define DWC3_DCTL_ACCEPTU2ENA (1 << 11) 314 #define DWC3_DCTL_INITU1ENA (1 << 10) 315 #define DWC3_DCTL_ACCEPTU1ENA (1 << 9) 316 #define DWC3_DCTL_TSTCTRL_MASK (0xf << 1) 317 318 #define DWC3_DCTL_ULSTCHNGREQ_MASK (0x0f << 5) 319 #define DWC3_DCTL_ULSTCHNGREQ(n) (((n) << 5) & DWC3_DCTL_ULSTCHNGREQ_MASK) 320 321 #define DWC3_DCTL_ULSTCHNG_NO_ACTION (DWC3_DCTL_ULSTCHNGREQ(0)) 322 #define DWC3_DCTL_ULSTCHNG_SS_DISABLED (DWC3_DCTL_ULSTCHNGREQ(4)) 323 #define DWC3_DCTL_ULSTCHNG_RX_DETECT (DWC3_DCTL_ULSTCHNGREQ(5)) 324 #define DWC3_DCTL_ULSTCHNG_SS_INACTIVE (DWC3_DCTL_ULSTCHNGREQ(6)) 325 #define DWC3_DCTL_ULSTCHNG_RECOVERY (DWC3_DCTL_ULSTCHNGREQ(8)) 326 #define DWC3_DCTL_ULSTCHNG_COMPLIANCE (DWC3_DCTL_ULSTCHNGREQ(10)) 327 #define DWC3_DCTL_ULSTCHNG_LOOPBACK (DWC3_DCTL_ULSTCHNGREQ(11)) 328 329 /* Device Event Enable Register */ 330 #define DWC3_DEVTEN_VNDRDEVTSTRCVEDEN (1 << 12) 331 #define DWC3_DEVTEN_EVNTOVERFLOWEN (1 << 11) 332 #define DWC3_DEVTEN_CMDCMPLTEN (1 << 10) 333 #define DWC3_DEVTEN_ERRTICERREN (1 << 9) 334 #define DWC3_DEVTEN_SOFEN (1 << 7) 335 #define DWC3_DEVTEN_EOPFEN (1 << 6) 336 #define DWC3_DEVTEN_HIBERNATIONREQEVTEN (1 << 5) 337 #define DWC3_DEVTEN_WKUPEVTEN (1 << 4) 338 #define DWC3_DEVTEN_ULSTCNGEN (1 << 3) 339 #define DWC3_DEVTEN_CONNECTDONEEN (1 << 2) 340 #define DWC3_DEVTEN_USBRSTEN (1 << 1) 341 #define DWC3_DEVTEN_DISCONNEVTEN (1 << 0) 342 343 /* Device Status Register */ 344 #define DWC3_DSTS_DCNRD (1 << 29) 345 346 /* This applies for core versions 1.87a and earlier */ 347 #define DWC3_DSTS_PWRUPREQ (1 << 24) 348 349 /* These apply for core versions 1.94a and later */ 350 #define DWC3_DSTS_RSS (1 << 25) 351 #define DWC3_DSTS_SSS (1 << 24) 352 353 #define DWC3_DSTS_COREIDLE (1 << 23) 354 #define DWC3_DSTS_DEVCTRLHLT (1 << 22) 355 356 #define DWC3_DSTS_USBLNKST_MASK (0x0f << 18) 357 #define DWC3_DSTS_USBLNKST(n) (((n) & DWC3_DSTS_USBLNKST_MASK) >> 18) 358 359 #define DWC3_DSTS_RXFIFOEMPTY (1 << 17) 360 361 #define DWC3_DSTS_SOFFN_MASK (0x3fff << 3) 362 #define DWC3_DSTS_SOFFN(n) (((n) & DWC3_DSTS_SOFFN_MASK) >> 3) 363 364 #define DWC3_DSTS_CONNECTSPD (7 << 0) 365 366 #define DWC3_DSTS_SUPERSPEED_PLUS (5 << 0) /* DWC_usb31 only */ 367 #define DWC3_DSTS_SUPERSPEED (4 << 0) 368 #define DWC3_DSTS_HIGHSPEED (0 << 0) 369 #define DWC3_DSTS_FULLSPEED2 (1 << 0) 370 #define DWC3_DSTS_LOWSPEED (2 << 0) 371 #define DWC3_DSTS_FULLSPEED1 (3 << 0) 372 373 /* Device Generic Command Register */ 374 #define DWC3_DGCMD_SET_LMP 0x01 375 #define DWC3_DGCMD_SET_PERIODIC_PAR 0x02 376 #define DWC3_DGCMD_XMIT_FUNCTION 0x03 377 378 /* These apply for core versions 1.94a and later */ 379 #define DWC3_DGCMD_SET_SCRATCHPAD_ADDR_LO 0x04 380 #define DWC3_DGCMD_SET_SCRATCHPAD_ADDR_HI 0x05 381 382 #define DWC3_DGCMD_SELECTED_FIFO_FLUSH 0x09 383 #define DWC3_DGCMD_ALL_FIFO_FLUSH 0x0a 384 #define DWC3_DGCMD_SET_ENDPOINT_NRDY 0x0c 385 #define DWC3_DGCMD_RUN_SOC_BUS_LOOPBACK 0x10 386 387 #define DWC3_DGCMD_STATUS(n) (((n) >> 12) & 0x0F) 388 #define DWC3_DGCMD_CMDACT (1 << 10) 389 #define DWC3_DGCMD_CMDIOC (1 << 8) 390 391 /* Device Generic Command Parameter Register */ 392 #define DWC3_DGCMDPAR_FORCE_LINKPM_ACCEPT (1 << 0) 393 #define DWC3_DGCMDPAR_FIFO_NUM(n) ((n) << 0) 394 #define DWC3_DGCMDPAR_RX_FIFO (0 << 5) 395 #define DWC3_DGCMDPAR_TX_FIFO (1 << 5) 396 #define DWC3_DGCMDPAR_LOOPBACK_DIS (0 << 0) 397 #define DWC3_DGCMDPAR_LOOPBACK_ENA (1 << 0) 398 399 /* Device Endpoint Command Register */ 400 #define DWC3_DEPCMD_PARAM_SHIFT 16 401 #define DWC3_DEPCMD_PARAM(x) ((x) << DWC3_DEPCMD_PARAM_SHIFT) 402 #define DWC3_DEPCMD_GET_RSC_IDX(x) (((x) >> DWC3_DEPCMD_PARAM_SHIFT) & 0x7f) 403 #define DWC3_DEPCMD_STATUS(x) (((x) >> 12) & 0x0F) 404 #define DWC3_DEPCMD_HIPRI_FORCERM (1 << 11) 405 #define DWC3_DEPCMD_CLEARPENDIN (1 << 11) 406 #define DWC3_DEPCMD_CMDACT (1 << 10) 407 #define DWC3_DEPCMD_CMDIOC (1 << 8) 408 409 #define DWC3_DEPCMD_DEPSTARTCFG (0x09 << 0) 410 #define DWC3_DEPCMD_ENDTRANSFER (0x08 << 0) 411 #define DWC3_DEPCMD_UPDATETRANSFER (0x07 << 0) 412 #define DWC3_DEPCMD_STARTTRANSFER (0x06 << 0) 413 #define DWC3_DEPCMD_CLEARSTALL (0x05 << 0) 414 #define DWC3_DEPCMD_SETSTALL (0x04 << 0) 415 /* This applies for core versions 1.90a and earlier */ 416 #define DWC3_DEPCMD_GETSEQNUMBER (0x03 << 0) 417 /* This applies for core versions 1.94a and later */ 418 #define DWC3_DEPCMD_GETEPSTATE (0x03 << 0) 419 #define DWC3_DEPCMD_SETTRANSFRESOURCE (0x02 << 0) 420 #define DWC3_DEPCMD_SETEPCONFIG (0x01 << 0) 421 422 /* The EP number goes 0..31 so ep0 is always out and ep1 is always in */ 423 #define DWC3_DALEPENA_EP(n) (1 << n) 424 425 #define DWC3_DEPCMD_TYPE_CONTROL 0 426 #define DWC3_DEPCMD_TYPE_ISOC 1 427 #define DWC3_DEPCMD_TYPE_BULK 2 428 #define DWC3_DEPCMD_TYPE_INTR 3 429 430 /* Structures */ 431 432 struct dwc3_trb; 433 434 /** 435 * struct dwc3_event_buffer - Software event buffer representation 436 * @buf: _THE_ buffer 437 * @length: size of this buffer 438 * @lpos: event offset 439 * @count: cache of last read event count register 440 * @flags: flags related to this event buffer 441 * @dma: dma_addr_t 442 * @dwc: pointer to DWC controller 443 */ 444 struct dwc3_event_buffer { 445 void *buf; 446 unsigned length; 447 unsigned int lpos; 448 unsigned int count; 449 unsigned int flags; 450 451 #define DWC3_EVENT_PENDING BIT(0) 452 453 dma_addr_t dma; 454 455 struct dwc3 *dwc; 456 }; 457 458 #define DWC3_EP_FLAG_STALLED (1 << 0) 459 #define DWC3_EP_FLAG_WEDGED (1 << 1) 460 461 #define DWC3_EP_DIRECTION_TX true 462 #define DWC3_EP_DIRECTION_RX false 463 464 #define DWC3_TRB_NUM 256 465 466 /** 467 * struct dwc3_ep - device side endpoint representation 468 * @endpoint: usb endpoint 469 * @pending_list: list of pending requests for this endpoint 470 * @started_list: list of started requests on this endpoint 471 * @trb_pool: array of transaction buffers 472 * @trb_pool_dma: dma address of @trb_pool 473 * @trb_enqueue: enqueue 'pointer' into TRB array 474 * @trb_dequeue: dequeue 'pointer' into TRB array 475 * @desc: usb_endpoint_descriptor pointer 476 * @dwc: pointer to DWC controller 477 * @saved_state: ep state saved during hibernation 478 * @flags: endpoint flags (wedged, stalled, ...) 479 * @number: endpoint number (1 - 15) 480 * @type: set to bmAttributes & USB_ENDPOINT_XFERTYPE_MASK 481 * @resource_index: Resource transfer index 482 * @interval: the interval on which the ISOC transfer is started 483 * @name: a human readable name e.g. ep1out-bulk 484 * @direction: true for TX, false for RX 485 * @stream_capable: true when streams are enabled 486 */ 487 struct dwc3_ep { 488 struct usb_ep endpoint; 489 struct list_head pending_list; 490 struct list_head started_list; 491 492 struct dwc3_trb *trb_pool; 493 dma_addr_t trb_pool_dma; 494 const struct usb_ss_ep_comp_descriptor *comp_desc; 495 struct dwc3 *dwc; 496 497 u32 saved_state; 498 unsigned flags; 499 #define DWC3_EP_ENABLED (1 << 0) 500 #define DWC3_EP_STALL (1 << 1) 501 #define DWC3_EP_WEDGE (1 << 2) 502 #define DWC3_EP_BUSY (1 << 4) 503 #define DWC3_EP_PENDING_REQUEST (1 << 5) 504 #define DWC3_EP_MISSED_ISOC (1 << 6) 505 506 /* This last one is specific to EP0 */ 507 #define DWC3_EP0_DIR_IN (1 << 31) 508 509 /* 510 * IMPORTANT: we *know* we have 256 TRBs in our @trb_pool, so we will 511 * use a u8 type here. If anybody decides to increase number of TRBs to 512 * anything larger than 256 - I can't see why people would want to do 513 * this though - then this type needs to be changed. 514 * 515 * By using u8 types we ensure that our % operator when incrementing 516 * enqueue and dequeue get optimized away by the compiler. 517 */ 518 u8 trb_enqueue; 519 u8 trb_dequeue; 520 521 u8 number; 522 u8 type; 523 u8 resource_index; 524 u32 interval; 525 526 char name[20]; 527 528 unsigned direction:1; 529 unsigned stream_capable:1; 530 }; 531 532 enum dwc3_phy { 533 DWC3_PHY_UNKNOWN = 0, 534 DWC3_PHY_USB3, 535 DWC3_PHY_USB2, 536 }; 537 538 enum dwc3_ep0_next { 539 DWC3_EP0_UNKNOWN = 0, 540 DWC3_EP0_COMPLETE, 541 DWC3_EP0_NRDY_DATA, 542 DWC3_EP0_NRDY_STATUS, 543 }; 544 545 enum dwc3_ep0_state { 546 EP0_UNCONNECTED = 0, 547 EP0_SETUP_PHASE, 548 EP0_DATA_PHASE, 549 EP0_STATUS_PHASE, 550 }; 551 552 enum dwc3_link_state { 553 /* In SuperSpeed */ 554 DWC3_LINK_STATE_U0 = 0x00, /* in HS, means ON */ 555 DWC3_LINK_STATE_U1 = 0x01, 556 DWC3_LINK_STATE_U2 = 0x02, /* in HS, means SLEEP */ 557 DWC3_LINK_STATE_U3 = 0x03, /* in HS, means SUSPEND */ 558 DWC3_LINK_STATE_SS_DIS = 0x04, 559 DWC3_LINK_STATE_RX_DET = 0x05, /* in HS, means Early Suspend */ 560 DWC3_LINK_STATE_SS_INACT = 0x06, 561 DWC3_LINK_STATE_POLL = 0x07, 562 DWC3_LINK_STATE_RECOV = 0x08, 563 DWC3_LINK_STATE_HRESET = 0x09, 564 DWC3_LINK_STATE_CMPLY = 0x0a, 565 DWC3_LINK_STATE_LPBK = 0x0b, 566 DWC3_LINK_STATE_RESET = 0x0e, 567 DWC3_LINK_STATE_RESUME = 0x0f, 568 DWC3_LINK_STATE_MASK = 0x0f, 569 }; 570 571 /* TRB Length, PCM and Status */ 572 #define DWC3_TRB_SIZE_MASK (0x00ffffff) 573 #define DWC3_TRB_SIZE_LENGTH(n) ((n) & DWC3_TRB_SIZE_MASK) 574 #define DWC3_TRB_SIZE_PCM1(n) (((n) & 0x03) << 24) 575 #define DWC3_TRB_SIZE_TRBSTS(n) (((n) & (0x0f << 28)) >> 28) 576 577 #define DWC3_TRBSTS_OK 0 578 #define DWC3_TRBSTS_MISSED_ISOC 1 579 #define DWC3_TRBSTS_SETUP_PENDING 2 580 #define DWC3_TRB_STS_XFER_IN_PROG 4 581 582 /* TRB Control */ 583 #define DWC3_TRB_CTRL_HWO (1 << 0) 584 #define DWC3_TRB_CTRL_LST (1 << 1) 585 #define DWC3_TRB_CTRL_CHN (1 << 2) 586 #define DWC3_TRB_CTRL_CSP (1 << 3) 587 #define DWC3_TRB_CTRL_TRBCTL(n) (((n) & 0x3f) << 4) 588 #define DWC3_TRB_CTRL_ISP_IMI (1 << 10) 589 #define DWC3_TRB_CTRL_IOC (1 << 11) 590 #define DWC3_TRB_CTRL_SID_SOFN(n) (((n) & 0xffff) << 14) 591 592 #define DWC3_TRBCTL_TYPE(n) ((n) & (0x3f << 4)) 593 #define DWC3_TRBCTL_NORMAL DWC3_TRB_CTRL_TRBCTL(1) 594 #define DWC3_TRBCTL_CONTROL_SETUP DWC3_TRB_CTRL_TRBCTL(2) 595 #define DWC3_TRBCTL_CONTROL_STATUS2 DWC3_TRB_CTRL_TRBCTL(3) 596 #define DWC3_TRBCTL_CONTROL_STATUS3 DWC3_TRB_CTRL_TRBCTL(4) 597 #define DWC3_TRBCTL_CONTROL_DATA DWC3_TRB_CTRL_TRBCTL(5) 598 #define DWC3_TRBCTL_ISOCHRONOUS_FIRST DWC3_TRB_CTRL_TRBCTL(6) 599 #define DWC3_TRBCTL_ISOCHRONOUS DWC3_TRB_CTRL_TRBCTL(7) 600 #define DWC3_TRBCTL_LINK_TRB DWC3_TRB_CTRL_TRBCTL(8) 601 602 /** 603 * struct dwc3_trb - transfer request block (hw format) 604 * @bpl: DW0-3 605 * @bph: DW4-7 606 * @size: DW8-B 607 * @trl: DWC-F 608 */ 609 struct dwc3_trb { 610 u32 bpl; 611 u32 bph; 612 u32 size; 613 u32 ctrl; 614 } __packed; 615 616 /** 617 * dwc3_hwparams - copy of HWPARAMS registers 618 * @hwparams0 - GHWPARAMS0 619 * @hwparams1 - GHWPARAMS1 620 * @hwparams2 - GHWPARAMS2 621 * @hwparams3 - GHWPARAMS3 622 * @hwparams4 - GHWPARAMS4 623 * @hwparams5 - GHWPARAMS5 624 * @hwparams6 - GHWPARAMS6 625 * @hwparams7 - GHWPARAMS7 626 * @hwparams8 - GHWPARAMS8 627 */ 628 struct dwc3_hwparams { 629 u32 hwparams0; 630 u32 hwparams1; 631 u32 hwparams2; 632 u32 hwparams3; 633 u32 hwparams4; 634 u32 hwparams5; 635 u32 hwparams6; 636 u32 hwparams7; 637 u32 hwparams8; 638 }; 639 640 /* HWPARAMS0 */ 641 #define DWC3_MODE(n) ((n) & 0x7) 642 643 #define DWC3_MDWIDTH(n) (((n) & 0xff00) >> 8) 644 645 /* HWPARAMS1 */ 646 #define DWC3_NUM_INT(n) (((n) & (0x3f << 15)) >> 15) 647 648 /* HWPARAMS3 */ 649 #define DWC3_NUM_IN_EPS_MASK (0x1f << 18) 650 #define DWC3_NUM_EPS_MASK (0x3f << 12) 651 #define DWC3_NUM_EPS(p) (((p)->hwparams3 & \ 652 (DWC3_NUM_EPS_MASK)) >> 12) 653 #define DWC3_NUM_IN_EPS(p) (((p)->hwparams3 & \ 654 (DWC3_NUM_IN_EPS_MASK)) >> 18) 655 656 /* HWPARAMS7 */ 657 #define DWC3_RAM1_DEPTH(n) ((n) & 0xffff) 658 659 /** 660 * struct dwc3_request - representation of a transfer request 661 * @request: struct usb_request to be transferred 662 * @list: a list_head used for request queueing 663 * @dep: struct dwc3_ep owning this request 664 * @first_trb_index: index to first trb used by this request 665 * @epnum: endpoint number to which this request refers 666 * @trb: pointer to struct dwc3_trb 667 * @trb_dma: DMA address of @trb 668 * @direction: IN or OUT direction flag 669 * @mapped: true when request has been dma-mapped 670 * @queued: true when request has been queued to HW 671 */ 672 struct dwc3_request { 673 struct usb_request request; 674 struct list_head list; 675 struct dwc3_ep *dep; 676 677 u8 first_trb_index; 678 u8 epnum; 679 struct dwc3_trb *trb; 680 dma_addr_t trb_dma; 681 682 unsigned direction:1; 683 unsigned mapped:1; 684 unsigned started:1; 685 }; 686 687 /* 688 * struct dwc3_scratchpad_array - hibernation scratchpad array 689 * (format defined by hw) 690 */ 691 struct dwc3_scratchpad_array { 692 __le64 dma_adr[DWC3_MAX_HIBER_SCRATCHBUFS]; 693 }; 694 695 /** 696 * struct dwc3 - representation of our controller 697 * @ctrl_req: usb control request which is used for ep0 698 * @ep0_trb: trb which is used for the ctrl_req 699 * @ep0_bounce: bounce buffer for ep0 700 * @zlp_buf: used when request->zero is set 701 * @setup_buf: used while precessing STD USB requests 702 * @ctrl_req_addr: dma address of ctrl_req 703 * @ep0_trb: dma address of ep0_trb 704 * @ep0_usb_req: dummy req used while handling STD USB requests 705 * @ep0_bounce_addr: dma address of ep0_bounce 706 * @scratch_addr: dma address of scratchbuf 707 * @lock: for synchronizing 708 * @dev: pointer to our struct device 709 * @xhci: pointer to our xHCI child 710 * @event_buffer_list: a list of event buffers 711 * @gadget: device side representation of the peripheral controller 712 * @gadget_driver: pointer to the gadget driver 713 * @regs: base address for our registers 714 * @regs_size: address space size 715 * @nr_scratch: number of scratch buffers 716 * @u1u2: only used on revisions <1.83a for workaround 717 * @maximum_speed: maximum speed requested (mainly for testing purposes) 718 * @revision: revision register contents 719 * @dr_mode: requested mode of operation 720 * @usb2_phy: pointer to USB2 PHY 721 * @usb3_phy: pointer to USB3 PHY 722 * @usb2_generic_phy: pointer to USB2 PHY 723 * @usb3_generic_phy: pointer to USB3 PHY 724 * @ulpi: pointer to ulpi interface 725 * @dcfg: saved contents of DCFG register 726 * @gctl: saved contents of GCTL register 727 * @isoch_delay: wValue from Set Isochronous Delay request; 728 * @u2sel: parameter from Set SEL request. 729 * @u2pel: parameter from Set SEL request. 730 * @u1sel: parameter from Set SEL request. 731 * @u1pel: parameter from Set SEL request. 732 * @num_out_eps: number of out endpoints 733 * @num_in_eps: number of in endpoints 734 * @ep0_next_event: hold the next expected event 735 * @ep0state: state of endpoint zero 736 * @link_state: link state 737 * @speed: device speed (super, high, full, low) 738 * @mem: points to start of memory which is used for this struct. 739 * @hwparams: copy of hwparams registers 740 * @root: debugfs root folder pointer 741 * @regset: debugfs pointer to regdump file 742 * @test_mode: true when we're entering a USB test mode 743 * @test_mode_nr: test feature selector 744 * @lpm_nyet_threshold: LPM NYET response threshold 745 * @hird_threshold: HIRD threshold 746 * @hsphy_interface: "utmi" or "ulpi" 747 * @delayed_status: true when gadget driver asks for delayed status 748 * @ep0_bounced: true when we used bounce buffer 749 * @ep0_expect_in: true when we expect a DATA IN transfer 750 * @has_hibernation: true when dwc3 was configured with Hibernation 751 * @has_lpm_erratum: true when core was configured with LPM Erratum. Note that 752 * there's now way for software to detect this in runtime. 753 * @is_utmi_l1_suspend: the core asserts output signal 754 * 0 - utmi_sleep_n 755 * 1 - utmi_l1_suspend_n 756 * @is_fpga: true when we are using the FPGA board 757 * @pullups_connected: true when Run/Stop bit is set 758 * @setup_packet_pending: true when there's a Setup Packet in FIFO. Workaround 759 * @start_config_issued: true when StartConfig command has been issued 760 * @three_stage_setup: set if we perform a three phase setup 761 * @usb3_lpm_capable: set if hadrware supports Link Power Management 762 * @disable_scramble_quirk: set if we enable the disable scramble quirk 763 * @u2exit_lfps_quirk: set if we enable u2exit lfps quirk 764 * @u2ss_inp3_quirk: set if we enable P3 OK for U2/SS Inactive quirk 765 * @req_p1p2p3_quirk: set if we enable request p1p2p3 quirk 766 * @del_p1p2p3_quirk: set if we enable delay p1p2p3 quirk 767 * @del_phy_power_chg_quirk: set if we enable delay phy power change quirk 768 * @lfps_filter_quirk: set if we enable LFPS filter quirk 769 * @rx_detect_poll_quirk: set if we enable rx_detect to polling lfps quirk 770 * @dis_u3_susphy_quirk: set if we disable usb3 suspend phy 771 * @dis_u2_susphy_quirk: set if we disable usb2 suspend phy 772 * @dis_enblslpm_quirk: set if we clear enblslpm in GUSB2PHYCFG, 773 * disabling the suspend signal to the PHY. 774 * @tx_de_emphasis_quirk: set if we enable Tx de-emphasis quirk 775 * @tx_de_emphasis: Tx de-emphasis value 776 * 0 - -6dB de-emphasis 777 * 1 - -3.5dB de-emphasis 778 * 2 - No de-emphasis 779 * 3 - Reserved 780 */ 781 struct dwc3 { 782 struct usb_ctrlrequest *ctrl_req; 783 struct dwc3_trb *ep0_trb; 784 void *ep0_bounce; 785 void *zlp_buf; 786 void *scratchbuf; 787 u8 *setup_buf; 788 dma_addr_t ctrl_req_addr; 789 dma_addr_t ep0_trb_addr; 790 dma_addr_t ep0_bounce_addr; 791 dma_addr_t scratch_addr; 792 struct dwc3_request ep0_usb_req; 793 794 /* device lock */ 795 spinlock_t lock; 796 797 struct device *dev; 798 799 struct platform_device *xhci; 800 struct resource xhci_resources[DWC3_XHCI_RESOURCES_NUM]; 801 802 struct dwc3_event_buffer *ev_buf; 803 struct dwc3_ep *eps[DWC3_ENDPOINTS_NUM]; 804 805 struct usb_gadget gadget; 806 struct usb_gadget_driver *gadget_driver; 807 808 struct usb_phy *usb2_phy; 809 struct usb_phy *usb3_phy; 810 811 struct phy *usb2_generic_phy; 812 struct phy *usb3_generic_phy; 813 814 struct ulpi *ulpi; 815 816 void __iomem *regs; 817 size_t regs_size; 818 819 enum usb_dr_mode dr_mode; 820 821 /* used for suspend/resume */ 822 u32 dcfg; 823 u32 gctl; 824 825 u32 nr_scratch; 826 u32 u1u2; 827 u32 maximum_speed; 828 829 /* 830 * All 3.1 IP version constants are greater than the 3.0 IP 831 * version constants. This works for most version checks in 832 * dwc3. However, in the future, this may not apply as 833 * features may be developed on newer versions of the 3.0 IP 834 * that are not in the 3.1 IP. 835 */ 836 u32 revision; 837 838 #define DWC3_REVISION_173A 0x5533173a 839 #define DWC3_REVISION_175A 0x5533175a 840 #define DWC3_REVISION_180A 0x5533180a 841 #define DWC3_REVISION_183A 0x5533183a 842 #define DWC3_REVISION_185A 0x5533185a 843 #define DWC3_REVISION_187A 0x5533187a 844 #define DWC3_REVISION_188A 0x5533188a 845 #define DWC3_REVISION_190A 0x5533190a 846 #define DWC3_REVISION_194A 0x5533194a 847 #define DWC3_REVISION_200A 0x5533200a 848 #define DWC3_REVISION_202A 0x5533202a 849 #define DWC3_REVISION_210A 0x5533210a 850 #define DWC3_REVISION_220A 0x5533220a 851 #define DWC3_REVISION_230A 0x5533230a 852 #define DWC3_REVISION_240A 0x5533240a 853 #define DWC3_REVISION_250A 0x5533250a 854 #define DWC3_REVISION_260A 0x5533260a 855 #define DWC3_REVISION_270A 0x5533270a 856 #define DWC3_REVISION_280A 0x5533280a 857 858 /* 859 * NOTICE: we're using bit 31 as a "is usb 3.1" flag. This is really 860 * just so dwc31 revisions are always larger than dwc3. 861 */ 862 #define DWC3_REVISION_IS_DWC31 0x80000000 863 #define DWC3_USB31_REVISION_110A (0x3131302a | DWC3_REVISION_IS_USB31) 864 865 enum dwc3_ep0_next ep0_next_event; 866 enum dwc3_ep0_state ep0state; 867 enum dwc3_link_state link_state; 868 869 u16 isoch_delay; 870 u16 u2sel; 871 u16 u2pel; 872 u8 u1sel; 873 u8 u1pel; 874 875 u8 speed; 876 877 u8 num_out_eps; 878 u8 num_in_eps; 879 880 void *mem; 881 882 struct dwc3_hwparams hwparams; 883 struct dentry *root; 884 struct debugfs_regset32 *regset; 885 886 u8 test_mode; 887 u8 test_mode_nr; 888 u8 lpm_nyet_threshold; 889 u8 hird_threshold; 890 891 const char *hsphy_interface; 892 893 unsigned delayed_status:1; 894 unsigned ep0_bounced:1; 895 unsigned ep0_expect_in:1; 896 unsigned has_hibernation:1; 897 unsigned has_lpm_erratum:1; 898 unsigned is_utmi_l1_suspend:1; 899 unsigned is_fpga:1; 900 unsigned pullups_connected:1; 901 unsigned setup_packet_pending:1; 902 unsigned three_stage_setup:1; 903 unsigned usb3_lpm_capable:1; 904 905 unsigned disable_scramble_quirk:1; 906 unsigned u2exit_lfps_quirk:1; 907 unsigned u2ss_inp3_quirk:1; 908 unsigned req_p1p2p3_quirk:1; 909 unsigned del_p1p2p3_quirk:1; 910 unsigned del_phy_power_chg_quirk:1; 911 unsigned lfps_filter_quirk:1; 912 unsigned rx_detect_poll_quirk:1; 913 unsigned dis_u3_susphy_quirk:1; 914 unsigned dis_u2_susphy_quirk:1; 915 unsigned dis_enblslpm_quirk:1; 916 unsigned dis_rxdet_inp3_quirk:1; 917 918 unsigned tx_de_emphasis_quirk:1; 919 unsigned tx_de_emphasis:2; 920 }; 921 922 /* -------------------------------------------------------------------------- */ 923 924 /* -------------------------------------------------------------------------- */ 925 926 struct dwc3_event_type { 927 u32 is_devspec:1; 928 u32 type:7; 929 u32 reserved8_31:24; 930 } __packed; 931 932 #define DWC3_DEPEVT_XFERCOMPLETE 0x01 933 #define DWC3_DEPEVT_XFERINPROGRESS 0x02 934 #define DWC3_DEPEVT_XFERNOTREADY 0x03 935 #define DWC3_DEPEVT_RXTXFIFOEVT 0x04 936 #define DWC3_DEPEVT_STREAMEVT 0x06 937 #define DWC3_DEPEVT_EPCMDCMPLT 0x07 938 939 /** 940 * struct dwc3_event_depvt - Device Endpoint Events 941 * @one_bit: indicates this is an endpoint event (not used) 942 * @endpoint_number: number of the endpoint 943 * @endpoint_event: The event we have: 944 * 0x00 - Reserved 945 * 0x01 - XferComplete 946 * 0x02 - XferInProgress 947 * 0x03 - XferNotReady 948 * 0x04 - RxTxFifoEvt (IN->Underrun, OUT->Overrun) 949 * 0x05 - Reserved 950 * 0x06 - StreamEvt 951 * 0x07 - EPCmdCmplt 952 * @reserved11_10: Reserved, don't use. 953 * @status: Indicates the status of the event. Refer to databook for 954 * more information. 955 * @parameters: Parameters of the current event. Refer to databook for 956 * more information. 957 */ 958 struct dwc3_event_depevt { 959 u32 one_bit:1; 960 u32 endpoint_number:5; 961 u32 endpoint_event:4; 962 u32 reserved11_10:2; 963 u32 status:4; 964 965 /* Within XferNotReady */ 966 #define DEPEVT_STATUS_TRANSFER_ACTIVE (1 << 3) 967 968 /* Within XferComplete */ 969 #define DEPEVT_STATUS_BUSERR (1 << 0) 970 #define DEPEVT_STATUS_SHORT (1 << 1) 971 #define DEPEVT_STATUS_IOC (1 << 2) 972 #define DEPEVT_STATUS_LST (1 << 3) 973 974 /* Stream event only */ 975 #define DEPEVT_STREAMEVT_FOUND 1 976 #define DEPEVT_STREAMEVT_NOTFOUND 2 977 978 /* Control-only Status */ 979 #define DEPEVT_STATUS_CONTROL_DATA 1 980 #define DEPEVT_STATUS_CONTROL_STATUS 2 981 982 /* In response to Start Transfer */ 983 #define DEPEVT_TRANSFER_NO_RESOURCE 1 984 #define DEPEVT_TRANSFER_BUS_EXPIRY 2 985 986 u32 parameters:16; 987 } __packed; 988 989 /** 990 * struct dwc3_event_devt - Device Events 991 * @one_bit: indicates this is a non-endpoint event (not used) 992 * @device_event: indicates it's a device event. Should read as 0x00 993 * @type: indicates the type of device event. 994 * 0 - DisconnEvt 995 * 1 - USBRst 996 * 2 - ConnectDone 997 * 3 - ULStChng 998 * 4 - WkUpEvt 999 * 5 - Reserved 1000 * 6 - EOPF 1001 * 7 - SOF 1002 * 8 - Reserved 1003 * 9 - ErrticErr 1004 * 10 - CmdCmplt 1005 * 11 - EvntOverflow 1006 * 12 - VndrDevTstRcved 1007 * @reserved15_12: Reserved, not used 1008 * @event_info: Information about this event 1009 * @reserved31_25: Reserved, not used 1010 */ 1011 struct dwc3_event_devt { 1012 u32 one_bit:1; 1013 u32 device_event:7; 1014 u32 type:4; 1015 u32 reserved15_12:4; 1016 u32 event_info:9; 1017 u32 reserved31_25:7; 1018 } __packed; 1019 1020 /** 1021 * struct dwc3_event_gevt - Other Core Events 1022 * @one_bit: indicates this is a non-endpoint event (not used) 1023 * @device_event: indicates it's (0x03) Carkit or (0x04) I2C event. 1024 * @phy_port_number: self-explanatory 1025 * @reserved31_12: Reserved, not used. 1026 */ 1027 struct dwc3_event_gevt { 1028 u32 one_bit:1; 1029 u32 device_event:7; 1030 u32 phy_port_number:4; 1031 u32 reserved31_12:20; 1032 } __packed; 1033 1034 /** 1035 * union dwc3_event - representation of Event Buffer contents 1036 * @raw: raw 32-bit event 1037 * @type: the type of the event 1038 * @depevt: Device Endpoint Event 1039 * @devt: Device Event 1040 * @gevt: Global Event 1041 */ 1042 union dwc3_event { 1043 u32 raw; 1044 struct dwc3_event_type type; 1045 struct dwc3_event_depevt depevt; 1046 struct dwc3_event_devt devt; 1047 struct dwc3_event_gevt gevt; 1048 }; 1049 1050 /** 1051 * struct dwc3_gadget_ep_cmd_params - representation of endpoint command 1052 * parameters 1053 * @param2: third parameter 1054 * @param1: second parameter 1055 * @param0: first parameter 1056 */ 1057 struct dwc3_gadget_ep_cmd_params { 1058 u32 param2; 1059 u32 param1; 1060 u32 param0; 1061 }; 1062 1063 /* 1064 * DWC3 Features to be used as Driver Data 1065 */ 1066 1067 #define DWC3_HAS_PERIPHERAL BIT(0) 1068 #define DWC3_HAS_XHCI BIT(1) 1069 #define DWC3_HAS_OTG BIT(3) 1070 1071 /* prototypes */ 1072 void dwc3_set_mode(struct dwc3 *dwc, u32 mode); 1073 u32 dwc3_core_fifo_space(struct dwc3_ep *dep, u8 type); 1074 1075 /* check whether we are on the DWC_usb31 core */ 1076 static inline bool dwc3_is_usb31(struct dwc3 *dwc) 1077 { 1078 return !!(dwc->revision & DWC3_REVISION_IS_DWC31); 1079 } 1080 1081 #if IS_ENABLED(CONFIG_USB_DWC3_HOST) || IS_ENABLED(CONFIG_USB_DWC3_DUAL_ROLE) 1082 int dwc3_host_init(struct dwc3 *dwc); 1083 void dwc3_host_exit(struct dwc3 *dwc); 1084 #else 1085 static inline int dwc3_host_init(struct dwc3 *dwc) 1086 { return 0; } 1087 static inline void dwc3_host_exit(struct dwc3 *dwc) 1088 { } 1089 #endif 1090 1091 #if IS_ENABLED(CONFIG_USB_DWC3_GADGET) || IS_ENABLED(CONFIG_USB_DWC3_DUAL_ROLE) 1092 int dwc3_gadget_init(struct dwc3 *dwc); 1093 void dwc3_gadget_exit(struct dwc3 *dwc); 1094 int dwc3_gadget_set_test_mode(struct dwc3 *dwc, int mode); 1095 int dwc3_gadget_get_link_state(struct dwc3 *dwc); 1096 int dwc3_gadget_set_link_state(struct dwc3 *dwc, enum dwc3_link_state state); 1097 int dwc3_send_gadget_ep_cmd(struct dwc3 *dwc, unsigned ep, 1098 unsigned cmd, struct dwc3_gadget_ep_cmd_params *params); 1099 int dwc3_send_gadget_generic_command(struct dwc3 *dwc, unsigned cmd, u32 param); 1100 #else 1101 static inline int dwc3_gadget_init(struct dwc3 *dwc) 1102 { return 0; } 1103 static inline void dwc3_gadget_exit(struct dwc3 *dwc) 1104 { } 1105 static inline int dwc3_gadget_set_test_mode(struct dwc3 *dwc, int mode) 1106 { return 0; } 1107 static inline int dwc3_gadget_get_link_state(struct dwc3 *dwc) 1108 { return 0; } 1109 static inline int dwc3_gadget_set_link_state(struct dwc3 *dwc, 1110 enum dwc3_link_state state) 1111 { return 0; } 1112 1113 static inline int dwc3_send_gadget_ep_cmd(struct dwc3 *dwc, unsigned ep, 1114 unsigned cmd, struct dwc3_gadget_ep_cmd_params *params) 1115 { return 0; } 1116 static inline int dwc3_send_gadget_generic_command(struct dwc3 *dwc, 1117 int cmd, u32 param) 1118 { return 0; } 1119 #endif 1120 1121 /* power management interface */ 1122 #if !IS_ENABLED(CONFIG_USB_DWC3_HOST) 1123 int dwc3_gadget_suspend(struct dwc3 *dwc); 1124 int dwc3_gadget_resume(struct dwc3 *dwc); 1125 #else 1126 static inline int dwc3_gadget_suspend(struct dwc3 *dwc) 1127 { 1128 return 0; 1129 } 1130 1131 static inline int dwc3_gadget_resume(struct dwc3 *dwc) 1132 { 1133 return 0; 1134 } 1135 #endif /* !IS_ENABLED(CONFIG_USB_DWC3_HOST) */ 1136 1137 #if IS_ENABLED(CONFIG_USB_DWC3_ULPI) 1138 int dwc3_ulpi_init(struct dwc3 *dwc); 1139 void dwc3_ulpi_exit(struct dwc3 *dwc); 1140 #else 1141 static inline int dwc3_ulpi_init(struct dwc3 *dwc) 1142 { return 0; } 1143 static inline void dwc3_ulpi_exit(struct dwc3 *dwc) 1144 { } 1145 #endif 1146 1147 #endif /* __DRIVERS_USB_DWC3_CORE_H */ 1148