1 /** 2 * core.h - DesignWare USB3 DRD Core Header 3 * 4 * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com 5 * 6 * Authors: Felipe Balbi <balbi@ti.com>, 7 * Sebastian Andrzej Siewior <bigeasy@linutronix.de> 8 * 9 * This program is free software: you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License version 2 of 11 * the License as published by the Free Software Foundation. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 */ 18 19 #ifndef __DRIVERS_USB_DWC3_CORE_H 20 #define __DRIVERS_USB_DWC3_CORE_H 21 22 #include <linux/device.h> 23 #include <linux/spinlock.h> 24 #include <linux/ioport.h> 25 #include <linux/list.h> 26 #include <linux/dma-mapping.h> 27 #include <linux/mm.h> 28 #include <linux/debugfs.h> 29 30 #include <linux/usb/ch9.h> 31 #include <linux/usb/gadget.h> 32 #include <linux/usb/otg.h> 33 #include <linux/ulpi/interface.h> 34 35 #include <linux/phy/phy.h> 36 37 #define DWC3_MSG_MAX 500 38 39 /* Global constants */ 40 #define DWC3_EP0_BOUNCE_SIZE 512 41 #define DWC3_ENDPOINTS_NUM 32 42 #define DWC3_XHCI_RESOURCES_NUM 2 43 44 #define DWC3_SCRATCHBUF_SIZE 4096 /* each buffer is assumed to be 4KiB */ 45 #define DWC3_EVENT_SIZE 4 /* bytes */ 46 #define DWC3_EVENT_MAX_NUM 64 /* 2 events/endpoint */ 47 #define DWC3_EVENT_BUFFERS_SIZE (DWC3_EVENT_SIZE * DWC3_EVENT_MAX_NUM) 48 #define DWC3_EVENT_TYPE_MASK 0xfe 49 50 #define DWC3_EVENT_TYPE_DEV 0 51 #define DWC3_EVENT_TYPE_CARKIT 3 52 #define DWC3_EVENT_TYPE_I2C 4 53 54 #define DWC3_DEVICE_EVENT_DISCONNECT 0 55 #define DWC3_DEVICE_EVENT_RESET 1 56 #define DWC3_DEVICE_EVENT_CONNECT_DONE 2 57 #define DWC3_DEVICE_EVENT_LINK_STATUS_CHANGE 3 58 #define DWC3_DEVICE_EVENT_WAKEUP 4 59 #define DWC3_DEVICE_EVENT_HIBER_REQ 5 60 #define DWC3_DEVICE_EVENT_EOPF 6 61 #define DWC3_DEVICE_EVENT_SOF 7 62 #define DWC3_DEVICE_EVENT_ERRATIC_ERROR 9 63 #define DWC3_DEVICE_EVENT_CMD_CMPL 10 64 #define DWC3_DEVICE_EVENT_OVERFLOW 11 65 66 #define DWC3_GEVNTCOUNT_MASK 0xfffc 67 #define DWC3_GSNPSID_MASK 0xffff0000 68 #define DWC3_GSNPSREV_MASK 0xffff 69 70 /* DWC3 registers memory space boundries */ 71 #define DWC3_XHCI_REGS_START 0x0 72 #define DWC3_XHCI_REGS_END 0x7fff 73 #define DWC3_GLOBALS_REGS_START 0xc100 74 #define DWC3_GLOBALS_REGS_END 0xc6ff 75 #define DWC3_DEVICE_REGS_START 0xc700 76 #define DWC3_DEVICE_REGS_END 0xcbff 77 #define DWC3_OTG_REGS_START 0xcc00 78 #define DWC3_OTG_REGS_END 0xccff 79 80 /* Global Registers */ 81 #define DWC3_GSBUSCFG0 0xc100 82 #define DWC3_GSBUSCFG1 0xc104 83 #define DWC3_GTXTHRCFG 0xc108 84 #define DWC3_GRXTHRCFG 0xc10c 85 #define DWC3_GCTL 0xc110 86 #define DWC3_GEVTEN 0xc114 87 #define DWC3_GSTS 0xc118 88 #define DWC3_GSNPSID 0xc120 89 #define DWC3_GGPIO 0xc124 90 #define DWC3_GUID 0xc128 91 #define DWC3_GUCTL 0xc12c 92 #define DWC3_GBUSERRADDR0 0xc130 93 #define DWC3_GBUSERRADDR1 0xc134 94 #define DWC3_GPRTBIMAP0 0xc138 95 #define DWC3_GPRTBIMAP1 0xc13c 96 #define DWC3_GHWPARAMS0 0xc140 97 #define DWC3_GHWPARAMS1 0xc144 98 #define DWC3_GHWPARAMS2 0xc148 99 #define DWC3_GHWPARAMS3 0xc14c 100 #define DWC3_GHWPARAMS4 0xc150 101 #define DWC3_GHWPARAMS5 0xc154 102 #define DWC3_GHWPARAMS6 0xc158 103 #define DWC3_GHWPARAMS7 0xc15c 104 #define DWC3_GDBGFIFOSPACE 0xc160 105 #define DWC3_GDBGLTSSM 0xc164 106 #define DWC3_GPRTBIMAP_HS0 0xc180 107 #define DWC3_GPRTBIMAP_HS1 0xc184 108 #define DWC3_GPRTBIMAP_FS0 0xc188 109 #define DWC3_GPRTBIMAP_FS1 0xc18c 110 111 #define DWC3_GUSB2PHYCFG(n) (0xc200 + (n * 0x04)) 112 #define DWC3_GUSB2I2CCTL(n) (0xc240 + (n * 0x04)) 113 114 #define DWC3_GUSB2PHYACC(n) (0xc280 + (n * 0x04)) 115 116 #define DWC3_GUSB3PIPECTL(n) (0xc2c0 + (n * 0x04)) 117 118 #define DWC3_GTXFIFOSIZ(n) (0xc300 + (n * 0x04)) 119 #define DWC3_GRXFIFOSIZ(n) (0xc380 + (n * 0x04)) 120 121 #define DWC3_GEVNTADRLO(n) (0xc400 + (n * 0x10)) 122 #define DWC3_GEVNTADRHI(n) (0xc404 + (n * 0x10)) 123 #define DWC3_GEVNTSIZ(n) (0xc408 + (n * 0x10)) 124 #define DWC3_GEVNTCOUNT(n) (0xc40c + (n * 0x10)) 125 126 #define DWC3_GHWPARAMS8 0xc600 127 128 /* Device Registers */ 129 #define DWC3_DCFG 0xc700 130 #define DWC3_DCTL 0xc704 131 #define DWC3_DEVTEN 0xc708 132 #define DWC3_DSTS 0xc70c 133 #define DWC3_DGCMDPAR 0xc710 134 #define DWC3_DGCMD 0xc714 135 #define DWC3_DALEPENA 0xc720 136 #define DWC3_DEPCMDPAR2(n) (0xc800 + (n * 0x10)) 137 #define DWC3_DEPCMDPAR1(n) (0xc804 + (n * 0x10)) 138 #define DWC3_DEPCMDPAR0(n) (0xc808 + (n * 0x10)) 139 #define DWC3_DEPCMD(n) (0xc80c + (n * 0x10)) 140 141 /* OTG Registers */ 142 #define DWC3_OCFG 0xcc00 143 #define DWC3_OCTL 0xcc04 144 #define DWC3_OEVT 0xcc08 145 #define DWC3_OEVTEN 0xcc0C 146 #define DWC3_OSTS 0xcc10 147 148 /* Bit fields */ 149 150 /* Global Configuration Register */ 151 #define DWC3_GCTL_PWRDNSCALE(n) ((n) << 19) 152 #define DWC3_GCTL_U2RSTECN (1 << 16) 153 #define DWC3_GCTL_RAMCLKSEL(x) (((x) & DWC3_GCTL_CLK_MASK) << 6) 154 #define DWC3_GCTL_CLK_BUS (0) 155 #define DWC3_GCTL_CLK_PIPE (1) 156 #define DWC3_GCTL_CLK_PIPEHALF (2) 157 #define DWC3_GCTL_CLK_MASK (3) 158 159 #define DWC3_GCTL_PRTCAP(n) (((n) & (3 << 12)) >> 12) 160 #define DWC3_GCTL_PRTCAPDIR(n) ((n) << 12) 161 #define DWC3_GCTL_PRTCAP_HOST 1 162 #define DWC3_GCTL_PRTCAP_DEVICE 2 163 #define DWC3_GCTL_PRTCAP_OTG 3 164 165 #define DWC3_GCTL_CORESOFTRESET (1 << 11) 166 #define DWC3_GCTL_SOFITPSYNC (1 << 10) 167 #define DWC3_GCTL_SCALEDOWN(n) ((n) << 4) 168 #define DWC3_GCTL_SCALEDOWN_MASK DWC3_GCTL_SCALEDOWN(3) 169 #define DWC3_GCTL_DISSCRAMBLE (1 << 3) 170 #define DWC3_GCTL_U2EXIT_LFPS (1 << 2) 171 #define DWC3_GCTL_GBLHIBERNATIONEN (1 << 1) 172 #define DWC3_GCTL_DSBLCLKGTNG (1 << 0) 173 174 /* Global USB2 PHY Configuration Register */ 175 #define DWC3_GUSB2PHYCFG_PHYSOFTRST (1 << 31) 176 #define DWC3_GUSB2PHYCFG_SUSPHY (1 << 6) 177 #define DWC3_GUSB2PHYCFG_ULPI_UTMI (1 << 4) 178 179 /* Global USB2 PHY Vendor Control Register */ 180 #define DWC3_GUSB2PHYACC_NEWREGREQ (1 << 25) 181 #define DWC3_GUSB2PHYACC_BUSY (1 << 23) 182 #define DWC3_GUSB2PHYACC_WRITE (1 << 22) 183 #define DWC3_GUSB2PHYACC_ADDR(n) (n << 16) 184 #define DWC3_GUSB2PHYACC_EXTEND_ADDR(n) (n << 8) 185 #define DWC3_GUSB2PHYACC_DATA(n) (n & 0xff) 186 187 /* Global USB3 PIPE Control Register */ 188 #define DWC3_GUSB3PIPECTL_PHYSOFTRST (1 << 31) 189 #define DWC3_GUSB3PIPECTL_U2SSINP3OK (1 << 29) 190 #define DWC3_GUSB3PIPECTL_REQP1P2P3 (1 << 24) 191 #define DWC3_GUSB3PIPECTL_DEP1P2P3(n) ((n) << 19) 192 #define DWC3_GUSB3PIPECTL_DEP1P2P3_MASK DWC3_GUSB3PIPECTL_DEP1P2P3(7) 193 #define DWC3_GUSB3PIPECTL_DEP1P2P3_EN DWC3_GUSB3PIPECTL_DEP1P2P3(1) 194 #define DWC3_GUSB3PIPECTL_DEPOCHANGE (1 << 18) 195 #define DWC3_GUSB3PIPECTL_SUSPHY (1 << 17) 196 #define DWC3_GUSB3PIPECTL_LFPSFILT (1 << 9) 197 #define DWC3_GUSB3PIPECTL_RX_DETOPOLL (1 << 8) 198 #define DWC3_GUSB3PIPECTL_TX_DEEPH_MASK DWC3_GUSB3PIPECTL_TX_DEEPH(3) 199 #define DWC3_GUSB3PIPECTL_TX_DEEPH(n) ((n) << 1) 200 201 /* Global TX Fifo Size Register */ 202 #define DWC3_GTXFIFOSIZ_TXFDEF(n) ((n) & 0xffff) 203 #define DWC3_GTXFIFOSIZ_TXFSTADDR(n) ((n) & 0xffff0000) 204 205 /* Global Event Size Registers */ 206 #define DWC3_GEVNTSIZ_INTMASK (1 << 31) 207 #define DWC3_GEVNTSIZ_SIZE(n) ((n) & 0xffff) 208 209 /* Global HWPARAMS1 Register */ 210 #define DWC3_GHWPARAMS1_EN_PWROPT(n) (((n) & (3 << 24)) >> 24) 211 #define DWC3_GHWPARAMS1_EN_PWROPT_NO 0 212 #define DWC3_GHWPARAMS1_EN_PWROPT_CLK 1 213 #define DWC3_GHWPARAMS1_EN_PWROPT_HIB 2 214 #define DWC3_GHWPARAMS1_PWROPT(n) ((n) << 24) 215 #define DWC3_GHWPARAMS1_PWROPT_MASK DWC3_GHWPARAMS1_PWROPT(3) 216 217 /* Global HWPARAMS3 Register */ 218 #define DWC3_GHWPARAMS3_SSPHY_IFC(n) ((n) & 3) 219 #define DWC3_GHWPARAMS3_SSPHY_IFC_DIS 0 220 #define DWC3_GHWPARAMS3_SSPHY_IFC_ENA 1 221 #define DWC3_GHWPARAMS3_HSPHY_IFC(n) (((n) & (3 << 2)) >> 2) 222 #define DWC3_GHWPARAMS3_HSPHY_IFC_DIS 0 223 #define DWC3_GHWPARAMS3_HSPHY_IFC_UTMI 1 224 #define DWC3_GHWPARAMS3_HSPHY_IFC_ULPI 2 225 #define DWC3_GHWPARAMS3_HSPHY_IFC_UTMI_ULPI 3 226 #define DWC3_GHWPARAMS3_FSPHY_IFC(n) (((n) & (3 << 4)) >> 4) 227 #define DWC3_GHWPARAMS3_FSPHY_IFC_DIS 0 228 #define DWC3_GHWPARAMS3_FSPHY_IFC_ENA 1 229 230 /* Global HWPARAMS4 Register */ 231 #define DWC3_GHWPARAMS4_HIBER_SCRATCHBUFS(n) (((n) & (0x0f << 13)) >> 13) 232 #define DWC3_MAX_HIBER_SCRATCHBUFS 15 233 234 /* Global HWPARAMS6 Register */ 235 #define DWC3_GHWPARAMS6_EN_FPGA (1 << 7) 236 237 /* Device Configuration Register */ 238 #define DWC3_DCFG_DEVADDR(addr) ((addr) << 3) 239 #define DWC3_DCFG_DEVADDR_MASK DWC3_DCFG_DEVADDR(0x7f) 240 241 #define DWC3_DCFG_SPEED_MASK (7 << 0) 242 #define DWC3_DCFG_SUPERSPEED (4 << 0) 243 #define DWC3_DCFG_HIGHSPEED (0 << 0) 244 #define DWC3_DCFG_FULLSPEED2 (1 << 0) 245 #define DWC3_DCFG_LOWSPEED (2 << 0) 246 #define DWC3_DCFG_FULLSPEED1 (3 << 0) 247 248 #define DWC3_DCFG_LPM_CAP (1 << 22) 249 250 /* Device Control Register */ 251 #define DWC3_DCTL_RUN_STOP (1 << 31) 252 #define DWC3_DCTL_CSFTRST (1 << 30) 253 #define DWC3_DCTL_LSFTRST (1 << 29) 254 255 #define DWC3_DCTL_HIRD_THRES_MASK (0x1f << 24) 256 #define DWC3_DCTL_HIRD_THRES(n) ((n) << 24) 257 258 #define DWC3_DCTL_APPL1RES (1 << 23) 259 260 /* These apply for core versions 1.87a and earlier */ 261 #define DWC3_DCTL_TRGTULST_MASK (0x0f << 17) 262 #define DWC3_DCTL_TRGTULST(n) ((n) << 17) 263 #define DWC3_DCTL_TRGTULST_U2 (DWC3_DCTL_TRGTULST(2)) 264 #define DWC3_DCTL_TRGTULST_U3 (DWC3_DCTL_TRGTULST(3)) 265 #define DWC3_DCTL_TRGTULST_SS_DIS (DWC3_DCTL_TRGTULST(4)) 266 #define DWC3_DCTL_TRGTULST_RX_DET (DWC3_DCTL_TRGTULST(5)) 267 #define DWC3_DCTL_TRGTULST_SS_INACT (DWC3_DCTL_TRGTULST(6)) 268 269 /* These apply for core versions 1.94a and later */ 270 #define DWC3_DCTL_LPM_ERRATA_MASK DWC3_DCTL_LPM_ERRATA(0xf) 271 #define DWC3_DCTL_LPM_ERRATA(n) ((n) << 20) 272 273 #define DWC3_DCTL_KEEP_CONNECT (1 << 19) 274 #define DWC3_DCTL_L1_HIBER_EN (1 << 18) 275 #define DWC3_DCTL_CRS (1 << 17) 276 #define DWC3_DCTL_CSS (1 << 16) 277 278 #define DWC3_DCTL_INITU2ENA (1 << 12) 279 #define DWC3_DCTL_ACCEPTU2ENA (1 << 11) 280 #define DWC3_DCTL_INITU1ENA (1 << 10) 281 #define DWC3_DCTL_ACCEPTU1ENA (1 << 9) 282 #define DWC3_DCTL_TSTCTRL_MASK (0xf << 1) 283 284 #define DWC3_DCTL_ULSTCHNGREQ_MASK (0x0f << 5) 285 #define DWC3_DCTL_ULSTCHNGREQ(n) (((n) << 5) & DWC3_DCTL_ULSTCHNGREQ_MASK) 286 287 #define DWC3_DCTL_ULSTCHNG_NO_ACTION (DWC3_DCTL_ULSTCHNGREQ(0)) 288 #define DWC3_DCTL_ULSTCHNG_SS_DISABLED (DWC3_DCTL_ULSTCHNGREQ(4)) 289 #define DWC3_DCTL_ULSTCHNG_RX_DETECT (DWC3_DCTL_ULSTCHNGREQ(5)) 290 #define DWC3_DCTL_ULSTCHNG_SS_INACTIVE (DWC3_DCTL_ULSTCHNGREQ(6)) 291 #define DWC3_DCTL_ULSTCHNG_RECOVERY (DWC3_DCTL_ULSTCHNGREQ(8)) 292 #define DWC3_DCTL_ULSTCHNG_COMPLIANCE (DWC3_DCTL_ULSTCHNGREQ(10)) 293 #define DWC3_DCTL_ULSTCHNG_LOOPBACK (DWC3_DCTL_ULSTCHNGREQ(11)) 294 295 /* Device Event Enable Register */ 296 #define DWC3_DEVTEN_VNDRDEVTSTRCVEDEN (1 << 12) 297 #define DWC3_DEVTEN_EVNTOVERFLOWEN (1 << 11) 298 #define DWC3_DEVTEN_CMDCMPLTEN (1 << 10) 299 #define DWC3_DEVTEN_ERRTICERREN (1 << 9) 300 #define DWC3_DEVTEN_SOFEN (1 << 7) 301 #define DWC3_DEVTEN_EOPFEN (1 << 6) 302 #define DWC3_DEVTEN_HIBERNATIONREQEVTEN (1 << 5) 303 #define DWC3_DEVTEN_WKUPEVTEN (1 << 4) 304 #define DWC3_DEVTEN_ULSTCNGEN (1 << 3) 305 #define DWC3_DEVTEN_CONNECTDONEEN (1 << 2) 306 #define DWC3_DEVTEN_USBRSTEN (1 << 1) 307 #define DWC3_DEVTEN_DISCONNEVTEN (1 << 0) 308 309 /* Device Status Register */ 310 #define DWC3_DSTS_DCNRD (1 << 29) 311 312 /* This applies for core versions 1.87a and earlier */ 313 #define DWC3_DSTS_PWRUPREQ (1 << 24) 314 315 /* These apply for core versions 1.94a and later */ 316 #define DWC3_DSTS_RSS (1 << 25) 317 #define DWC3_DSTS_SSS (1 << 24) 318 319 #define DWC3_DSTS_COREIDLE (1 << 23) 320 #define DWC3_DSTS_DEVCTRLHLT (1 << 22) 321 322 #define DWC3_DSTS_USBLNKST_MASK (0x0f << 18) 323 #define DWC3_DSTS_USBLNKST(n) (((n) & DWC3_DSTS_USBLNKST_MASK) >> 18) 324 325 #define DWC3_DSTS_RXFIFOEMPTY (1 << 17) 326 327 #define DWC3_DSTS_SOFFN_MASK (0x3fff << 3) 328 #define DWC3_DSTS_SOFFN(n) (((n) & DWC3_DSTS_SOFFN_MASK) >> 3) 329 330 #define DWC3_DSTS_CONNECTSPD (7 << 0) 331 332 #define DWC3_DSTS_SUPERSPEED (4 << 0) 333 #define DWC3_DSTS_HIGHSPEED (0 << 0) 334 #define DWC3_DSTS_FULLSPEED2 (1 << 0) 335 #define DWC3_DSTS_LOWSPEED (2 << 0) 336 #define DWC3_DSTS_FULLSPEED1 (3 << 0) 337 338 /* Device Generic Command Register */ 339 #define DWC3_DGCMD_SET_LMP 0x01 340 #define DWC3_DGCMD_SET_PERIODIC_PAR 0x02 341 #define DWC3_DGCMD_XMIT_FUNCTION 0x03 342 343 /* These apply for core versions 1.94a and later */ 344 #define DWC3_DGCMD_SET_SCRATCHPAD_ADDR_LO 0x04 345 #define DWC3_DGCMD_SET_SCRATCHPAD_ADDR_HI 0x05 346 347 #define DWC3_DGCMD_SELECTED_FIFO_FLUSH 0x09 348 #define DWC3_DGCMD_ALL_FIFO_FLUSH 0x0a 349 #define DWC3_DGCMD_SET_ENDPOINT_NRDY 0x0c 350 #define DWC3_DGCMD_RUN_SOC_BUS_LOOPBACK 0x10 351 352 #define DWC3_DGCMD_STATUS(n) (((n) >> 12) & 0x0F) 353 #define DWC3_DGCMD_CMDACT (1 << 10) 354 #define DWC3_DGCMD_CMDIOC (1 << 8) 355 356 /* Device Generic Command Parameter Register */ 357 #define DWC3_DGCMDPAR_FORCE_LINKPM_ACCEPT (1 << 0) 358 #define DWC3_DGCMDPAR_FIFO_NUM(n) ((n) << 0) 359 #define DWC3_DGCMDPAR_RX_FIFO (0 << 5) 360 #define DWC3_DGCMDPAR_TX_FIFO (1 << 5) 361 #define DWC3_DGCMDPAR_LOOPBACK_DIS (0 << 0) 362 #define DWC3_DGCMDPAR_LOOPBACK_ENA (1 << 0) 363 364 /* Device Endpoint Command Register */ 365 #define DWC3_DEPCMD_PARAM_SHIFT 16 366 #define DWC3_DEPCMD_PARAM(x) ((x) << DWC3_DEPCMD_PARAM_SHIFT) 367 #define DWC3_DEPCMD_GET_RSC_IDX(x) (((x) >> DWC3_DEPCMD_PARAM_SHIFT) & 0x7f) 368 #define DWC3_DEPCMD_STATUS(x) (((x) >> 12) & 0x0F) 369 #define DWC3_DEPCMD_HIPRI_FORCERM (1 << 11) 370 #define DWC3_DEPCMD_CMDACT (1 << 10) 371 #define DWC3_DEPCMD_CMDIOC (1 << 8) 372 373 #define DWC3_DEPCMD_DEPSTARTCFG (0x09 << 0) 374 #define DWC3_DEPCMD_ENDTRANSFER (0x08 << 0) 375 #define DWC3_DEPCMD_UPDATETRANSFER (0x07 << 0) 376 #define DWC3_DEPCMD_STARTTRANSFER (0x06 << 0) 377 #define DWC3_DEPCMD_CLEARSTALL (0x05 << 0) 378 #define DWC3_DEPCMD_SETSTALL (0x04 << 0) 379 /* This applies for core versions 1.90a and earlier */ 380 #define DWC3_DEPCMD_GETSEQNUMBER (0x03 << 0) 381 /* This applies for core versions 1.94a and later */ 382 #define DWC3_DEPCMD_GETEPSTATE (0x03 << 0) 383 #define DWC3_DEPCMD_SETTRANSFRESOURCE (0x02 << 0) 384 #define DWC3_DEPCMD_SETEPCONFIG (0x01 << 0) 385 386 /* The EP number goes 0..31 so ep0 is always out and ep1 is always in */ 387 #define DWC3_DALEPENA_EP(n) (1 << n) 388 389 #define DWC3_DEPCMD_TYPE_CONTROL 0 390 #define DWC3_DEPCMD_TYPE_ISOC 1 391 #define DWC3_DEPCMD_TYPE_BULK 2 392 #define DWC3_DEPCMD_TYPE_INTR 3 393 394 /* Structures */ 395 396 struct dwc3_trb; 397 398 /** 399 * struct dwc3_event_buffer - Software event buffer representation 400 * @buf: _THE_ buffer 401 * @length: size of this buffer 402 * @lpos: event offset 403 * @count: cache of last read event count register 404 * @flags: flags related to this event buffer 405 * @dma: dma_addr_t 406 * @dwc: pointer to DWC controller 407 */ 408 struct dwc3_event_buffer { 409 void *buf; 410 unsigned length; 411 unsigned int lpos; 412 unsigned int count; 413 unsigned int flags; 414 415 #define DWC3_EVENT_PENDING BIT(0) 416 417 dma_addr_t dma; 418 419 struct dwc3 *dwc; 420 }; 421 422 #define DWC3_EP_FLAG_STALLED (1 << 0) 423 #define DWC3_EP_FLAG_WEDGED (1 << 1) 424 425 #define DWC3_EP_DIRECTION_TX true 426 #define DWC3_EP_DIRECTION_RX false 427 428 #define DWC3_TRB_NUM 32 429 #define DWC3_TRB_MASK (DWC3_TRB_NUM - 1) 430 431 /** 432 * struct dwc3_ep - device side endpoint representation 433 * @endpoint: usb endpoint 434 * @request_list: list of requests for this endpoint 435 * @req_queued: list of requests on this ep which have TRBs setup 436 * @trb_pool: array of transaction buffers 437 * @trb_pool_dma: dma address of @trb_pool 438 * @free_slot: next slot which is going to be used 439 * @busy_slot: first slot which is owned by HW 440 * @desc: usb_endpoint_descriptor pointer 441 * @dwc: pointer to DWC controller 442 * @saved_state: ep state saved during hibernation 443 * @flags: endpoint flags (wedged, stalled, ...) 444 * @number: endpoint number (1 - 15) 445 * @type: set to bmAttributes & USB_ENDPOINT_XFERTYPE_MASK 446 * @resource_index: Resource transfer index 447 * @interval: the interval on which the ISOC transfer is started 448 * @name: a human readable name e.g. ep1out-bulk 449 * @direction: true for TX, false for RX 450 * @stream_capable: true when streams are enabled 451 */ 452 struct dwc3_ep { 453 struct usb_ep endpoint; 454 struct list_head request_list; 455 struct list_head req_queued; 456 457 struct dwc3_trb *trb_pool; 458 dma_addr_t trb_pool_dma; 459 u32 free_slot; 460 u32 busy_slot; 461 const struct usb_ss_ep_comp_descriptor *comp_desc; 462 struct dwc3 *dwc; 463 464 u32 saved_state; 465 unsigned flags; 466 #define DWC3_EP_ENABLED (1 << 0) 467 #define DWC3_EP_STALL (1 << 1) 468 #define DWC3_EP_WEDGE (1 << 2) 469 #define DWC3_EP_BUSY (1 << 4) 470 #define DWC3_EP_PENDING_REQUEST (1 << 5) 471 #define DWC3_EP_MISSED_ISOC (1 << 6) 472 473 /* This last one is specific to EP0 */ 474 #define DWC3_EP0_DIR_IN (1 << 31) 475 476 u8 number; 477 u8 type; 478 u8 resource_index; 479 u32 interval; 480 481 char name[20]; 482 483 unsigned direction:1; 484 unsigned stream_capable:1; 485 }; 486 487 enum dwc3_phy { 488 DWC3_PHY_UNKNOWN = 0, 489 DWC3_PHY_USB3, 490 DWC3_PHY_USB2, 491 }; 492 493 enum dwc3_ep0_next { 494 DWC3_EP0_UNKNOWN = 0, 495 DWC3_EP0_COMPLETE, 496 DWC3_EP0_NRDY_DATA, 497 DWC3_EP0_NRDY_STATUS, 498 }; 499 500 enum dwc3_ep0_state { 501 EP0_UNCONNECTED = 0, 502 EP0_SETUP_PHASE, 503 EP0_DATA_PHASE, 504 EP0_STATUS_PHASE, 505 }; 506 507 enum dwc3_link_state { 508 /* In SuperSpeed */ 509 DWC3_LINK_STATE_U0 = 0x00, /* in HS, means ON */ 510 DWC3_LINK_STATE_U1 = 0x01, 511 DWC3_LINK_STATE_U2 = 0x02, /* in HS, means SLEEP */ 512 DWC3_LINK_STATE_U3 = 0x03, /* in HS, means SUSPEND */ 513 DWC3_LINK_STATE_SS_DIS = 0x04, 514 DWC3_LINK_STATE_RX_DET = 0x05, /* in HS, means Early Suspend */ 515 DWC3_LINK_STATE_SS_INACT = 0x06, 516 DWC3_LINK_STATE_POLL = 0x07, 517 DWC3_LINK_STATE_RECOV = 0x08, 518 DWC3_LINK_STATE_HRESET = 0x09, 519 DWC3_LINK_STATE_CMPLY = 0x0a, 520 DWC3_LINK_STATE_LPBK = 0x0b, 521 DWC3_LINK_STATE_RESET = 0x0e, 522 DWC3_LINK_STATE_RESUME = 0x0f, 523 DWC3_LINK_STATE_MASK = 0x0f, 524 }; 525 526 /* TRB Length, PCM and Status */ 527 #define DWC3_TRB_SIZE_MASK (0x00ffffff) 528 #define DWC3_TRB_SIZE_LENGTH(n) ((n) & DWC3_TRB_SIZE_MASK) 529 #define DWC3_TRB_SIZE_PCM1(n) (((n) & 0x03) << 24) 530 #define DWC3_TRB_SIZE_TRBSTS(n) (((n) & (0x0f << 28)) >> 28) 531 532 #define DWC3_TRBSTS_OK 0 533 #define DWC3_TRBSTS_MISSED_ISOC 1 534 #define DWC3_TRBSTS_SETUP_PENDING 2 535 #define DWC3_TRB_STS_XFER_IN_PROG 4 536 537 /* TRB Control */ 538 #define DWC3_TRB_CTRL_HWO (1 << 0) 539 #define DWC3_TRB_CTRL_LST (1 << 1) 540 #define DWC3_TRB_CTRL_CHN (1 << 2) 541 #define DWC3_TRB_CTRL_CSP (1 << 3) 542 #define DWC3_TRB_CTRL_TRBCTL(n) (((n) & 0x3f) << 4) 543 #define DWC3_TRB_CTRL_ISP_IMI (1 << 10) 544 #define DWC3_TRB_CTRL_IOC (1 << 11) 545 #define DWC3_TRB_CTRL_SID_SOFN(n) (((n) & 0xffff) << 14) 546 547 #define DWC3_TRBCTL_NORMAL DWC3_TRB_CTRL_TRBCTL(1) 548 #define DWC3_TRBCTL_CONTROL_SETUP DWC3_TRB_CTRL_TRBCTL(2) 549 #define DWC3_TRBCTL_CONTROL_STATUS2 DWC3_TRB_CTRL_TRBCTL(3) 550 #define DWC3_TRBCTL_CONTROL_STATUS3 DWC3_TRB_CTRL_TRBCTL(4) 551 #define DWC3_TRBCTL_CONTROL_DATA DWC3_TRB_CTRL_TRBCTL(5) 552 #define DWC3_TRBCTL_ISOCHRONOUS_FIRST DWC3_TRB_CTRL_TRBCTL(6) 553 #define DWC3_TRBCTL_ISOCHRONOUS DWC3_TRB_CTRL_TRBCTL(7) 554 #define DWC3_TRBCTL_LINK_TRB DWC3_TRB_CTRL_TRBCTL(8) 555 556 /** 557 * struct dwc3_trb - transfer request block (hw format) 558 * @bpl: DW0-3 559 * @bph: DW4-7 560 * @size: DW8-B 561 * @trl: DWC-F 562 */ 563 struct dwc3_trb { 564 u32 bpl; 565 u32 bph; 566 u32 size; 567 u32 ctrl; 568 } __packed; 569 570 /** 571 * dwc3_hwparams - copy of HWPARAMS registers 572 * @hwparams0 - GHWPARAMS0 573 * @hwparams1 - GHWPARAMS1 574 * @hwparams2 - GHWPARAMS2 575 * @hwparams3 - GHWPARAMS3 576 * @hwparams4 - GHWPARAMS4 577 * @hwparams5 - GHWPARAMS5 578 * @hwparams6 - GHWPARAMS6 579 * @hwparams7 - GHWPARAMS7 580 * @hwparams8 - GHWPARAMS8 581 */ 582 struct dwc3_hwparams { 583 u32 hwparams0; 584 u32 hwparams1; 585 u32 hwparams2; 586 u32 hwparams3; 587 u32 hwparams4; 588 u32 hwparams5; 589 u32 hwparams6; 590 u32 hwparams7; 591 u32 hwparams8; 592 }; 593 594 /* HWPARAMS0 */ 595 #define DWC3_MODE(n) ((n) & 0x7) 596 597 #define DWC3_MDWIDTH(n) (((n) & 0xff00) >> 8) 598 599 /* HWPARAMS1 */ 600 #define DWC3_NUM_INT(n) (((n) & (0x3f << 15)) >> 15) 601 602 /* HWPARAMS3 */ 603 #define DWC3_NUM_IN_EPS_MASK (0x1f << 18) 604 #define DWC3_NUM_EPS_MASK (0x3f << 12) 605 #define DWC3_NUM_EPS(p) (((p)->hwparams3 & \ 606 (DWC3_NUM_EPS_MASK)) >> 12) 607 #define DWC3_NUM_IN_EPS(p) (((p)->hwparams3 & \ 608 (DWC3_NUM_IN_EPS_MASK)) >> 18) 609 610 /* HWPARAMS7 */ 611 #define DWC3_RAM1_DEPTH(n) ((n) & 0xffff) 612 613 struct dwc3_request { 614 struct usb_request request; 615 struct list_head list; 616 struct dwc3_ep *dep; 617 u32 start_slot; 618 619 u8 epnum; 620 struct dwc3_trb *trb; 621 dma_addr_t trb_dma; 622 623 unsigned direction:1; 624 unsigned mapped:1; 625 unsigned queued:1; 626 }; 627 628 /* 629 * struct dwc3_scratchpad_array - hibernation scratchpad array 630 * (format defined by hw) 631 */ 632 struct dwc3_scratchpad_array { 633 __le64 dma_adr[DWC3_MAX_HIBER_SCRATCHBUFS]; 634 }; 635 636 /** 637 * struct dwc3 - representation of our controller 638 * @ctrl_req: usb control request which is used for ep0 639 * @ep0_trb: trb which is used for the ctrl_req 640 * @ep0_bounce: bounce buffer for ep0 641 * @setup_buf: used while precessing STD USB requests 642 * @ctrl_req_addr: dma address of ctrl_req 643 * @ep0_trb: dma address of ep0_trb 644 * @ep0_usb_req: dummy req used while handling STD USB requests 645 * @ep0_bounce_addr: dma address of ep0_bounce 646 * @scratch_addr: dma address of scratchbuf 647 * @lock: for synchronizing 648 * @dev: pointer to our struct device 649 * @xhci: pointer to our xHCI child 650 * @event_buffer_list: a list of event buffers 651 * @gadget: device side representation of the peripheral controller 652 * @gadget_driver: pointer to the gadget driver 653 * @regs: base address for our registers 654 * @regs_size: address space size 655 * @nr_scratch: number of scratch buffers 656 * @num_event_buffers: calculated number of event buffers 657 * @u1u2: only used on revisions <1.83a for workaround 658 * @maximum_speed: maximum speed requested (mainly for testing purposes) 659 * @revision: revision register contents 660 * @dr_mode: requested mode of operation 661 * @usb2_phy: pointer to USB2 PHY 662 * @usb3_phy: pointer to USB3 PHY 663 * @usb2_generic_phy: pointer to USB2 PHY 664 * @usb3_generic_phy: pointer to USB3 PHY 665 * @ulpi: pointer to ulpi interface 666 * @dcfg: saved contents of DCFG register 667 * @gctl: saved contents of GCTL register 668 * @isoch_delay: wValue from Set Isochronous Delay request; 669 * @u2sel: parameter from Set SEL request. 670 * @u2pel: parameter from Set SEL request. 671 * @u1sel: parameter from Set SEL request. 672 * @u1pel: parameter from Set SEL request. 673 * @num_out_eps: number of out endpoints 674 * @num_in_eps: number of in endpoints 675 * @ep0_next_event: hold the next expected event 676 * @ep0state: state of endpoint zero 677 * @link_state: link state 678 * @speed: device speed (super, high, full, low) 679 * @mem: points to start of memory which is used for this struct. 680 * @hwparams: copy of hwparams registers 681 * @root: debugfs root folder pointer 682 * @regset: debugfs pointer to regdump file 683 * @test_mode: true when we're entering a USB test mode 684 * @test_mode_nr: test feature selector 685 * @lpm_nyet_threshold: LPM NYET response threshold 686 * @hird_threshold: HIRD threshold 687 * @hsphy_interface: "utmi" or "ulpi" 688 * @delayed_status: true when gadget driver asks for delayed status 689 * @ep0_bounced: true when we used bounce buffer 690 * @ep0_expect_in: true when we expect a DATA IN transfer 691 * @has_hibernation: true when dwc3 was configured with Hibernation 692 * @has_lpm_erratum: true when core was configured with LPM Erratum. Note that 693 * there's now way for software to detect this in runtime. 694 * @is_utmi_l1_suspend: the core asserts output signal 695 * 0 - utmi_sleep_n 696 * 1 - utmi_l1_suspend_n 697 * @is_fpga: true when we are using the FPGA board 698 * @needs_fifo_resize: not all users might want fifo resizing, flag it 699 * @pullups_connected: true when Run/Stop bit is set 700 * @resize_fifos: tells us it's ok to reconfigure our TxFIFO sizes. 701 * @setup_packet_pending: true when there's a Setup Packet in FIFO. Workaround 702 * @start_config_issued: true when StartConfig command has been issued 703 * @three_stage_setup: set if we perform a three phase setup 704 * @usb3_lpm_capable: set if hadrware supports Link Power Management 705 * @disable_scramble_quirk: set if we enable the disable scramble quirk 706 * @u2exit_lfps_quirk: set if we enable u2exit lfps quirk 707 * @u2ss_inp3_quirk: set if we enable P3 OK for U2/SS Inactive quirk 708 * @req_p1p2p3_quirk: set if we enable request p1p2p3 quirk 709 * @del_p1p2p3_quirk: set if we enable delay p1p2p3 quirk 710 * @del_phy_power_chg_quirk: set if we enable delay phy power change quirk 711 * @lfps_filter_quirk: set if we enable LFPS filter quirk 712 * @rx_detect_poll_quirk: set if we enable rx_detect to polling lfps quirk 713 * @dis_u3_susphy_quirk: set if we disable usb3 suspend phy 714 * @dis_u2_susphy_quirk: set if we disable usb2 suspend phy 715 * @tx_de_emphasis_quirk: set if we enable Tx de-emphasis quirk 716 * @tx_de_emphasis: Tx de-emphasis value 717 * 0 - -6dB de-emphasis 718 * 1 - -3.5dB de-emphasis 719 * 2 - No de-emphasis 720 * 3 - Reserved 721 */ 722 struct dwc3 { 723 struct usb_ctrlrequest *ctrl_req; 724 struct dwc3_trb *ep0_trb; 725 void *ep0_bounce; 726 void *scratchbuf; 727 u8 *setup_buf; 728 dma_addr_t ctrl_req_addr; 729 dma_addr_t ep0_trb_addr; 730 dma_addr_t ep0_bounce_addr; 731 dma_addr_t scratch_addr; 732 struct dwc3_request ep0_usb_req; 733 734 /* device lock */ 735 spinlock_t lock; 736 737 struct device *dev; 738 739 struct platform_device *xhci; 740 struct resource xhci_resources[DWC3_XHCI_RESOURCES_NUM]; 741 742 struct dwc3_event_buffer **ev_buffs; 743 struct dwc3_ep *eps[DWC3_ENDPOINTS_NUM]; 744 745 struct usb_gadget gadget; 746 struct usb_gadget_driver *gadget_driver; 747 748 struct usb_phy *usb2_phy; 749 struct usb_phy *usb3_phy; 750 751 struct phy *usb2_generic_phy; 752 struct phy *usb3_generic_phy; 753 754 struct ulpi *ulpi; 755 756 void __iomem *regs; 757 size_t regs_size; 758 759 enum usb_dr_mode dr_mode; 760 761 /* used for suspend/resume */ 762 u32 dcfg; 763 u32 gctl; 764 765 u32 nr_scratch; 766 u32 num_event_buffers; 767 u32 u1u2; 768 u32 maximum_speed; 769 u32 revision; 770 771 #define DWC3_REVISION_173A 0x5533173a 772 #define DWC3_REVISION_175A 0x5533175a 773 #define DWC3_REVISION_180A 0x5533180a 774 #define DWC3_REVISION_183A 0x5533183a 775 #define DWC3_REVISION_185A 0x5533185a 776 #define DWC3_REVISION_187A 0x5533187a 777 #define DWC3_REVISION_188A 0x5533188a 778 #define DWC3_REVISION_190A 0x5533190a 779 #define DWC3_REVISION_194A 0x5533194a 780 #define DWC3_REVISION_200A 0x5533200a 781 #define DWC3_REVISION_202A 0x5533202a 782 #define DWC3_REVISION_210A 0x5533210a 783 #define DWC3_REVISION_220A 0x5533220a 784 #define DWC3_REVISION_230A 0x5533230a 785 #define DWC3_REVISION_240A 0x5533240a 786 #define DWC3_REVISION_250A 0x5533250a 787 #define DWC3_REVISION_260A 0x5533260a 788 #define DWC3_REVISION_270A 0x5533270a 789 #define DWC3_REVISION_280A 0x5533280a 790 791 enum dwc3_ep0_next ep0_next_event; 792 enum dwc3_ep0_state ep0state; 793 enum dwc3_link_state link_state; 794 795 u16 isoch_delay; 796 u16 u2sel; 797 u16 u2pel; 798 u8 u1sel; 799 u8 u1pel; 800 801 u8 speed; 802 803 u8 num_out_eps; 804 u8 num_in_eps; 805 806 void *mem; 807 808 struct dwc3_hwparams hwparams; 809 struct dentry *root; 810 struct debugfs_regset32 *regset; 811 812 u8 test_mode; 813 u8 test_mode_nr; 814 u8 lpm_nyet_threshold; 815 u8 hird_threshold; 816 817 const char *hsphy_interface; 818 819 unsigned delayed_status:1; 820 unsigned ep0_bounced:1; 821 unsigned ep0_expect_in:1; 822 unsigned has_hibernation:1; 823 unsigned has_lpm_erratum:1; 824 unsigned is_utmi_l1_suspend:1; 825 unsigned is_fpga:1; 826 unsigned needs_fifo_resize:1; 827 unsigned pullups_connected:1; 828 unsigned resize_fifos:1; 829 unsigned setup_packet_pending:1; 830 unsigned start_config_issued:1; 831 unsigned three_stage_setup:1; 832 unsigned usb3_lpm_capable:1; 833 834 unsigned disable_scramble_quirk:1; 835 unsigned u2exit_lfps_quirk:1; 836 unsigned u2ss_inp3_quirk:1; 837 unsigned req_p1p2p3_quirk:1; 838 unsigned del_p1p2p3_quirk:1; 839 unsigned del_phy_power_chg_quirk:1; 840 unsigned lfps_filter_quirk:1; 841 unsigned rx_detect_poll_quirk:1; 842 unsigned dis_u3_susphy_quirk:1; 843 unsigned dis_u2_susphy_quirk:1; 844 845 unsigned tx_de_emphasis_quirk:1; 846 unsigned tx_de_emphasis:2; 847 }; 848 849 /* -------------------------------------------------------------------------- */ 850 851 /* -------------------------------------------------------------------------- */ 852 853 struct dwc3_event_type { 854 u32 is_devspec:1; 855 u32 type:7; 856 u32 reserved8_31:24; 857 } __packed; 858 859 #define DWC3_DEPEVT_XFERCOMPLETE 0x01 860 #define DWC3_DEPEVT_XFERINPROGRESS 0x02 861 #define DWC3_DEPEVT_XFERNOTREADY 0x03 862 #define DWC3_DEPEVT_RXTXFIFOEVT 0x04 863 #define DWC3_DEPEVT_STREAMEVT 0x06 864 #define DWC3_DEPEVT_EPCMDCMPLT 0x07 865 866 /** 867 * struct dwc3_event_depvt - Device Endpoint Events 868 * @one_bit: indicates this is an endpoint event (not used) 869 * @endpoint_number: number of the endpoint 870 * @endpoint_event: The event we have: 871 * 0x00 - Reserved 872 * 0x01 - XferComplete 873 * 0x02 - XferInProgress 874 * 0x03 - XferNotReady 875 * 0x04 - RxTxFifoEvt (IN->Underrun, OUT->Overrun) 876 * 0x05 - Reserved 877 * 0x06 - StreamEvt 878 * 0x07 - EPCmdCmplt 879 * @reserved11_10: Reserved, don't use. 880 * @status: Indicates the status of the event. Refer to databook for 881 * more information. 882 * @parameters: Parameters of the current event. Refer to databook for 883 * more information. 884 */ 885 struct dwc3_event_depevt { 886 u32 one_bit:1; 887 u32 endpoint_number:5; 888 u32 endpoint_event:4; 889 u32 reserved11_10:2; 890 u32 status:4; 891 892 /* Within XferNotReady */ 893 #define DEPEVT_STATUS_TRANSFER_ACTIVE (1 << 3) 894 895 /* Within XferComplete */ 896 #define DEPEVT_STATUS_BUSERR (1 << 0) 897 #define DEPEVT_STATUS_SHORT (1 << 1) 898 #define DEPEVT_STATUS_IOC (1 << 2) 899 #define DEPEVT_STATUS_LST (1 << 3) 900 901 /* Stream event only */ 902 #define DEPEVT_STREAMEVT_FOUND 1 903 #define DEPEVT_STREAMEVT_NOTFOUND 2 904 905 /* Control-only Status */ 906 #define DEPEVT_STATUS_CONTROL_DATA 1 907 #define DEPEVT_STATUS_CONTROL_STATUS 2 908 909 u32 parameters:16; 910 } __packed; 911 912 /** 913 * struct dwc3_event_devt - Device Events 914 * @one_bit: indicates this is a non-endpoint event (not used) 915 * @device_event: indicates it's a device event. Should read as 0x00 916 * @type: indicates the type of device event. 917 * 0 - DisconnEvt 918 * 1 - USBRst 919 * 2 - ConnectDone 920 * 3 - ULStChng 921 * 4 - WkUpEvt 922 * 5 - Reserved 923 * 6 - EOPF 924 * 7 - SOF 925 * 8 - Reserved 926 * 9 - ErrticErr 927 * 10 - CmdCmplt 928 * 11 - EvntOverflow 929 * 12 - VndrDevTstRcved 930 * @reserved15_12: Reserved, not used 931 * @event_info: Information about this event 932 * @reserved31_25: Reserved, not used 933 */ 934 struct dwc3_event_devt { 935 u32 one_bit:1; 936 u32 device_event:7; 937 u32 type:4; 938 u32 reserved15_12:4; 939 u32 event_info:9; 940 u32 reserved31_25:7; 941 } __packed; 942 943 /** 944 * struct dwc3_event_gevt - Other Core Events 945 * @one_bit: indicates this is a non-endpoint event (not used) 946 * @device_event: indicates it's (0x03) Carkit or (0x04) I2C event. 947 * @phy_port_number: self-explanatory 948 * @reserved31_12: Reserved, not used. 949 */ 950 struct dwc3_event_gevt { 951 u32 one_bit:1; 952 u32 device_event:7; 953 u32 phy_port_number:4; 954 u32 reserved31_12:20; 955 } __packed; 956 957 /** 958 * union dwc3_event - representation of Event Buffer contents 959 * @raw: raw 32-bit event 960 * @type: the type of the event 961 * @depevt: Device Endpoint Event 962 * @devt: Device Event 963 * @gevt: Global Event 964 */ 965 union dwc3_event { 966 u32 raw; 967 struct dwc3_event_type type; 968 struct dwc3_event_depevt depevt; 969 struct dwc3_event_devt devt; 970 struct dwc3_event_gevt gevt; 971 }; 972 973 /** 974 * struct dwc3_gadget_ep_cmd_params - representation of endpoint command 975 * parameters 976 * @param2: third parameter 977 * @param1: second parameter 978 * @param0: first parameter 979 */ 980 struct dwc3_gadget_ep_cmd_params { 981 u32 param2; 982 u32 param1; 983 u32 param0; 984 }; 985 986 /* 987 * DWC3 Features to be used as Driver Data 988 */ 989 990 #define DWC3_HAS_PERIPHERAL BIT(0) 991 #define DWC3_HAS_XHCI BIT(1) 992 #define DWC3_HAS_OTG BIT(3) 993 994 /* prototypes */ 995 void dwc3_set_mode(struct dwc3 *dwc, u32 mode); 996 int dwc3_gadget_resize_tx_fifos(struct dwc3 *dwc); 997 998 #if IS_ENABLED(CONFIG_USB_DWC3_HOST) || IS_ENABLED(CONFIG_USB_DWC3_DUAL_ROLE) 999 int dwc3_host_init(struct dwc3 *dwc); 1000 void dwc3_host_exit(struct dwc3 *dwc); 1001 #else 1002 static inline int dwc3_host_init(struct dwc3 *dwc) 1003 { return 0; } 1004 static inline void dwc3_host_exit(struct dwc3 *dwc) 1005 { } 1006 #endif 1007 1008 #if IS_ENABLED(CONFIG_USB_DWC3_GADGET) || IS_ENABLED(CONFIG_USB_DWC3_DUAL_ROLE) 1009 int dwc3_gadget_init(struct dwc3 *dwc); 1010 void dwc3_gadget_exit(struct dwc3 *dwc); 1011 int dwc3_gadget_set_test_mode(struct dwc3 *dwc, int mode); 1012 int dwc3_gadget_get_link_state(struct dwc3 *dwc); 1013 int dwc3_gadget_set_link_state(struct dwc3 *dwc, enum dwc3_link_state state); 1014 int dwc3_send_gadget_ep_cmd(struct dwc3 *dwc, unsigned ep, 1015 unsigned cmd, struct dwc3_gadget_ep_cmd_params *params); 1016 int dwc3_send_gadget_generic_command(struct dwc3 *dwc, unsigned cmd, u32 param); 1017 #else 1018 static inline int dwc3_gadget_init(struct dwc3 *dwc) 1019 { return 0; } 1020 static inline void dwc3_gadget_exit(struct dwc3 *dwc) 1021 { } 1022 static inline int dwc3_gadget_set_test_mode(struct dwc3 *dwc, int mode) 1023 { return 0; } 1024 static inline int dwc3_gadget_get_link_state(struct dwc3 *dwc) 1025 { return 0; } 1026 static inline int dwc3_gadget_set_link_state(struct dwc3 *dwc, 1027 enum dwc3_link_state state) 1028 { return 0; } 1029 1030 static inline int dwc3_send_gadget_ep_cmd(struct dwc3 *dwc, unsigned ep, 1031 unsigned cmd, struct dwc3_gadget_ep_cmd_params *params) 1032 { return 0; } 1033 static inline int dwc3_send_gadget_generic_command(struct dwc3 *dwc, 1034 int cmd, u32 param) 1035 { return 0; } 1036 #endif 1037 1038 /* power management interface */ 1039 #if !IS_ENABLED(CONFIG_USB_DWC3_HOST) 1040 int dwc3_gadget_suspend(struct dwc3 *dwc); 1041 int dwc3_gadget_resume(struct dwc3 *dwc); 1042 #else 1043 static inline int dwc3_gadget_suspend(struct dwc3 *dwc) 1044 { 1045 return 0; 1046 } 1047 1048 static inline int dwc3_gadget_resume(struct dwc3 *dwc) 1049 { 1050 return 0; 1051 } 1052 #endif /* !IS_ENABLED(CONFIG_USB_DWC3_HOST) */ 1053 1054 #if IS_ENABLED(CONFIG_USB_DWC3_ULPI) 1055 int dwc3_ulpi_init(struct dwc3 *dwc); 1056 void dwc3_ulpi_exit(struct dwc3 *dwc); 1057 #else 1058 static inline int dwc3_ulpi_init(struct dwc3 *dwc) 1059 { return 0; } 1060 static inline void dwc3_ulpi_exit(struct dwc3 *dwc) 1061 { } 1062 #endif 1063 1064 #endif /* __DRIVERS_USB_DWC3_CORE_H */ 1065