xref: /openbmc/linux/drivers/usb/dwc3/core.h (revision 2c684d89)
1 /**
2  * core.h - DesignWare USB3 DRD Core Header
3  *
4  * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
5  *
6  * Authors: Felipe Balbi <balbi@ti.com>,
7  *	    Sebastian Andrzej Siewior <bigeasy@linutronix.de>
8  *
9  * This program is free software: you can redistribute it and/or modify
10  * it under the terms of the GNU General Public License version 2  of
11  * the License as published by the Free Software Foundation.
12  *
13  * This program is distributed in the hope that it will be useful,
14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
16  * GNU General Public License for more details.
17  */
18 
19 #ifndef __DRIVERS_USB_DWC3_CORE_H
20 #define __DRIVERS_USB_DWC3_CORE_H
21 
22 #include <linux/device.h>
23 #include <linux/spinlock.h>
24 #include <linux/ioport.h>
25 #include <linux/list.h>
26 #include <linux/dma-mapping.h>
27 #include <linux/mm.h>
28 #include <linux/debugfs.h>
29 
30 #include <linux/usb/ch9.h>
31 #include <linux/usb/gadget.h>
32 #include <linux/usb/otg.h>
33 #include <linux/ulpi/interface.h>
34 
35 #include <linux/phy/phy.h>
36 
37 #define DWC3_MSG_MAX	500
38 
39 /* Global constants */
40 #define DWC3_EP0_BOUNCE_SIZE	512
41 #define DWC3_ENDPOINTS_NUM	32
42 #define DWC3_XHCI_RESOURCES_NUM	2
43 
44 #define DWC3_SCRATCHBUF_SIZE	4096	/* each buffer is assumed to be 4KiB */
45 #define DWC3_EVENT_SIZE		4	/* bytes */
46 #define DWC3_EVENT_MAX_NUM	64	/* 2 events/endpoint */
47 #define DWC3_EVENT_BUFFERS_SIZE	(DWC3_EVENT_SIZE * DWC3_EVENT_MAX_NUM)
48 #define DWC3_EVENT_TYPE_MASK	0xfe
49 
50 #define DWC3_EVENT_TYPE_DEV	0
51 #define DWC3_EVENT_TYPE_CARKIT	3
52 #define DWC3_EVENT_TYPE_I2C	4
53 
54 #define DWC3_DEVICE_EVENT_DISCONNECT		0
55 #define DWC3_DEVICE_EVENT_RESET			1
56 #define DWC3_DEVICE_EVENT_CONNECT_DONE		2
57 #define DWC3_DEVICE_EVENT_LINK_STATUS_CHANGE	3
58 #define DWC3_DEVICE_EVENT_WAKEUP		4
59 #define DWC3_DEVICE_EVENT_HIBER_REQ		5
60 #define DWC3_DEVICE_EVENT_EOPF			6
61 #define DWC3_DEVICE_EVENT_SOF			7
62 #define DWC3_DEVICE_EVENT_ERRATIC_ERROR		9
63 #define DWC3_DEVICE_EVENT_CMD_CMPL		10
64 #define DWC3_DEVICE_EVENT_OVERFLOW		11
65 
66 #define DWC3_GEVNTCOUNT_MASK	0xfffc
67 #define DWC3_GSNPSID_MASK	0xffff0000
68 #define DWC3_GSNPSREV_MASK	0xffff
69 
70 /* DWC3 registers memory space boundries */
71 #define DWC3_XHCI_REGS_START		0x0
72 #define DWC3_XHCI_REGS_END		0x7fff
73 #define DWC3_GLOBALS_REGS_START		0xc100
74 #define DWC3_GLOBALS_REGS_END		0xc6ff
75 #define DWC3_DEVICE_REGS_START		0xc700
76 #define DWC3_DEVICE_REGS_END		0xcbff
77 #define DWC3_OTG_REGS_START		0xcc00
78 #define DWC3_OTG_REGS_END		0xccff
79 
80 /* Global Registers */
81 #define DWC3_GSBUSCFG0		0xc100
82 #define DWC3_GSBUSCFG1		0xc104
83 #define DWC3_GTXTHRCFG		0xc108
84 #define DWC3_GRXTHRCFG		0xc10c
85 #define DWC3_GCTL		0xc110
86 #define DWC3_GEVTEN		0xc114
87 #define DWC3_GSTS		0xc118
88 #define DWC3_GSNPSID		0xc120
89 #define DWC3_GGPIO		0xc124
90 #define DWC3_GUID		0xc128
91 #define DWC3_GUCTL		0xc12c
92 #define DWC3_GBUSERRADDR0	0xc130
93 #define DWC3_GBUSERRADDR1	0xc134
94 #define DWC3_GPRTBIMAP0		0xc138
95 #define DWC3_GPRTBIMAP1		0xc13c
96 #define DWC3_GHWPARAMS0		0xc140
97 #define DWC3_GHWPARAMS1		0xc144
98 #define DWC3_GHWPARAMS2		0xc148
99 #define DWC3_GHWPARAMS3		0xc14c
100 #define DWC3_GHWPARAMS4		0xc150
101 #define DWC3_GHWPARAMS5		0xc154
102 #define DWC3_GHWPARAMS6		0xc158
103 #define DWC3_GHWPARAMS7		0xc15c
104 #define DWC3_GDBGFIFOSPACE	0xc160
105 #define DWC3_GDBGLTSSM		0xc164
106 #define DWC3_GPRTBIMAP_HS0	0xc180
107 #define DWC3_GPRTBIMAP_HS1	0xc184
108 #define DWC3_GPRTBIMAP_FS0	0xc188
109 #define DWC3_GPRTBIMAP_FS1	0xc18c
110 
111 #define DWC3_VER_NUMBER		0xc1a0
112 #define DWC3_VER_TYPE		0xc1a4
113 
114 #define DWC3_GUSB2PHYCFG(n)	(0xc200 + (n * 0x04))
115 #define DWC3_GUSB2I2CCTL(n)	(0xc240 + (n * 0x04))
116 
117 #define DWC3_GUSB2PHYACC(n)	(0xc280 + (n * 0x04))
118 
119 #define DWC3_GUSB3PIPECTL(n)	(0xc2c0 + (n * 0x04))
120 
121 #define DWC3_GTXFIFOSIZ(n)	(0xc300 + (n * 0x04))
122 #define DWC3_GRXFIFOSIZ(n)	(0xc380 + (n * 0x04))
123 
124 #define DWC3_GEVNTADRLO(n)	(0xc400 + (n * 0x10))
125 #define DWC3_GEVNTADRHI(n)	(0xc404 + (n * 0x10))
126 #define DWC3_GEVNTSIZ(n)	(0xc408 + (n * 0x10))
127 #define DWC3_GEVNTCOUNT(n)	(0xc40c + (n * 0x10))
128 
129 #define DWC3_GHWPARAMS8		0xc600
130 #define DWC3_GFLADJ		0xc630
131 
132 /* Device Registers */
133 #define DWC3_DCFG		0xc700
134 #define DWC3_DCTL		0xc704
135 #define DWC3_DEVTEN		0xc708
136 #define DWC3_DSTS		0xc70c
137 #define DWC3_DGCMDPAR		0xc710
138 #define DWC3_DGCMD		0xc714
139 #define DWC3_DALEPENA		0xc720
140 #define DWC3_DEPCMDPAR2(n)	(0xc800 + (n * 0x10))
141 #define DWC3_DEPCMDPAR1(n)	(0xc804 + (n * 0x10))
142 #define DWC3_DEPCMDPAR0(n)	(0xc808 + (n * 0x10))
143 #define DWC3_DEPCMD(n)		(0xc80c + (n * 0x10))
144 
145 /* OTG Registers */
146 #define DWC3_OCFG		0xcc00
147 #define DWC3_OCTL		0xcc04
148 #define DWC3_OEVT		0xcc08
149 #define DWC3_OEVTEN		0xcc0C
150 #define DWC3_OSTS		0xcc10
151 
152 /* Bit fields */
153 
154 /* Global Configuration Register */
155 #define DWC3_GCTL_PWRDNSCALE(n)	((n) << 19)
156 #define DWC3_GCTL_U2RSTECN	(1 << 16)
157 #define DWC3_GCTL_RAMCLKSEL(x)	(((x) & DWC3_GCTL_CLK_MASK) << 6)
158 #define DWC3_GCTL_CLK_BUS	(0)
159 #define DWC3_GCTL_CLK_PIPE	(1)
160 #define DWC3_GCTL_CLK_PIPEHALF	(2)
161 #define DWC3_GCTL_CLK_MASK	(3)
162 
163 #define DWC3_GCTL_PRTCAP(n)	(((n) & (3 << 12)) >> 12)
164 #define DWC3_GCTL_PRTCAPDIR(n)	((n) << 12)
165 #define DWC3_GCTL_PRTCAP_HOST	1
166 #define DWC3_GCTL_PRTCAP_DEVICE	2
167 #define DWC3_GCTL_PRTCAP_OTG	3
168 
169 #define DWC3_GCTL_CORESOFTRESET		(1 << 11)
170 #define DWC3_GCTL_SOFITPSYNC		(1 << 10)
171 #define DWC3_GCTL_SCALEDOWN(n)		((n) << 4)
172 #define DWC3_GCTL_SCALEDOWN_MASK	DWC3_GCTL_SCALEDOWN(3)
173 #define DWC3_GCTL_DISSCRAMBLE		(1 << 3)
174 #define DWC3_GCTL_U2EXIT_LFPS		(1 << 2)
175 #define DWC3_GCTL_GBLHIBERNATIONEN	(1 << 1)
176 #define DWC3_GCTL_DSBLCLKGTNG		(1 << 0)
177 
178 /* Global USB2 PHY Configuration Register */
179 #define DWC3_GUSB2PHYCFG_PHYSOFTRST	(1 << 31)
180 #define DWC3_GUSB2PHYCFG_SUSPHY		(1 << 6)
181 #define DWC3_GUSB2PHYCFG_ULPI_UTMI	(1 << 4)
182 #define DWC3_GUSB2PHYCFG_ENBLSLPM	(1 << 8)
183 
184 /* Global USB2 PHY Vendor Control Register */
185 #define DWC3_GUSB2PHYACC_NEWREGREQ	(1 << 25)
186 #define DWC3_GUSB2PHYACC_BUSY		(1 << 23)
187 #define DWC3_GUSB2PHYACC_WRITE		(1 << 22)
188 #define DWC3_GUSB2PHYACC_ADDR(n)	(n << 16)
189 #define DWC3_GUSB2PHYACC_EXTEND_ADDR(n)	(n << 8)
190 #define DWC3_GUSB2PHYACC_DATA(n)	(n & 0xff)
191 
192 /* Global USB3 PIPE Control Register */
193 #define DWC3_GUSB3PIPECTL_PHYSOFTRST	(1 << 31)
194 #define DWC3_GUSB3PIPECTL_U2SSINP3OK	(1 << 29)
195 #define DWC3_GUSB3PIPECTL_REQP1P2P3	(1 << 24)
196 #define DWC3_GUSB3PIPECTL_DEP1P2P3(n)	((n) << 19)
197 #define DWC3_GUSB3PIPECTL_DEP1P2P3_MASK	DWC3_GUSB3PIPECTL_DEP1P2P3(7)
198 #define DWC3_GUSB3PIPECTL_DEP1P2P3_EN	DWC3_GUSB3PIPECTL_DEP1P2P3(1)
199 #define DWC3_GUSB3PIPECTL_DEPOCHANGE	(1 << 18)
200 #define DWC3_GUSB3PIPECTL_SUSPHY	(1 << 17)
201 #define DWC3_GUSB3PIPECTL_LFPSFILT	(1 << 9)
202 #define DWC3_GUSB3PIPECTL_RX_DETOPOLL	(1 << 8)
203 #define DWC3_GUSB3PIPECTL_TX_DEEPH_MASK	DWC3_GUSB3PIPECTL_TX_DEEPH(3)
204 #define DWC3_GUSB3PIPECTL_TX_DEEPH(n)	((n) << 1)
205 
206 /* Global TX Fifo Size Register */
207 #define DWC3_GTXFIFOSIZ_TXFDEF(n)	((n) & 0xffff)
208 #define DWC3_GTXFIFOSIZ_TXFSTADDR(n)	((n) & 0xffff0000)
209 
210 /* Global Event Size Registers */
211 #define DWC3_GEVNTSIZ_INTMASK		(1 << 31)
212 #define DWC3_GEVNTSIZ_SIZE(n)		((n) & 0xffff)
213 
214 /* Global HWPARAMS1 Register */
215 #define DWC3_GHWPARAMS1_EN_PWROPT(n)	(((n) & (3 << 24)) >> 24)
216 #define DWC3_GHWPARAMS1_EN_PWROPT_NO	0
217 #define DWC3_GHWPARAMS1_EN_PWROPT_CLK	1
218 #define DWC3_GHWPARAMS1_EN_PWROPT_HIB	2
219 #define DWC3_GHWPARAMS1_PWROPT(n)	((n) << 24)
220 #define DWC3_GHWPARAMS1_PWROPT_MASK	DWC3_GHWPARAMS1_PWROPT(3)
221 
222 /* Global HWPARAMS3 Register */
223 #define DWC3_GHWPARAMS3_SSPHY_IFC(n)		((n) & 3)
224 #define DWC3_GHWPARAMS3_SSPHY_IFC_DIS		0
225 #define DWC3_GHWPARAMS3_SSPHY_IFC_ENA		1
226 #define DWC3_GHWPARAMS3_HSPHY_IFC(n)		(((n) & (3 << 2)) >> 2)
227 #define DWC3_GHWPARAMS3_HSPHY_IFC_DIS		0
228 #define DWC3_GHWPARAMS3_HSPHY_IFC_UTMI		1
229 #define DWC3_GHWPARAMS3_HSPHY_IFC_ULPI		2
230 #define DWC3_GHWPARAMS3_HSPHY_IFC_UTMI_ULPI	3
231 #define DWC3_GHWPARAMS3_FSPHY_IFC(n)		(((n) & (3 << 4)) >> 4)
232 #define DWC3_GHWPARAMS3_FSPHY_IFC_DIS		0
233 #define DWC3_GHWPARAMS3_FSPHY_IFC_ENA		1
234 
235 /* Global HWPARAMS4 Register */
236 #define DWC3_GHWPARAMS4_HIBER_SCRATCHBUFS(n)	(((n) & (0x0f << 13)) >> 13)
237 #define DWC3_MAX_HIBER_SCRATCHBUFS		15
238 
239 /* Global HWPARAMS6 Register */
240 #define DWC3_GHWPARAMS6_EN_FPGA			(1 << 7)
241 
242 /* Global Frame Length Adjustment Register */
243 #define DWC3_GFLADJ_30MHZ_SDBND_SEL		(1 << 7)
244 #define DWC3_GFLADJ_30MHZ_MASK			0x3f
245 
246 /* Device Configuration Register */
247 #define DWC3_DCFG_DEVADDR(addr)	((addr) << 3)
248 #define DWC3_DCFG_DEVADDR_MASK	DWC3_DCFG_DEVADDR(0x7f)
249 
250 #define DWC3_DCFG_SPEED_MASK	(7 << 0)
251 #define DWC3_DCFG_SUPERSPEED	(4 << 0)
252 #define DWC3_DCFG_HIGHSPEED	(0 << 0)
253 #define DWC3_DCFG_FULLSPEED2	(1 << 0)
254 #define DWC3_DCFG_LOWSPEED	(2 << 0)
255 #define DWC3_DCFG_FULLSPEED1	(3 << 0)
256 
257 #define DWC3_DCFG_LPM_CAP	(1 << 22)
258 
259 /* Device Control Register */
260 #define DWC3_DCTL_RUN_STOP	(1 << 31)
261 #define DWC3_DCTL_CSFTRST	(1 << 30)
262 #define DWC3_DCTL_LSFTRST	(1 << 29)
263 
264 #define DWC3_DCTL_HIRD_THRES_MASK	(0x1f << 24)
265 #define DWC3_DCTL_HIRD_THRES(n)	((n) << 24)
266 
267 #define DWC3_DCTL_APPL1RES	(1 << 23)
268 
269 /* These apply for core versions 1.87a and earlier */
270 #define DWC3_DCTL_TRGTULST_MASK		(0x0f << 17)
271 #define DWC3_DCTL_TRGTULST(n)		((n) << 17)
272 #define DWC3_DCTL_TRGTULST_U2		(DWC3_DCTL_TRGTULST(2))
273 #define DWC3_DCTL_TRGTULST_U3		(DWC3_DCTL_TRGTULST(3))
274 #define DWC3_DCTL_TRGTULST_SS_DIS	(DWC3_DCTL_TRGTULST(4))
275 #define DWC3_DCTL_TRGTULST_RX_DET	(DWC3_DCTL_TRGTULST(5))
276 #define DWC3_DCTL_TRGTULST_SS_INACT	(DWC3_DCTL_TRGTULST(6))
277 
278 /* These apply for core versions 1.94a and later */
279 #define DWC3_DCTL_LPM_ERRATA_MASK	DWC3_DCTL_LPM_ERRATA(0xf)
280 #define DWC3_DCTL_LPM_ERRATA(n)		((n) << 20)
281 
282 #define DWC3_DCTL_KEEP_CONNECT		(1 << 19)
283 #define DWC3_DCTL_L1_HIBER_EN		(1 << 18)
284 #define DWC3_DCTL_CRS			(1 << 17)
285 #define DWC3_DCTL_CSS			(1 << 16)
286 
287 #define DWC3_DCTL_INITU2ENA		(1 << 12)
288 #define DWC3_DCTL_ACCEPTU2ENA		(1 << 11)
289 #define DWC3_DCTL_INITU1ENA		(1 << 10)
290 #define DWC3_DCTL_ACCEPTU1ENA		(1 << 9)
291 #define DWC3_DCTL_TSTCTRL_MASK		(0xf << 1)
292 
293 #define DWC3_DCTL_ULSTCHNGREQ_MASK	(0x0f << 5)
294 #define DWC3_DCTL_ULSTCHNGREQ(n) (((n) << 5) & DWC3_DCTL_ULSTCHNGREQ_MASK)
295 
296 #define DWC3_DCTL_ULSTCHNG_NO_ACTION	(DWC3_DCTL_ULSTCHNGREQ(0))
297 #define DWC3_DCTL_ULSTCHNG_SS_DISABLED	(DWC3_DCTL_ULSTCHNGREQ(4))
298 #define DWC3_DCTL_ULSTCHNG_RX_DETECT	(DWC3_DCTL_ULSTCHNGREQ(5))
299 #define DWC3_DCTL_ULSTCHNG_SS_INACTIVE	(DWC3_DCTL_ULSTCHNGREQ(6))
300 #define DWC3_DCTL_ULSTCHNG_RECOVERY	(DWC3_DCTL_ULSTCHNGREQ(8))
301 #define DWC3_DCTL_ULSTCHNG_COMPLIANCE	(DWC3_DCTL_ULSTCHNGREQ(10))
302 #define DWC3_DCTL_ULSTCHNG_LOOPBACK	(DWC3_DCTL_ULSTCHNGREQ(11))
303 
304 /* Device Event Enable Register */
305 #define DWC3_DEVTEN_VNDRDEVTSTRCVEDEN	(1 << 12)
306 #define DWC3_DEVTEN_EVNTOVERFLOWEN	(1 << 11)
307 #define DWC3_DEVTEN_CMDCMPLTEN		(1 << 10)
308 #define DWC3_DEVTEN_ERRTICERREN		(1 << 9)
309 #define DWC3_DEVTEN_SOFEN		(1 << 7)
310 #define DWC3_DEVTEN_EOPFEN		(1 << 6)
311 #define DWC3_DEVTEN_HIBERNATIONREQEVTEN	(1 << 5)
312 #define DWC3_DEVTEN_WKUPEVTEN		(1 << 4)
313 #define DWC3_DEVTEN_ULSTCNGEN		(1 << 3)
314 #define DWC3_DEVTEN_CONNECTDONEEN	(1 << 2)
315 #define DWC3_DEVTEN_USBRSTEN		(1 << 1)
316 #define DWC3_DEVTEN_DISCONNEVTEN	(1 << 0)
317 
318 /* Device Status Register */
319 #define DWC3_DSTS_DCNRD			(1 << 29)
320 
321 /* This applies for core versions 1.87a and earlier */
322 #define DWC3_DSTS_PWRUPREQ		(1 << 24)
323 
324 /* These apply for core versions 1.94a and later */
325 #define DWC3_DSTS_RSS			(1 << 25)
326 #define DWC3_DSTS_SSS			(1 << 24)
327 
328 #define DWC3_DSTS_COREIDLE		(1 << 23)
329 #define DWC3_DSTS_DEVCTRLHLT		(1 << 22)
330 
331 #define DWC3_DSTS_USBLNKST_MASK		(0x0f << 18)
332 #define DWC3_DSTS_USBLNKST(n)		(((n) & DWC3_DSTS_USBLNKST_MASK) >> 18)
333 
334 #define DWC3_DSTS_RXFIFOEMPTY		(1 << 17)
335 
336 #define DWC3_DSTS_SOFFN_MASK		(0x3fff << 3)
337 #define DWC3_DSTS_SOFFN(n)		(((n) & DWC3_DSTS_SOFFN_MASK) >> 3)
338 
339 #define DWC3_DSTS_CONNECTSPD		(7 << 0)
340 
341 #define DWC3_DSTS_SUPERSPEED		(4 << 0)
342 #define DWC3_DSTS_HIGHSPEED		(0 << 0)
343 #define DWC3_DSTS_FULLSPEED2		(1 << 0)
344 #define DWC3_DSTS_LOWSPEED		(2 << 0)
345 #define DWC3_DSTS_FULLSPEED1		(3 << 0)
346 
347 /* Device Generic Command Register */
348 #define DWC3_DGCMD_SET_LMP		0x01
349 #define DWC3_DGCMD_SET_PERIODIC_PAR	0x02
350 #define DWC3_DGCMD_XMIT_FUNCTION	0x03
351 
352 /* These apply for core versions 1.94a and later */
353 #define DWC3_DGCMD_SET_SCRATCHPAD_ADDR_LO	0x04
354 #define DWC3_DGCMD_SET_SCRATCHPAD_ADDR_HI	0x05
355 
356 #define DWC3_DGCMD_SELECTED_FIFO_FLUSH	0x09
357 #define DWC3_DGCMD_ALL_FIFO_FLUSH	0x0a
358 #define DWC3_DGCMD_SET_ENDPOINT_NRDY	0x0c
359 #define DWC3_DGCMD_RUN_SOC_BUS_LOOPBACK	0x10
360 
361 #define DWC3_DGCMD_STATUS(n)		(((n) >> 12) & 0x0F)
362 #define DWC3_DGCMD_CMDACT		(1 << 10)
363 #define DWC3_DGCMD_CMDIOC		(1 << 8)
364 
365 /* Device Generic Command Parameter Register */
366 #define DWC3_DGCMDPAR_FORCE_LINKPM_ACCEPT	(1 << 0)
367 #define DWC3_DGCMDPAR_FIFO_NUM(n)		((n) << 0)
368 #define DWC3_DGCMDPAR_RX_FIFO			(0 << 5)
369 #define DWC3_DGCMDPAR_TX_FIFO			(1 << 5)
370 #define DWC3_DGCMDPAR_LOOPBACK_DIS		(0 << 0)
371 #define DWC3_DGCMDPAR_LOOPBACK_ENA		(1 << 0)
372 
373 /* Device Endpoint Command Register */
374 #define DWC3_DEPCMD_PARAM_SHIFT		16
375 #define DWC3_DEPCMD_PARAM(x)		((x) << DWC3_DEPCMD_PARAM_SHIFT)
376 #define DWC3_DEPCMD_GET_RSC_IDX(x)	(((x) >> DWC3_DEPCMD_PARAM_SHIFT) & 0x7f)
377 #define DWC3_DEPCMD_STATUS(x)		(((x) >> 12) & 0x0F)
378 #define DWC3_DEPCMD_HIPRI_FORCERM	(1 << 11)
379 #define DWC3_DEPCMD_CMDACT		(1 << 10)
380 #define DWC3_DEPCMD_CMDIOC		(1 << 8)
381 
382 #define DWC3_DEPCMD_DEPSTARTCFG		(0x09 << 0)
383 #define DWC3_DEPCMD_ENDTRANSFER		(0x08 << 0)
384 #define DWC3_DEPCMD_UPDATETRANSFER	(0x07 << 0)
385 #define DWC3_DEPCMD_STARTTRANSFER	(0x06 << 0)
386 #define DWC3_DEPCMD_CLEARSTALL		(0x05 << 0)
387 #define DWC3_DEPCMD_SETSTALL		(0x04 << 0)
388 /* This applies for core versions 1.90a and earlier */
389 #define DWC3_DEPCMD_GETSEQNUMBER	(0x03 << 0)
390 /* This applies for core versions 1.94a and later */
391 #define DWC3_DEPCMD_GETEPSTATE		(0x03 << 0)
392 #define DWC3_DEPCMD_SETTRANSFRESOURCE	(0x02 << 0)
393 #define DWC3_DEPCMD_SETEPCONFIG		(0x01 << 0)
394 
395 /* The EP number goes 0..31 so ep0 is always out and ep1 is always in */
396 #define DWC3_DALEPENA_EP(n)		(1 << n)
397 
398 #define DWC3_DEPCMD_TYPE_CONTROL	0
399 #define DWC3_DEPCMD_TYPE_ISOC		1
400 #define DWC3_DEPCMD_TYPE_BULK		2
401 #define DWC3_DEPCMD_TYPE_INTR		3
402 
403 /* Structures */
404 
405 struct dwc3_trb;
406 
407 /**
408  * struct dwc3_event_buffer - Software event buffer representation
409  * @buf: _THE_ buffer
410  * @length: size of this buffer
411  * @lpos: event offset
412  * @count: cache of last read event count register
413  * @flags: flags related to this event buffer
414  * @dma: dma_addr_t
415  * @dwc: pointer to DWC controller
416  */
417 struct dwc3_event_buffer {
418 	void			*buf;
419 	unsigned		length;
420 	unsigned int		lpos;
421 	unsigned int		count;
422 	unsigned int		flags;
423 
424 #define DWC3_EVENT_PENDING	BIT(0)
425 
426 	dma_addr_t		dma;
427 
428 	struct dwc3		*dwc;
429 };
430 
431 #define DWC3_EP_FLAG_STALLED	(1 << 0)
432 #define DWC3_EP_FLAG_WEDGED	(1 << 1)
433 
434 #define DWC3_EP_DIRECTION_TX	true
435 #define DWC3_EP_DIRECTION_RX	false
436 
437 #define DWC3_TRB_NUM		32
438 #define DWC3_TRB_MASK		(DWC3_TRB_NUM - 1)
439 
440 /**
441  * struct dwc3_ep - device side endpoint representation
442  * @endpoint: usb endpoint
443  * @request_list: list of requests for this endpoint
444  * @req_queued: list of requests on this ep which have TRBs setup
445  * @trb_pool: array of transaction buffers
446  * @trb_pool_dma: dma address of @trb_pool
447  * @free_slot: next slot which is going to be used
448  * @busy_slot: first slot which is owned by HW
449  * @desc: usb_endpoint_descriptor pointer
450  * @dwc: pointer to DWC controller
451  * @saved_state: ep state saved during hibernation
452  * @flags: endpoint flags (wedged, stalled, ...)
453  * @number: endpoint number (1 - 15)
454  * @type: set to bmAttributes & USB_ENDPOINT_XFERTYPE_MASK
455  * @resource_index: Resource transfer index
456  * @interval: the interval on which the ISOC transfer is started
457  * @name: a human readable name e.g. ep1out-bulk
458  * @direction: true for TX, false for RX
459  * @stream_capable: true when streams are enabled
460  */
461 struct dwc3_ep {
462 	struct usb_ep		endpoint;
463 	struct list_head	request_list;
464 	struct list_head	req_queued;
465 
466 	struct dwc3_trb		*trb_pool;
467 	dma_addr_t		trb_pool_dma;
468 	u32			free_slot;
469 	u32			busy_slot;
470 	const struct usb_ss_ep_comp_descriptor *comp_desc;
471 	struct dwc3		*dwc;
472 
473 	u32			saved_state;
474 	unsigned		flags;
475 #define DWC3_EP_ENABLED		(1 << 0)
476 #define DWC3_EP_STALL		(1 << 1)
477 #define DWC3_EP_WEDGE		(1 << 2)
478 #define DWC3_EP_BUSY		(1 << 4)
479 #define DWC3_EP_PENDING_REQUEST	(1 << 5)
480 #define DWC3_EP_MISSED_ISOC	(1 << 6)
481 
482 	/* This last one is specific to EP0 */
483 #define DWC3_EP0_DIR_IN		(1 << 31)
484 
485 	u8			number;
486 	u8			type;
487 	u8			resource_index;
488 	u32			interval;
489 
490 	char			name[20];
491 
492 	unsigned		direction:1;
493 	unsigned		stream_capable:1;
494 };
495 
496 enum dwc3_phy {
497 	DWC3_PHY_UNKNOWN = 0,
498 	DWC3_PHY_USB3,
499 	DWC3_PHY_USB2,
500 };
501 
502 enum dwc3_ep0_next {
503 	DWC3_EP0_UNKNOWN = 0,
504 	DWC3_EP0_COMPLETE,
505 	DWC3_EP0_NRDY_DATA,
506 	DWC3_EP0_NRDY_STATUS,
507 };
508 
509 enum dwc3_ep0_state {
510 	EP0_UNCONNECTED		= 0,
511 	EP0_SETUP_PHASE,
512 	EP0_DATA_PHASE,
513 	EP0_STATUS_PHASE,
514 };
515 
516 enum dwc3_link_state {
517 	/* In SuperSpeed */
518 	DWC3_LINK_STATE_U0		= 0x00, /* in HS, means ON */
519 	DWC3_LINK_STATE_U1		= 0x01,
520 	DWC3_LINK_STATE_U2		= 0x02, /* in HS, means SLEEP */
521 	DWC3_LINK_STATE_U3		= 0x03, /* in HS, means SUSPEND */
522 	DWC3_LINK_STATE_SS_DIS		= 0x04,
523 	DWC3_LINK_STATE_RX_DET		= 0x05, /* in HS, means Early Suspend */
524 	DWC3_LINK_STATE_SS_INACT	= 0x06,
525 	DWC3_LINK_STATE_POLL		= 0x07,
526 	DWC3_LINK_STATE_RECOV		= 0x08,
527 	DWC3_LINK_STATE_HRESET		= 0x09,
528 	DWC3_LINK_STATE_CMPLY		= 0x0a,
529 	DWC3_LINK_STATE_LPBK		= 0x0b,
530 	DWC3_LINK_STATE_RESET		= 0x0e,
531 	DWC3_LINK_STATE_RESUME		= 0x0f,
532 	DWC3_LINK_STATE_MASK		= 0x0f,
533 };
534 
535 /* TRB Length, PCM and Status */
536 #define DWC3_TRB_SIZE_MASK	(0x00ffffff)
537 #define DWC3_TRB_SIZE_LENGTH(n)	((n) & DWC3_TRB_SIZE_MASK)
538 #define DWC3_TRB_SIZE_PCM1(n)	(((n) & 0x03) << 24)
539 #define DWC3_TRB_SIZE_TRBSTS(n)	(((n) & (0x0f << 28)) >> 28)
540 
541 #define DWC3_TRBSTS_OK			0
542 #define DWC3_TRBSTS_MISSED_ISOC		1
543 #define DWC3_TRBSTS_SETUP_PENDING	2
544 #define DWC3_TRB_STS_XFER_IN_PROG	4
545 
546 /* TRB Control */
547 #define DWC3_TRB_CTRL_HWO		(1 << 0)
548 #define DWC3_TRB_CTRL_LST		(1 << 1)
549 #define DWC3_TRB_CTRL_CHN		(1 << 2)
550 #define DWC3_TRB_CTRL_CSP		(1 << 3)
551 #define DWC3_TRB_CTRL_TRBCTL(n)		(((n) & 0x3f) << 4)
552 #define DWC3_TRB_CTRL_ISP_IMI		(1 << 10)
553 #define DWC3_TRB_CTRL_IOC		(1 << 11)
554 #define DWC3_TRB_CTRL_SID_SOFN(n)	(((n) & 0xffff) << 14)
555 
556 #define DWC3_TRBCTL_NORMAL		DWC3_TRB_CTRL_TRBCTL(1)
557 #define DWC3_TRBCTL_CONTROL_SETUP	DWC3_TRB_CTRL_TRBCTL(2)
558 #define DWC3_TRBCTL_CONTROL_STATUS2	DWC3_TRB_CTRL_TRBCTL(3)
559 #define DWC3_TRBCTL_CONTROL_STATUS3	DWC3_TRB_CTRL_TRBCTL(4)
560 #define DWC3_TRBCTL_CONTROL_DATA	DWC3_TRB_CTRL_TRBCTL(5)
561 #define DWC3_TRBCTL_ISOCHRONOUS_FIRST	DWC3_TRB_CTRL_TRBCTL(6)
562 #define DWC3_TRBCTL_ISOCHRONOUS		DWC3_TRB_CTRL_TRBCTL(7)
563 #define DWC3_TRBCTL_LINK_TRB		DWC3_TRB_CTRL_TRBCTL(8)
564 
565 /**
566  * struct dwc3_trb - transfer request block (hw format)
567  * @bpl: DW0-3
568  * @bph: DW4-7
569  * @size: DW8-B
570  * @trl: DWC-F
571  */
572 struct dwc3_trb {
573 	u32		bpl;
574 	u32		bph;
575 	u32		size;
576 	u32		ctrl;
577 } __packed;
578 
579 /**
580  * dwc3_hwparams - copy of HWPARAMS registers
581  * @hwparams0 - GHWPARAMS0
582  * @hwparams1 - GHWPARAMS1
583  * @hwparams2 - GHWPARAMS2
584  * @hwparams3 - GHWPARAMS3
585  * @hwparams4 - GHWPARAMS4
586  * @hwparams5 - GHWPARAMS5
587  * @hwparams6 - GHWPARAMS6
588  * @hwparams7 - GHWPARAMS7
589  * @hwparams8 - GHWPARAMS8
590  */
591 struct dwc3_hwparams {
592 	u32	hwparams0;
593 	u32	hwparams1;
594 	u32	hwparams2;
595 	u32	hwparams3;
596 	u32	hwparams4;
597 	u32	hwparams5;
598 	u32	hwparams6;
599 	u32	hwparams7;
600 	u32	hwparams8;
601 };
602 
603 /* HWPARAMS0 */
604 #define DWC3_MODE(n)		((n) & 0x7)
605 
606 #define DWC3_MDWIDTH(n)		(((n) & 0xff00) >> 8)
607 
608 /* HWPARAMS1 */
609 #define DWC3_NUM_INT(n)		(((n) & (0x3f << 15)) >> 15)
610 
611 /* HWPARAMS3 */
612 #define DWC3_NUM_IN_EPS_MASK	(0x1f << 18)
613 #define DWC3_NUM_EPS_MASK	(0x3f << 12)
614 #define DWC3_NUM_EPS(p)		(((p)->hwparams3 &		\
615 			(DWC3_NUM_EPS_MASK)) >> 12)
616 #define DWC3_NUM_IN_EPS(p)	(((p)->hwparams3 &		\
617 			(DWC3_NUM_IN_EPS_MASK)) >> 18)
618 
619 /* HWPARAMS7 */
620 #define DWC3_RAM1_DEPTH(n)	((n) & 0xffff)
621 
622 struct dwc3_request {
623 	struct usb_request	request;
624 	struct list_head	list;
625 	struct dwc3_ep		*dep;
626 	u32			start_slot;
627 
628 	u8			epnum;
629 	struct dwc3_trb		*trb;
630 	dma_addr_t		trb_dma;
631 
632 	unsigned		direction:1;
633 	unsigned		mapped:1;
634 	unsigned		queued:1;
635 };
636 
637 /*
638  * struct dwc3_scratchpad_array - hibernation scratchpad array
639  * (format defined by hw)
640  */
641 struct dwc3_scratchpad_array {
642 	__le64	dma_adr[DWC3_MAX_HIBER_SCRATCHBUFS];
643 };
644 
645 /**
646  * struct dwc3 - representation of our controller
647  * @ctrl_req: usb control request which is used for ep0
648  * @ep0_trb: trb which is used for the ctrl_req
649  * @ep0_bounce: bounce buffer for ep0
650  * @setup_buf: used while precessing STD USB requests
651  * @ctrl_req_addr: dma address of ctrl_req
652  * @ep0_trb: dma address of ep0_trb
653  * @ep0_usb_req: dummy req used while handling STD USB requests
654  * @ep0_bounce_addr: dma address of ep0_bounce
655  * @scratch_addr: dma address of scratchbuf
656  * @lock: for synchronizing
657  * @dev: pointer to our struct device
658  * @xhci: pointer to our xHCI child
659  * @event_buffer_list: a list of event buffers
660  * @gadget: device side representation of the peripheral controller
661  * @gadget_driver: pointer to the gadget driver
662  * @regs: base address for our registers
663  * @regs_size: address space size
664  * @nr_scratch: number of scratch buffers
665  * @num_event_buffers: calculated number of event buffers
666  * @u1u2: only used on revisions <1.83a for workaround
667  * @maximum_speed: maximum speed requested (mainly for testing purposes)
668  * @revision: revision register contents
669  * @dr_mode: requested mode of operation
670  * @usb2_phy: pointer to USB2 PHY
671  * @usb3_phy: pointer to USB3 PHY
672  * @usb2_generic_phy: pointer to USB2 PHY
673  * @usb3_generic_phy: pointer to USB3 PHY
674  * @ulpi: pointer to ulpi interface
675  * @dcfg: saved contents of DCFG register
676  * @gctl: saved contents of GCTL register
677  * @isoch_delay: wValue from Set Isochronous Delay request;
678  * @u2sel: parameter from Set SEL request.
679  * @u2pel: parameter from Set SEL request.
680  * @u1sel: parameter from Set SEL request.
681  * @u1pel: parameter from Set SEL request.
682  * @num_out_eps: number of out endpoints
683  * @num_in_eps: number of in endpoints
684  * @ep0_next_event: hold the next expected event
685  * @ep0state: state of endpoint zero
686  * @link_state: link state
687  * @speed: device speed (super, high, full, low)
688  * @mem: points to start of memory which is used for this struct.
689  * @hwparams: copy of hwparams registers
690  * @root: debugfs root folder pointer
691  * @regset: debugfs pointer to regdump file
692  * @test_mode: true when we're entering a USB test mode
693  * @test_mode_nr: test feature selector
694  * @lpm_nyet_threshold: LPM NYET response threshold
695  * @hird_threshold: HIRD threshold
696  * @hsphy_interface: "utmi" or "ulpi"
697  * @delayed_status: true when gadget driver asks for delayed status
698  * @ep0_bounced: true when we used bounce buffer
699  * @ep0_expect_in: true when we expect a DATA IN transfer
700  * @has_hibernation: true when dwc3 was configured with Hibernation
701  * @has_lpm_erratum: true when core was configured with LPM Erratum. Note that
702  *			there's now way for software to detect this in runtime.
703  * @is_utmi_l1_suspend: the core asserts output signal
704  * 	0	- utmi_sleep_n
705  * 	1	- utmi_l1_suspend_n
706  * @is_fpga: true when we are using the FPGA board
707  * @needs_fifo_resize: not all users might want fifo resizing, flag it
708  * @pullups_connected: true when Run/Stop bit is set
709  * @resize_fifos: tells us it's ok to reconfigure our TxFIFO sizes.
710  * @setup_packet_pending: true when there's a Setup Packet in FIFO. Workaround
711  * @start_config_issued: true when StartConfig command has been issued
712  * @three_stage_setup: set if we perform a three phase setup
713  * @usb3_lpm_capable: set if hadrware supports Link Power Management
714  * @disable_scramble_quirk: set if we enable the disable scramble quirk
715  * @u2exit_lfps_quirk: set if we enable u2exit lfps quirk
716  * @u2ss_inp3_quirk: set if we enable P3 OK for U2/SS Inactive quirk
717  * @req_p1p2p3_quirk: set if we enable request p1p2p3 quirk
718  * @del_p1p2p3_quirk: set if we enable delay p1p2p3 quirk
719  * @del_phy_power_chg_quirk: set if we enable delay phy power change quirk
720  * @lfps_filter_quirk: set if we enable LFPS filter quirk
721  * @rx_detect_poll_quirk: set if we enable rx_detect to polling lfps quirk
722  * @dis_u3_susphy_quirk: set if we disable usb3 suspend phy
723  * @dis_u2_susphy_quirk: set if we disable usb2 suspend phy
724  * @dis_enblslpm_quirk: set if we clear enblslpm in GUSB2PHYCFG,
725  *                      disabling the suspend signal to the PHY.
726  * @tx_de_emphasis_quirk: set if we enable Tx de-emphasis quirk
727  * @tx_de_emphasis: Tx de-emphasis value
728  * 	0	- -6dB de-emphasis
729  * 	1	- -3.5dB de-emphasis
730  * 	2	- No de-emphasis
731  * 	3	- Reserved
732  */
733 struct dwc3 {
734 	struct usb_ctrlrequest	*ctrl_req;
735 	struct dwc3_trb		*ep0_trb;
736 	void			*ep0_bounce;
737 	void			*scratchbuf;
738 	u8			*setup_buf;
739 	dma_addr_t		ctrl_req_addr;
740 	dma_addr_t		ep0_trb_addr;
741 	dma_addr_t		ep0_bounce_addr;
742 	dma_addr_t		scratch_addr;
743 	struct dwc3_request	ep0_usb_req;
744 
745 	/* device lock */
746 	spinlock_t		lock;
747 
748 	struct device		*dev;
749 
750 	struct platform_device	*xhci;
751 	struct resource		xhci_resources[DWC3_XHCI_RESOURCES_NUM];
752 
753 	struct dwc3_event_buffer **ev_buffs;
754 	struct dwc3_ep		*eps[DWC3_ENDPOINTS_NUM];
755 
756 	struct usb_gadget	gadget;
757 	struct usb_gadget_driver *gadget_driver;
758 
759 	struct usb_phy		*usb2_phy;
760 	struct usb_phy		*usb3_phy;
761 
762 	struct phy		*usb2_generic_phy;
763 	struct phy		*usb3_generic_phy;
764 
765 	struct ulpi		*ulpi;
766 
767 	void __iomem		*regs;
768 	size_t			regs_size;
769 
770 	enum usb_dr_mode	dr_mode;
771 
772 	/* used for suspend/resume */
773 	u32			dcfg;
774 	u32			gctl;
775 
776 	u32			nr_scratch;
777 	u32			num_event_buffers;
778 	u32			u1u2;
779 	u32			maximum_speed;
780 
781 	/*
782 	 * All 3.1 IP version constants are greater than the 3.0 IP
783 	 * version constants. This works for most version checks in
784 	 * dwc3. However, in the future, this may not apply as
785 	 * features may be developed on newer versions of the 3.0 IP
786 	 * that are not in the 3.1 IP.
787 	 */
788 	u32			revision;
789 
790 #define DWC3_REVISION_173A	0x5533173a
791 #define DWC3_REVISION_175A	0x5533175a
792 #define DWC3_REVISION_180A	0x5533180a
793 #define DWC3_REVISION_183A	0x5533183a
794 #define DWC3_REVISION_185A	0x5533185a
795 #define DWC3_REVISION_187A	0x5533187a
796 #define DWC3_REVISION_188A	0x5533188a
797 #define DWC3_REVISION_190A	0x5533190a
798 #define DWC3_REVISION_194A	0x5533194a
799 #define DWC3_REVISION_200A	0x5533200a
800 #define DWC3_REVISION_202A	0x5533202a
801 #define DWC3_REVISION_210A	0x5533210a
802 #define DWC3_REVISION_220A	0x5533220a
803 #define DWC3_REVISION_230A	0x5533230a
804 #define DWC3_REVISION_240A	0x5533240a
805 #define DWC3_REVISION_250A	0x5533250a
806 #define DWC3_REVISION_260A	0x5533260a
807 #define DWC3_REVISION_270A	0x5533270a
808 #define DWC3_REVISION_280A	0x5533280a
809 
810 /*
811  * NOTICE: we're using bit 31 as a "is usb 3.1" flag. This is really
812  * just so dwc31 revisions are always larger than dwc3.
813  */
814 #define DWC3_REVISION_IS_DWC31		0x80000000
815 #define DWC3_USB31_REVISION_110A	(0x3131302a | DWC3_REVISION_IS_USB31)
816 
817 	enum dwc3_ep0_next	ep0_next_event;
818 	enum dwc3_ep0_state	ep0state;
819 	enum dwc3_link_state	link_state;
820 
821 	u16			isoch_delay;
822 	u16			u2sel;
823 	u16			u2pel;
824 	u8			u1sel;
825 	u8			u1pel;
826 
827 	u8			speed;
828 
829 	u8			num_out_eps;
830 	u8			num_in_eps;
831 
832 	void			*mem;
833 
834 	struct dwc3_hwparams	hwparams;
835 	struct dentry		*root;
836 	struct debugfs_regset32	*regset;
837 
838 	u8			test_mode;
839 	u8			test_mode_nr;
840 	u8			lpm_nyet_threshold;
841 	u8			hird_threshold;
842 
843 	const char		*hsphy_interface;
844 
845 	unsigned		delayed_status:1;
846 	unsigned		ep0_bounced:1;
847 	unsigned		ep0_expect_in:1;
848 	unsigned		has_hibernation:1;
849 	unsigned		has_lpm_erratum:1;
850 	unsigned		is_utmi_l1_suspend:1;
851 	unsigned		is_fpga:1;
852 	unsigned		needs_fifo_resize:1;
853 	unsigned		pullups_connected:1;
854 	unsigned		resize_fifos:1;
855 	unsigned		setup_packet_pending:1;
856 	unsigned		start_config_issued:1;
857 	unsigned		three_stage_setup:1;
858 	unsigned		usb3_lpm_capable:1;
859 
860 	unsigned		disable_scramble_quirk:1;
861 	unsigned		u2exit_lfps_quirk:1;
862 	unsigned		u2ss_inp3_quirk:1;
863 	unsigned		req_p1p2p3_quirk:1;
864 	unsigned                del_p1p2p3_quirk:1;
865 	unsigned		del_phy_power_chg_quirk:1;
866 	unsigned		lfps_filter_quirk:1;
867 	unsigned		rx_detect_poll_quirk:1;
868 	unsigned		dis_u3_susphy_quirk:1;
869 	unsigned		dis_u2_susphy_quirk:1;
870 	unsigned		dis_enblslpm_quirk:1;
871 
872 	unsigned		tx_de_emphasis_quirk:1;
873 	unsigned		tx_de_emphasis:2;
874 };
875 
876 /* -------------------------------------------------------------------------- */
877 
878 /* -------------------------------------------------------------------------- */
879 
880 struct dwc3_event_type {
881 	u32	is_devspec:1;
882 	u32	type:7;
883 	u32	reserved8_31:24;
884 } __packed;
885 
886 #define DWC3_DEPEVT_XFERCOMPLETE	0x01
887 #define DWC3_DEPEVT_XFERINPROGRESS	0x02
888 #define DWC3_DEPEVT_XFERNOTREADY	0x03
889 #define DWC3_DEPEVT_RXTXFIFOEVT		0x04
890 #define DWC3_DEPEVT_STREAMEVT		0x06
891 #define DWC3_DEPEVT_EPCMDCMPLT		0x07
892 
893 /**
894  * struct dwc3_event_depvt - Device Endpoint Events
895  * @one_bit: indicates this is an endpoint event (not used)
896  * @endpoint_number: number of the endpoint
897  * @endpoint_event: The event we have:
898  *	0x00	- Reserved
899  *	0x01	- XferComplete
900  *	0x02	- XferInProgress
901  *	0x03	- XferNotReady
902  *	0x04	- RxTxFifoEvt (IN->Underrun, OUT->Overrun)
903  *	0x05	- Reserved
904  *	0x06	- StreamEvt
905  *	0x07	- EPCmdCmplt
906  * @reserved11_10: Reserved, don't use.
907  * @status: Indicates the status of the event. Refer to databook for
908  *	more information.
909  * @parameters: Parameters of the current event. Refer to databook for
910  *	more information.
911  */
912 struct dwc3_event_depevt {
913 	u32	one_bit:1;
914 	u32	endpoint_number:5;
915 	u32	endpoint_event:4;
916 	u32	reserved11_10:2;
917 	u32	status:4;
918 
919 /* Within XferNotReady */
920 #define DEPEVT_STATUS_TRANSFER_ACTIVE	(1 << 3)
921 
922 /* Within XferComplete */
923 #define DEPEVT_STATUS_BUSERR	(1 << 0)
924 #define DEPEVT_STATUS_SHORT	(1 << 1)
925 #define DEPEVT_STATUS_IOC	(1 << 2)
926 #define DEPEVT_STATUS_LST	(1 << 3)
927 
928 /* Stream event only */
929 #define DEPEVT_STREAMEVT_FOUND		1
930 #define DEPEVT_STREAMEVT_NOTFOUND	2
931 
932 /* Control-only Status */
933 #define DEPEVT_STATUS_CONTROL_DATA	1
934 #define DEPEVT_STATUS_CONTROL_STATUS	2
935 
936 	u32	parameters:16;
937 } __packed;
938 
939 /**
940  * struct dwc3_event_devt - Device Events
941  * @one_bit: indicates this is a non-endpoint event (not used)
942  * @device_event: indicates it's a device event. Should read as 0x00
943  * @type: indicates the type of device event.
944  *	0	- DisconnEvt
945  *	1	- USBRst
946  *	2	- ConnectDone
947  *	3	- ULStChng
948  *	4	- WkUpEvt
949  *	5	- Reserved
950  *	6	- EOPF
951  *	7	- SOF
952  *	8	- Reserved
953  *	9	- ErrticErr
954  *	10	- CmdCmplt
955  *	11	- EvntOverflow
956  *	12	- VndrDevTstRcved
957  * @reserved15_12: Reserved, not used
958  * @event_info: Information about this event
959  * @reserved31_25: Reserved, not used
960  */
961 struct dwc3_event_devt {
962 	u32	one_bit:1;
963 	u32	device_event:7;
964 	u32	type:4;
965 	u32	reserved15_12:4;
966 	u32	event_info:9;
967 	u32	reserved31_25:7;
968 } __packed;
969 
970 /**
971  * struct dwc3_event_gevt - Other Core Events
972  * @one_bit: indicates this is a non-endpoint event (not used)
973  * @device_event: indicates it's (0x03) Carkit or (0x04) I2C event.
974  * @phy_port_number: self-explanatory
975  * @reserved31_12: Reserved, not used.
976  */
977 struct dwc3_event_gevt {
978 	u32	one_bit:1;
979 	u32	device_event:7;
980 	u32	phy_port_number:4;
981 	u32	reserved31_12:20;
982 } __packed;
983 
984 /**
985  * union dwc3_event - representation of Event Buffer contents
986  * @raw: raw 32-bit event
987  * @type: the type of the event
988  * @depevt: Device Endpoint Event
989  * @devt: Device Event
990  * @gevt: Global Event
991  */
992 union dwc3_event {
993 	u32				raw;
994 	struct dwc3_event_type		type;
995 	struct dwc3_event_depevt	depevt;
996 	struct dwc3_event_devt		devt;
997 	struct dwc3_event_gevt		gevt;
998 };
999 
1000 /**
1001  * struct dwc3_gadget_ep_cmd_params - representation of endpoint command
1002  * parameters
1003  * @param2: third parameter
1004  * @param1: second parameter
1005  * @param0: first parameter
1006  */
1007 struct dwc3_gadget_ep_cmd_params {
1008 	u32	param2;
1009 	u32	param1;
1010 	u32	param0;
1011 };
1012 
1013 /*
1014  * DWC3 Features to be used as Driver Data
1015  */
1016 
1017 #define DWC3_HAS_PERIPHERAL		BIT(0)
1018 #define DWC3_HAS_XHCI			BIT(1)
1019 #define DWC3_HAS_OTG			BIT(3)
1020 
1021 /* prototypes */
1022 void dwc3_set_mode(struct dwc3 *dwc, u32 mode);
1023 int dwc3_gadget_resize_tx_fifos(struct dwc3 *dwc);
1024 
1025 #if IS_ENABLED(CONFIG_USB_DWC3_HOST) || IS_ENABLED(CONFIG_USB_DWC3_DUAL_ROLE)
1026 int dwc3_host_init(struct dwc3 *dwc);
1027 void dwc3_host_exit(struct dwc3 *dwc);
1028 #else
1029 static inline int dwc3_host_init(struct dwc3 *dwc)
1030 { return 0; }
1031 static inline void dwc3_host_exit(struct dwc3 *dwc)
1032 { }
1033 #endif
1034 
1035 #if IS_ENABLED(CONFIG_USB_DWC3_GADGET) || IS_ENABLED(CONFIG_USB_DWC3_DUAL_ROLE)
1036 int dwc3_gadget_init(struct dwc3 *dwc);
1037 void dwc3_gadget_exit(struct dwc3 *dwc);
1038 int dwc3_gadget_set_test_mode(struct dwc3 *dwc, int mode);
1039 int dwc3_gadget_get_link_state(struct dwc3 *dwc);
1040 int dwc3_gadget_set_link_state(struct dwc3 *dwc, enum dwc3_link_state state);
1041 int dwc3_send_gadget_ep_cmd(struct dwc3 *dwc, unsigned ep,
1042 		unsigned cmd, struct dwc3_gadget_ep_cmd_params *params);
1043 int dwc3_send_gadget_generic_command(struct dwc3 *dwc, unsigned cmd, u32 param);
1044 #else
1045 static inline int dwc3_gadget_init(struct dwc3 *dwc)
1046 { return 0; }
1047 static inline void dwc3_gadget_exit(struct dwc3 *dwc)
1048 { }
1049 static inline int dwc3_gadget_set_test_mode(struct dwc3 *dwc, int mode)
1050 { return 0; }
1051 static inline int dwc3_gadget_get_link_state(struct dwc3 *dwc)
1052 { return 0; }
1053 static inline int dwc3_gadget_set_link_state(struct dwc3 *dwc,
1054 		enum dwc3_link_state state)
1055 { return 0; }
1056 
1057 static inline int dwc3_send_gadget_ep_cmd(struct dwc3 *dwc, unsigned ep,
1058 		unsigned cmd, struct dwc3_gadget_ep_cmd_params *params)
1059 { return 0; }
1060 static inline int dwc3_send_gadget_generic_command(struct dwc3 *dwc,
1061 		int cmd, u32 param)
1062 { return 0; }
1063 #endif
1064 
1065 /* power management interface */
1066 #if !IS_ENABLED(CONFIG_USB_DWC3_HOST)
1067 int dwc3_gadget_suspend(struct dwc3 *dwc);
1068 int dwc3_gadget_resume(struct dwc3 *dwc);
1069 #else
1070 static inline int dwc3_gadget_suspend(struct dwc3 *dwc)
1071 {
1072 	return 0;
1073 }
1074 
1075 static inline int dwc3_gadget_resume(struct dwc3 *dwc)
1076 {
1077 	return 0;
1078 }
1079 #endif /* !IS_ENABLED(CONFIG_USB_DWC3_HOST) */
1080 
1081 #if IS_ENABLED(CONFIG_USB_DWC3_ULPI)
1082 int dwc3_ulpi_init(struct dwc3 *dwc);
1083 void dwc3_ulpi_exit(struct dwc3 *dwc);
1084 #else
1085 static inline int dwc3_ulpi_init(struct dwc3 *dwc)
1086 { return 0; }
1087 static inline void dwc3_ulpi_exit(struct dwc3 *dwc)
1088 { }
1089 #endif
1090 
1091 #endif /* __DRIVERS_USB_DWC3_CORE_H */
1092