1 /** 2 * core.h - DesignWare USB3 DRD Core Header 3 * 4 * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com 5 * 6 * Authors: Felipe Balbi <balbi@ti.com>, 7 * Sebastian Andrzej Siewior <bigeasy@linutronix.de> 8 * 9 * This program is free software: you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License version 2 of 11 * the License as published by the Free Software Foundation. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 */ 18 19 #ifndef __DRIVERS_USB_DWC3_CORE_H 20 #define __DRIVERS_USB_DWC3_CORE_H 21 22 #include <linux/device.h> 23 #include <linux/spinlock.h> 24 #include <linux/ioport.h> 25 #include <linux/list.h> 26 #include <linux/dma-mapping.h> 27 #include <linux/mm.h> 28 #include <linux/debugfs.h> 29 30 #include <linux/usb/ch9.h> 31 #include <linux/usb/gadget.h> 32 #include <linux/usb/otg.h> 33 34 #include <linux/phy/phy.h> 35 36 /* Global constants */ 37 #define DWC3_EP0_BOUNCE_SIZE 512 38 #define DWC3_ENDPOINTS_NUM 32 39 #define DWC3_XHCI_RESOURCES_NUM 2 40 41 #define DWC3_SCRATCHBUF_SIZE 4096 /* each buffer is assumed to be 4KiB */ 42 #define DWC3_EVENT_SIZE 4 /* bytes */ 43 #define DWC3_EVENT_MAX_NUM 64 /* 2 events/endpoint */ 44 #define DWC3_EVENT_BUFFERS_SIZE (DWC3_EVENT_SIZE * DWC3_EVENT_MAX_NUM) 45 #define DWC3_EVENT_TYPE_MASK 0xfe 46 47 #define DWC3_EVENT_TYPE_DEV 0 48 #define DWC3_EVENT_TYPE_CARKIT 3 49 #define DWC3_EVENT_TYPE_I2C 4 50 51 #define DWC3_DEVICE_EVENT_DISCONNECT 0 52 #define DWC3_DEVICE_EVENT_RESET 1 53 #define DWC3_DEVICE_EVENT_CONNECT_DONE 2 54 #define DWC3_DEVICE_EVENT_LINK_STATUS_CHANGE 3 55 #define DWC3_DEVICE_EVENT_WAKEUP 4 56 #define DWC3_DEVICE_EVENT_HIBER_REQ 5 57 #define DWC3_DEVICE_EVENT_EOPF 6 58 #define DWC3_DEVICE_EVENT_SOF 7 59 #define DWC3_DEVICE_EVENT_ERRATIC_ERROR 9 60 #define DWC3_DEVICE_EVENT_CMD_CMPL 10 61 #define DWC3_DEVICE_EVENT_OVERFLOW 11 62 63 #define DWC3_GEVNTCOUNT_MASK 0xfffc 64 #define DWC3_GSNPSID_MASK 0xffff0000 65 #define DWC3_GSNPSREV_MASK 0xffff 66 67 /* DWC3 registers memory space boundries */ 68 #define DWC3_XHCI_REGS_START 0x0 69 #define DWC3_XHCI_REGS_END 0x7fff 70 #define DWC3_GLOBALS_REGS_START 0xc100 71 #define DWC3_GLOBALS_REGS_END 0xc6ff 72 #define DWC3_DEVICE_REGS_START 0xc700 73 #define DWC3_DEVICE_REGS_END 0xcbff 74 #define DWC3_OTG_REGS_START 0xcc00 75 #define DWC3_OTG_REGS_END 0xccff 76 77 /* Global Registers */ 78 #define DWC3_GSBUSCFG0 0xc100 79 #define DWC3_GSBUSCFG1 0xc104 80 #define DWC3_GTXTHRCFG 0xc108 81 #define DWC3_GRXTHRCFG 0xc10c 82 #define DWC3_GCTL 0xc110 83 #define DWC3_GEVTEN 0xc114 84 #define DWC3_GSTS 0xc118 85 #define DWC3_GSNPSID 0xc120 86 #define DWC3_GGPIO 0xc124 87 #define DWC3_GUID 0xc128 88 #define DWC3_GUCTL 0xc12c 89 #define DWC3_GBUSERRADDR0 0xc130 90 #define DWC3_GBUSERRADDR1 0xc134 91 #define DWC3_GPRTBIMAP0 0xc138 92 #define DWC3_GPRTBIMAP1 0xc13c 93 #define DWC3_GHWPARAMS0 0xc140 94 #define DWC3_GHWPARAMS1 0xc144 95 #define DWC3_GHWPARAMS2 0xc148 96 #define DWC3_GHWPARAMS3 0xc14c 97 #define DWC3_GHWPARAMS4 0xc150 98 #define DWC3_GHWPARAMS5 0xc154 99 #define DWC3_GHWPARAMS6 0xc158 100 #define DWC3_GHWPARAMS7 0xc15c 101 #define DWC3_GDBGFIFOSPACE 0xc160 102 #define DWC3_GDBGLTSSM 0xc164 103 #define DWC3_GPRTBIMAP_HS0 0xc180 104 #define DWC3_GPRTBIMAP_HS1 0xc184 105 #define DWC3_GPRTBIMAP_FS0 0xc188 106 #define DWC3_GPRTBIMAP_FS1 0xc18c 107 108 #define DWC3_GUSB2PHYCFG(n) (0xc200 + (n * 0x04)) 109 #define DWC3_GUSB2I2CCTL(n) (0xc240 + (n * 0x04)) 110 111 #define DWC3_GUSB2PHYACC(n) (0xc280 + (n * 0x04)) 112 113 #define DWC3_GUSB3PIPECTL(n) (0xc2c0 + (n * 0x04)) 114 115 #define DWC3_GTXFIFOSIZ(n) (0xc300 + (n * 0x04)) 116 #define DWC3_GRXFIFOSIZ(n) (0xc380 + (n * 0x04)) 117 118 #define DWC3_GEVNTADRLO(n) (0xc400 + (n * 0x10)) 119 #define DWC3_GEVNTADRHI(n) (0xc404 + (n * 0x10)) 120 #define DWC3_GEVNTSIZ(n) (0xc408 + (n * 0x10)) 121 #define DWC3_GEVNTCOUNT(n) (0xc40c + (n * 0x10)) 122 123 #define DWC3_GHWPARAMS8 0xc600 124 125 /* Device Registers */ 126 #define DWC3_DCFG 0xc700 127 #define DWC3_DCTL 0xc704 128 #define DWC3_DEVTEN 0xc708 129 #define DWC3_DSTS 0xc70c 130 #define DWC3_DGCMDPAR 0xc710 131 #define DWC3_DGCMD 0xc714 132 #define DWC3_DALEPENA 0xc720 133 #define DWC3_DEPCMDPAR2(n) (0xc800 + (n * 0x10)) 134 #define DWC3_DEPCMDPAR1(n) (0xc804 + (n * 0x10)) 135 #define DWC3_DEPCMDPAR0(n) (0xc808 + (n * 0x10)) 136 #define DWC3_DEPCMD(n) (0xc80c + (n * 0x10)) 137 138 /* OTG Registers */ 139 #define DWC3_OCFG 0xcc00 140 #define DWC3_OCTL 0xcc04 141 #define DWC3_OEVT 0xcc08 142 #define DWC3_OEVTEN 0xcc0C 143 #define DWC3_OSTS 0xcc10 144 145 /* Bit fields */ 146 147 /* Global Configuration Register */ 148 #define DWC3_GCTL_PWRDNSCALE(n) ((n) << 19) 149 #define DWC3_GCTL_U2RSTECN (1 << 16) 150 #define DWC3_GCTL_RAMCLKSEL(x) (((x) & DWC3_GCTL_CLK_MASK) << 6) 151 #define DWC3_GCTL_CLK_BUS (0) 152 #define DWC3_GCTL_CLK_PIPE (1) 153 #define DWC3_GCTL_CLK_PIPEHALF (2) 154 #define DWC3_GCTL_CLK_MASK (3) 155 156 #define DWC3_GCTL_PRTCAP(n) (((n) & (3 << 12)) >> 12) 157 #define DWC3_GCTL_PRTCAPDIR(n) ((n) << 12) 158 #define DWC3_GCTL_PRTCAP_HOST 1 159 #define DWC3_GCTL_PRTCAP_DEVICE 2 160 #define DWC3_GCTL_PRTCAP_OTG 3 161 162 #define DWC3_GCTL_CORESOFTRESET (1 << 11) 163 #define DWC3_GCTL_SOFITPSYNC (1 << 10) 164 #define DWC3_GCTL_SCALEDOWN(n) ((n) << 4) 165 #define DWC3_GCTL_SCALEDOWN_MASK DWC3_GCTL_SCALEDOWN(3) 166 #define DWC3_GCTL_DISSCRAMBLE (1 << 3) 167 #define DWC3_GCTL_GBLHIBERNATIONEN (1 << 1) 168 #define DWC3_GCTL_DSBLCLKGTNG (1 << 0) 169 170 /* Global USB2 PHY Configuration Register */ 171 #define DWC3_GUSB2PHYCFG_PHYSOFTRST (1 << 31) 172 #define DWC3_GUSB2PHYCFG_SUSPHY (1 << 6) 173 174 /* Global USB3 PIPE Control Register */ 175 #define DWC3_GUSB3PIPECTL_PHYSOFTRST (1 << 31) 176 #define DWC3_GUSB3PIPECTL_SUSPHY (1 << 17) 177 178 /* Global TX Fifo Size Register */ 179 #define DWC3_GTXFIFOSIZ_TXFDEF(n) ((n) & 0xffff) 180 #define DWC3_GTXFIFOSIZ_TXFSTADDR(n) ((n) & 0xffff0000) 181 182 /* Global Event Size Registers */ 183 #define DWC3_GEVNTSIZ_INTMASK (1 << 31) 184 #define DWC3_GEVNTSIZ_SIZE(n) ((n) & 0xffff) 185 186 /* Global HWPARAMS1 Register */ 187 #define DWC3_GHWPARAMS1_EN_PWROPT(n) (((n) & (3 << 24)) >> 24) 188 #define DWC3_GHWPARAMS1_EN_PWROPT_NO 0 189 #define DWC3_GHWPARAMS1_EN_PWROPT_CLK 1 190 #define DWC3_GHWPARAMS1_EN_PWROPT_HIB 2 191 #define DWC3_GHWPARAMS1_PWROPT(n) ((n) << 24) 192 #define DWC3_GHWPARAMS1_PWROPT_MASK DWC3_GHWPARAMS1_PWROPT(3) 193 194 /* Global HWPARAMS3 Register */ 195 #define DWC3_GHWPARAMS3_SSPHY_IFC(n) ((n) & 3) 196 #define DWC3_GHWPARAMS3_SSPHY_IFC_DIS 0 197 #define DWC3_GHWPARAMS3_SSPHY_IFC_ENA 1 198 #define DWC3_GHWPARAMS3_HSPHY_IFC(n) (((n) & (3 << 2)) >> 2) 199 #define DWC3_GHWPARAMS3_HSPHY_IFC_DIS 0 200 #define DWC3_GHWPARAMS3_HSPHY_IFC_UTMI 1 201 #define DWC3_GHWPARAMS3_HSPHY_IFC_ULPI 2 202 #define DWC3_GHWPARAMS3_HSPHY_IFC_UTMI_ULPI 3 203 #define DWC3_GHWPARAMS3_FSPHY_IFC(n) (((n) & (3 << 4)) >> 4) 204 #define DWC3_GHWPARAMS3_FSPHY_IFC_DIS 0 205 #define DWC3_GHWPARAMS3_FSPHY_IFC_ENA 1 206 207 /* Global HWPARAMS4 Register */ 208 #define DWC3_GHWPARAMS4_HIBER_SCRATCHBUFS(n) (((n) & (0x0f << 13)) >> 13) 209 #define DWC3_MAX_HIBER_SCRATCHBUFS 15 210 211 /* Device Configuration Register */ 212 #define DWC3_DCFG_DEVADDR(addr) ((addr) << 3) 213 #define DWC3_DCFG_DEVADDR_MASK DWC3_DCFG_DEVADDR(0x7f) 214 215 #define DWC3_DCFG_SPEED_MASK (7 << 0) 216 #define DWC3_DCFG_SUPERSPEED (4 << 0) 217 #define DWC3_DCFG_HIGHSPEED (0 << 0) 218 #define DWC3_DCFG_FULLSPEED2 (1 << 0) 219 #define DWC3_DCFG_LOWSPEED (2 << 0) 220 #define DWC3_DCFG_FULLSPEED1 (3 << 0) 221 222 #define DWC3_DCFG_LPM_CAP (1 << 22) 223 224 /* Device Control Register */ 225 #define DWC3_DCTL_RUN_STOP (1 << 31) 226 #define DWC3_DCTL_CSFTRST (1 << 30) 227 #define DWC3_DCTL_LSFTRST (1 << 29) 228 229 #define DWC3_DCTL_HIRD_THRES_MASK (0x1f << 24) 230 #define DWC3_DCTL_HIRD_THRES(n) ((n) << 24) 231 232 #define DWC3_DCTL_APPL1RES (1 << 23) 233 234 /* These apply for core versions 1.87a and earlier */ 235 #define DWC3_DCTL_TRGTULST_MASK (0x0f << 17) 236 #define DWC3_DCTL_TRGTULST(n) ((n) << 17) 237 #define DWC3_DCTL_TRGTULST_U2 (DWC3_DCTL_TRGTULST(2)) 238 #define DWC3_DCTL_TRGTULST_U3 (DWC3_DCTL_TRGTULST(3)) 239 #define DWC3_DCTL_TRGTULST_SS_DIS (DWC3_DCTL_TRGTULST(4)) 240 #define DWC3_DCTL_TRGTULST_RX_DET (DWC3_DCTL_TRGTULST(5)) 241 #define DWC3_DCTL_TRGTULST_SS_INACT (DWC3_DCTL_TRGTULST(6)) 242 243 /* These apply for core versions 1.94a and later */ 244 #define DWC3_DCTL_KEEP_CONNECT (1 << 19) 245 #define DWC3_DCTL_L1_HIBER_EN (1 << 18) 246 #define DWC3_DCTL_CRS (1 << 17) 247 #define DWC3_DCTL_CSS (1 << 16) 248 249 #define DWC3_DCTL_INITU2ENA (1 << 12) 250 #define DWC3_DCTL_ACCEPTU2ENA (1 << 11) 251 #define DWC3_DCTL_INITU1ENA (1 << 10) 252 #define DWC3_DCTL_ACCEPTU1ENA (1 << 9) 253 #define DWC3_DCTL_TSTCTRL_MASK (0xf << 1) 254 255 #define DWC3_DCTL_ULSTCHNGREQ_MASK (0x0f << 5) 256 #define DWC3_DCTL_ULSTCHNGREQ(n) (((n) << 5) & DWC3_DCTL_ULSTCHNGREQ_MASK) 257 258 #define DWC3_DCTL_ULSTCHNG_NO_ACTION (DWC3_DCTL_ULSTCHNGREQ(0)) 259 #define DWC3_DCTL_ULSTCHNG_SS_DISABLED (DWC3_DCTL_ULSTCHNGREQ(4)) 260 #define DWC3_DCTL_ULSTCHNG_RX_DETECT (DWC3_DCTL_ULSTCHNGREQ(5)) 261 #define DWC3_DCTL_ULSTCHNG_SS_INACTIVE (DWC3_DCTL_ULSTCHNGREQ(6)) 262 #define DWC3_DCTL_ULSTCHNG_RECOVERY (DWC3_DCTL_ULSTCHNGREQ(8)) 263 #define DWC3_DCTL_ULSTCHNG_COMPLIANCE (DWC3_DCTL_ULSTCHNGREQ(10)) 264 #define DWC3_DCTL_ULSTCHNG_LOOPBACK (DWC3_DCTL_ULSTCHNGREQ(11)) 265 266 /* Device Event Enable Register */ 267 #define DWC3_DEVTEN_VNDRDEVTSTRCVEDEN (1 << 12) 268 #define DWC3_DEVTEN_EVNTOVERFLOWEN (1 << 11) 269 #define DWC3_DEVTEN_CMDCMPLTEN (1 << 10) 270 #define DWC3_DEVTEN_ERRTICERREN (1 << 9) 271 #define DWC3_DEVTEN_SOFEN (1 << 7) 272 #define DWC3_DEVTEN_EOPFEN (1 << 6) 273 #define DWC3_DEVTEN_HIBERNATIONREQEVTEN (1 << 5) 274 #define DWC3_DEVTEN_WKUPEVTEN (1 << 4) 275 #define DWC3_DEVTEN_ULSTCNGEN (1 << 3) 276 #define DWC3_DEVTEN_CONNECTDONEEN (1 << 2) 277 #define DWC3_DEVTEN_USBRSTEN (1 << 1) 278 #define DWC3_DEVTEN_DISCONNEVTEN (1 << 0) 279 280 /* Device Status Register */ 281 #define DWC3_DSTS_DCNRD (1 << 29) 282 283 /* This applies for core versions 1.87a and earlier */ 284 #define DWC3_DSTS_PWRUPREQ (1 << 24) 285 286 /* These apply for core versions 1.94a and later */ 287 #define DWC3_DSTS_RSS (1 << 25) 288 #define DWC3_DSTS_SSS (1 << 24) 289 290 #define DWC3_DSTS_COREIDLE (1 << 23) 291 #define DWC3_DSTS_DEVCTRLHLT (1 << 22) 292 293 #define DWC3_DSTS_USBLNKST_MASK (0x0f << 18) 294 #define DWC3_DSTS_USBLNKST(n) (((n) & DWC3_DSTS_USBLNKST_MASK) >> 18) 295 296 #define DWC3_DSTS_RXFIFOEMPTY (1 << 17) 297 298 #define DWC3_DSTS_SOFFN_MASK (0x3fff << 3) 299 #define DWC3_DSTS_SOFFN(n) (((n) & DWC3_DSTS_SOFFN_MASK) >> 3) 300 301 #define DWC3_DSTS_CONNECTSPD (7 << 0) 302 303 #define DWC3_DSTS_SUPERSPEED (4 << 0) 304 #define DWC3_DSTS_HIGHSPEED (0 << 0) 305 #define DWC3_DSTS_FULLSPEED2 (1 << 0) 306 #define DWC3_DSTS_LOWSPEED (2 << 0) 307 #define DWC3_DSTS_FULLSPEED1 (3 << 0) 308 309 /* Device Generic Command Register */ 310 #define DWC3_DGCMD_SET_LMP 0x01 311 #define DWC3_DGCMD_SET_PERIODIC_PAR 0x02 312 #define DWC3_DGCMD_XMIT_FUNCTION 0x03 313 314 /* These apply for core versions 1.94a and later */ 315 #define DWC3_DGCMD_SET_SCRATCHPAD_ADDR_LO 0x04 316 #define DWC3_DGCMD_SET_SCRATCHPAD_ADDR_HI 0x05 317 318 #define DWC3_DGCMD_SELECTED_FIFO_FLUSH 0x09 319 #define DWC3_DGCMD_ALL_FIFO_FLUSH 0x0a 320 #define DWC3_DGCMD_SET_ENDPOINT_NRDY 0x0c 321 #define DWC3_DGCMD_RUN_SOC_BUS_LOOPBACK 0x10 322 323 #define DWC3_DGCMD_STATUS(n) (((n) >> 15) & 1) 324 #define DWC3_DGCMD_CMDACT (1 << 10) 325 #define DWC3_DGCMD_CMDIOC (1 << 8) 326 327 /* Device Generic Command Parameter Register */ 328 #define DWC3_DGCMDPAR_FORCE_LINKPM_ACCEPT (1 << 0) 329 #define DWC3_DGCMDPAR_FIFO_NUM(n) ((n) << 0) 330 #define DWC3_DGCMDPAR_RX_FIFO (0 << 5) 331 #define DWC3_DGCMDPAR_TX_FIFO (1 << 5) 332 #define DWC3_DGCMDPAR_LOOPBACK_DIS (0 << 0) 333 #define DWC3_DGCMDPAR_LOOPBACK_ENA (1 << 0) 334 335 /* Device Endpoint Command Register */ 336 #define DWC3_DEPCMD_PARAM_SHIFT 16 337 #define DWC3_DEPCMD_PARAM(x) ((x) << DWC3_DEPCMD_PARAM_SHIFT) 338 #define DWC3_DEPCMD_GET_RSC_IDX(x) (((x) >> DWC3_DEPCMD_PARAM_SHIFT) & 0x7f) 339 #define DWC3_DEPCMD_STATUS(x) (((x) >> 15) & 1) 340 #define DWC3_DEPCMD_HIPRI_FORCERM (1 << 11) 341 #define DWC3_DEPCMD_CMDACT (1 << 10) 342 #define DWC3_DEPCMD_CMDIOC (1 << 8) 343 344 #define DWC3_DEPCMD_DEPSTARTCFG (0x09 << 0) 345 #define DWC3_DEPCMD_ENDTRANSFER (0x08 << 0) 346 #define DWC3_DEPCMD_UPDATETRANSFER (0x07 << 0) 347 #define DWC3_DEPCMD_STARTTRANSFER (0x06 << 0) 348 #define DWC3_DEPCMD_CLEARSTALL (0x05 << 0) 349 #define DWC3_DEPCMD_SETSTALL (0x04 << 0) 350 /* This applies for core versions 1.90a and earlier */ 351 #define DWC3_DEPCMD_GETSEQNUMBER (0x03 << 0) 352 /* This applies for core versions 1.94a and later */ 353 #define DWC3_DEPCMD_GETEPSTATE (0x03 << 0) 354 #define DWC3_DEPCMD_SETTRANSFRESOURCE (0x02 << 0) 355 #define DWC3_DEPCMD_SETEPCONFIG (0x01 << 0) 356 357 /* The EP number goes 0..31 so ep0 is always out and ep1 is always in */ 358 #define DWC3_DALEPENA_EP(n) (1 << n) 359 360 #define DWC3_DEPCMD_TYPE_CONTROL 0 361 #define DWC3_DEPCMD_TYPE_ISOC 1 362 #define DWC3_DEPCMD_TYPE_BULK 2 363 #define DWC3_DEPCMD_TYPE_INTR 3 364 365 /* Structures */ 366 367 struct dwc3_trb; 368 369 /** 370 * struct dwc3_event_buffer - Software event buffer representation 371 * @buf: _THE_ buffer 372 * @length: size of this buffer 373 * @lpos: event offset 374 * @count: cache of last read event count register 375 * @flags: flags related to this event buffer 376 * @dma: dma_addr_t 377 * @dwc: pointer to DWC controller 378 */ 379 struct dwc3_event_buffer { 380 void *buf; 381 unsigned length; 382 unsigned int lpos; 383 unsigned int count; 384 unsigned int flags; 385 386 #define DWC3_EVENT_PENDING BIT(0) 387 388 dma_addr_t dma; 389 390 struct dwc3 *dwc; 391 }; 392 393 #define DWC3_EP_FLAG_STALLED (1 << 0) 394 #define DWC3_EP_FLAG_WEDGED (1 << 1) 395 396 #define DWC3_EP_DIRECTION_TX true 397 #define DWC3_EP_DIRECTION_RX false 398 399 #define DWC3_TRB_NUM 32 400 #define DWC3_TRB_MASK (DWC3_TRB_NUM - 1) 401 402 /** 403 * struct dwc3_ep - device side endpoint representation 404 * @endpoint: usb endpoint 405 * @request_list: list of requests for this endpoint 406 * @req_queued: list of requests on this ep which have TRBs setup 407 * @trb_pool: array of transaction buffers 408 * @trb_pool_dma: dma address of @trb_pool 409 * @free_slot: next slot which is going to be used 410 * @busy_slot: first slot which is owned by HW 411 * @desc: usb_endpoint_descriptor pointer 412 * @dwc: pointer to DWC controller 413 * @saved_state: ep state saved during hibernation 414 * @flags: endpoint flags (wedged, stalled, ...) 415 * @current_trb: index of current used trb 416 * @number: endpoint number (1 - 15) 417 * @type: set to bmAttributes & USB_ENDPOINT_XFERTYPE_MASK 418 * @resource_index: Resource transfer index 419 * @interval: the interval on which the ISOC transfer is started 420 * @name: a human readable name e.g. ep1out-bulk 421 * @direction: true for TX, false for RX 422 * @stream_capable: true when streams are enabled 423 */ 424 struct dwc3_ep { 425 struct usb_ep endpoint; 426 struct list_head request_list; 427 struct list_head req_queued; 428 429 struct dwc3_trb *trb_pool; 430 dma_addr_t trb_pool_dma; 431 u32 free_slot; 432 u32 busy_slot; 433 const struct usb_ss_ep_comp_descriptor *comp_desc; 434 struct dwc3 *dwc; 435 436 u32 saved_state; 437 unsigned flags; 438 #define DWC3_EP_ENABLED (1 << 0) 439 #define DWC3_EP_STALL (1 << 1) 440 #define DWC3_EP_WEDGE (1 << 2) 441 #define DWC3_EP_BUSY (1 << 4) 442 #define DWC3_EP_PENDING_REQUEST (1 << 5) 443 #define DWC3_EP_MISSED_ISOC (1 << 6) 444 445 /* This last one is specific to EP0 */ 446 #define DWC3_EP0_DIR_IN (1 << 31) 447 448 unsigned current_trb; 449 450 u8 number; 451 u8 type; 452 u8 resource_index; 453 u32 interval; 454 455 char name[20]; 456 457 unsigned direction:1; 458 unsigned stream_capable:1; 459 }; 460 461 enum dwc3_phy { 462 DWC3_PHY_UNKNOWN = 0, 463 DWC3_PHY_USB3, 464 DWC3_PHY_USB2, 465 }; 466 467 enum dwc3_ep0_next { 468 DWC3_EP0_UNKNOWN = 0, 469 DWC3_EP0_COMPLETE, 470 DWC3_EP0_NRDY_DATA, 471 DWC3_EP0_NRDY_STATUS, 472 }; 473 474 enum dwc3_ep0_state { 475 EP0_UNCONNECTED = 0, 476 EP0_SETUP_PHASE, 477 EP0_DATA_PHASE, 478 EP0_STATUS_PHASE, 479 }; 480 481 enum dwc3_link_state { 482 /* In SuperSpeed */ 483 DWC3_LINK_STATE_U0 = 0x00, /* in HS, means ON */ 484 DWC3_LINK_STATE_U1 = 0x01, 485 DWC3_LINK_STATE_U2 = 0x02, /* in HS, means SLEEP */ 486 DWC3_LINK_STATE_U3 = 0x03, /* in HS, means SUSPEND */ 487 DWC3_LINK_STATE_SS_DIS = 0x04, 488 DWC3_LINK_STATE_RX_DET = 0x05, /* in HS, means Early Suspend */ 489 DWC3_LINK_STATE_SS_INACT = 0x06, 490 DWC3_LINK_STATE_POLL = 0x07, 491 DWC3_LINK_STATE_RECOV = 0x08, 492 DWC3_LINK_STATE_HRESET = 0x09, 493 DWC3_LINK_STATE_CMPLY = 0x0a, 494 DWC3_LINK_STATE_LPBK = 0x0b, 495 DWC3_LINK_STATE_RESET = 0x0e, 496 DWC3_LINK_STATE_RESUME = 0x0f, 497 DWC3_LINK_STATE_MASK = 0x0f, 498 }; 499 500 /* TRB Length, PCM and Status */ 501 #define DWC3_TRB_SIZE_MASK (0x00ffffff) 502 #define DWC3_TRB_SIZE_LENGTH(n) ((n) & DWC3_TRB_SIZE_MASK) 503 #define DWC3_TRB_SIZE_PCM1(n) (((n) & 0x03) << 24) 504 #define DWC3_TRB_SIZE_TRBSTS(n) (((n) & (0x0f << 28)) >> 28) 505 506 #define DWC3_TRBSTS_OK 0 507 #define DWC3_TRBSTS_MISSED_ISOC 1 508 #define DWC3_TRBSTS_SETUP_PENDING 2 509 #define DWC3_TRB_STS_XFER_IN_PROG 4 510 511 /* TRB Control */ 512 #define DWC3_TRB_CTRL_HWO (1 << 0) 513 #define DWC3_TRB_CTRL_LST (1 << 1) 514 #define DWC3_TRB_CTRL_CHN (1 << 2) 515 #define DWC3_TRB_CTRL_CSP (1 << 3) 516 #define DWC3_TRB_CTRL_TRBCTL(n) (((n) & 0x3f) << 4) 517 #define DWC3_TRB_CTRL_ISP_IMI (1 << 10) 518 #define DWC3_TRB_CTRL_IOC (1 << 11) 519 #define DWC3_TRB_CTRL_SID_SOFN(n) (((n) & 0xffff) << 14) 520 521 #define DWC3_TRBCTL_NORMAL DWC3_TRB_CTRL_TRBCTL(1) 522 #define DWC3_TRBCTL_CONTROL_SETUP DWC3_TRB_CTRL_TRBCTL(2) 523 #define DWC3_TRBCTL_CONTROL_STATUS2 DWC3_TRB_CTRL_TRBCTL(3) 524 #define DWC3_TRBCTL_CONTROL_STATUS3 DWC3_TRB_CTRL_TRBCTL(4) 525 #define DWC3_TRBCTL_CONTROL_DATA DWC3_TRB_CTRL_TRBCTL(5) 526 #define DWC3_TRBCTL_ISOCHRONOUS_FIRST DWC3_TRB_CTRL_TRBCTL(6) 527 #define DWC3_TRBCTL_ISOCHRONOUS DWC3_TRB_CTRL_TRBCTL(7) 528 #define DWC3_TRBCTL_LINK_TRB DWC3_TRB_CTRL_TRBCTL(8) 529 530 /** 531 * struct dwc3_trb - transfer request block (hw format) 532 * @bpl: DW0-3 533 * @bph: DW4-7 534 * @size: DW8-B 535 * @trl: DWC-F 536 */ 537 struct dwc3_trb { 538 u32 bpl; 539 u32 bph; 540 u32 size; 541 u32 ctrl; 542 } __packed; 543 544 /** 545 * dwc3_hwparams - copy of HWPARAMS registers 546 * @hwparams0 - GHWPARAMS0 547 * @hwparams1 - GHWPARAMS1 548 * @hwparams2 - GHWPARAMS2 549 * @hwparams3 - GHWPARAMS3 550 * @hwparams4 - GHWPARAMS4 551 * @hwparams5 - GHWPARAMS5 552 * @hwparams6 - GHWPARAMS6 553 * @hwparams7 - GHWPARAMS7 554 * @hwparams8 - GHWPARAMS8 555 */ 556 struct dwc3_hwparams { 557 u32 hwparams0; 558 u32 hwparams1; 559 u32 hwparams2; 560 u32 hwparams3; 561 u32 hwparams4; 562 u32 hwparams5; 563 u32 hwparams6; 564 u32 hwparams7; 565 u32 hwparams8; 566 }; 567 568 /* HWPARAMS0 */ 569 #define DWC3_MODE(n) ((n) & 0x7) 570 571 #define DWC3_MDWIDTH(n) (((n) & 0xff00) >> 8) 572 573 /* HWPARAMS1 */ 574 #define DWC3_NUM_INT(n) (((n) & (0x3f << 15)) >> 15) 575 576 /* HWPARAMS3 */ 577 #define DWC3_NUM_IN_EPS_MASK (0x1f << 18) 578 #define DWC3_NUM_EPS_MASK (0x3f << 12) 579 #define DWC3_NUM_EPS(p) (((p)->hwparams3 & \ 580 (DWC3_NUM_EPS_MASK)) >> 12) 581 #define DWC3_NUM_IN_EPS(p) (((p)->hwparams3 & \ 582 (DWC3_NUM_IN_EPS_MASK)) >> 18) 583 584 /* HWPARAMS7 */ 585 #define DWC3_RAM1_DEPTH(n) ((n) & 0xffff) 586 587 struct dwc3_request { 588 struct usb_request request; 589 struct list_head list; 590 struct dwc3_ep *dep; 591 u32 start_slot; 592 593 u8 epnum; 594 struct dwc3_trb *trb; 595 dma_addr_t trb_dma; 596 597 unsigned direction:1; 598 unsigned mapped:1; 599 unsigned queued:1; 600 }; 601 602 /* 603 * struct dwc3_scratchpad_array - hibernation scratchpad array 604 * (format defined by hw) 605 */ 606 struct dwc3_scratchpad_array { 607 __le64 dma_adr[DWC3_MAX_HIBER_SCRATCHBUFS]; 608 }; 609 610 /** 611 * struct dwc3 - representation of our controller 612 * @ctrl_req: usb control request which is used for ep0 613 * @ep0_trb: trb which is used for the ctrl_req 614 * @ep0_bounce: bounce buffer for ep0 615 * @setup_buf: used while precessing STD USB requests 616 * @ctrl_req_addr: dma address of ctrl_req 617 * @ep0_trb: dma address of ep0_trb 618 * @ep0_usb_req: dummy req used while handling STD USB requests 619 * @ep0_bounce_addr: dma address of ep0_bounce 620 * @scratch_addr: dma address of scratchbuf 621 * @lock: for synchronizing 622 * @dev: pointer to our struct device 623 * @xhci: pointer to our xHCI child 624 * @event_buffer_list: a list of event buffers 625 * @gadget: device side representation of the peripheral controller 626 * @gadget_driver: pointer to the gadget driver 627 * @regs: base address for our registers 628 * @regs_size: address space size 629 * @nr_scratch: number of scratch buffers 630 * @num_event_buffers: calculated number of event buffers 631 * @u1u2: only used on revisions <1.83a for workaround 632 * @maximum_speed: maximum speed requested (mainly for testing purposes) 633 * @revision: revision register contents 634 * @dr_mode: requested mode of operation 635 * @usb2_phy: pointer to USB2 PHY 636 * @usb3_phy: pointer to USB3 PHY 637 * @usb2_generic_phy: pointer to USB2 PHY 638 * @usb3_generic_phy: pointer to USB3 PHY 639 * @dcfg: saved contents of DCFG register 640 * @gctl: saved contents of GCTL register 641 * @isoch_delay: wValue from Set Isochronous Delay request; 642 * @u2sel: parameter from Set SEL request. 643 * @u2pel: parameter from Set SEL request. 644 * @u1sel: parameter from Set SEL request. 645 * @u1pel: parameter from Set SEL request. 646 * @num_out_eps: number of out endpoints 647 * @num_in_eps: number of in endpoints 648 * @ep0_next_event: hold the next expected event 649 * @ep0state: state of endpoint zero 650 * @link_state: link state 651 * @speed: device speed (super, high, full, low) 652 * @mem: points to start of memory which is used for this struct. 653 * @hwparams: copy of hwparams registers 654 * @root: debugfs root folder pointer 655 * @regset: debugfs pointer to regdump file 656 * @test_mode: true when we're entering a USB test mode 657 * @test_mode_nr: test feature selector 658 * @delayed_status: true when gadget driver asks for delayed status 659 * @ep0_bounced: true when we used bounce buffer 660 * @ep0_expect_in: true when we expect a DATA IN transfer 661 * @has_hibernation: true when dwc3 was configured with Hibernation 662 * @is_selfpowered: true when we are selfpowered 663 * @needs_fifo_resize: not all users might want fifo resizing, flag it 664 * @pullups_connected: true when Run/Stop bit is set 665 * @resize_fifos: tells us it's ok to reconfigure our TxFIFO sizes. 666 * @setup_packet_pending: true when there's a Setup Packet in FIFO. Workaround 667 * @start_config_issued: true when StartConfig command has been issued 668 * @three_stage_setup: set if we perform a three phase setup 669 */ 670 struct dwc3 { 671 struct usb_ctrlrequest *ctrl_req; 672 struct dwc3_trb *ep0_trb; 673 void *ep0_bounce; 674 void *scratchbuf; 675 u8 *setup_buf; 676 dma_addr_t ctrl_req_addr; 677 dma_addr_t ep0_trb_addr; 678 dma_addr_t ep0_bounce_addr; 679 dma_addr_t scratch_addr; 680 struct dwc3_request ep0_usb_req; 681 682 /* device lock */ 683 spinlock_t lock; 684 685 struct device *dev; 686 687 struct platform_device *xhci; 688 struct resource xhci_resources[DWC3_XHCI_RESOURCES_NUM]; 689 690 struct dwc3_event_buffer **ev_buffs; 691 struct dwc3_ep *eps[DWC3_ENDPOINTS_NUM]; 692 693 struct usb_gadget gadget; 694 struct usb_gadget_driver *gadget_driver; 695 696 struct usb_phy *usb2_phy; 697 struct usb_phy *usb3_phy; 698 699 struct phy *usb2_generic_phy; 700 struct phy *usb3_generic_phy; 701 702 void __iomem *regs; 703 size_t regs_size; 704 705 enum usb_dr_mode dr_mode; 706 707 /* used for suspend/resume */ 708 u32 dcfg; 709 u32 gctl; 710 711 u32 nr_scratch; 712 u32 num_event_buffers; 713 u32 u1u2; 714 u32 maximum_speed; 715 u32 revision; 716 717 #define DWC3_REVISION_173A 0x5533173a 718 #define DWC3_REVISION_175A 0x5533175a 719 #define DWC3_REVISION_180A 0x5533180a 720 #define DWC3_REVISION_183A 0x5533183a 721 #define DWC3_REVISION_185A 0x5533185a 722 #define DWC3_REVISION_187A 0x5533187a 723 #define DWC3_REVISION_188A 0x5533188a 724 #define DWC3_REVISION_190A 0x5533190a 725 #define DWC3_REVISION_194A 0x5533194a 726 #define DWC3_REVISION_200A 0x5533200a 727 #define DWC3_REVISION_202A 0x5533202a 728 #define DWC3_REVISION_210A 0x5533210a 729 #define DWC3_REVISION_220A 0x5533220a 730 #define DWC3_REVISION_230A 0x5533230a 731 #define DWC3_REVISION_240A 0x5533240a 732 #define DWC3_REVISION_250A 0x5533250a 733 #define DWC3_REVISION_260A 0x5533260a 734 #define DWC3_REVISION_270A 0x5533270a 735 #define DWC3_REVISION_280A 0x5533280a 736 737 enum dwc3_ep0_next ep0_next_event; 738 enum dwc3_ep0_state ep0state; 739 enum dwc3_link_state link_state; 740 741 u16 isoch_delay; 742 u16 u2sel; 743 u16 u2pel; 744 u8 u1sel; 745 u8 u1pel; 746 747 u8 speed; 748 749 u8 num_out_eps; 750 u8 num_in_eps; 751 752 void *mem; 753 754 struct dwc3_hwparams hwparams; 755 struct dentry *root; 756 struct debugfs_regset32 *regset; 757 758 u8 test_mode; 759 u8 test_mode_nr; 760 761 unsigned delayed_status:1; 762 unsigned ep0_bounced:1; 763 unsigned ep0_expect_in:1; 764 unsigned has_hibernation:1; 765 unsigned is_selfpowered:1; 766 unsigned needs_fifo_resize:1; 767 unsigned pullups_connected:1; 768 unsigned resize_fifos:1; 769 unsigned setup_packet_pending:1; 770 unsigned start_config_issued:1; 771 unsigned three_stage_setup:1; 772 }; 773 774 /* -------------------------------------------------------------------------- */ 775 776 /* -------------------------------------------------------------------------- */ 777 778 struct dwc3_event_type { 779 u32 is_devspec:1; 780 u32 type:7; 781 u32 reserved8_31:24; 782 } __packed; 783 784 #define DWC3_DEPEVT_XFERCOMPLETE 0x01 785 #define DWC3_DEPEVT_XFERINPROGRESS 0x02 786 #define DWC3_DEPEVT_XFERNOTREADY 0x03 787 #define DWC3_DEPEVT_RXTXFIFOEVT 0x04 788 #define DWC3_DEPEVT_STREAMEVT 0x06 789 #define DWC3_DEPEVT_EPCMDCMPLT 0x07 790 791 /** 792 * struct dwc3_event_depvt - Device Endpoint Events 793 * @one_bit: indicates this is an endpoint event (not used) 794 * @endpoint_number: number of the endpoint 795 * @endpoint_event: The event we have: 796 * 0x00 - Reserved 797 * 0x01 - XferComplete 798 * 0x02 - XferInProgress 799 * 0x03 - XferNotReady 800 * 0x04 - RxTxFifoEvt (IN->Underrun, OUT->Overrun) 801 * 0x05 - Reserved 802 * 0x06 - StreamEvt 803 * 0x07 - EPCmdCmplt 804 * @reserved11_10: Reserved, don't use. 805 * @status: Indicates the status of the event. Refer to databook for 806 * more information. 807 * @parameters: Parameters of the current event. Refer to databook for 808 * more information. 809 */ 810 struct dwc3_event_depevt { 811 u32 one_bit:1; 812 u32 endpoint_number:5; 813 u32 endpoint_event:4; 814 u32 reserved11_10:2; 815 u32 status:4; 816 817 /* Within XferNotReady */ 818 #define DEPEVT_STATUS_TRANSFER_ACTIVE (1 << 3) 819 820 /* Within XferComplete */ 821 #define DEPEVT_STATUS_BUSERR (1 << 0) 822 #define DEPEVT_STATUS_SHORT (1 << 1) 823 #define DEPEVT_STATUS_IOC (1 << 2) 824 #define DEPEVT_STATUS_LST (1 << 3) 825 826 /* Stream event only */ 827 #define DEPEVT_STREAMEVT_FOUND 1 828 #define DEPEVT_STREAMEVT_NOTFOUND 2 829 830 /* Control-only Status */ 831 #define DEPEVT_STATUS_CONTROL_DATA 1 832 #define DEPEVT_STATUS_CONTROL_STATUS 2 833 834 u32 parameters:16; 835 } __packed; 836 837 /** 838 * struct dwc3_event_devt - Device Events 839 * @one_bit: indicates this is a non-endpoint event (not used) 840 * @device_event: indicates it's a device event. Should read as 0x00 841 * @type: indicates the type of device event. 842 * 0 - DisconnEvt 843 * 1 - USBRst 844 * 2 - ConnectDone 845 * 3 - ULStChng 846 * 4 - WkUpEvt 847 * 5 - Reserved 848 * 6 - EOPF 849 * 7 - SOF 850 * 8 - Reserved 851 * 9 - ErrticErr 852 * 10 - CmdCmplt 853 * 11 - EvntOverflow 854 * 12 - VndrDevTstRcved 855 * @reserved15_12: Reserved, not used 856 * @event_info: Information about this event 857 * @reserved31_25: Reserved, not used 858 */ 859 struct dwc3_event_devt { 860 u32 one_bit:1; 861 u32 device_event:7; 862 u32 type:4; 863 u32 reserved15_12:4; 864 u32 event_info:9; 865 u32 reserved31_25:7; 866 } __packed; 867 868 /** 869 * struct dwc3_event_gevt - Other Core Events 870 * @one_bit: indicates this is a non-endpoint event (not used) 871 * @device_event: indicates it's (0x03) Carkit or (0x04) I2C event. 872 * @phy_port_number: self-explanatory 873 * @reserved31_12: Reserved, not used. 874 */ 875 struct dwc3_event_gevt { 876 u32 one_bit:1; 877 u32 device_event:7; 878 u32 phy_port_number:4; 879 u32 reserved31_12:20; 880 } __packed; 881 882 /** 883 * union dwc3_event - representation of Event Buffer contents 884 * @raw: raw 32-bit event 885 * @type: the type of the event 886 * @depevt: Device Endpoint Event 887 * @devt: Device Event 888 * @gevt: Global Event 889 */ 890 union dwc3_event { 891 u32 raw; 892 struct dwc3_event_type type; 893 struct dwc3_event_depevt depevt; 894 struct dwc3_event_devt devt; 895 struct dwc3_event_gevt gevt; 896 }; 897 898 /** 899 * struct dwc3_gadget_ep_cmd_params - representation of endpoint command 900 * parameters 901 * @param2: third parameter 902 * @param1: second parameter 903 * @param0: first parameter 904 */ 905 struct dwc3_gadget_ep_cmd_params { 906 u32 param2; 907 u32 param1; 908 u32 param0; 909 }; 910 911 /* 912 * DWC3 Features to be used as Driver Data 913 */ 914 915 #define DWC3_HAS_PERIPHERAL BIT(0) 916 #define DWC3_HAS_XHCI BIT(1) 917 #define DWC3_HAS_OTG BIT(3) 918 919 /* prototypes */ 920 void dwc3_set_mode(struct dwc3 *dwc, u32 mode); 921 int dwc3_gadget_resize_tx_fifos(struct dwc3 *dwc); 922 923 #if IS_ENABLED(CONFIG_USB_DWC3_HOST) || IS_ENABLED(CONFIG_USB_DWC3_DUAL_ROLE) 924 int dwc3_host_init(struct dwc3 *dwc); 925 void dwc3_host_exit(struct dwc3 *dwc); 926 #else 927 static inline int dwc3_host_init(struct dwc3 *dwc) 928 { return 0; } 929 static inline void dwc3_host_exit(struct dwc3 *dwc) 930 { } 931 #endif 932 933 #if IS_ENABLED(CONFIG_USB_DWC3_GADGET) || IS_ENABLED(CONFIG_USB_DWC3_DUAL_ROLE) 934 int dwc3_gadget_init(struct dwc3 *dwc); 935 void dwc3_gadget_exit(struct dwc3 *dwc); 936 int dwc3_gadget_set_test_mode(struct dwc3 *dwc, int mode); 937 int dwc3_gadget_get_link_state(struct dwc3 *dwc); 938 int dwc3_gadget_set_link_state(struct dwc3 *dwc, enum dwc3_link_state state); 939 int dwc3_send_gadget_ep_cmd(struct dwc3 *dwc, unsigned ep, 940 unsigned cmd, struct dwc3_gadget_ep_cmd_params *params); 941 int dwc3_send_gadget_generic_command(struct dwc3 *dwc, int cmd, u32 param); 942 #else 943 static inline int dwc3_gadget_init(struct dwc3 *dwc) 944 { return 0; } 945 static inline void dwc3_gadget_exit(struct dwc3 *dwc) 946 { } 947 static inline int dwc3_gadget_set_test_mode(struct dwc3 *dwc, int mode) 948 { return 0; } 949 static inline int dwc3_gadget_get_link_state(struct dwc3 *dwc) 950 { return 0; } 951 static inline int dwc3_gadget_set_link_state(struct dwc3 *dwc, 952 enum dwc3_link_state state) 953 { return 0; } 954 955 static inline int dwc3_send_gadget_ep_cmd(struct dwc3 *dwc, unsigned ep, 956 unsigned cmd, struct dwc3_gadget_ep_cmd_params *params) 957 { return 0; } 958 static inline int dwc3_send_gadget_generic_command(struct dwc3 *dwc, 959 int cmd, u32 param) 960 { return 0; } 961 #endif 962 963 /* power management interface */ 964 #if !IS_ENABLED(CONFIG_USB_DWC3_HOST) 965 int dwc3_gadget_prepare(struct dwc3 *dwc); 966 void dwc3_gadget_complete(struct dwc3 *dwc); 967 int dwc3_gadget_suspend(struct dwc3 *dwc); 968 int dwc3_gadget_resume(struct dwc3 *dwc); 969 #else 970 static inline int dwc3_gadget_prepare(struct dwc3 *dwc) 971 { 972 return 0; 973 } 974 975 static inline void dwc3_gadget_complete(struct dwc3 *dwc) 976 { 977 } 978 979 static inline int dwc3_gadget_suspend(struct dwc3 *dwc) 980 { 981 return 0; 982 } 983 984 static inline int dwc3_gadget_resume(struct dwc3 *dwc) 985 { 986 return 0; 987 } 988 #endif /* !IS_ENABLED(CONFIG_USB_DWC3_HOST) */ 989 990 #endif /* __DRIVERS_USB_DWC3_CORE_H */ 991