172246da4SFelipe Balbi /** 272246da4SFelipe Balbi * core.h - DesignWare USB3 DRD Core Header 372246da4SFelipe Balbi * 472246da4SFelipe Balbi * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com 572246da4SFelipe Balbi * All rights reserved. 672246da4SFelipe Balbi * 772246da4SFelipe Balbi * Authors: Felipe Balbi <balbi@ti.com>, 872246da4SFelipe Balbi * Sebastian Andrzej Siewior <bigeasy@linutronix.de> 972246da4SFelipe Balbi * 1072246da4SFelipe Balbi * Redistribution and use in source and binary forms, with or without 1172246da4SFelipe Balbi * modification, are permitted provided that the following conditions 1272246da4SFelipe Balbi * are met: 1372246da4SFelipe Balbi * 1. Redistributions of source code must retain the above copyright 1472246da4SFelipe Balbi * notice, this list of conditions, and the following disclaimer, 1572246da4SFelipe Balbi * without modification. 1672246da4SFelipe Balbi * 2. Redistributions in binary form must reproduce the above copyright 1772246da4SFelipe Balbi * notice, this list of conditions and the following disclaimer in the 1872246da4SFelipe Balbi * documentation and/or other materials provided with the distribution. 1972246da4SFelipe Balbi * 3. The names of the above-listed copyright holders may not be used 2072246da4SFelipe Balbi * to endorse or promote products derived from this software without 2172246da4SFelipe Balbi * specific prior written permission. 2272246da4SFelipe Balbi * 2372246da4SFelipe Balbi * ALTERNATIVELY, this software may be distributed under the terms of the 2472246da4SFelipe Balbi * GNU General Public License ("GPL") version 2, as published by the Free 2572246da4SFelipe Balbi * Software Foundation. 2672246da4SFelipe Balbi * 2772246da4SFelipe Balbi * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS 2872246da4SFelipe Balbi * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 2972246da4SFelipe Balbi * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 3072246da4SFelipe Balbi * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR 3172246da4SFelipe Balbi * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 3272246da4SFelipe Balbi * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 3372246da4SFelipe Balbi * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 3472246da4SFelipe Balbi * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF 3572246da4SFelipe Balbi * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING 3672246da4SFelipe Balbi * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 3772246da4SFelipe Balbi * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 3872246da4SFelipe Balbi */ 3972246da4SFelipe Balbi 4072246da4SFelipe Balbi #ifndef __DRIVERS_USB_DWC3_CORE_H 4172246da4SFelipe Balbi #define __DRIVERS_USB_DWC3_CORE_H 4272246da4SFelipe Balbi 4372246da4SFelipe Balbi #include <linux/device.h> 4472246da4SFelipe Balbi #include <linux/spinlock.h> 4572246da4SFelipe Balbi #include <linux/list.h> 4672246da4SFelipe Balbi #include <linux/dma-mapping.h> 4772246da4SFelipe Balbi #include <linux/mm.h> 4872246da4SFelipe Balbi #include <linux/debugfs.h> 4972246da4SFelipe Balbi 5072246da4SFelipe Balbi #include <linux/usb/ch9.h> 5172246da4SFelipe Balbi #include <linux/usb/gadget.h> 5272246da4SFelipe Balbi 5372246da4SFelipe Balbi /* Global constants */ 5472246da4SFelipe Balbi #define DWC3_ENDPOINTS_NUM 32 5572246da4SFelipe Balbi 5672246da4SFelipe Balbi #define DWC3_EVENT_BUFFERS_NUM 2 5772246da4SFelipe Balbi #define DWC3_EVENT_BUFFERS_SIZE PAGE_SIZE 5872246da4SFelipe Balbi #define DWC3_EVENT_TYPE_MASK 0xfe 5972246da4SFelipe Balbi 6072246da4SFelipe Balbi #define DWC3_EVENT_TYPE_DEV 0 6172246da4SFelipe Balbi #define DWC3_EVENT_TYPE_CARKIT 3 6272246da4SFelipe Balbi #define DWC3_EVENT_TYPE_I2C 4 6372246da4SFelipe Balbi 6472246da4SFelipe Balbi #define DWC3_DEVICE_EVENT_DISCONNECT 0 6572246da4SFelipe Balbi #define DWC3_DEVICE_EVENT_RESET 1 6672246da4SFelipe Balbi #define DWC3_DEVICE_EVENT_CONNECT_DONE 2 6772246da4SFelipe Balbi #define DWC3_DEVICE_EVENT_LINK_STATUS_CHANGE 3 6872246da4SFelipe Balbi #define DWC3_DEVICE_EVENT_WAKEUP 4 6972246da4SFelipe Balbi #define DWC3_DEVICE_EVENT_EOPF 6 7072246da4SFelipe Balbi #define DWC3_DEVICE_EVENT_SOF 7 7172246da4SFelipe Balbi #define DWC3_DEVICE_EVENT_ERRATIC_ERROR 9 7272246da4SFelipe Balbi #define DWC3_DEVICE_EVENT_CMD_CMPL 10 7372246da4SFelipe Balbi #define DWC3_DEVICE_EVENT_OVERFLOW 11 7472246da4SFelipe Balbi 7572246da4SFelipe Balbi #define DWC3_GEVNTCOUNT_MASK 0xfffc 7672246da4SFelipe Balbi #define DWC3_GSNPSID_MASK 0xffff0000 7772246da4SFelipe Balbi #define DWC3_GSNPSREV_MASK 0xffff 7872246da4SFelipe Balbi 7972246da4SFelipe Balbi /* Global Registers */ 8072246da4SFelipe Balbi #define DWC3_GSBUSCFG0 0xc100 8172246da4SFelipe Balbi #define DWC3_GSBUSCFG1 0xc104 8272246da4SFelipe Balbi #define DWC3_GTXTHRCFG 0xc108 8372246da4SFelipe Balbi #define DWC3_GRXTHRCFG 0xc10c 8472246da4SFelipe Balbi #define DWC3_GCTL 0xc110 8572246da4SFelipe Balbi #define DWC3_GEVTEN 0xc114 8672246da4SFelipe Balbi #define DWC3_GSTS 0xc118 8772246da4SFelipe Balbi #define DWC3_GSNPSID 0xc120 8872246da4SFelipe Balbi #define DWC3_GGPIO 0xc124 8972246da4SFelipe Balbi #define DWC3_GUID 0xc128 9072246da4SFelipe Balbi #define DWC3_GUCTL 0xc12c 9172246da4SFelipe Balbi #define DWC3_GBUSERRADDR0 0xc130 9272246da4SFelipe Balbi #define DWC3_GBUSERRADDR1 0xc134 9372246da4SFelipe Balbi #define DWC3_GPRTBIMAP0 0xc138 9472246da4SFelipe Balbi #define DWC3_GPRTBIMAP1 0xc13c 9572246da4SFelipe Balbi #define DWC3_GHWPARAMS0 0xc140 9672246da4SFelipe Balbi #define DWC3_GHWPARAMS1 0xc144 9772246da4SFelipe Balbi #define DWC3_GHWPARAMS2 0xc148 9872246da4SFelipe Balbi #define DWC3_GHWPARAMS3 0xc14c 9972246da4SFelipe Balbi #define DWC3_GHWPARAMS4 0xc150 10072246da4SFelipe Balbi #define DWC3_GHWPARAMS5 0xc154 10172246da4SFelipe Balbi #define DWC3_GHWPARAMS6 0xc158 10272246da4SFelipe Balbi #define DWC3_GHWPARAMS7 0xc15c 10372246da4SFelipe Balbi #define DWC3_GDBGFIFOSPACE 0xc160 10472246da4SFelipe Balbi #define DWC3_GDBGLTSSM 0xc164 10572246da4SFelipe Balbi #define DWC3_GPRTBIMAP_HS0 0xc180 10672246da4SFelipe Balbi #define DWC3_GPRTBIMAP_HS1 0xc184 10772246da4SFelipe Balbi #define DWC3_GPRTBIMAP_FS0 0xc188 10872246da4SFelipe Balbi #define DWC3_GPRTBIMAP_FS1 0xc18c 10972246da4SFelipe Balbi 11072246da4SFelipe Balbi #define DWC3_GUSB2PHYCFG(n) (0xc200 + (n * 0x04)) 11172246da4SFelipe Balbi #define DWC3_GUSB2I2CCTL(n) (0xc240 + (n * 0x04)) 11272246da4SFelipe Balbi 11372246da4SFelipe Balbi #define DWC3_GUSB2PHYACC(n) (0xc280 + (n * 0x04)) 11472246da4SFelipe Balbi 11572246da4SFelipe Balbi #define DWC3_GUSB3PIPECTL(n) (0xc2c0 + (n * 0x04)) 11672246da4SFelipe Balbi 11772246da4SFelipe Balbi #define DWC3_GTXFIFOSIZ(n) (0xc300 + (n * 0x04)) 11872246da4SFelipe Balbi #define DWC3_GRXFIFOSIZ(n) (0xc380 + (n * 0x04)) 11972246da4SFelipe Balbi 12072246da4SFelipe Balbi #define DWC3_GEVNTADRLO(n) (0xc400 + (n * 0x10)) 12172246da4SFelipe Balbi #define DWC3_GEVNTADRHI(n) (0xc404 + (n * 0x10)) 12272246da4SFelipe Balbi #define DWC3_GEVNTSIZ(n) (0xc408 + (n * 0x10)) 12372246da4SFelipe Balbi #define DWC3_GEVNTCOUNT(n) (0xc40c + (n * 0x10)) 12472246da4SFelipe Balbi 12572246da4SFelipe Balbi #define DWC3_GHWPARAMS8 0xc600 12672246da4SFelipe Balbi 12772246da4SFelipe Balbi /* Device Registers */ 12872246da4SFelipe Balbi #define DWC3_DCFG 0xc700 12972246da4SFelipe Balbi #define DWC3_DCTL 0xc704 13072246da4SFelipe Balbi #define DWC3_DEVTEN 0xc708 13172246da4SFelipe Balbi #define DWC3_DSTS 0xc70c 13272246da4SFelipe Balbi #define DWC3_DGCMDPAR 0xc710 13372246da4SFelipe Balbi #define DWC3_DGCMD 0xc714 13472246da4SFelipe Balbi #define DWC3_DALEPENA 0xc720 13572246da4SFelipe Balbi #define DWC3_DEPCMDPAR2(n) (0xc800 + (n * 0x10)) 13672246da4SFelipe Balbi #define DWC3_DEPCMDPAR1(n) (0xc804 + (n * 0x10)) 13772246da4SFelipe Balbi #define DWC3_DEPCMDPAR0(n) (0xc808 + (n * 0x10)) 13872246da4SFelipe Balbi #define DWC3_DEPCMD(n) (0xc80c + (n * 0x10)) 13972246da4SFelipe Balbi 14072246da4SFelipe Balbi /* OTG Registers */ 14172246da4SFelipe Balbi #define DWC3_OCFG 0xcc00 14272246da4SFelipe Balbi #define DWC3_OCTL 0xcc04 14372246da4SFelipe Balbi #define DWC3_OEVTEN 0xcc08 14472246da4SFelipe Balbi #define DWC3_OSTS 0xcc0C 14572246da4SFelipe Balbi 14672246da4SFelipe Balbi /* Bit fields */ 14772246da4SFelipe Balbi 14872246da4SFelipe Balbi /* Global Configuration Register */ 14972246da4SFelipe Balbi #define DWC3_GCTL_PWRDNSCALE(n) (n << 19) 150f4aadbe4SFelipe Balbi #define DWC3_GCTL_U2RSTECN (1 << 16) 15172246da4SFelipe Balbi #define DWC3_GCTL_RAMCLKSEL(x) ((x & DWC3_GCTL_CLK_MASK) << 6) 15272246da4SFelipe Balbi #define DWC3_GCTL_CLK_BUS (0) 15372246da4SFelipe Balbi #define DWC3_GCTL_CLK_PIPE (1) 15472246da4SFelipe Balbi #define DWC3_GCTL_CLK_PIPEHALF (2) 15572246da4SFelipe Balbi #define DWC3_GCTL_CLK_MASK (3) 15672246da4SFelipe Balbi 15772246da4SFelipe Balbi #define DWC3_GCTL_PRTCAPDIR(n) (n << 12) 15872246da4SFelipe Balbi #define DWC3_GCTL_PRTCAP_HOST 1 15972246da4SFelipe Balbi #define DWC3_GCTL_PRTCAP_DEVICE 2 16072246da4SFelipe Balbi #define DWC3_GCTL_PRTCAP_OTG 3 16172246da4SFelipe Balbi 16272246da4SFelipe Balbi #define DWC3_GCTL_CORESOFTRESET (1 << 11) 163*f78d32e7SFelipe Balbi #define DWC3_GCTL_SCALEDOWN(n) (n << 4) 16472246da4SFelipe Balbi #define DWC3_GCTL_DISSCRAMBLE (1 << 3) 16572246da4SFelipe Balbi 16672246da4SFelipe Balbi /* Global USB2 PHY Configuration Register */ 16772246da4SFelipe Balbi #define DWC3_GUSB2PHYCFG_PHYSOFTRST (1 << 31) 16872246da4SFelipe Balbi #define DWC3_GUSB2PHYCFG_SUSPHY (1 << 6) 16972246da4SFelipe Balbi 17072246da4SFelipe Balbi /* Global USB3 PIPE Control Register */ 17172246da4SFelipe Balbi #define DWC3_GUSB3PIPECTL_PHYSOFTRST (1 << 31) 17272246da4SFelipe Balbi #define DWC3_GUSB3PIPECTL_SUSPHY (1 << 17) 17372246da4SFelipe Balbi 17472246da4SFelipe Balbi /* Device Configuration Register */ 17572246da4SFelipe Balbi #define DWC3_DCFG_DEVADDR(addr) ((addr) << 3) 17672246da4SFelipe Balbi #define DWC3_DCFG_DEVADDR_MASK DWC3_DCFG_DEVADDR(0x7f) 17772246da4SFelipe Balbi 17872246da4SFelipe Balbi #define DWC3_DCFG_SPEED_MASK (7 << 0) 17972246da4SFelipe Balbi #define DWC3_DCFG_SUPERSPEED (4 << 0) 18072246da4SFelipe Balbi #define DWC3_DCFG_HIGHSPEED (0 << 0) 18172246da4SFelipe Balbi #define DWC3_DCFG_FULLSPEED2 (1 << 0) 18272246da4SFelipe Balbi #define DWC3_DCFG_LOWSPEED (2 << 0) 18372246da4SFelipe Balbi #define DWC3_DCFG_FULLSPEED1 (3 << 0) 18472246da4SFelipe Balbi 18572246da4SFelipe Balbi /* Device Control Register */ 18672246da4SFelipe Balbi #define DWC3_DCTL_RUN_STOP (1 << 31) 18772246da4SFelipe Balbi #define DWC3_DCTL_CSFTRST (1 << 30) 18872246da4SFelipe Balbi #define DWC3_DCTL_LSFTRST (1 << 29) 18972246da4SFelipe Balbi 19072246da4SFelipe Balbi #define DWC3_DCTL_HIRD_THRES_MASK (0x1f << 24) 19172246da4SFelipe Balbi #define DWC3_DCTL_HIRD_THRES(n) (((n) & DWC3_DCTL_HIRD_THRES_MASK) >> 24) 19272246da4SFelipe Balbi 19372246da4SFelipe Balbi #define DWC3_DCTL_APPL1RES (1 << 23) 19472246da4SFelipe Balbi 19572246da4SFelipe Balbi #define DWC3_DCTL_INITU2ENA (1 << 12) 19672246da4SFelipe Balbi #define DWC3_DCTL_ACCEPTU2ENA (1 << 11) 19772246da4SFelipe Balbi #define DWC3_DCTL_INITU1ENA (1 << 10) 19872246da4SFelipe Balbi #define DWC3_DCTL_ACCEPTU1ENA (1 << 9) 19972246da4SFelipe Balbi #define DWC3_DCTL_TSTCTRL_MASK (0xf << 1) 20072246da4SFelipe Balbi 20172246da4SFelipe Balbi #define DWC3_DCTL_ULSTCHNGREQ_MASK (0x0f << 5) 20272246da4SFelipe Balbi #define DWC3_DCTL_ULSTCHNGREQ(n) (((n) << 5) & DWC3_DCTL_ULSTCHNGREQ_MASK) 20372246da4SFelipe Balbi 20472246da4SFelipe Balbi #define DWC3_DCTL_ULSTCHNG_NO_ACTION (DWC3_DCTL_ULSTCHNGREQ(0)) 20572246da4SFelipe Balbi #define DWC3_DCTL_ULSTCHNG_SS_DISABLED (DWC3_DCTL_ULSTCHNGREQ(4)) 20672246da4SFelipe Balbi #define DWC3_DCTL_ULSTCHNG_RX_DETECT (DWC3_DCTL_ULSTCHNGREQ(5)) 20772246da4SFelipe Balbi #define DWC3_DCTL_ULSTCHNG_SS_INACTIVE (DWC3_DCTL_ULSTCHNGREQ(6)) 20872246da4SFelipe Balbi #define DWC3_DCTL_ULSTCHNG_RECOVERY (DWC3_DCTL_ULSTCHNGREQ(8)) 20972246da4SFelipe Balbi #define DWC3_DCTL_ULSTCHNG_COMPLIANCE (DWC3_DCTL_ULSTCHNGREQ(10)) 21072246da4SFelipe Balbi #define DWC3_DCTL_ULSTCHNG_LOOPBACK (DWC3_DCTL_ULSTCHNGREQ(11)) 21172246da4SFelipe Balbi 21272246da4SFelipe Balbi /* Device Event Enable Register */ 21372246da4SFelipe Balbi #define DWC3_DEVTEN_VNDRDEVTSTRCVEDEN (1 << 12) 21472246da4SFelipe Balbi #define DWC3_DEVTEN_EVNTOVERFLOWEN (1 << 11) 21572246da4SFelipe Balbi #define DWC3_DEVTEN_CMDCMPLTEN (1 << 10) 21672246da4SFelipe Balbi #define DWC3_DEVTEN_ERRTICERREN (1 << 9) 21772246da4SFelipe Balbi #define DWC3_DEVTEN_SOFEN (1 << 7) 21872246da4SFelipe Balbi #define DWC3_DEVTEN_EOPFEN (1 << 6) 21972246da4SFelipe Balbi #define DWC3_DEVTEN_WKUPEVTEN (1 << 4) 22072246da4SFelipe Balbi #define DWC3_DEVTEN_ULSTCNGEN (1 << 3) 22172246da4SFelipe Balbi #define DWC3_DEVTEN_CONNECTDONEEN (1 << 2) 22272246da4SFelipe Balbi #define DWC3_DEVTEN_USBRSTEN (1 << 1) 22372246da4SFelipe Balbi #define DWC3_DEVTEN_DISCONNEVTEN (1 << 0) 22472246da4SFelipe Balbi 22572246da4SFelipe Balbi /* Device Status Register */ 22672246da4SFelipe Balbi #define DWC3_DSTS_PWRUPREQ (1 << 24) 22772246da4SFelipe Balbi #define DWC3_DSTS_COREIDLE (1 << 23) 22872246da4SFelipe Balbi #define DWC3_DSTS_DEVCTRLHLT (1 << 22) 22972246da4SFelipe Balbi 23072246da4SFelipe Balbi #define DWC3_DSTS_USBLNKST_MASK (0x0f << 18) 23172246da4SFelipe Balbi #define DWC3_DSTS_USBLNKST(n) (((n) & DWC3_DSTS_USBLNKST_MASK) >> 18) 23272246da4SFelipe Balbi 23372246da4SFelipe Balbi #define DWC3_DSTS_RXFIFOEMPTY (1 << 17) 23472246da4SFelipe Balbi 23572246da4SFelipe Balbi #define DWC3_DSTS_SOFFN_MASK (0x3ff << 3) 23672246da4SFelipe Balbi #define DWC3_DSTS_SOFFN(n) (((n) & DWC3_DSTS_SOFFN_MASK) >> 3) 23772246da4SFelipe Balbi 23872246da4SFelipe Balbi #define DWC3_DSTS_CONNECTSPD (7 << 0) 23972246da4SFelipe Balbi 24072246da4SFelipe Balbi #define DWC3_DSTS_SUPERSPEED (4 << 0) 24172246da4SFelipe Balbi #define DWC3_DSTS_HIGHSPEED (0 << 0) 24272246da4SFelipe Balbi #define DWC3_DSTS_FULLSPEED2 (1 << 0) 24372246da4SFelipe Balbi #define DWC3_DSTS_LOWSPEED (2 << 0) 24472246da4SFelipe Balbi #define DWC3_DSTS_FULLSPEED1 (3 << 0) 24572246da4SFelipe Balbi 24672246da4SFelipe Balbi /* Device Generic Command Register */ 24772246da4SFelipe Balbi #define DWC3_DGCMD_SET_LMP 0x01 24872246da4SFelipe Balbi #define DWC3_DGCMD_SET_PERIODIC_PAR 0x02 24972246da4SFelipe Balbi #define DWC3_DGCMD_XMIT_FUNCTION 0x03 25072246da4SFelipe Balbi #define DWC3_DGCMD_SELECTED_FIFO_FLUSH 0x09 25172246da4SFelipe Balbi #define DWC3_DGCMD_ALL_FIFO_FLUSH 0x0a 25272246da4SFelipe Balbi #define DWC3_DGCMD_SET_ENDPOINT_NRDY 0x0c 25372246da4SFelipe Balbi #define DWC3_DGCMD_RUN_SOC_BUS_LOOPBACK 0x10 25472246da4SFelipe Balbi 25572246da4SFelipe Balbi /* Device Endpoint Command Register */ 25672246da4SFelipe Balbi #define DWC3_DEPCMD_PARAM_SHIFT 16 25772246da4SFelipe Balbi #define DWC3_DEPCMD_PARAM(x) (x << DWC3_DEPCMD_PARAM_SHIFT) 25872246da4SFelipe Balbi #define DWC3_DEPCMD_GET_RSC_IDX(x) ((x >> DWC3_DEPCMD_PARAM_SHIFT) & 0x7f) 25972246da4SFelipe Balbi #define DWC3_DEPCMD_STATUS_MASK (0x0f << 12) 26072246da4SFelipe Balbi #define DWC3_DEPCMD_STATUS(x) ((x & DWC3_DEPCMD_STATUS_MASK) >> 12) 26172246da4SFelipe Balbi #define DWC3_DEPCMD_HIPRI_FORCERM (1 << 11) 26272246da4SFelipe Balbi #define DWC3_DEPCMD_CMDACT (1 << 10) 26372246da4SFelipe Balbi #define DWC3_DEPCMD_CMDIOC (1 << 8) 26472246da4SFelipe Balbi 26572246da4SFelipe Balbi #define DWC3_DEPCMD_DEPSTARTCFG (0x09 << 0) 26672246da4SFelipe Balbi #define DWC3_DEPCMD_ENDTRANSFER (0x08 << 0) 26772246da4SFelipe Balbi #define DWC3_DEPCMD_UPDATETRANSFER (0x07 << 0) 26872246da4SFelipe Balbi #define DWC3_DEPCMD_STARTTRANSFER (0x06 << 0) 26972246da4SFelipe Balbi #define DWC3_DEPCMD_CLEARSTALL (0x05 << 0) 27072246da4SFelipe Balbi #define DWC3_DEPCMD_SETSTALL (0x04 << 0) 27172246da4SFelipe Balbi #define DWC3_DEPCMD_GETSEQNUMBER (0x03 << 0) 27272246da4SFelipe Balbi #define DWC3_DEPCMD_SETTRANSFRESOURCE (0x02 << 0) 27372246da4SFelipe Balbi #define DWC3_DEPCMD_SETEPCONFIG (0x01 << 0) 27472246da4SFelipe Balbi 27572246da4SFelipe Balbi /* The EP number goes 0..31 so ep0 is always out and ep1 is always in */ 27672246da4SFelipe Balbi #define DWC3_DALEPENA_EP(n) (1 << n) 27772246da4SFelipe Balbi 27872246da4SFelipe Balbi #define DWC3_DEPCMD_TYPE_CONTROL 0 27972246da4SFelipe Balbi #define DWC3_DEPCMD_TYPE_ISOC 1 28072246da4SFelipe Balbi #define DWC3_DEPCMD_TYPE_BULK 2 28172246da4SFelipe Balbi #define DWC3_DEPCMD_TYPE_INTR 3 28272246da4SFelipe Balbi 28372246da4SFelipe Balbi /* Structures */ 28472246da4SFelipe Balbi 28572246da4SFelipe Balbi struct dwc3_trb_hw; 28672246da4SFelipe Balbi 28772246da4SFelipe Balbi /** 28872246da4SFelipe Balbi * struct dwc3_event_buffer - Software event buffer representation 28972246da4SFelipe Balbi * @list: a list of event buffers 29072246da4SFelipe Balbi * @buf: _THE_ buffer 29172246da4SFelipe Balbi * @length: size of this buffer 29272246da4SFelipe Balbi * @dma: dma_addr_t 29372246da4SFelipe Balbi * @dwc: pointer to DWC controller 29472246da4SFelipe Balbi */ 29572246da4SFelipe Balbi struct dwc3_event_buffer { 29672246da4SFelipe Balbi void *buf; 29772246da4SFelipe Balbi unsigned length; 29872246da4SFelipe Balbi unsigned int lpos; 29972246da4SFelipe Balbi 30072246da4SFelipe Balbi dma_addr_t dma; 30172246da4SFelipe Balbi 30272246da4SFelipe Balbi struct dwc3 *dwc; 30372246da4SFelipe Balbi }; 30472246da4SFelipe Balbi 30572246da4SFelipe Balbi #define DWC3_EP_FLAG_STALLED (1 << 0) 30672246da4SFelipe Balbi #define DWC3_EP_FLAG_WEDGED (1 << 1) 30772246da4SFelipe Balbi 30872246da4SFelipe Balbi #define DWC3_EP_DIRECTION_TX true 30972246da4SFelipe Balbi #define DWC3_EP_DIRECTION_RX false 31072246da4SFelipe Balbi 31172246da4SFelipe Balbi #define DWC3_TRB_NUM 32 31272246da4SFelipe Balbi #define DWC3_TRB_MASK (DWC3_TRB_NUM - 1) 31372246da4SFelipe Balbi 31472246da4SFelipe Balbi /** 31572246da4SFelipe Balbi * struct dwc3_ep - device side endpoint representation 31672246da4SFelipe Balbi * @endpoint: usb endpoint 31772246da4SFelipe Balbi * @request_list: list of requests for this endpoint 31872246da4SFelipe Balbi * @req_queued: list of requests on this ep which have TRBs setup 31972246da4SFelipe Balbi * @trb_pool: array of transaction buffers 32072246da4SFelipe Balbi * @trb_pool_dma: dma address of @trb_pool 32172246da4SFelipe Balbi * @free_slot: next slot which is going to be used 32272246da4SFelipe Balbi * @busy_slot: first slot which is owned by HW 32372246da4SFelipe Balbi * @desc: usb_endpoint_descriptor pointer 32472246da4SFelipe Balbi * @dwc: pointer to DWC controller 32572246da4SFelipe Balbi * @flags: endpoint flags (wedged, stalled, ...) 32672246da4SFelipe Balbi * @current_trb: index of current used trb 32772246da4SFelipe Balbi * @number: endpoint number (1 - 15) 32872246da4SFelipe Balbi * @type: set to bmAttributes & USB_ENDPOINT_XFERTYPE_MASK 32972246da4SFelipe Balbi * @res_trans_idx: Resource transfer index 33072246da4SFelipe Balbi * @interval: the intervall on which the ISOC transfer is started 33172246da4SFelipe Balbi * @name: a human readable name e.g. ep1out-bulk 33272246da4SFelipe Balbi * @direction: true for TX, false for RX 33372246da4SFelipe Balbi */ 33472246da4SFelipe Balbi struct dwc3_ep { 33572246da4SFelipe Balbi struct usb_ep endpoint; 33672246da4SFelipe Balbi struct list_head request_list; 33772246da4SFelipe Balbi struct list_head req_queued; 33872246da4SFelipe Balbi 33972246da4SFelipe Balbi struct dwc3_trb_hw *trb_pool; 34072246da4SFelipe Balbi dma_addr_t trb_pool_dma; 34172246da4SFelipe Balbi u32 free_slot; 34272246da4SFelipe Balbi u32 busy_slot; 34372246da4SFelipe Balbi const struct usb_endpoint_descriptor *desc; 34472246da4SFelipe Balbi struct dwc3 *dwc; 34572246da4SFelipe Balbi 34672246da4SFelipe Balbi unsigned flags; 34772246da4SFelipe Balbi #define DWC3_EP_ENABLED (1 << 0) 34872246da4SFelipe Balbi #define DWC3_EP_STALL (1 << 1) 34972246da4SFelipe Balbi #define DWC3_EP_WEDGE (1 << 2) 35072246da4SFelipe Balbi #define DWC3_EP_BUSY (1 << 4) 35172246da4SFelipe Balbi #define DWC3_EP_PENDING_REQUEST (1 << 5) 35272246da4SFelipe Balbi 353984f66a6SFelipe Balbi /* This last one is specific to EP0 */ 354984f66a6SFelipe Balbi #define DWC3_EP0_DIR_IN (1 << 31) 355984f66a6SFelipe Balbi 35672246da4SFelipe Balbi unsigned current_trb; 35772246da4SFelipe Balbi 35872246da4SFelipe Balbi u8 number; 35972246da4SFelipe Balbi u8 type; 36072246da4SFelipe Balbi u8 res_trans_idx; 36172246da4SFelipe Balbi u32 interval; 36272246da4SFelipe Balbi 36372246da4SFelipe Balbi char name[20]; 36472246da4SFelipe Balbi 36572246da4SFelipe Balbi unsigned direction:1; 36672246da4SFelipe Balbi }; 36772246da4SFelipe Balbi 36872246da4SFelipe Balbi enum dwc3_phy { 36972246da4SFelipe Balbi DWC3_PHY_UNKNOWN = 0, 37072246da4SFelipe Balbi DWC3_PHY_USB3, 37172246da4SFelipe Balbi DWC3_PHY_USB2, 37272246da4SFelipe Balbi }; 37372246da4SFelipe Balbi 374b53c772dSFelipe Balbi enum dwc3_ep0_next { 375b53c772dSFelipe Balbi DWC3_EP0_UNKNOWN = 0, 376b53c772dSFelipe Balbi DWC3_EP0_COMPLETE, 377b53c772dSFelipe Balbi DWC3_EP0_NRDY_SETUP, 378b53c772dSFelipe Balbi DWC3_EP0_NRDY_DATA, 379b53c772dSFelipe Balbi DWC3_EP0_NRDY_STATUS, 380b53c772dSFelipe Balbi }; 381b53c772dSFelipe Balbi 38272246da4SFelipe Balbi enum dwc3_ep0_state { 38372246da4SFelipe Balbi EP0_UNCONNECTED = 0, 384c7fcdeb2SFelipe Balbi EP0_SETUP_PHASE, 385c7fcdeb2SFelipe Balbi EP0_DATA_PHASE, 386c7fcdeb2SFelipe Balbi EP0_STATUS_PHASE, 38772246da4SFelipe Balbi }; 38872246da4SFelipe Balbi 38972246da4SFelipe Balbi enum dwc3_link_state { 39072246da4SFelipe Balbi /* In SuperSpeed */ 39172246da4SFelipe Balbi DWC3_LINK_STATE_U0 = 0x00, /* in HS, means ON */ 39272246da4SFelipe Balbi DWC3_LINK_STATE_U1 = 0x01, 39372246da4SFelipe Balbi DWC3_LINK_STATE_U2 = 0x02, /* in HS, means SLEEP */ 39472246da4SFelipe Balbi DWC3_LINK_STATE_U3 = 0x03, /* in HS, means SUSPEND */ 39572246da4SFelipe Balbi DWC3_LINK_STATE_SS_DIS = 0x04, 39672246da4SFelipe Balbi DWC3_LINK_STATE_RX_DET = 0x05, /* in HS, means Early Suspend */ 39772246da4SFelipe Balbi DWC3_LINK_STATE_SS_INACT = 0x06, 39872246da4SFelipe Balbi DWC3_LINK_STATE_POLL = 0x07, 39972246da4SFelipe Balbi DWC3_LINK_STATE_RECOV = 0x08, 40072246da4SFelipe Balbi DWC3_LINK_STATE_HRESET = 0x09, 40172246da4SFelipe Balbi DWC3_LINK_STATE_CMPLY = 0x0a, 40272246da4SFelipe Balbi DWC3_LINK_STATE_LPBK = 0x0b, 40372246da4SFelipe Balbi DWC3_LINK_STATE_MASK = 0x0f, 40472246da4SFelipe Balbi }; 40572246da4SFelipe Balbi 40672246da4SFelipe Balbi enum dwc3_device_state { 40772246da4SFelipe Balbi DWC3_DEFAULT_STATE, 40872246da4SFelipe Balbi DWC3_ADDRESS_STATE, 40972246da4SFelipe Balbi DWC3_CONFIGURED_STATE, 41072246da4SFelipe Balbi }; 41172246da4SFelipe Balbi 41272246da4SFelipe Balbi /** 41372246da4SFelipe Balbi * struct dwc3_trb - transfer request block 41472246da4SFelipe Balbi * @bpl: lower 32bit of the buffer 41572246da4SFelipe Balbi * @bph: higher 32bit of the buffer 41672246da4SFelipe Balbi * @length: buffer size (up to 16mb - 1) 41772246da4SFelipe Balbi * @pcm1: packet count m1 41872246da4SFelipe Balbi * @trbsts: trb status 41972246da4SFelipe Balbi * 0 = ok 42072246da4SFelipe Balbi * 1 = missed isoc 42172246da4SFelipe Balbi * 2 = setup pending 42272246da4SFelipe Balbi * @hwo: hardware owner of descriptor 42372246da4SFelipe Balbi * @lst: last trb 42472246da4SFelipe Balbi * @chn: chain buffers 42572246da4SFelipe Balbi * @csp: continue on short packets (only supported on isoc eps) 42672246da4SFelipe Balbi * @trbctl: trb control 42772246da4SFelipe Balbi * 1 = normal 42872246da4SFelipe Balbi * 2 = control-setup 42972246da4SFelipe Balbi * 3 = control-status-2 43072246da4SFelipe Balbi * 4 = control-status-3 43172246da4SFelipe Balbi * 5 = control-data (first trb of data stage) 43272246da4SFelipe Balbi * 6 = isochronous-first (first trb of service interval) 43372246da4SFelipe Balbi * 7 = isochronous 43472246da4SFelipe Balbi * 8 = link trb 43572246da4SFelipe Balbi * others = reserved 43672246da4SFelipe Balbi * @isp_imi: interrupt on short packet / interrupt on missed isoc 43772246da4SFelipe Balbi * @ioc: interrupt on complete 43872246da4SFelipe Balbi * @sid_sofn: Stream ID / SOF Number 43972246da4SFelipe Balbi */ 44072246da4SFelipe Balbi struct dwc3_trb { 44172246da4SFelipe Balbi u64 bplh; 44272246da4SFelipe Balbi 44372246da4SFelipe Balbi union { 44472246da4SFelipe Balbi struct { 44572246da4SFelipe Balbi u32 length:24; 44672246da4SFelipe Balbi u32 pcm1:2; 44772246da4SFelipe Balbi u32 reserved27_26:2; 44872246da4SFelipe Balbi u32 trbsts:4; 44972246da4SFelipe Balbi #define DWC3_TRB_STS_OKAY 0 45072246da4SFelipe Balbi #define DWC3_TRB_STS_MISSED_ISOC 1 45172246da4SFelipe Balbi #define DWC3_TRB_STS_SETUP_PENDING 2 45272246da4SFelipe Balbi }; 45372246da4SFelipe Balbi u32 len_pcm; 45472246da4SFelipe Balbi }; 45572246da4SFelipe Balbi 45672246da4SFelipe Balbi union { 45772246da4SFelipe Balbi struct { 45872246da4SFelipe Balbi u32 hwo:1; 45972246da4SFelipe Balbi u32 lst:1; 46072246da4SFelipe Balbi u32 chn:1; 46172246da4SFelipe Balbi u32 csp:1; 46272246da4SFelipe Balbi u32 trbctl:6; 46372246da4SFelipe Balbi u32 isp_imi:1; 46472246da4SFelipe Balbi u32 ioc:1; 46572246da4SFelipe Balbi u32 reserved13_12:2; 46672246da4SFelipe Balbi u32 sid_sofn:16; 46772246da4SFelipe Balbi u32 reserved31_30:2; 46872246da4SFelipe Balbi }; 46972246da4SFelipe Balbi u32 control; 47072246da4SFelipe Balbi }; 47172246da4SFelipe Balbi } __packed; 47272246da4SFelipe Balbi 47372246da4SFelipe Balbi /** 47472246da4SFelipe Balbi * struct dwc3_trb_hw - transfer request block (hw format) 47572246da4SFelipe Balbi * @bpl: DW0-3 47672246da4SFelipe Balbi * @bph: DW4-7 47772246da4SFelipe Balbi * @size: DW8-B 47872246da4SFelipe Balbi * @trl: DWC-F 47972246da4SFelipe Balbi */ 48072246da4SFelipe Balbi struct dwc3_trb_hw { 48172246da4SFelipe Balbi __le32 bpl; 48272246da4SFelipe Balbi __le32 bph; 48372246da4SFelipe Balbi __le32 size; 48472246da4SFelipe Balbi __le32 ctrl; 48572246da4SFelipe Balbi } __packed; 48672246da4SFelipe Balbi 48772246da4SFelipe Balbi static inline void dwc3_trb_to_hw(struct dwc3_trb *nat, struct dwc3_trb_hw *hw) 48872246da4SFelipe Balbi { 48972246da4SFelipe Balbi hw->bpl = cpu_to_le32(lower_32_bits(nat->bplh)); 49072246da4SFelipe Balbi hw->bph = cpu_to_le32(upper_32_bits(nat->bplh)); 49172246da4SFelipe Balbi hw->size = cpu_to_le32p(&nat->len_pcm); 49272246da4SFelipe Balbi /* HWO is written last */ 49372246da4SFelipe Balbi hw->ctrl = cpu_to_le32p(&nat->control); 49472246da4SFelipe Balbi } 49572246da4SFelipe Balbi 49672246da4SFelipe Balbi static inline void dwc3_trb_to_nat(struct dwc3_trb_hw *hw, struct dwc3_trb *nat) 49772246da4SFelipe Balbi { 49872246da4SFelipe Balbi u64 bplh; 49972246da4SFelipe Balbi 50072246da4SFelipe Balbi bplh = le32_to_cpup(&hw->bpl); 50172246da4SFelipe Balbi bplh |= (u64) le32_to_cpup(&hw->bph) << 32; 50272246da4SFelipe Balbi nat->bplh = bplh; 50372246da4SFelipe Balbi 50472246da4SFelipe Balbi nat->len_pcm = le32_to_cpup(&hw->size); 50572246da4SFelipe Balbi nat->control = le32_to_cpup(&hw->ctrl); 50672246da4SFelipe Balbi } 50772246da4SFelipe Balbi 50872246da4SFelipe Balbi /** 50972246da4SFelipe Balbi * struct dwc3 - representation of our controller 51091db07dcSFelipe Balbi * @ctrl_req: usb control request which is used for ep0 51191db07dcSFelipe Balbi * @ep0_trb: trb which is used for the ctrl_req 5125812b1c2SFelipe Balbi * @ep0_bounce: bounce buffer for ep0 51391db07dcSFelipe Balbi * @setup_buf: used while precessing STD USB requests 51491db07dcSFelipe Balbi * @ctrl_req_addr: dma address of ctrl_req 51591db07dcSFelipe Balbi * @ep0_trb: dma address of ep0_trb 51691db07dcSFelipe Balbi * @ep0_usb_req: dummy req used while handling STD USB requests 51791db07dcSFelipe Balbi * @setup_buf_addr: dma address of setup_buf 5185812b1c2SFelipe Balbi * @ep0_bounce_addr: dma address of ep0_bounce 51972246da4SFelipe Balbi * @lock: for synchronizing 52072246da4SFelipe Balbi * @dev: pointer to our struct device 52172246da4SFelipe Balbi * @event_buffer_list: a list of event buffers 52272246da4SFelipe Balbi * @gadget: device side representation of the peripheral controller 52372246da4SFelipe Balbi * @gadget_driver: pointer to the gadget driver 52472246da4SFelipe Balbi * @regs: base address for our registers 52572246da4SFelipe Balbi * @regs_size: address space size 52672246da4SFelipe Balbi * @irq: IRQ number 52772246da4SFelipe Balbi * @revision: revision register contents 52872246da4SFelipe Balbi * @is_selfpowered: true when we are selfpowered 52972246da4SFelipe Balbi * @three_stage_setup: set if we perform a three phase setup 53072246da4SFelipe Balbi * @ep0_status_pending: ep0 status response without a req is pending 5315812b1c2SFelipe Balbi * @ep0_bounced: true when we used bounce buffer 532b53c772dSFelipe Balbi * @ep0_next_event: hold the next expected event 53372246da4SFelipe Balbi * @ep0state: state of endpoint zero 53472246da4SFelipe Balbi * @link_state: link state 53572246da4SFelipe Balbi * @speed: device speed (super, high, full, low) 53672246da4SFelipe Balbi * @mem: points to start of memory which is used for this struct. 53772246da4SFelipe Balbi * @root: debugfs root folder pointer 53872246da4SFelipe Balbi */ 53972246da4SFelipe Balbi struct dwc3 { 54072246da4SFelipe Balbi struct usb_ctrlrequest *ctrl_req; 54172246da4SFelipe Balbi struct dwc3_trb_hw *ep0_trb; 5425812b1c2SFelipe Balbi void *ep0_bounce; 54372246da4SFelipe Balbi u8 *setup_buf; 54472246da4SFelipe Balbi dma_addr_t ctrl_req_addr; 54572246da4SFelipe Balbi dma_addr_t ep0_trb_addr; 54672246da4SFelipe Balbi dma_addr_t setup_buf_addr; 5475812b1c2SFelipe Balbi dma_addr_t ep0_bounce_addr; 54872246da4SFelipe Balbi struct usb_request ep0_usb_req; 54972246da4SFelipe Balbi /* device lock */ 55072246da4SFelipe Balbi spinlock_t lock; 55172246da4SFelipe Balbi struct device *dev; 55272246da4SFelipe Balbi 55372246da4SFelipe Balbi struct dwc3_event_buffer *ev_buffs[DWC3_EVENT_BUFFERS_NUM]; 55472246da4SFelipe Balbi struct dwc3_ep *eps[DWC3_ENDPOINTS_NUM]; 55572246da4SFelipe Balbi 55672246da4SFelipe Balbi struct usb_gadget gadget; 55772246da4SFelipe Balbi struct usb_gadget_driver *gadget_driver; 55872246da4SFelipe Balbi 55972246da4SFelipe Balbi void __iomem *regs; 56072246da4SFelipe Balbi size_t regs_size; 56172246da4SFelipe Balbi 56272246da4SFelipe Balbi int irq; 56372246da4SFelipe Balbi 56472246da4SFelipe Balbi u32 revision; 56572246da4SFelipe Balbi 56672246da4SFelipe Balbi #define DWC3_REVISION_173A 0x5533173a 56772246da4SFelipe Balbi #define DWC3_REVISION_175A 0x5533175a 56872246da4SFelipe Balbi #define DWC3_REVISION_180A 0x5533180a 56972246da4SFelipe Balbi #define DWC3_REVISION_183A 0x5533183a 57072246da4SFelipe Balbi #define DWC3_REVISION_185A 0x5533185a 57172246da4SFelipe Balbi #define DWC3_REVISION_188A 0x5533188a 57272246da4SFelipe Balbi #define DWC3_REVISION_190A 0x5533190a 57372246da4SFelipe Balbi 57472246da4SFelipe Balbi unsigned is_selfpowered:1; 57572246da4SFelipe Balbi unsigned three_stage_setup:1; 57672246da4SFelipe Balbi unsigned ep0_status_pending:1; 5775812b1c2SFelipe Balbi unsigned ep0_bounced:1; 57872246da4SFelipe Balbi 579b53c772dSFelipe Balbi enum dwc3_ep0_next ep0_next_event; 58072246da4SFelipe Balbi enum dwc3_ep0_state ep0state; 58172246da4SFelipe Balbi enum dwc3_link_state link_state; 58272246da4SFelipe Balbi enum dwc3_device_state dev_state; 58372246da4SFelipe Balbi 58472246da4SFelipe Balbi u8 speed; 58572246da4SFelipe Balbi void *mem; 58672246da4SFelipe Balbi 58772246da4SFelipe Balbi struct dentry *root; 58872246da4SFelipe Balbi }; 58972246da4SFelipe Balbi 59072246da4SFelipe Balbi /* -------------------------------------------------------------------------- */ 59172246da4SFelipe Balbi 59272246da4SFelipe Balbi #define DWC3_TRBSTS_OK 0 59372246da4SFelipe Balbi #define DWC3_TRBSTS_MISSED_ISOC 1 59472246da4SFelipe Balbi #define DWC3_TRBSTS_SETUP_PENDING 2 59572246da4SFelipe Balbi 59672246da4SFelipe Balbi #define DWC3_TRBCTL_NORMAL 1 59772246da4SFelipe Balbi #define DWC3_TRBCTL_CONTROL_SETUP 2 59872246da4SFelipe Balbi #define DWC3_TRBCTL_CONTROL_STATUS2 3 59972246da4SFelipe Balbi #define DWC3_TRBCTL_CONTROL_STATUS3 4 60072246da4SFelipe Balbi #define DWC3_TRBCTL_CONTROL_DATA 5 60172246da4SFelipe Balbi #define DWC3_TRBCTL_ISOCHRONOUS_FIRST 6 60272246da4SFelipe Balbi #define DWC3_TRBCTL_ISOCHRONOUS 7 60372246da4SFelipe Balbi #define DWC3_TRBCTL_LINK_TRB 8 60472246da4SFelipe Balbi 60572246da4SFelipe Balbi /* -------------------------------------------------------------------------- */ 60672246da4SFelipe Balbi 60772246da4SFelipe Balbi struct dwc3_event_type { 60872246da4SFelipe Balbi u32 is_devspec:1; 60972246da4SFelipe Balbi u32 type:6; 61072246da4SFelipe Balbi u32 reserved8_31:25; 61172246da4SFelipe Balbi } __packed; 61272246da4SFelipe Balbi 61372246da4SFelipe Balbi #define DWC3_DEPEVT_XFERCOMPLETE 0x01 61472246da4SFelipe Balbi #define DWC3_DEPEVT_XFERINPROGRESS 0x02 61572246da4SFelipe Balbi #define DWC3_DEPEVT_XFERNOTREADY 0x03 61672246da4SFelipe Balbi #define DWC3_DEPEVT_RXTXFIFOEVT 0x04 61772246da4SFelipe Balbi #define DWC3_DEPEVT_STREAMEVT 0x06 61872246da4SFelipe Balbi #define DWC3_DEPEVT_EPCMDCMPLT 0x07 61972246da4SFelipe Balbi 62072246da4SFelipe Balbi /** 62172246da4SFelipe Balbi * struct dwc3_event_depvt - Device Endpoint Events 62272246da4SFelipe Balbi * @one_bit: indicates this is an endpoint event (not used) 62372246da4SFelipe Balbi * @endpoint_number: number of the endpoint 62472246da4SFelipe Balbi * @endpoint_event: The event we have: 62572246da4SFelipe Balbi * 0x00 - Reserved 62672246da4SFelipe Balbi * 0x01 - XferComplete 62772246da4SFelipe Balbi * 0x02 - XferInProgress 62872246da4SFelipe Balbi * 0x03 - XferNotReady 62972246da4SFelipe Balbi * 0x04 - RxTxFifoEvt (IN->Underrun, OUT->Overrun) 63072246da4SFelipe Balbi * 0x05 - Reserved 63172246da4SFelipe Balbi * 0x06 - StreamEvt 63272246da4SFelipe Balbi * 0x07 - EPCmdCmplt 63372246da4SFelipe Balbi * @reserved11_10: Reserved, don't use. 63472246da4SFelipe Balbi * @status: Indicates the status of the event. Refer to databook for 63572246da4SFelipe Balbi * more information. 63672246da4SFelipe Balbi * @parameters: Parameters of the current event. Refer to databook for 63772246da4SFelipe Balbi * more information. 63872246da4SFelipe Balbi */ 63972246da4SFelipe Balbi struct dwc3_event_depevt { 64072246da4SFelipe Balbi u32 one_bit:1; 64172246da4SFelipe Balbi u32 endpoint_number:5; 64272246da4SFelipe Balbi u32 endpoint_event:4; 64372246da4SFelipe Balbi u32 reserved11_10:2; 64472246da4SFelipe Balbi u32 status:4; 64572246da4SFelipe Balbi #define DEPEVT_STATUS_BUSERR (1 << 0) 64672246da4SFelipe Balbi #define DEPEVT_STATUS_SHORT (1 << 1) 64772246da4SFelipe Balbi #define DEPEVT_STATUS_IOC (1 << 2) 64872246da4SFelipe Balbi #define DEPEVT_STATUS_LST (1 << 3) 649dc137f01SFelipe Balbi 650dc137f01SFelipe Balbi /* Control-only Status */ 651dc137f01SFelipe Balbi #define DEPEVT_STATUS_CONTROL_SETUP 0 652dc137f01SFelipe Balbi #define DEPEVT_STATUS_CONTROL_DATA 1 653dc137f01SFelipe Balbi #define DEPEVT_STATUS_CONTROL_STATUS 2 654dc137f01SFelipe Balbi 65572246da4SFelipe Balbi u32 parameters:16; 65672246da4SFelipe Balbi } __packed; 65772246da4SFelipe Balbi 65872246da4SFelipe Balbi /** 65972246da4SFelipe Balbi * struct dwc3_event_devt - Device Events 66072246da4SFelipe Balbi * @one_bit: indicates this is a non-endpoint event (not used) 66172246da4SFelipe Balbi * @device_event: indicates it's a device event. Should read as 0x00 66272246da4SFelipe Balbi * @type: indicates the type of device event. 66372246da4SFelipe Balbi * 0 - DisconnEvt 66472246da4SFelipe Balbi * 1 - USBRst 66572246da4SFelipe Balbi * 2 - ConnectDone 66672246da4SFelipe Balbi * 3 - ULStChng 66772246da4SFelipe Balbi * 4 - WkUpEvt 66872246da4SFelipe Balbi * 5 - Reserved 66972246da4SFelipe Balbi * 6 - EOPF 67072246da4SFelipe Balbi * 7 - SOF 67172246da4SFelipe Balbi * 8 - Reserved 67272246da4SFelipe Balbi * 9 - ErrticErr 67372246da4SFelipe Balbi * 10 - CmdCmplt 67472246da4SFelipe Balbi * 11 - EvntOverflow 67572246da4SFelipe Balbi * 12 - VndrDevTstRcved 67672246da4SFelipe Balbi * @reserved15_12: Reserved, not used 67772246da4SFelipe Balbi * @event_info: Information about this event 67872246da4SFelipe Balbi * @reserved31_24: Reserved, not used 67972246da4SFelipe Balbi */ 68072246da4SFelipe Balbi struct dwc3_event_devt { 68172246da4SFelipe Balbi u32 one_bit:1; 68272246da4SFelipe Balbi u32 device_event:7; 68372246da4SFelipe Balbi u32 type:4; 68472246da4SFelipe Balbi u32 reserved15_12:4; 68572246da4SFelipe Balbi u32 event_info:8; 68672246da4SFelipe Balbi u32 reserved31_24:8; 68772246da4SFelipe Balbi } __packed; 68872246da4SFelipe Balbi 68972246da4SFelipe Balbi /** 69072246da4SFelipe Balbi * struct dwc3_event_gevt - Other Core Events 69172246da4SFelipe Balbi * @one_bit: indicates this is a non-endpoint event (not used) 69272246da4SFelipe Balbi * @device_event: indicates it's (0x03) Carkit or (0x04) I2C event. 69372246da4SFelipe Balbi * @phy_port_number: self-explanatory 69472246da4SFelipe Balbi * @reserved31_12: Reserved, not used. 69572246da4SFelipe Balbi */ 69672246da4SFelipe Balbi struct dwc3_event_gevt { 69772246da4SFelipe Balbi u32 one_bit:1; 69872246da4SFelipe Balbi u32 device_event:7; 69972246da4SFelipe Balbi u32 phy_port_number:4; 70072246da4SFelipe Balbi u32 reserved31_12:20; 70172246da4SFelipe Balbi } __packed; 70272246da4SFelipe Balbi 70372246da4SFelipe Balbi /** 70472246da4SFelipe Balbi * union dwc3_event - representation of Event Buffer contents 70572246da4SFelipe Balbi * @raw: raw 32-bit event 70672246da4SFelipe Balbi * @type: the type of the event 70772246da4SFelipe Balbi * @depevt: Device Endpoint Event 70872246da4SFelipe Balbi * @devt: Device Event 70972246da4SFelipe Balbi * @gevt: Global Event 71072246da4SFelipe Balbi */ 71172246da4SFelipe Balbi union dwc3_event { 71272246da4SFelipe Balbi u32 raw; 71372246da4SFelipe Balbi struct dwc3_event_type type; 71472246da4SFelipe Balbi struct dwc3_event_depevt depevt; 71572246da4SFelipe Balbi struct dwc3_event_devt devt; 71672246da4SFelipe Balbi struct dwc3_event_gevt gevt; 71772246da4SFelipe Balbi }; 71872246da4SFelipe Balbi 71972246da4SFelipe Balbi /* 72072246da4SFelipe Balbi * DWC3 Features to be used as Driver Data 72172246da4SFelipe Balbi */ 72272246da4SFelipe Balbi 72372246da4SFelipe Balbi #define DWC3_HAS_PERIPHERAL BIT(0) 72472246da4SFelipe Balbi #define DWC3_HAS_XHCI BIT(1) 72572246da4SFelipe Balbi #define DWC3_HAS_OTG BIT(3) 72672246da4SFelipe Balbi 72772246da4SFelipe Balbi #endif /* __DRIVERS_USB_DWC3_CORE_H */ 728