1b33f69f5SNishad Kamdar /* SPDX-License-Identifier: GPL-2.0 */ 2bfad65eeSFelipe Balbi /* 372246da4SFelipe Balbi * core.h - DesignWare USB3 DRD Core Header 472246da4SFelipe Balbi * 510623b87SAlexander A. Klimov * Copyright (C) 2010-2011 Texas Instruments Incorporated - https://www.ti.com 672246da4SFelipe Balbi * 772246da4SFelipe Balbi * Authors: Felipe Balbi <balbi@ti.com>, 872246da4SFelipe Balbi * Sebastian Andrzej Siewior <bigeasy@linutronix.de> 972246da4SFelipe Balbi */ 1072246da4SFelipe Balbi 1172246da4SFelipe Balbi #ifndef __DRIVERS_USB_DWC3_CORE_H 1272246da4SFelipe Balbi #define __DRIVERS_USB_DWC3_CORE_H 1372246da4SFelipe Balbi 1472246da4SFelipe Balbi #include <linux/device.h> 1572246da4SFelipe Balbi #include <linux/spinlock.h> 16d07e8819SFelipe Balbi #include <linux/ioport.h> 1772246da4SFelipe Balbi #include <linux/list.h> 18ff3f0789SRoger Quadros #include <linux/bitops.h> 1972246da4SFelipe Balbi #include <linux/dma-mapping.h> 2072246da4SFelipe Balbi #include <linux/mm.h> 2172246da4SFelipe Balbi #include <linux/debugfs.h> 2276a638f8SBaolin Wang #include <linux/wait.h> 2341ce1456SRoger Quadros #include <linux/workqueue.h> 2472246da4SFelipe Balbi 2572246da4SFelipe Balbi #include <linux/usb/ch9.h> 2672246da4SFelipe Balbi #include <linux/usb/gadget.h> 27a45c82b8SRuchika Kharwar #include <linux/usb/otg.h> 288a0a1379SYu Chen #include <linux/usb/role.h> 2988bc9d19SHeikki Krogerus #include <linux/ulpi/interface.h> 3072246da4SFelipe Balbi 3157303488SKishon Vijay Abraham I #include <linux/phy/phy.h> 3257303488SKishon Vijay Abraham I 332c4cbe6eSFelipe Balbi #define DWC3_MSG_MAX 500 342c4cbe6eSFelipe Balbi 3572246da4SFelipe Balbi /* Global constants */ 36bb014736SBaolin Wang #define DWC3_PULL_UP_TIMEOUT 500 /* ms */ 37905dc04eSFelipe Balbi #define DWC3_BOUNCE_SIZE 1024 /* size of a superspeed bulk */ 384199c5f8SFelipe Balbi #define DWC3_EP0_SETUP_SIZE 512 3972246da4SFelipe Balbi #define DWC3_ENDPOINTS_NUM 32 4051249dcaSIdo Shayevitz #define DWC3_XHCI_RESOURCES_NUM 2 41d5370106SFelipe Balbi #define DWC3_ISOC_MAX_RETRIES 5 4272246da4SFelipe Balbi 430ffcaf37SFelipe Balbi #define DWC3_SCRATCHBUF_SIZE 4096 /* each buffer is assumed to be 4KiB */ 44e71d363dSFelipe Balbi #define DWC3_EVENT_BUFFERS_SIZE 4096 4572246da4SFelipe Balbi #define DWC3_EVENT_TYPE_MASK 0xfe 4672246da4SFelipe Balbi 4772246da4SFelipe Balbi #define DWC3_EVENT_TYPE_DEV 0 4872246da4SFelipe Balbi #define DWC3_EVENT_TYPE_CARKIT 3 4972246da4SFelipe Balbi #define DWC3_EVENT_TYPE_I2C 4 5072246da4SFelipe Balbi 5172246da4SFelipe Balbi #define DWC3_DEVICE_EVENT_DISCONNECT 0 5272246da4SFelipe Balbi #define DWC3_DEVICE_EVENT_RESET 1 5372246da4SFelipe Balbi #define DWC3_DEVICE_EVENT_CONNECT_DONE 2 5472246da4SFelipe Balbi #define DWC3_DEVICE_EVENT_LINK_STATUS_CHANGE 3 5572246da4SFelipe Balbi #define DWC3_DEVICE_EVENT_WAKEUP 4 562c61a8efSPaul Zimmerman #define DWC3_DEVICE_EVENT_HIBER_REQ 5 5772246da4SFelipe Balbi #define DWC3_DEVICE_EVENT_EOPF 6 5872246da4SFelipe Balbi #define DWC3_DEVICE_EVENT_SOF 7 5972246da4SFelipe Balbi #define DWC3_DEVICE_EVENT_ERRATIC_ERROR 9 6072246da4SFelipe Balbi #define DWC3_DEVICE_EVENT_CMD_CMPL 10 6172246da4SFelipe Balbi #define DWC3_DEVICE_EVENT_OVERFLOW 11 6272246da4SFelipe Balbi 63f09cc79bSRoger Quadros /* Controller's role while using the OTG block */ 64f09cc79bSRoger Quadros #define DWC3_OTG_ROLE_IDLE 0 65f09cc79bSRoger Quadros #define DWC3_OTG_ROLE_HOST 1 66f09cc79bSRoger Quadros #define DWC3_OTG_ROLE_DEVICE 2 67f09cc79bSRoger Quadros 6872246da4SFelipe Balbi #define DWC3_GEVNTCOUNT_MASK 0xfffc 69ff3f0789SRoger Quadros #define DWC3_GEVNTCOUNT_EHB BIT(31) 7072246da4SFelipe Balbi #define DWC3_GSNPSID_MASK 0xffff0000 7172246da4SFelipe Balbi #define DWC3_GSNPSREV_MASK 0xffff 729af21dd6SThinh Nguyen #define DWC3_GSNPS_ID(p) (((p) & DWC3_GSNPSID_MASK) >> 16) 7372246da4SFelipe Balbi 7451249dcaSIdo Shayevitz /* DWC3 registers memory space boundries */ 7551249dcaSIdo Shayevitz #define DWC3_XHCI_REGS_START 0x0 7651249dcaSIdo Shayevitz #define DWC3_XHCI_REGS_END 0x7fff 7751249dcaSIdo Shayevitz #define DWC3_GLOBALS_REGS_START 0xc100 7851249dcaSIdo Shayevitz #define DWC3_GLOBALS_REGS_END 0xc6ff 7951249dcaSIdo Shayevitz #define DWC3_DEVICE_REGS_START 0xc700 8051249dcaSIdo Shayevitz #define DWC3_DEVICE_REGS_END 0xcbff 8151249dcaSIdo Shayevitz #define DWC3_OTG_REGS_START 0xcc00 8251249dcaSIdo Shayevitz #define DWC3_OTG_REGS_END 0xccff 8351249dcaSIdo Shayevitz 8472246da4SFelipe Balbi /* Global Registers */ 8572246da4SFelipe Balbi #define DWC3_GSBUSCFG0 0xc100 8672246da4SFelipe Balbi #define DWC3_GSBUSCFG1 0xc104 8772246da4SFelipe Balbi #define DWC3_GTXTHRCFG 0xc108 8872246da4SFelipe Balbi #define DWC3_GRXTHRCFG 0xc10c 8972246da4SFelipe Balbi #define DWC3_GCTL 0xc110 9072246da4SFelipe Balbi #define DWC3_GEVTEN 0xc114 9172246da4SFelipe Balbi #define DWC3_GSTS 0xc118 92475c8bebSWilliam Wu #define DWC3_GUCTL1 0xc11c 9372246da4SFelipe Balbi #define DWC3_GSNPSID 0xc120 9472246da4SFelipe Balbi #define DWC3_GGPIO 0xc124 9572246da4SFelipe Balbi #define DWC3_GUID 0xc128 9672246da4SFelipe Balbi #define DWC3_GUCTL 0xc12c 9772246da4SFelipe Balbi #define DWC3_GBUSERRADDR0 0xc130 9872246da4SFelipe Balbi #define DWC3_GBUSERRADDR1 0xc134 9972246da4SFelipe Balbi #define DWC3_GPRTBIMAP0 0xc138 10072246da4SFelipe Balbi #define DWC3_GPRTBIMAP1 0xc13c 10172246da4SFelipe Balbi #define DWC3_GHWPARAMS0 0xc140 10272246da4SFelipe Balbi #define DWC3_GHWPARAMS1 0xc144 10372246da4SFelipe Balbi #define DWC3_GHWPARAMS2 0xc148 10472246da4SFelipe Balbi #define DWC3_GHWPARAMS3 0xc14c 10572246da4SFelipe Balbi #define DWC3_GHWPARAMS4 0xc150 10672246da4SFelipe Balbi #define DWC3_GHWPARAMS5 0xc154 10772246da4SFelipe Balbi #define DWC3_GHWPARAMS6 0xc158 10872246da4SFelipe Balbi #define DWC3_GHWPARAMS7 0xc15c 10972246da4SFelipe Balbi #define DWC3_GDBGFIFOSPACE 0xc160 11072246da4SFelipe Balbi #define DWC3_GDBGLTSSM 0xc164 11180b77634SThinh Nguyen #define DWC3_GDBGBMU 0xc16c 11280b77634SThinh Nguyen #define DWC3_GDBGLSPMUX 0xc170 11380b77634SThinh Nguyen #define DWC3_GDBGLSP 0xc174 11480b77634SThinh Nguyen #define DWC3_GDBGEPINFO0 0xc178 11580b77634SThinh Nguyen #define DWC3_GDBGEPINFO1 0xc17c 11672246da4SFelipe Balbi #define DWC3_GPRTBIMAP_HS0 0xc180 11772246da4SFelipe Balbi #define DWC3_GPRTBIMAP_HS1 0xc184 11872246da4SFelipe Balbi #define DWC3_GPRTBIMAP_FS0 0xc188 11972246da4SFelipe Balbi #define DWC3_GPRTBIMAP_FS1 0xc18c 12006281d46SJohn Youn #define DWC3_GUCTL2 0xc19c 12172246da4SFelipe Balbi 122690fb371SJohn Youn #define DWC3_VER_NUMBER 0xc1a0 123690fb371SJohn Youn #define DWC3_VER_TYPE 0xc1a4 124690fb371SJohn Youn 1258261bd4eSRoger Quadros #define DWC3_GUSB2PHYCFG(n) (0xc200 + ((n) * 0x04)) 1268261bd4eSRoger Quadros #define DWC3_GUSB2I2CCTL(n) (0xc240 + ((n) * 0x04)) 12772246da4SFelipe Balbi 1288261bd4eSRoger Quadros #define DWC3_GUSB2PHYACC(n) (0xc280 + ((n) * 0x04)) 12972246da4SFelipe Balbi 1308261bd4eSRoger Quadros #define DWC3_GUSB3PIPECTL(n) (0xc2c0 + ((n) * 0x04)) 13172246da4SFelipe Balbi 1328261bd4eSRoger Quadros #define DWC3_GTXFIFOSIZ(n) (0xc300 + ((n) * 0x04)) 1338261bd4eSRoger Quadros #define DWC3_GRXFIFOSIZ(n) (0xc380 + ((n) * 0x04)) 13472246da4SFelipe Balbi 1358261bd4eSRoger Quadros #define DWC3_GEVNTADRLO(n) (0xc400 + ((n) * 0x10)) 1368261bd4eSRoger Quadros #define DWC3_GEVNTADRHI(n) (0xc404 + ((n) * 0x10)) 1378261bd4eSRoger Quadros #define DWC3_GEVNTSIZ(n) (0xc408 + ((n) * 0x10)) 1388261bd4eSRoger Quadros #define DWC3_GEVNTCOUNT(n) (0xc40c + ((n) * 0x10)) 13972246da4SFelipe Balbi 14072246da4SFelipe Balbi #define DWC3_GHWPARAMS8 0xc600 141f580170fSYu Chen #define DWC3_GUCTL3 0xc60c 142db2be4e9SNikhil Badola #define DWC3_GFLADJ 0xc630 14372246da4SFelipe Balbi 14472246da4SFelipe Balbi /* Device Registers */ 14572246da4SFelipe Balbi #define DWC3_DCFG 0xc700 14672246da4SFelipe Balbi #define DWC3_DCTL 0xc704 14772246da4SFelipe Balbi #define DWC3_DEVTEN 0xc708 14872246da4SFelipe Balbi #define DWC3_DSTS 0xc70c 14972246da4SFelipe Balbi #define DWC3_DGCMDPAR 0xc710 15072246da4SFelipe Balbi #define DWC3_DGCMD 0xc714 15172246da4SFelipe Balbi #define DWC3_DALEPENA 0xc720 1522eb88016SFelipe Balbi 1538261bd4eSRoger Quadros #define DWC3_DEP_BASE(n) (0xc800 + ((n) * 0x10)) 1542eb88016SFelipe Balbi #define DWC3_DEPCMDPAR2 0x00 1552eb88016SFelipe Balbi #define DWC3_DEPCMDPAR1 0x04 1562eb88016SFelipe Balbi #define DWC3_DEPCMDPAR0 0x08 1572eb88016SFelipe Balbi #define DWC3_DEPCMD 0x0c 15872246da4SFelipe Balbi 1598261bd4eSRoger Quadros #define DWC3_DEV_IMOD(n) (0xca00 + ((n) * 0x4)) 160cf40b86bSJohn Youn 16172246da4SFelipe Balbi /* OTG Registers */ 16272246da4SFelipe Balbi #define DWC3_OCFG 0xcc00 16372246da4SFelipe Balbi #define DWC3_OCTL 0xcc04 164d4436c3aSGeorge Cherian #define DWC3_OEVT 0xcc08 165d4436c3aSGeorge Cherian #define DWC3_OEVTEN 0xcc0C 166d4436c3aSGeorge Cherian #define DWC3_OSTS 0xcc10 16772246da4SFelipe Balbi 16872246da4SFelipe Balbi /* Bit fields */ 16972246da4SFelipe Balbi 170d635db55SPengbo Mu /* Global SoC Bus Configuration INCRx Register 0 */ 171d635db55SPengbo Mu #define DWC3_GSBUSCFG0_INCR256BRSTENA (1 << 7) /* INCR256 burst */ 172d635db55SPengbo Mu #define DWC3_GSBUSCFG0_INCR128BRSTENA (1 << 6) /* INCR128 burst */ 173d635db55SPengbo Mu #define DWC3_GSBUSCFG0_INCR64BRSTENA (1 << 5) /* INCR64 burst */ 174d635db55SPengbo Mu #define DWC3_GSBUSCFG0_INCR32BRSTENA (1 << 4) /* INCR32 burst */ 175d635db55SPengbo Mu #define DWC3_GSBUSCFG0_INCR16BRSTENA (1 << 3) /* INCR16 burst */ 176d635db55SPengbo Mu #define DWC3_GSBUSCFG0_INCR8BRSTENA (1 << 2) /* INCR8 burst */ 177d635db55SPengbo Mu #define DWC3_GSBUSCFG0_INCR4BRSTENA (1 << 1) /* INCR4 burst */ 178d635db55SPengbo Mu #define DWC3_GSBUSCFG0_INCRBRSTENA (1 << 0) /* undefined length enable */ 179d635db55SPengbo Mu #define DWC3_GSBUSCFG0_INCRBRST_MASK 0xff 180d635db55SPengbo Mu 18162ba09d6SThinh Nguyen /* Global Debug LSP MUX Select */ 18262ba09d6SThinh Nguyen #define DWC3_GDBGLSPMUX_ENDBC BIT(15) /* Host only */ 18362ba09d6SThinh Nguyen #define DWC3_GDBGLSPMUX_HOSTSELECT(n) ((n) & 0x3fff) 18462ba09d6SThinh Nguyen #define DWC3_GDBGLSPMUX_DEVSELECT(n) (((n) & 0xf) << 4) 18562ba09d6SThinh Nguyen #define DWC3_GDBGLSPMUX_EPSELECT(n) ((n) & 0xf) 18662ba09d6SThinh Nguyen 187cf6d867dSFelipe Balbi /* Global Debug Queue/FIFO Space Available Register */ 188cf6d867dSFelipe Balbi #define DWC3_GDBGFIFOSPACE_NUM(n) ((n) & 0x1f) 189cf6d867dSFelipe Balbi #define DWC3_GDBGFIFOSPACE_TYPE(n) (((n) << 5) & 0x1e0) 190cf6d867dSFelipe Balbi #define DWC3_GDBGFIFOSPACE_SPACE_AVAILABLE(n) (((n) >> 16) & 0xffff) 191cf6d867dSFelipe Balbi 1922c85a181SThinh Nguyen #define DWC3_TXFIFO 0 1932c85a181SThinh Nguyen #define DWC3_RXFIFO 1 194b16ea8b9SThinh Nguyen #define DWC3_TXREQQ 2 195b16ea8b9SThinh Nguyen #define DWC3_RXREQQ 3 196b16ea8b9SThinh Nguyen #define DWC3_RXINFOQ 4 197b16ea8b9SThinh Nguyen #define DWC3_PSTATQ 5 198b16ea8b9SThinh Nguyen #define DWC3_DESCFETCHQ 6 199b16ea8b9SThinh Nguyen #define DWC3_EVENTQ 7 200b16ea8b9SThinh Nguyen #define DWC3_AUXEVENTQ 8 201cf6d867dSFelipe Balbi 2022a58f9c1SFelipe Balbi /* Global RX Threshold Configuration Register */ 2032a58f9c1SFelipe Balbi #define DWC3_GRXTHRCFG_MAXRXBURSTSIZE(n) (((n) & 0x1f) << 19) 2042a58f9c1SFelipe Balbi #define DWC3_GRXTHRCFG_RXPKTCNT(n) (((n) & 0xf) << 24) 205ff3f0789SRoger Quadros #define DWC3_GRXTHRCFG_PKTCNTSEL BIT(29) 2062a58f9c1SFelipe Balbi 2072fbc5bdcSThinh Nguyen /* Global RX Threshold Configuration Register for DWC_usb31 only */ 2082fbc5bdcSThinh Nguyen #define DWC31_GRXTHRCFG_MAXRXBURSTSIZE(n) (((n) & 0x1f) << 16) 2092fbc5bdcSThinh Nguyen #define DWC31_GRXTHRCFG_RXPKTCNT(n) (((n) & 0x1f) << 21) 2102fbc5bdcSThinh Nguyen #define DWC31_GRXTHRCFG_PKTCNTSEL BIT(26) 2112fbc5bdcSThinh Nguyen #define DWC31_RXTHRNUMPKTSEL_HS_PRD BIT(15) 2122fbc5bdcSThinh Nguyen #define DWC31_RXTHRNUMPKT_HS_PRD(n) (((n) & 0x3) << 13) 2132fbc5bdcSThinh Nguyen #define DWC31_RXTHRNUMPKTSEL_PRD BIT(10) 2142fbc5bdcSThinh Nguyen #define DWC31_RXTHRNUMPKT_PRD(n) (((n) & 0x1f) << 5) 2152fbc5bdcSThinh Nguyen #define DWC31_MAXRXBURSTSIZE_PRD(n) ((n) & 0x1f) 2162fbc5bdcSThinh Nguyen 2176743e817SThinh Nguyen /* Global TX Threshold Configuration Register for DWC_usb31 only */ 2186743e817SThinh Nguyen #define DWC31_GTXTHRCFG_MAXTXBURSTSIZE(n) (((n) & 0x1f) << 16) 2196743e817SThinh Nguyen #define DWC31_GTXTHRCFG_TXPKTCNT(n) (((n) & 0x1f) << 21) 2206743e817SThinh Nguyen #define DWC31_GTXTHRCFG_PKTCNTSEL BIT(26) 2216743e817SThinh Nguyen #define DWC31_TXTHRNUMPKTSEL_HS_PRD BIT(15) 2226743e817SThinh Nguyen #define DWC31_TXTHRNUMPKT_HS_PRD(n) (((n) & 0x3) << 13) 2236743e817SThinh Nguyen #define DWC31_TXTHRNUMPKTSEL_PRD BIT(10) 2246743e817SThinh Nguyen #define DWC31_TXTHRNUMPKT_PRD(n) (((n) & 0x1f) << 5) 2256743e817SThinh Nguyen #define DWC31_MAXTXBURSTSIZE_PRD(n) ((n) & 0x1f) 2266743e817SThinh Nguyen 22772246da4SFelipe Balbi /* Global Configuration Register */ 2281d046793SPaul Zimmerman #define DWC3_GCTL_PWRDNSCALE(n) ((n) << 19) 229ff3f0789SRoger Quadros #define DWC3_GCTL_U2RSTECN BIT(16) 2301d046793SPaul Zimmerman #define DWC3_GCTL_RAMCLKSEL(x) (((x) & DWC3_GCTL_CLK_MASK) << 6) 23172246da4SFelipe Balbi #define DWC3_GCTL_CLK_BUS (0) 23272246da4SFelipe Balbi #define DWC3_GCTL_CLK_PIPE (1) 23372246da4SFelipe Balbi #define DWC3_GCTL_CLK_PIPEHALF (2) 23472246da4SFelipe Balbi #define DWC3_GCTL_CLK_MASK (3) 23572246da4SFelipe Balbi 2360b9fe32dSFelipe Balbi #define DWC3_GCTL_PRTCAP(n) (((n) & (3 << 12)) >> 12) 2371d046793SPaul Zimmerman #define DWC3_GCTL_PRTCAPDIR(n) ((n) << 12) 23872246da4SFelipe Balbi #define DWC3_GCTL_PRTCAP_HOST 1 23972246da4SFelipe Balbi #define DWC3_GCTL_PRTCAP_DEVICE 2 24072246da4SFelipe Balbi #define DWC3_GCTL_PRTCAP_OTG 3 24172246da4SFelipe Balbi 242ff3f0789SRoger Quadros #define DWC3_GCTL_CORESOFTRESET BIT(11) 243ff3f0789SRoger Quadros #define DWC3_GCTL_SOFITPSYNC BIT(10) 2441d046793SPaul Zimmerman #define DWC3_GCTL_SCALEDOWN(n) ((n) << 4) 2453e87c42aSPaul Zimmerman #define DWC3_GCTL_SCALEDOWN_MASK DWC3_GCTL_SCALEDOWN(3) 246ff3f0789SRoger Quadros #define DWC3_GCTL_DISSCRAMBLE BIT(3) 247ff3f0789SRoger Quadros #define DWC3_GCTL_U2EXIT_LFPS BIT(2) 248ff3f0789SRoger Quadros #define DWC3_GCTL_GBLHIBERNATIONEN BIT(1) 249ff3f0789SRoger Quadros #define DWC3_GCTL_DSBLCLKGTNG BIT(0) 25072246da4SFelipe Balbi 251b138e23dSAnurag Kumar Vulisha /* Global User Control Register */ 252b138e23dSAnurag Kumar Vulisha #define DWC3_GUCTL_HSTINAUTORETRY BIT(14) 253b138e23dSAnurag Kumar Vulisha 2540bb39ca1SJohn Youn /* Global User Control 1 Register */ 2557ba6b09fSNeil Armstrong #define DWC3_GUCTL1_PARKMODE_DISABLE_SS BIT(17) 25665db7a0cSWilliam Wu #define DWC3_GUCTL1_TX_IPGAP_LINECHECK_DIS BIT(28) 257ff3f0789SRoger Quadros #define DWC3_GUCTL1_DEV_L1_EXIT_BY_HW BIT(24) 2580bb39ca1SJohn Youn 2594cff75c7SRoger Quadros /* Global Status Register */ 2604cff75c7SRoger Quadros #define DWC3_GSTS_OTG_IP BIT(10) 2614cff75c7SRoger Quadros #define DWC3_GSTS_BC_IP BIT(9) 2624cff75c7SRoger Quadros #define DWC3_GSTS_ADP_IP BIT(8) 2634cff75c7SRoger Quadros #define DWC3_GSTS_HOST_IP BIT(7) 2644cff75c7SRoger Quadros #define DWC3_GSTS_DEVICE_IP BIT(6) 2654cff75c7SRoger Quadros #define DWC3_GSTS_CSR_TIMEOUT BIT(5) 2664cff75c7SRoger Quadros #define DWC3_GSTS_BUS_ERR_ADDR_VLD BIT(4) 26762ba09d6SThinh Nguyen #define DWC3_GSTS_CURMOD(n) ((n) & 0x3) 26862ba09d6SThinh Nguyen #define DWC3_GSTS_CURMOD_DEVICE 0 26962ba09d6SThinh Nguyen #define DWC3_GSTS_CURMOD_HOST 1 2704cff75c7SRoger Quadros 27172246da4SFelipe Balbi /* Global USB2 PHY Configuration Register */ 272ff3f0789SRoger Quadros #define DWC3_GUSB2PHYCFG_PHYSOFTRST BIT(31) 273ff3f0789SRoger Quadros #define DWC3_GUSB2PHYCFG_U2_FREECLK_EXISTS BIT(30) 274ff3f0789SRoger Quadros #define DWC3_GUSB2PHYCFG_SUSPHY BIT(6) 275ff3f0789SRoger Quadros #define DWC3_GUSB2PHYCFG_ULPI_UTMI BIT(4) 276ff3f0789SRoger Quadros #define DWC3_GUSB2PHYCFG_ENBLSLPM BIT(8) 27732f2ed86SWilliam Wu #define DWC3_GUSB2PHYCFG_PHYIF(n) (n << 3) 27832f2ed86SWilliam Wu #define DWC3_GUSB2PHYCFG_PHYIF_MASK DWC3_GUSB2PHYCFG_PHYIF(1) 27932f2ed86SWilliam Wu #define DWC3_GUSB2PHYCFG_USBTRDTIM(n) (n << 10) 28032f2ed86SWilliam Wu #define DWC3_GUSB2PHYCFG_USBTRDTIM_MASK DWC3_GUSB2PHYCFG_USBTRDTIM(0xf) 28132f2ed86SWilliam Wu #define USBTRDTIM_UTMI_8_BIT 9 28232f2ed86SWilliam Wu #define USBTRDTIM_UTMI_16_BIT 5 28332f2ed86SWilliam Wu #define UTMI_PHYIF_16_BIT 1 28432f2ed86SWilliam Wu #define UTMI_PHYIF_8_BIT 0 28572246da4SFelipe Balbi 286b5699eeeSHeikki Krogerus /* Global USB2 PHY Vendor Control Register */ 287ff3f0789SRoger Quadros #define DWC3_GUSB2PHYACC_NEWREGREQ BIT(25) 288ff3f0789SRoger Quadros #define DWC3_GUSB2PHYACC_BUSY BIT(23) 289ff3f0789SRoger Quadros #define DWC3_GUSB2PHYACC_WRITE BIT(22) 290b5699eeeSHeikki Krogerus #define DWC3_GUSB2PHYACC_ADDR(n) (n << 16) 291b5699eeeSHeikki Krogerus #define DWC3_GUSB2PHYACC_EXTEND_ADDR(n) (n << 8) 292b5699eeeSHeikki Krogerus #define DWC3_GUSB2PHYACC_DATA(n) (n & 0xff) 293b5699eeeSHeikki Krogerus 29472246da4SFelipe Balbi /* Global USB3 PIPE Control Register */ 295ff3f0789SRoger Quadros #define DWC3_GUSB3PIPECTL_PHYSOFTRST BIT(31) 296ff3f0789SRoger Quadros #define DWC3_GUSB3PIPECTL_U2SSINP3OK BIT(29) 297ff3f0789SRoger Quadros #define DWC3_GUSB3PIPECTL_DISRXDETINP3 BIT(28) 298ff3f0789SRoger Quadros #define DWC3_GUSB3PIPECTL_UX_EXIT_PX BIT(27) 299ff3f0789SRoger Quadros #define DWC3_GUSB3PIPECTL_REQP1P2P3 BIT(24) 300a2a1d0f5SHuang Rui #define DWC3_GUSB3PIPECTL_DEP1P2P3(n) ((n) << 19) 301a2a1d0f5SHuang Rui #define DWC3_GUSB3PIPECTL_DEP1P2P3_MASK DWC3_GUSB3PIPECTL_DEP1P2P3(7) 302a2a1d0f5SHuang Rui #define DWC3_GUSB3PIPECTL_DEP1P2P3_EN DWC3_GUSB3PIPECTL_DEP1P2P3(1) 303ff3f0789SRoger Quadros #define DWC3_GUSB3PIPECTL_DEPOCHANGE BIT(18) 304ff3f0789SRoger Quadros #define DWC3_GUSB3PIPECTL_SUSPHY BIT(17) 305ff3f0789SRoger Quadros #define DWC3_GUSB3PIPECTL_LFPSFILT BIT(9) 306ff3f0789SRoger Quadros #define DWC3_GUSB3PIPECTL_RX_DETOPOLL BIT(8) 3076b6a0c9aSHuang Rui #define DWC3_GUSB3PIPECTL_TX_DEEPH_MASK DWC3_GUSB3PIPECTL_TX_DEEPH(3) 3086b6a0c9aSHuang Rui #define DWC3_GUSB3PIPECTL_TX_DEEPH(n) ((n) << 1) 30972246da4SFelipe Balbi 310457e84b6SFelipe Balbi /* Global TX Fifo Size Register */ 3110cab8d26SThinh Nguyen #define DWC31_GTXFIFOSIZ_TXFRAMNUM BIT(15) /* DWC_usb31 only */ 312586f4335SThinh Nguyen #define DWC31_GTXFIFOSIZ_TXFDEP(n) ((n) & 0x7fff) /* DWC_usb31 only */ 313586f4335SThinh Nguyen #define DWC3_GTXFIFOSIZ_TXFDEP(n) ((n) & 0xffff) 314457e84b6SFelipe Balbi #define DWC3_GTXFIFOSIZ_TXFSTADDR(n) ((n) & 0xffff0000) 315457e84b6SFelipe Balbi 316d94ea531SThinh Nguyen /* Global RX Fifo Size Register */ 317d94ea531SThinh Nguyen #define DWC31_GRXFIFOSIZ_RXFDEP(n) ((n) & 0x7fff) /* DWC_usb31 only */ 318d94ea531SThinh Nguyen #define DWC3_GRXFIFOSIZ_RXFDEP(n) ((n) & 0xffff) 319d94ea531SThinh Nguyen 32068d6a01bSFelipe Balbi /* Global Event Size Registers */ 321ff3f0789SRoger Quadros #define DWC3_GEVNTSIZ_INTMASK BIT(31) 32268d6a01bSFelipe Balbi #define DWC3_GEVNTSIZ_SIZE(n) ((n) & 0xffff) 32368d6a01bSFelipe Balbi 3244e99472bSFelipe Balbi /* Global HWPARAMS0 Register */ 3259d6173e1SThinh Nguyen #define DWC3_GHWPARAMS0_MODE(n) ((n) & 0x3) 3269d6173e1SThinh Nguyen #define DWC3_GHWPARAMS0_MODE_GADGET 0 3279d6173e1SThinh Nguyen #define DWC3_GHWPARAMS0_MODE_HOST 1 3289d6173e1SThinh Nguyen #define DWC3_GHWPARAMS0_MODE_DRD 2 3294e99472bSFelipe Balbi #define DWC3_GHWPARAMS0_MBUS_TYPE(n) (((n) >> 3) & 0x7) 3304e99472bSFelipe Balbi #define DWC3_GHWPARAMS0_SBUS_TYPE(n) (((n) >> 6) & 0x3) 3314e99472bSFelipe Balbi #define DWC3_GHWPARAMS0_MDWIDTH(n) (((n) >> 8) & 0xff) 3324e99472bSFelipe Balbi #define DWC3_GHWPARAMS0_SDWIDTH(n) (((n) >> 16) & 0xff) 3334e99472bSFelipe Balbi #define DWC3_GHWPARAMS0_AWIDTH(n) (((n) >> 24) & 0xff) 3344e99472bSFelipe Balbi 335aabb7075SFelipe Balbi /* Global HWPARAMS1 Register */ 3361d046793SPaul Zimmerman #define DWC3_GHWPARAMS1_EN_PWROPT(n) (((n) & (3 << 24)) >> 24) 337aabb7075SFelipe Balbi #define DWC3_GHWPARAMS1_EN_PWROPT_NO 0 338aabb7075SFelipe Balbi #define DWC3_GHWPARAMS1_EN_PWROPT_CLK 1 3392c61a8efSPaul Zimmerman #define DWC3_GHWPARAMS1_EN_PWROPT_HIB 2 3402c61a8efSPaul Zimmerman #define DWC3_GHWPARAMS1_PWROPT(n) ((n) << 24) 3412c61a8efSPaul Zimmerman #define DWC3_GHWPARAMS1_PWROPT_MASK DWC3_GHWPARAMS1_PWROPT(3) 34262ba09d6SThinh Nguyen #define DWC3_GHWPARAMS1_ENDBC BIT(31) 3432c61a8efSPaul Zimmerman 3440e1e5c47SPaul Zimmerman /* Global HWPARAMS3 Register */ 3450e1e5c47SPaul Zimmerman #define DWC3_GHWPARAMS3_SSPHY_IFC(n) ((n) & 3) 3460e1e5c47SPaul Zimmerman #define DWC3_GHWPARAMS3_SSPHY_IFC_DIS 0 3471f38f88aSJohn Youn #define DWC3_GHWPARAMS3_SSPHY_IFC_GEN1 1 3481f38f88aSJohn Youn #define DWC3_GHWPARAMS3_SSPHY_IFC_GEN2 2 /* DWC_usb31 only */ 3490e1e5c47SPaul Zimmerman #define DWC3_GHWPARAMS3_HSPHY_IFC(n) (((n) & (3 << 2)) >> 2) 3500e1e5c47SPaul Zimmerman #define DWC3_GHWPARAMS3_HSPHY_IFC_DIS 0 3510e1e5c47SPaul Zimmerman #define DWC3_GHWPARAMS3_HSPHY_IFC_UTMI 1 3520e1e5c47SPaul Zimmerman #define DWC3_GHWPARAMS3_HSPHY_IFC_ULPI 2 3530e1e5c47SPaul Zimmerman #define DWC3_GHWPARAMS3_HSPHY_IFC_UTMI_ULPI 3 3540e1e5c47SPaul Zimmerman #define DWC3_GHWPARAMS3_FSPHY_IFC(n) (((n) & (3 << 4)) >> 4) 3550e1e5c47SPaul Zimmerman #define DWC3_GHWPARAMS3_FSPHY_IFC_DIS 0 3560e1e5c47SPaul Zimmerman #define DWC3_GHWPARAMS3_FSPHY_IFC_ENA 1 3570e1e5c47SPaul Zimmerman 3582c61a8efSPaul Zimmerman /* Global HWPARAMS4 Register */ 3592c61a8efSPaul Zimmerman #define DWC3_GHWPARAMS4_HIBER_SCRATCHBUFS(n) (((n) & (0x0f << 13)) >> 13) 3602c61a8efSPaul Zimmerman #define DWC3_MAX_HIBER_SCRATCHBUFS 15 361aabb7075SFelipe Balbi 362946bd579SHuang Rui /* Global HWPARAMS6 Register */ 3634cff75c7SRoger Quadros #define DWC3_GHWPARAMS6_BCSUPPORT BIT(14) 3644cff75c7SRoger Quadros #define DWC3_GHWPARAMS6_OTG3SUPPORT BIT(13) 3654cff75c7SRoger Quadros #define DWC3_GHWPARAMS6_ADPSUPPORT BIT(12) 3664cff75c7SRoger Quadros #define DWC3_GHWPARAMS6_HNPSUPPORT BIT(11) 3674cff75c7SRoger Quadros #define DWC3_GHWPARAMS6_SRPSUPPORT BIT(10) 368ff3f0789SRoger Quadros #define DWC3_GHWPARAMS6_EN_FPGA BIT(7) 369946bd579SHuang Rui 3704244ba02SThinh Nguyen /* DWC_usb32 only */ 3714244ba02SThinh Nguyen #define DWC3_GHWPARAMS6_MDWIDTH(n) ((n) & (0x3 << 8)) 3724244ba02SThinh Nguyen 3734e99472bSFelipe Balbi /* Global HWPARAMS7 Register */ 3744e99472bSFelipe Balbi #define DWC3_GHWPARAMS7_RAM1_DEPTH(n) ((n) & 0xffff) 3754e99472bSFelipe Balbi #define DWC3_GHWPARAMS7_RAM2_DEPTH(n) (((n) >> 16) & 0xffff) 3764e99472bSFelipe Balbi 377db2be4e9SNikhil Badola /* Global Frame Length Adjustment Register */ 378ff3f0789SRoger Quadros #define DWC3_GFLADJ_30MHZ_SDBND_SEL BIT(7) 379db2be4e9SNikhil Badola #define DWC3_GFLADJ_30MHZ_MASK 0x3f 380db2be4e9SNikhil Badola 38106281d46SJohn Youn /* Global User Control Register 2 */ 382ff3f0789SRoger Quadros #define DWC3_GUCTL2_RST_ACTBITLATER BIT(14) 38306281d46SJohn Youn 384f580170fSYu Chen /* Global User Control Register 3 */ 385f580170fSYu Chen #define DWC3_GUCTL3_SPLITDISABLE BIT(14) 386f580170fSYu Chen 38772246da4SFelipe Balbi /* Device Configuration Register */ 38872246da4SFelipe Balbi #define DWC3_DCFG_DEVADDR(addr) ((addr) << 3) 38972246da4SFelipe Balbi #define DWC3_DCFG_DEVADDR_MASK DWC3_DCFG_DEVADDR(0x7f) 39072246da4SFelipe Balbi 39172246da4SFelipe Balbi #define DWC3_DCFG_SPEED_MASK (7 << 0) 3921f38f88aSJohn Youn #define DWC3_DCFG_SUPERSPEED_PLUS (5 << 0) /* DWC_usb31 only */ 39372246da4SFelipe Balbi #define DWC3_DCFG_SUPERSPEED (4 << 0) 39472246da4SFelipe Balbi #define DWC3_DCFG_HIGHSPEED (0 << 0) 395ff3f0789SRoger Quadros #define DWC3_DCFG_FULLSPEED BIT(0) 39672246da4SFelipe Balbi #define DWC3_DCFG_LOWSPEED (2 << 0) 39772246da4SFelipe Balbi 398676e3497SFelipe Balbi #define DWC3_DCFG_NUMP_SHIFT 17 39997398612SDan Carpenter #define DWC3_DCFG_NUMP(n) (((n) >> DWC3_DCFG_NUMP_SHIFT) & 0x1f) 400676e3497SFelipe Balbi #define DWC3_DCFG_NUMP_MASK (0x1f << DWC3_DCFG_NUMP_SHIFT) 401ff3f0789SRoger Quadros #define DWC3_DCFG_LPM_CAP BIT(22) 4022c61a8efSPaul Zimmerman 40372246da4SFelipe Balbi /* Device Control Register */ 404ff3f0789SRoger Quadros #define DWC3_DCTL_RUN_STOP BIT(31) 405ff3f0789SRoger Quadros #define DWC3_DCTL_CSFTRST BIT(30) 406ff3f0789SRoger Quadros #define DWC3_DCTL_LSFTRST BIT(29) 40772246da4SFelipe Balbi 40872246da4SFelipe Balbi #define DWC3_DCTL_HIRD_THRES_MASK (0x1f << 24) 4097e39b817SPratyush Anand #define DWC3_DCTL_HIRD_THRES(n) ((n) << 24) 41072246da4SFelipe Balbi 411ff3f0789SRoger Quadros #define DWC3_DCTL_APPL1RES BIT(23) 41272246da4SFelipe Balbi 4132c61a8efSPaul Zimmerman /* These apply for core versions 1.87a and earlier */ 4148db7ed15SFelipe Balbi #define DWC3_DCTL_TRGTULST_MASK (0x0f << 17) 4158db7ed15SFelipe Balbi #define DWC3_DCTL_TRGTULST(n) ((n) << 17) 4168db7ed15SFelipe Balbi #define DWC3_DCTL_TRGTULST_U2 (DWC3_DCTL_TRGTULST(2)) 4178db7ed15SFelipe Balbi #define DWC3_DCTL_TRGTULST_U3 (DWC3_DCTL_TRGTULST(3)) 4188db7ed15SFelipe Balbi #define DWC3_DCTL_TRGTULST_SS_DIS (DWC3_DCTL_TRGTULST(4)) 4198db7ed15SFelipe Balbi #define DWC3_DCTL_TRGTULST_RX_DET (DWC3_DCTL_TRGTULST(5)) 4208db7ed15SFelipe Balbi #define DWC3_DCTL_TRGTULST_SS_INACT (DWC3_DCTL_TRGTULST(6)) 4218db7ed15SFelipe Balbi 4222c61a8efSPaul Zimmerman /* These apply for core versions 1.94a and later */ 4232e487d28SThinh Nguyen #define DWC3_DCTL_NYET_THRES(n) (((n) & 0xf) << 20) 42480caf7d2SHuang Rui 425ff3f0789SRoger Quadros #define DWC3_DCTL_KEEP_CONNECT BIT(19) 426ff3f0789SRoger Quadros #define DWC3_DCTL_L1_HIBER_EN BIT(18) 427ff3f0789SRoger Quadros #define DWC3_DCTL_CRS BIT(17) 428ff3f0789SRoger Quadros #define DWC3_DCTL_CSS BIT(16) 4292c61a8efSPaul Zimmerman 430ff3f0789SRoger Quadros #define DWC3_DCTL_INITU2ENA BIT(12) 431ff3f0789SRoger Quadros #define DWC3_DCTL_ACCEPTU2ENA BIT(11) 432ff3f0789SRoger Quadros #define DWC3_DCTL_INITU1ENA BIT(10) 433ff3f0789SRoger Quadros #define DWC3_DCTL_ACCEPTU1ENA BIT(9) 43472246da4SFelipe Balbi #define DWC3_DCTL_TSTCTRL_MASK (0xf << 1) 43572246da4SFelipe Balbi 43672246da4SFelipe Balbi #define DWC3_DCTL_ULSTCHNGREQ_MASK (0x0f << 5) 43772246da4SFelipe Balbi #define DWC3_DCTL_ULSTCHNGREQ(n) (((n) << 5) & DWC3_DCTL_ULSTCHNGREQ_MASK) 43872246da4SFelipe Balbi 43972246da4SFelipe Balbi #define DWC3_DCTL_ULSTCHNG_NO_ACTION (DWC3_DCTL_ULSTCHNGREQ(0)) 44072246da4SFelipe Balbi #define DWC3_DCTL_ULSTCHNG_SS_DISABLED (DWC3_DCTL_ULSTCHNGREQ(4)) 44172246da4SFelipe Balbi #define DWC3_DCTL_ULSTCHNG_RX_DETECT (DWC3_DCTL_ULSTCHNGREQ(5)) 44272246da4SFelipe Balbi #define DWC3_DCTL_ULSTCHNG_SS_INACTIVE (DWC3_DCTL_ULSTCHNGREQ(6)) 44372246da4SFelipe Balbi #define DWC3_DCTL_ULSTCHNG_RECOVERY (DWC3_DCTL_ULSTCHNGREQ(8)) 44472246da4SFelipe Balbi #define DWC3_DCTL_ULSTCHNG_COMPLIANCE (DWC3_DCTL_ULSTCHNGREQ(10)) 44572246da4SFelipe Balbi #define DWC3_DCTL_ULSTCHNG_LOOPBACK (DWC3_DCTL_ULSTCHNGREQ(11)) 44672246da4SFelipe Balbi 44772246da4SFelipe Balbi /* Device Event Enable Register */ 448ff3f0789SRoger Quadros #define DWC3_DEVTEN_VNDRDEVTSTRCVEDEN BIT(12) 449ff3f0789SRoger Quadros #define DWC3_DEVTEN_EVNTOVERFLOWEN BIT(11) 450ff3f0789SRoger Quadros #define DWC3_DEVTEN_CMDCMPLTEN BIT(10) 451ff3f0789SRoger Quadros #define DWC3_DEVTEN_ERRTICERREN BIT(9) 452ff3f0789SRoger Quadros #define DWC3_DEVTEN_SOFEN BIT(7) 453ff3f0789SRoger Quadros #define DWC3_DEVTEN_EOPFEN BIT(6) 454ff3f0789SRoger Quadros #define DWC3_DEVTEN_HIBERNATIONREQEVTEN BIT(5) 455ff3f0789SRoger Quadros #define DWC3_DEVTEN_WKUPEVTEN BIT(4) 456ff3f0789SRoger Quadros #define DWC3_DEVTEN_ULSTCNGEN BIT(3) 457ff3f0789SRoger Quadros #define DWC3_DEVTEN_CONNECTDONEEN BIT(2) 458ff3f0789SRoger Quadros #define DWC3_DEVTEN_USBRSTEN BIT(1) 459ff3f0789SRoger Quadros #define DWC3_DEVTEN_DISCONNEVTEN BIT(0) 46072246da4SFelipe Balbi 46172246da4SFelipe Balbi /* Device Status Register */ 462ff3f0789SRoger Quadros #define DWC3_DSTS_DCNRD BIT(29) 4632c61a8efSPaul Zimmerman 4642c61a8efSPaul Zimmerman /* This applies for core versions 1.87a and earlier */ 465ff3f0789SRoger Quadros #define DWC3_DSTS_PWRUPREQ BIT(24) 4662c61a8efSPaul Zimmerman 4672c61a8efSPaul Zimmerman /* These apply for core versions 1.94a and later */ 468ff3f0789SRoger Quadros #define DWC3_DSTS_RSS BIT(25) 469ff3f0789SRoger Quadros #define DWC3_DSTS_SSS BIT(24) 4702c61a8efSPaul Zimmerman 471ff3f0789SRoger Quadros #define DWC3_DSTS_COREIDLE BIT(23) 472ff3f0789SRoger Quadros #define DWC3_DSTS_DEVCTRLHLT BIT(22) 47372246da4SFelipe Balbi 47472246da4SFelipe Balbi #define DWC3_DSTS_USBLNKST_MASK (0x0f << 18) 47572246da4SFelipe Balbi #define DWC3_DSTS_USBLNKST(n) (((n) & DWC3_DSTS_USBLNKST_MASK) >> 18) 47672246da4SFelipe Balbi 477ff3f0789SRoger Quadros #define DWC3_DSTS_RXFIFOEMPTY BIT(17) 47872246da4SFelipe Balbi 479d05b8182SPratyush Anand #define DWC3_DSTS_SOFFN_MASK (0x3fff << 3) 48072246da4SFelipe Balbi #define DWC3_DSTS_SOFFN(n) (((n) & DWC3_DSTS_SOFFN_MASK) >> 3) 48172246da4SFelipe Balbi 48272246da4SFelipe Balbi #define DWC3_DSTS_CONNECTSPD (7 << 0) 48372246da4SFelipe Balbi 4841f38f88aSJohn Youn #define DWC3_DSTS_SUPERSPEED_PLUS (5 << 0) /* DWC_usb31 only */ 48572246da4SFelipe Balbi #define DWC3_DSTS_SUPERSPEED (4 << 0) 48672246da4SFelipe Balbi #define DWC3_DSTS_HIGHSPEED (0 << 0) 487ff3f0789SRoger Quadros #define DWC3_DSTS_FULLSPEED BIT(0) 48872246da4SFelipe Balbi #define DWC3_DSTS_LOWSPEED (2 << 0) 48972246da4SFelipe Balbi 49072246da4SFelipe Balbi /* Device Generic Command Register */ 49172246da4SFelipe Balbi #define DWC3_DGCMD_SET_LMP 0x01 49272246da4SFelipe Balbi #define DWC3_DGCMD_SET_PERIODIC_PAR 0x02 49372246da4SFelipe Balbi #define DWC3_DGCMD_XMIT_FUNCTION 0x03 4942c61a8efSPaul Zimmerman 4952c61a8efSPaul Zimmerman /* These apply for core versions 1.94a and later */ 4962c61a8efSPaul Zimmerman #define DWC3_DGCMD_SET_SCRATCHPAD_ADDR_LO 0x04 4972c61a8efSPaul Zimmerman #define DWC3_DGCMD_SET_SCRATCHPAD_ADDR_HI 0x05 4982c61a8efSPaul Zimmerman 49972246da4SFelipe Balbi #define DWC3_DGCMD_SELECTED_FIFO_FLUSH 0x09 50072246da4SFelipe Balbi #define DWC3_DGCMD_ALL_FIFO_FLUSH 0x0a 50172246da4SFelipe Balbi #define DWC3_DGCMD_SET_ENDPOINT_NRDY 0x0c 502140ca4cfSThinh Nguyen #define DWC3_DGCMD_SET_ENDPOINT_PRIME 0x0d 50372246da4SFelipe Balbi #define DWC3_DGCMD_RUN_SOC_BUS_LOOPBACK 0x10 50472246da4SFelipe Balbi 505459e210cSSubbaraya Sundeep Bhatta #define DWC3_DGCMD_STATUS(n) (((n) >> 12) & 0x0F) 506ff3f0789SRoger Quadros #define DWC3_DGCMD_CMDACT BIT(10) 507ff3f0789SRoger Quadros #define DWC3_DGCMD_CMDIOC BIT(8) 5082c61a8efSPaul Zimmerman 5092c61a8efSPaul Zimmerman /* Device Generic Command Parameter Register */ 510ff3f0789SRoger Quadros #define DWC3_DGCMDPAR_FORCE_LINKPM_ACCEPT BIT(0) 5112c61a8efSPaul Zimmerman #define DWC3_DGCMDPAR_FIFO_NUM(n) ((n) << 0) 5122c61a8efSPaul Zimmerman #define DWC3_DGCMDPAR_RX_FIFO (0 << 5) 513ff3f0789SRoger Quadros #define DWC3_DGCMDPAR_TX_FIFO BIT(5) 5142c61a8efSPaul Zimmerman #define DWC3_DGCMDPAR_LOOPBACK_DIS (0 << 0) 515ff3f0789SRoger Quadros #define DWC3_DGCMDPAR_LOOPBACK_ENA BIT(0) 516b09bb642SFelipe Balbi 51772246da4SFelipe Balbi /* Device Endpoint Command Register */ 51872246da4SFelipe Balbi #define DWC3_DEPCMD_PARAM_SHIFT 16 5191d046793SPaul Zimmerman #define DWC3_DEPCMD_PARAM(x) ((x) << DWC3_DEPCMD_PARAM_SHIFT) 5201d046793SPaul Zimmerman #define DWC3_DEPCMD_GET_RSC_IDX(x) (((x) >> DWC3_DEPCMD_PARAM_SHIFT) & 0x7f) 521459e210cSSubbaraya Sundeep Bhatta #define DWC3_DEPCMD_STATUS(x) (((x) >> 12) & 0x0F) 522ff3f0789SRoger Quadros #define DWC3_DEPCMD_HIPRI_FORCERM BIT(11) 523ff3f0789SRoger Quadros #define DWC3_DEPCMD_CLEARPENDIN BIT(11) 524ff3f0789SRoger Quadros #define DWC3_DEPCMD_CMDACT BIT(10) 525ff3f0789SRoger Quadros #define DWC3_DEPCMD_CMDIOC BIT(8) 52672246da4SFelipe Balbi 52772246da4SFelipe Balbi #define DWC3_DEPCMD_DEPSTARTCFG (0x09 << 0) 52872246da4SFelipe Balbi #define DWC3_DEPCMD_ENDTRANSFER (0x08 << 0) 52972246da4SFelipe Balbi #define DWC3_DEPCMD_UPDATETRANSFER (0x07 << 0) 53072246da4SFelipe Balbi #define DWC3_DEPCMD_STARTTRANSFER (0x06 << 0) 53172246da4SFelipe Balbi #define DWC3_DEPCMD_CLEARSTALL (0x05 << 0) 53272246da4SFelipe Balbi #define DWC3_DEPCMD_SETSTALL (0x04 << 0) 5332c61a8efSPaul Zimmerman /* This applies for core versions 1.90a and earlier */ 53472246da4SFelipe Balbi #define DWC3_DEPCMD_GETSEQNUMBER (0x03 << 0) 5352c61a8efSPaul Zimmerman /* This applies for core versions 1.94a and later */ 5362c61a8efSPaul Zimmerman #define DWC3_DEPCMD_GETEPSTATE (0x03 << 0) 53772246da4SFelipe Balbi #define DWC3_DEPCMD_SETTRANSFRESOURCE (0x02 << 0) 53872246da4SFelipe Balbi #define DWC3_DEPCMD_SETEPCONFIG (0x01 << 0) 53972246da4SFelipe Balbi 5405999914fSFelipe Balbi #define DWC3_DEPCMD_CMD(x) ((x) & 0xf) 5415999914fSFelipe Balbi 54272246da4SFelipe Balbi /* The EP number goes 0..31 so ep0 is always out and ep1 is always in */ 543ff3f0789SRoger Quadros #define DWC3_DALEPENA_EP(n) BIT(n) 54472246da4SFelipe Balbi 54572246da4SFelipe Balbi #define DWC3_DEPCMD_TYPE_CONTROL 0 54672246da4SFelipe Balbi #define DWC3_DEPCMD_TYPE_ISOC 1 54772246da4SFelipe Balbi #define DWC3_DEPCMD_TYPE_BULK 2 54872246da4SFelipe Balbi #define DWC3_DEPCMD_TYPE_INTR 3 54972246da4SFelipe Balbi 550cf40b86bSJohn Youn #define DWC3_DEV_IMOD_COUNT_SHIFT 16 551cf40b86bSJohn Youn #define DWC3_DEV_IMOD_COUNT_MASK (0xffff << 16) 552cf40b86bSJohn Youn #define DWC3_DEV_IMOD_INTERVAL_SHIFT 0 553cf40b86bSJohn Youn #define DWC3_DEV_IMOD_INTERVAL_MASK (0xffff << 0) 554cf40b86bSJohn Youn 5554cff75c7SRoger Quadros /* OTG Configuration Register */ 5564cff75c7SRoger Quadros #define DWC3_OCFG_DISPWRCUTTOFF BIT(5) 5574cff75c7SRoger Quadros #define DWC3_OCFG_HIBDISMASK BIT(4) 5584cff75c7SRoger Quadros #define DWC3_OCFG_SFTRSTMASK BIT(3) 5594cff75c7SRoger Quadros #define DWC3_OCFG_OTGVERSION BIT(2) 5604cff75c7SRoger Quadros #define DWC3_OCFG_HNPCAP BIT(1) 5614cff75c7SRoger Quadros #define DWC3_OCFG_SRPCAP BIT(0) 5624cff75c7SRoger Quadros 5634cff75c7SRoger Quadros /* OTG CTL Register */ 5644cff75c7SRoger Quadros #define DWC3_OCTL_OTG3GOERR BIT(7) 5654cff75c7SRoger Quadros #define DWC3_OCTL_PERIMODE BIT(6) 5664cff75c7SRoger Quadros #define DWC3_OCTL_PRTPWRCTL BIT(5) 5674cff75c7SRoger Quadros #define DWC3_OCTL_HNPREQ BIT(4) 5684cff75c7SRoger Quadros #define DWC3_OCTL_SESREQ BIT(3) 5694cff75c7SRoger Quadros #define DWC3_OCTL_TERMSELIDPULSE BIT(2) 5704cff75c7SRoger Quadros #define DWC3_OCTL_DEVSETHNPEN BIT(1) 5714cff75c7SRoger Quadros #define DWC3_OCTL_HSTSETHNPEN BIT(0) 5724cff75c7SRoger Quadros 5734cff75c7SRoger Quadros /* OTG Event Register */ 5744cff75c7SRoger Quadros #define DWC3_OEVT_DEVICEMODE BIT(31) 5754cff75c7SRoger Quadros #define DWC3_OEVT_XHCIRUNSTPSET BIT(27) 5764cff75c7SRoger Quadros #define DWC3_OEVT_DEVRUNSTPSET BIT(26) 5774cff75c7SRoger Quadros #define DWC3_OEVT_HIBENTRY BIT(25) 5784cff75c7SRoger Quadros #define DWC3_OEVT_CONIDSTSCHNG BIT(24) 5794cff75c7SRoger Quadros #define DWC3_OEVT_HRRCONFNOTIF BIT(23) 5804cff75c7SRoger Quadros #define DWC3_OEVT_HRRINITNOTIF BIT(22) 5814cff75c7SRoger Quadros #define DWC3_OEVT_ADEVIDLE BIT(21) 5824cff75c7SRoger Quadros #define DWC3_OEVT_ADEVBHOSTEND BIT(20) 5834cff75c7SRoger Quadros #define DWC3_OEVT_ADEVHOST BIT(19) 5844cff75c7SRoger Quadros #define DWC3_OEVT_ADEVHNPCHNG BIT(18) 5854cff75c7SRoger Quadros #define DWC3_OEVT_ADEVSRPDET BIT(17) 5864cff75c7SRoger Quadros #define DWC3_OEVT_ADEVSESSENDDET BIT(16) 5874cff75c7SRoger Quadros #define DWC3_OEVT_BDEVBHOSTEND BIT(11) 5884cff75c7SRoger Quadros #define DWC3_OEVT_BDEVHNPCHNG BIT(10) 5894cff75c7SRoger Quadros #define DWC3_OEVT_BDEVSESSVLDDET BIT(9) 5904cff75c7SRoger Quadros #define DWC3_OEVT_BDEVVBUSCHNG BIT(8) 5914cff75c7SRoger Quadros #define DWC3_OEVT_BSESSVLD BIT(3) 5924cff75c7SRoger Quadros #define DWC3_OEVT_HSTNEGSTS BIT(2) 5934cff75c7SRoger Quadros #define DWC3_OEVT_SESREQSTS BIT(1) 5944cff75c7SRoger Quadros #define DWC3_OEVT_ERROR BIT(0) 5954cff75c7SRoger Quadros 5964cff75c7SRoger Quadros /* OTG Event Enable Register */ 5974cff75c7SRoger Quadros #define DWC3_OEVTEN_XHCIRUNSTPSETEN BIT(27) 5984cff75c7SRoger Quadros #define DWC3_OEVTEN_DEVRUNSTPSETEN BIT(26) 5994cff75c7SRoger Quadros #define DWC3_OEVTEN_HIBENTRYEN BIT(25) 6004cff75c7SRoger Quadros #define DWC3_OEVTEN_CONIDSTSCHNGEN BIT(24) 6014cff75c7SRoger Quadros #define DWC3_OEVTEN_HRRCONFNOTIFEN BIT(23) 6024cff75c7SRoger Quadros #define DWC3_OEVTEN_HRRINITNOTIFEN BIT(22) 6034cff75c7SRoger Quadros #define DWC3_OEVTEN_ADEVIDLEEN BIT(21) 6044cff75c7SRoger Quadros #define DWC3_OEVTEN_ADEVBHOSTENDEN BIT(20) 6054cff75c7SRoger Quadros #define DWC3_OEVTEN_ADEVHOSTEN BIT(19) 6064cff75c7SRoger Quadros #define DWC3_OEVTEN_ADEVHNPCHNGEN BIT(18) 6074cff75c7SRoger Quadros #define DWC3_OEVTEN_ADEVSRPDETEN BIT(17) 6084cff75c7SRoger Quadros #define DWC3_OEVTEN_ADEVSESSENDDETEN BIT(16) 6094cff75c7SRoger Quadros #define DWC3_OEVTEN_BDEVBHOSTENDEN BIT(11) 6104cff75c7SRoger Quadros #define DWC3_OEVTEN_BDEVHNPCHNGEN BIT(10) 6114cff75c7SRoger Quadros #define DWC3_OEVTEN_BDEVSESSVLDDETEN BIT(9) 6124cff75c7SRoger Quadros #define DWC3_OEVTEN_BDEVVBUSCHNGEN BIT(8) 6134cff75c7SRoger Quadros 6144cff75c7SRoger Quadros /* OTG Status Register */ 6154cff75c7SRoger Quadros #define DWC3_OSTS_DEVRUNSTP BIT(13) 6164cff75c7SRoger Quadros #define DWC3_OSTS_XHCIRUNSTP BIT(12) 6174cff75c7SRoger Quadros #define DWC3_OSTS_PERIPHERALSTATE BIT(4) 6184cff75c7SRoger Quadros #define DWC3_OSTS_XHCIPRTPOWER BIT(3) 6194cff75c7SRoger Quadros #define DWC3_OSTS_BSESVLD BIT(2) 6204cff75c7SRoger Quadros #define DWC3_OSTS_VBUSVLD BIT(1) 6214cff75c7SRoger Quadros #define DWC3_OSTS_CONIDSTS BIT(0) 6224cff75c7SRoger Quadros 62372246da4SFelipe Balbi /* Structures */ 62472246da4SFelipe Balbi 625f6bafc6aSFelipe Balbi struct dwc3_trb; 62672246da4SFelipe Balbi 62772246da4SFelipe Balbi /** 62872246da4SFelipe Balbi * struct dwc3_event_buffer - Software event buffer representation 62972246da4SFelipe Balbi * @buf: _THE_ buffer 630d9fa4c63SJohn Youn * @cache: The buffer cache used in the threaded interrupt 63172246da4SFelipe Balbi * @length: size of this buffer 632abed4118SFelipe Balbi * @lpos: event offset 63360d04bbeSFelipe Balbi * @count: cache of last read event count register 634abed4118SFelipe Balbi * @flags: flags related to this event buffer 63572246da4SFelipe Balbi * @dma: dma_addr_t 63672246da4SFelipe Balbi * @dwc: pointer to DWC controller 63772246da4SFelipe Balbi */ 63872246da4SFelipe Balbi struct dwc3_event_buffer { 63972246da4SFelipe Balbi void *buf; 640d9fa4c63SJohn Youn void *cache; 64187b923a2SFelipe Balbi unsigned int length; 64272246da4SFelipe Balbi unsigned int lpos; 64360d04bbeSFelipe Balbi unsigned int count; 644abed4118SFelipe Balbi unsigned int flags; 645abed4118SFelipe Balbi 646abed4118SFelipe Balbi #define DWC3_EVENT_PENDING BIT(0) 64772246da4SFelipe Balbi 64872246da4SFelipe Balbi dma_addr_t dma; 64972246da4SFelipe Balbi 65072246da4SFelipe Balbi struct dwc3 *dwc; 65172246da4SFelipe Balbi }; 65272246da4SFelipe Balbi 653ff3f0789SRoger Quadros #define DWC3_EP_FLAG_STALLED BIT(0) 654ff3f0789SRoger Quadros #define DWC3_EP_FLAG_WEDGED BIT(1) 65572246da4SFelipe Balbi 65672246da4SFelipe Balbi #define DWC3_EP_DIRECTION_TX true 65772246da4SFelipe Balbi #define DWC3_EP_DIRECTION_RX false 65872246da4SFelipe Balbi 6598495036eSFelipe Balbi #define DWC3_TRB_NUM 256 66072246da4SFelipe Balbi 66172246da4SFelipe Balbi /** 66272246da4SFelipe Balbi * struct dwc3_ep - device side endpoint representation 66372246da4SFelipe Balbi * @endpoint: usb endpoint 664d5443bbfSFelipe Balbi * @cancelled_list: list of cancelled requests for this endpoint 665aa3342c8SFelipe Balbi * @pending_list: list of pending requests for this endpoint 666aa3342c8SFelipe Balbi * @started_list: list of started requests on this endpoint 6672eb88016SFelipe Balbi * @regs: pointer to first endpoint register 66872246da4SFelipe Balbi * @trb_pool: array of transaction buffers 66972246da4SFelipe Balbi * @trb_pool_dma: dma address of @trb_pool 67053fd8818SFelipe Balbi * @trb_enqueue: enqueue 'pointer' into TRB array 67153fd8818SFelipe Balbi * @trb_dequeue: dequeue 'pointer' into TRB array 67272246da4SFelipe Balbi * @dwc: pointer to DWC controller 6734cfcf876SPaul Zimmerman * @saved_state: ep state saved during hibernation 67472246da4SFelipe Balbi * @flags: endpoint flags (wedged, stalled, ...) 67572246da4SFelipe Balbi * @number: endpoint number (1 - 15) 67672246da4SFelipe Balbi * @type: set to bmAttributes & USB_ENDPOINT_XFERTYPE_MASK 677b4996a86SFelipe Balbi * @resource_index: Resource transfer index 678502a37b9SFelipe Balbi * @frame_number: set to the frame number we want this transfer to start (ISOC) 679c75f52fbSHuang Rui * @interval: the interval on which the ISOC transfer is started 68072246da4SFelipe Balbi * @name: a human readable name e.g. ep1out-bulk 68172246da4SFelipe Balbi * @direction: true for TX, false for RX 682879631aaSFelipe Balbi * @stream_capable: true when streams are enabled 683d92021f6SThinh Nguyen * @combo_num: the test combination BIT[15:14] of the frame number to test 684d92021f6SThinh Nguyen * isochronous START TRANSFER command failure workaround 685d92021f6SThinh Nguyen * @start_cmd_status: the status of testing START TRANSFER command with 686d92021f6SThinh Nguyen * combo_num = 'b00 68772246da4SFelipe Balbi */ 68872246da4SFelipe Balbi struct dwc3_ep { 68972246da4SFelipe Balbi struct usb_ep endpoint; 690d5443bbfSFelipe Balbi struct list_head cancelled_list; 691aa3342c8SFelipe Balbi struct list_head pending_list; 692aa3342c8SFelipe Balbi struct list_head started_list; 69372246da4SFelipe Balbi 6942eb88016SFelipe Balbi void __iomem *regs; 6952eb88016SFelipe Balbi 696f6bafc6aSFelipe Balbi struct dwc3_trb *trb_pool; 69772246da4SFelipe Balbi dma_addr_t trb_pool_dma; 69872246da4SFelipe Balbi struct dwc3 *dwc; 69972246da4SFelipe Balbi 7004cfcf876SPaul Zimmerman u32 saved_state; 70187b923a2SFelipe Balbi unsigned int flags; 702ff3f0789SRoger Quadros #define DWC3_EP_ENABLED BIT(0) 703ff3f0789SRoger Quadros #define DWC3_EP_STALL BIT(1) 704ff3f0789SRoger Quadros #define DWC3_EP_WEDGE BIT(2) 7055f2e7975SFelipe Balbi #define DWC3_EP_TRANSFER_STARTED BIT(3) 706c58d8bfcSThinh Nguyen #define DWC3_EP_END_TRANSFER_PENDING BIT(4) 707ff3f0789SRoger Quadros #define DWC3_EP_PENDING_REQUEST BIT(5) 708da10bcddSThinh Nguyen #define DWC3_EP_DELAY_START BIT(6) 709e0d19563SThinh Nguyen #define DWC3_EP_WAIT_TRANSFER_COMPLETE BIT(7) 710140ca4cfSThinh Nguyen #define DWC3_EP_IGNORE_NEXT_NOSTREAM BIT(8) 711140ca4cfSThinh Nguyen #define DWC3_EP_FORCE_RESTART_STREAM BIT(9) 712140ca4cfSThinh Nguyen #define DWC3_EP_FIRST_STREAM_PRIMED BIT(10) 713d97c78a1SThinh Nguyen #define DWC3_EP_PENDING_CLEAR_STALL BIT(11) 71472246da4SFelipe Balbi 715984f66a6SFelipe Balbi /* This last one is specific to EP0 */ 716ff3f0789SRoger Quadros #define DWC3_EP0_DIR_IN BIT(31) 717984f66a6SFelipe Balbi 718c28f8259SFelipe Balbi /* 719c28f8259SFelipe Balbi * IMPORTANT: we *know* we have 256 TRBs in our @trb_pool, so we will 720c28f8259SFelipe Balbi * use a u8 type here. If anybody decides to increase number of TRBs to 721c28f8259SFelipe Balbi * anything larger than 256 - I can't see why people would want to do 722c28f8259SFelipe Balbi * this though - then this type needs to be changed. 723c28f8259SFelipe Balbi * 724c28f8259SFelipe Balbi * By using u8 types we ensure that our % operator when incrementing 725c28f8259SFelipe Balbi * enqueue and dequeue get optimized away by the compiler. 726c28f8259SFelipe Balbi */ 727c28f8259SFelipe Balbi u8 trb_enqueue; 728c28f8259SFelipe Balbi u8 trb_dequeue; 729c28f8259SFelipe Balbi 73072246da4SFelipe Balbi u8 number; 73172246da4SFelipe Balbi u8 type; 732b4996a86SFelipe Balbi u8 resource_index; 733502a37b9SFelipe Balbi u32 frame_number; 73472246da4SFelipe Balbi u32 interval; 73572246da4SFelipe Balbi 73672246da4SFelipe Balbi char name[20]; 73772246da4SFelipe Balbi 73872246da4SFelipe Balbi unsigned direction:1; 739879631aaSFelipe Balbi unsigned stream_capable:1; 740d92021f6SThinh Nguyen 741d92021f6SThinh Nguyen /* For isochronous START TRANSFER workaround only */ 742d92021f6SThinh Nguyen u8 combo_num; 743d92021f6SThinh Nguyen int start_cmd_status; 74472246da4SFelipe Balbi }; 74572246da4SFelipe Balbi 74672246da4SFelipe Balbi enum dwc3_phy { 74772246da4SFelipe Balbi DWC3_PHY_UNKNOWN = 0, 74872246da4SFelipe Balbi DWC3_PHY_USB3, 74972246da4SFelipe Balbi DWC3_PHY_USB2, 75072246da4SFelipe Balbi }; 75172246da4SFelipe Balbi 752b53c772dSFelipe Balbi enum dwc3_ep0_next { 753b53c772dSFelipe Balbi DWC3_EP0_UNKNOWN = 0, 754b53c772dSFelipe Balbi DWC3_EP0_COMPLETE, 755b53c772dSFelipe Balbi DWC3_EP0_NRDY_DATA, 756b53c772dSFelipe Balbi DWC3_EP0_NRDY_STATUS, 757b53c772dSFelipe Balbi }; 758b53c772dSFelipe Balbi 75972246da4SFelipe Balbi enum dwc3_ep0_state { 76072246da4SFelipe Balbi EP0_UNCONNECTED = 0, 761c7fcdeb2SFelipe Balbi EP0_SETUP_PHASE, 762c7fcdeb2SFelipe Balbi EP0_DATA_PHASE, 763c7fcdeb2SFelipe Balbi EP0_STATUS_PHASE, 76472246da4SFelipe Balbi }; 76572246da4SFelipe Balbi 76672246da4SFelipe Balbi enum dwc3_link_state { 76772246da4SFelipe Balbi /* In SuperSpeed */ 76872246da4SFelipe Balbi DWC3_LINK_STATE_U0 = 0x00, /* in HS, means ON */ 76972246da4SFelipe Balbi DWC3_LINK_STATE_U1 = 0x01, 77072246da4SFelipe Balbi DWC3_LINK_STATE_U2 = 0x02, /* in HS, means SLEEP */ 77172246da4SFelipe Balbi DWC3_LINK_STATE_U3 = 0x03, /* in HS, means SUSPEND */ 77272246da4SFelipe Balbi DWC3_LINK_STATE_SS_DIS = 0x04, 77372246da4SFelipe Balbi DWC3_LINK_STATE_RX_DET = 0x05, /* in HS, means Early Suspend */ 77472246da4SFelipe Balbi DWC3_LINK_STATE_SS_INACT = 0x06, 77572246da4SFelipe Balbi DWC3_LINK_STATE_POLL = 0x07, 77672246da4SFelipe Balbi DWC3_LINK_STATE_RECOV = 0x08, 77772246da4SFelipe Balbi DWC3_LINK_STATE_HRESET = 0x09, 77872246da4SFelipe Balbi DWC3_LINK_STATE_CMPLY = 0x0a, 77972246da4SFelipe Balbi DWC3_LINK_STATE_LPBK = 0x0b, 7802c61a8efSPaul Zimmerman DWC3_LINK_STATE_RESET = 0x0e, 7812c61a8efSPaul Zimmerman DWC3_LINK_STATE_RESUME = 0x0f, 78272246da4SFelipe Balbi DWC3_LINK_STATE_MASK = 0x0f, 78372246da4SFelipe Balbi }; 78472246da4SFelipe Balbi 785f6bafc6aSFelipe Balbi /* TRB Length, PCM and Status */ 786f6bafc6aSFelipe Balbi #define DWC3_TRB_SIZE_MASK (0x00ffffff) 787f6bafc6aSFelipe Balbi #define DWC3_TRB_SIZE_LENGTH(n) ((n) & DWC3_TRB_SIZE_MASK) 788f6bafc6aSFelipe Balbi #define DWC3_TRB_SIZE_PCM1(n) (((n) & 0x03) << 24) 789389f2828SPratyush Anand #define DWC3_TRB_SIZE_TRBSTS(n) (((n) & (0x0f << 28)) >> 28) 79072246da4SFelipe Balbi 791f6bafc6aSFelipe Balbi #define DWC3_TRBSTS_OK 0 792f6bafc6aSFelipe Balbi #define DWC3_TRBSTS_MISSED_ISOC 1 793f6bafc6aSFelipe Balbi #define DWC3_TRBSTS_SETUP_PENDING 2 7942c61a8efSPaul Zimmerman #define DWC3_TRB_STS_XFER_IN_PROG 4 79572246da4SFelipe Balbi 796f6bafc6aSFelipe Balbi /* TRB Control */ 797ff3f0789SRoger Quadros #define DWC3_TRB_CTRL_HWO BIT(0) 798ff3f0789SRoger Quadros #define DWC3_TRB_CTRL_LST BIT(1) 799ff3f0789SRoger Quadros #define DWC3_TRB_CTRL_CHN BIT(2) 800ff3f0789SRoger Quadros #define DWC3_TRB_CTRL_CSP BIT(3) 801f6bafc6aSFelipe Balbi #define DWC3_TRB_CTRL_TRBCTL(n) (((n) & 0x3f) << 4) 802ff3f0789SRoger Quadros #define DWC3_TRB_CTRL_ISP_IMI BIT(10) 803ff3f0789SRoger Quadros #define DWC3_TRB_CTRL_IOC BIT(11) 804f6bafc6aSFelipe Balbi #define DWC3_TRB_CTRL_SID_SOFN(n) (((n) & 0xffff) << 14) 8056abfa0f5SThinh Nguyen #define DWC3_TRB_CTRL_GET_SID_SOFN(n) (((n) & (0xffff << 14)) >> 14) 806f6bafc6aSFelipe Balbi 807b058f3e8SFelipe Balbi #define DWC3_TRBCTL_TYPE(n) ((n) & (0x3f << 4)) 808f6bafc6aSFelipe Balbi #define DWC3_TRBCTL_NORMAL DWC3_TRB_CTRL_TRBCTL(1) 809f6bafc6aSFelipe Balbi #define DWC3_TRBCTL_CONTROL_SETUP DWC3_TRB_CTRL_TRBCTL(2) 810f6bafc6aSFelipe Balbi #define DWC3_TRBCTL_CONTROL_STATUS2 DWC3_TRB_CTRL_TRBCTL(3) 811f6bafc6aSFelipe Balbi #define DWC3_TRBCTL_CONTROL_STATUS3 DWC3_TRB_CTRL_TRBCTL(4) 812f6bafc6aSFelipe Balbi #define DWC3_TRBCTL_CONTROL_DATA DWC3_TRB_CTRL_TRBCTL(5) 813f6bafc6aSFelipe Balbi #define DWC3_TRBCTL_ISOCHRONOUS_FIRST DWC3_TRB_CTRL_TRBCTL(6) 814f6bafc6aSFelipe Balbi #define DWC3_TRBCTL_ISOCHRONOUS DWC3_TRB_CTRL_TRBCTL(7) 815f6bafc6aSFelipe Balbi #define DWC3_TRBCTL_LINK_TRB DWC3_TRB_CTRL_TRBCTL(8) 81672246da4SFelipe Balbi 81772246da4SFelipe Balbi /** 818f6bafc6aSFelipe Balbi * struct dwc3_trb - transfer request block (hw format) 81972246da4SFelipe Balbi * @bpl: DW0-3 82072246da4SFelipe Balbi * @bph: DW4-7 82172246da4SFelipe Balbi * @size: DW8-B 822bfad65eeSFelipe Balbi * @ctrl: DWC-F 82372246da4SFelipe Balbi */ 824f6bafc6aSFelipe Balbi struct dwc3_trb { 825f6bafc6aSFelipe Balbi u32 bpl; 826f6bafc6aSFelipe Balbi u32 bph; 827f6bafc6aSFelipe Balbi u32 size; 828f6bafc6aSFelipe Balbi u32 ctrl; 82972246da4SFelipe Balbi } __packed; 83072246da4SFelipe Balbi 83172246da4SFelipe Balbi /** 832bfad65eeSFelipe Balbi * struct dwc3_hwparams - copy of HWPARAMS registers 833bfad65eeSFelipe Balbi * @hwparams0: GHWPARAMS0 834bfad65eeSFelipe Balbi * @hwparams1: GHWPARAMS1 835bfad65eeSFelipe Balbi * @hwparams2: GHWPARAMS2 836bfad65eeSFelipe Balbi * @hwparams3: GHWPARAMS3 837bfad65eeSFelipe Balbi * @hwparams4: GHWPARAMS4 838bfad65eeSFelipe Balbi * @hwparams5: GHWPARAMS5 839bfad65eeSFelipe Balbi * @hwparams6: GHWPARAMS6 840bfad65eeSFelipe Balbi * @hwparams7: GHWPARAMS7 841bfad65eeSFelipe Balbi * @hwparams8: GHWPARAMS8 842a3299499SFelipe Balbi */ 843a3299499SFelipe Balbi struct dwc3_hwparams { 844a3299499SFelipe Balbi u32 hwparams0; 845a3299499SFelipe Balbi u32 hwparams1; 846a3299499SFelipe Balbi u32 hwparams2; 847a3299499SFelipe Balbi u32 hwparams3; 848a3299499SFelipe Balbi u32 hwparams4; 849a3299499SFelipe Balbi u32 hwparams5; 850a3299499SFelipe Balbi u32 hwparams6; 851a3299499SFelipe Balbi u32 hwparams7; 852a3299499SFelipe Balbi u32 hwparams8; 853a3299499SFelipe Balbi }; 854a3299499SFelipe Balbi 8550949e99bSFelipe Balbi /* HWPARAMS0 */ 8560949e99bSFelipe Balbi #define DWC3_MODE(n) ((n) & 0x7) 8570949e99bSFelipe Balbi 858457e84b6SFelipe Balbi #define DWC3_MDWIDTH(n) (((n) & 0xff00) >> 8) 859457e84b6SFelipe Balbi 8600949e99bSFelipe Balbi /* HWPARAMS1 */ 8619f622b2aSFelipe Balbi #define DWC3_NUM_INT(n) (((n) & (0x3f << 15)) >> 15) 8629f622b2aSFelipe Balbi 863789451f6SFelipe Balbi /* HWPARAMS3 */ 864789451f6SFelipe Balbi #define DWC3_NUM_IN_EPS_MASK (0x1f << 18) 865789451f6SFelipe Balbi #define DWC3_NUM_EPS_MASK (0x3f << 12) 866789451f6SFelipe Balbi #define DWC3_NUM_EPS(p) (((p)->hwparams3 & \ 867789451f6SFelipe Balbi (DWC3_NUM_EPS_MASK)) >> 12) 868789451f6SFelipe Balbi #define DWC3_NUM_IN_EPS(p) (((p)->hwparams3 & \ 869789451f6SFelipe Balbi (DWC3_NUM_IN_EPS_MASK)) >> 18) 870789451f6SFelipe Balbi 871457e84b6SFelipe Balbi /* HWPARAMS7 */ 872457e84b6SFelipe Balbi #define DWC3_RAM1_DEPTH(n) ((n) & 0xffff) 873457e84b6SFelipe Balbi 8745ef68c56SFelipe Balbi /** 8755ef68c56SFelipe Balbi * struct dwc3_request - representation of a transfer request 8765ef68c56SFelipe Balbi * @request: struct usb_request to be transferred 8775ef68c56SFelipe Balbi * @list: a list_head used for request queueing 8785ef68c56SFelipe Balbi * @dep: struct dwc3_ep owning this request 8790b3e4af3SFelipe Balbi * @sg: pointer to first incomplete sg 880a31e63b6SAnurag Kumar Vulisha * @start_sg: pointer to the sg which should be queued next 8810b3e4af3SFelipe Balbi * @num_pending_sgs: counter to pending sgs 882c96e6725SAnurag Kumar Vulisha * @num_queued_sgs: counter to the number of sgs which already got queued 883e62c5bc5SFelipe Balbi * @remaining: amount of data remaining 884a3af5e3aSFelipe Balbi * @status: internal dwc3 request status tracking 8855ef68c56SFelipe Balbi * @epnum: endpoint number to which this request refers 8865ef68c56SFelipe Balbi * @trb: pointer to struct dwc3_trb 8875ef68c56SFelipe Balbi * @trb_dma: DMA address of @trb 88809fe1f8dSFelipe Balbi * @num_trbs: number of TRBs used by this request 8891a22ec64SFelipe Balbi * @needs_extra_trb: true when request needs one extra TRB (either due to ZLP 8901a22ec64SFelipe Balbi * or unaligned OUT) 8915ef68c56SFelipe Balbi * @direction: IN or OUT direction flag 8925ef68c56SFelipe Balbi * @mapped: true when request has been dma-mapped 8935ef68c56SFelipe Balbi */ 894e0ce0b0aSSebastian Andrzej Siewior struct dwc3_request { 895e0ce0b0aSSebastian Andrzej Siewior struct usb_request request; 896e0ce0b0aSSebastian Andrzej Siewior struct list_head list; 897e0ce0b0aSSebastian Andrzej Siewior struct dwc3_ep *dep; 8980b3e4af3SFelipe Balbi struct scatterlist *sg; 899a31e63b6SAnurag Kumar Vulisha struct scatterlist *start_sg; 900e0ce0b0aSSebastian Andrzej Siewior 90187b923a2SFelipe Balbi unsigned int num_pending_sgs; 902c96e6725SAnurag Kumar Vulisha unsigned int num_queued_sgs; 90387b923a2SFelipe Balbi unsigned int remaining; 904a3af5e3aSFelipe Balbi 905a3af5e3aSFelipe Balbi unsigned int status; 906a3af5e3aSFelipe Balbi #define DWC3_REQUEST_STATUS_QUEUED 0 907a3af5e3aSFelipe Balbi #define DWC3_REQUEST_STATUS_STARTED 1 908a3af5e3aSFelipe Balbi #define DWC3_REQUEST_STATUS_CANCELLED 2 909a3af5e3aSFelipe Balbi #define DWC3_REQUEST_STATUS_COMPLETED 3 910a3af5e3aSFelipe Balbi #define DWC3_REQUEST_STATUS_UNKNOWN -1 911a3af5e3aSFelipe Balbi 912e0ce0b0aSSebastian Andrzej Siewior u8 epnum; 913f6bafc6aSFelipe Balbi struct dwc3_trb *trb; 914e0ce0b0aSSebastian Andrzej Siewior dma_addr_t trb_dma; 915e0ce0b0aSSebastian Andrzej Siewior 91687b923a2SFelipe Balbi unsigned int num_trbs; 91709fe1f8dSFelipe Balbi 91887b923a2SFelipe Balbi unsigned int needs_extra_trb:1; 91987b923a2SFelipe Balbi unsigned int direction:1; 92087b923a2SFelipe Balbi unsigned int mapped:1; 921e0ce0b0aSSebastian Andrzej Siewior }; 922e0ce0b0aSSebastian Andrzej Siewior 9232c61a8efSPaul Zimmerman /* 9242c61a8efSPaul Zimmerman * struct dwc3_scratchpad_array - hibernation scratchpad array 9252c61a8efSPaul Zimmerman * (format defined by hw) 9262c61a8efSPaul Zimmerman */ 9272c61a8efSPaul Zimmerman struct dwc3_scratchpad_array { 9282c61a8efSPaul Zimmerman __le64 dma_adr[DWC3_MAX_HIBER_SCRATCHBUFS]; 9292c61a8efSPaul Zimmerman }; 9302c61a8efSPaul Zimmerman 931a3299499SFelipe Balbi /** 93272246da4SFelipe Balbi * struct dwc3 - representation of our controller 933bfad65eeSFelipe Balbi * @drd_work: workqueue used for role swapping 93491db07dcSFelipe Balbi * @ep0_trb: trb which is used for the ctrl_req 935bfad65eeSFelipe Balbi * @bounce: address of bounce buffer 936bfad65eeSFelipe Balbi * @scratchbuf: address of scratch buffer 93791db07dcSFelipe Balbi * @setup_buf: used while precessing STD USB requests 938bfad65eeSFelipe Balbi * @ep0_trb_addr: dma address of @ep0_trb 939bfad65eeSFelipe Balbi * @bounce_addr: dma address of @bounce 94091db07dcSFelipe Balbi * @ep0_usb_req: dummy req used while handling STD USB requests 9410ffcaf37SFelipe Balbi * @scratch_addr: dma address of scratchbuf 942bb014736SBaolin Wang * @ep0_in_setup: one control transfer is completed and enter setup phase 94372246da4SFelipe Balbi * @lock: for synchronizing 94472246da4SFelipe Balbi * @dev: pointer to our struct device 945bfad65eeSFelipe Balbi * @sysdev: pointer to the DMA-capable device 946d07e8819SFelipe Balbi * @xhci: pointer to our xHCI child 947bfad65eeSFelipe Balbi * @xhci_resources: struct resources for our @xhci child 948bfad65eeSFelipe Balbi * @ev_buf: struct dwc3_event_buffer pointer 949bfad65eeSFelipe Balbi * @eps: endpoint array 95072246da4SFelipe Balbi * @gadget: device side representation of the peripheral controller 95172246da4SFelipe Balbi * @gadget_driver: pointer to the gadget driver 952fe8abf33SMasahiro Yamada * @clks: array of clocks 953fe8abf33SMasahiro Yamada * @num_clks: number of clocks 954fe8abf33SMasahiro Yamada * @reset: reset control 95572246da4SFelipe Balbi * @regs: base address for our registers 95672246da4SFelipe Balbi * @regs_size: address space size 957bcdb3272SFelipe Balbi * @fladj: frame length adjustment 9583f308d17SFelipe Balbi * @irq_gadget: peripheral controller's IRQ number 959f09cc79bSRoger Quadros * @otg_irq: IRQ number for OTG IRQs 960f09cc79bSRoger Quadros * @current_otg_role: current role of operation while using the OTG block 961f09cc79bSRoger Quadros * @desired_otg_role: desired role of operation while using the OTG block 962f09cc79bSRoger Quadros * @otg_restart_host: flag that OTG controller needs to restart host 9630ffcaf37SFelipe Balbi * @nr_scratch: number of scratch buffers 964fae2b904SFelipe Balbi * @u1u2: only used on revisions <1.83a for workaround 9656c167fc9SFelipe Balbi * @maximum_speed: maximum speed requested (mainly for testing purposes) 9669af21dd6SThinh Nguyen * @ip: controller's ID 9679af21dd6SThinh Nguyen * @revision: controller's version of an IP 968475d8e01SThinh Nguyen * @version_type: VERSIONTYPE register contents, a sub release of a revision 969a45c82b8SRuchika Kharwar * @dr_mode: requested mode of operation 9706b3261a2SRoger Quadros * @current_dr_role: current role of operation when in dual-role mode 97141ce1456SRoger Quadros * @desired_dr_role: desired role of operation when in dual-role mode 9729840354fSRoger Quadros * @edev: extcon handle 9739840354fSRoger Quadros * @edev_nb: extcon notifier 97432f2ed86SWilliam Wu * @hsphy_mode: UTMI phy mode, one of following: 97532f2ed86SWilliam Wu * - USBPHY_INTERFACE_MODE_UTMI 97632f2ed86SWilliam Wu * - USBPHY_INTERFACE_MODE_UTMIW 9778a0a1379SYu Chen * @role_sw: usb_role_switch handle 97898ed256aSJohn Stultz * @role_switch_default_mode: default operation mode of controller while 97998ed256aSJohn Stultz * usb role is USB_ROLE_NONE. 98051e1e7bcSFelipe Balbi * @usb2_phy: pointer to USB2 PHY 98151e1e7bcSFelipe Balbi * @usb3_phy: pointer to USB3 PHY 98257303488SKishon Vijay Abraham I * @usb2_generic_phy: pointer to USB2 PHY 98357303488SKishon Vijay Abraham I * @usb3_generic_phy: pointer to USB3 PHY 98498112041SRoger Quadros * @phys_ready: flag to indicate that PHYs are ready 98588bc9d19SHeikki Krogerus * @ulpi: pointer to ulpi interface 98698112041SRoger Quadros * @ulpi_ready: flag to indicate that ULPI is initialized 987865e09e7SFelipe Balbi * @u2sel: parameter from Set SEL request. 988865e09e7SFelipe Balbi * @u2pel: parameter from Set SEL request. 989865e09e7SFelipe Balbi * @u1sel: parameter from Set SEL request. 990865e09e7SFelipe Balbi * @u1pel: parameter from Set SEL request. 99147d3946eSBryan O'Donoghue * @num_eps: number of endpoints 992b53c772dSFelipe Balbi * @ep0_next_event: hold the next expected event 99372246da4SFelipe Balbi * @ep0state: state of endpoint zero 99472246da4SFelipe Balbi * @link_state: link state 99572246da4SFelipe Balbi * @speed: device speed (super, high, full, low) 996a3299499SFelipe Balbi * @hwparams: copy of hwparams registers 99772246da4SFelipe Balbi * @root: debugfs root folder pointer 998f2b685d5SFelipe Balbi * @regset: debugfs pointer to regdump file 99962ba09d6SThinh Nguyen * @dbg_lsp_select: current debug lsp mux register selection 1000f2b685d5SFelipe Balbi * @test_mode: true when we're entering a USB test mode 1001f2b685d5SFelipe Balbi * @test_mode_nr: test feature selector 100280caf7d2SHuang Rui * @lpm_nyet_threshold: LPM NYET response threshold 1003460d098cSHuang Rui * @hird_threshold: HIRD threshold 1004938a5ad1SThinh Nguyen * @rx_thr_num_pkt_prd: periodic ESS receive packet count 1005938a5ad1SThinh Nguyen * @rx_max_burst_prd: max periodic ESS receive burst size 1006938a5ad1SThinh Nguyen * @tx_thr_num_pkt_prd: periodic ESS transmit packet count 1007938a5ad1SThinh Nguyen * @tx_max_burst_prd: max periodic ESS transmit burst size 10083e10a2ceSHeikki Krogerus * @hsphy_interface: "utmi" or "ulpi" 1009fc8bb91bSFelipe Balbi * @connected: true when we're connected to a host, false otherwise 1010f2b685d5SFelipe Balbi * @delayed_status: true when gadget driver asks for delayed status 1011f2b685d5SFelipe Balbi * @ep0_bounced: true when we used bounce buffer 1012f2b685d5SFelipe Balbi * @ep0_expect_in: true when we expect a DATA IN transfer 101381bc5599SFelipe Balbi * @has_hibernation: true when dwc3 was configured with Hibernation 1014d64ff406SArnd Bergmann * @sysdev_is_parent: true when dwc3 device has a parent driver 101580caf7d2SHuang Rui * @has_lpm_erratum: true when core was configured with LPM Erratum. Note that 101680caf7d2SHuang Rui * there's now way for software to detect this in runtime. 1017460d098cSHuang Rui * @is_utmi_l1_suspend: the core asserts output signal 1018460d098cSHuang Rui * 0 - utmi_sleep_n 1019460d098cSHuang Rui * 1 - utmi_l1_suspend_n 1020946bd579SHuang Rui * @is_fpga: true when we are using the FPGA board 1021fc8bb91bSFelipe Balbi * @pending_events: true when we have pending IRQs to be handled 1022f2b685d5SFelipe Balbi * @pullups_connected: true when Run/Stop bit is set 1023f2b685d5SFelipe Balbi * @setup_packet_pending: true when there's a Setup Packet in FIFO. Workaround 1024f2b685d5SFelipe Balbi * @three_stage_setup: set if we perform a three phase setup 1025d92021f6SThinh Nguyen * @dis_start_transfer_quirk: set if start_transfer failure SW workaround is 1026d92021f6SThinh Nguyen * not needed for DWC_usb31 version 1.70a-ea06 and below 1027eac68e8fSRobert Baldyga * @usb3_lpm_capable: set if hadrware supports Link Power Management 1028022a0208SThinh Nguyen * @usb2_lpm_disable: set to disable usb2 lpm 10293b81221aSHuang Rui * @disable_scramble_quirk: set if we enable the disable scramble quirk 10309a5b2f31SHuang Rui * @u2exit_lfps_quirk: set if we enable u2exit lfps quirk 1031b5a65c40SHuang Rui * @u2ss_inp3_quirk: set if we enable P3 OK for U2/SS Inactive quirk 1032df31f5b3SHuang Rui * @req_p1p2p3_quirk: set if we enable request p1p2p3 quirk 1033a2a1d0f5SHuang Rui * @del_p1p2p3_quirk: set if we enable delay p1p2p3 quirk 103441c06ffdSHuang Rui * @del_phy_power_chg_quirk: set if we enable delay phy power change quirk 1035fb67afcaSHuang Rui * @lfps_filter_quirk: set if we enable LFPS filter quirk 103614f4ac53SHuang Rui * @rx_detect_poll_quirk: set if we enable rx_detect to polling lfps quirk 103759acfa20SHuang Rui * @dis_u3_susphy_quirk: set if we disable usb3 suspend phy 10380effe0a3SHuang Rui * @dis_u2_susphy_quirk: set if we disable usb2 suspend phy 1039ec791d14SJohn Youn * @dis_enblslpm_quirk: set if we clear enblslpm in GUSB2PHYCFG, 1040ec791d14SJohn Youn * disabling the suspend signal to the PHY. 1041729dcffdSAnurag Kumar Vulisha * @dis_u1_entry_quirk: set if link entering into U1 state needs to be disabled. 1042729dcffdSAnurag Kumar Vulisha * @dis_u2_entry_quirk: set if link entering into U2 state needs to be disabled. 1043bfad65eeSFelipe Balbi * @dis_rxdet_inp3_quirk: set if we disable Rx.Detect in P3 104416199f33SWilliam Wu * @dis_u2_freeclk_exists_quirk : set if we clear u2_freeclk_exists 104516199f33SWilliam Wu * in GUSB2PHYCFG, specify that USB2 PHY doesn't 104616199f33SWilliam Wu * provide a free-running PHY clock. 104700fe081dSWilliam Wu * @dis_del_phy_power_chg_quirk: set if we disable delay phy power 104800fe081dSWilliam Wu * change quirk. 104965db7a0cSWilliam Wu * @dis_tx_ipgap_linecheck_quirk: set if we disable u2mac linestate 105065db7a0cSWilliam Wu * check during HS transmit. 10517ba6b09fSNeil Armstrong * @parkmode_disable_ss_quirk: set if we need to disable all SuperSpeed 10527ba6b09fSNeil Armstrong * instances in park mode. 10536b6a0c9aSHuang Rui * @tx_de_emphasis_quirk: set if we enable Tx de-emphasis quirk 10546b6a0c9aSHuang Rui * @tx_de_emphasis: Tx de-emphasis value 10556b6a0c9aSHuang Rui * 0 - -6dB de-emphasis 10566b6a0c9aSHuang Rui * 1 - -3.5dB de-emphasis 10576b6a0c9aSHuang Rui * 2 - No de-emphasis 10586b6a0c9aSHuang Rui * 3 - Reserved 105942bf02ecSRoger Quadros * @dis_metastability_quirk: set to disable metastability quirk. 1060f580170fSYu Chen * @dis_split_quirk: set to disable split boundary. 1061cf40b86bSJohn Youn * @imod_interval: set the interrupt moderation interval in 250ns 1062cf40b86bSJohn Youn * increments or 0 to disable. 106372246da4SFelipe Balbi */ 106472246da4SFelipe Balbi struct dwc3 { 106541ce1456SRoger Quadros struct work_struct drd_work; 1066f6bafc6aSFelipe Balbi struct dwc3_trb *ep0_trb; 1067905dc04eSFelipe Balbi void *bounce; 10680ffcaf37SFelipe Balbi void *scratchbuf; 106972246da4SFelipe Balbi u8 *setup_buf; 107072246da4SFelipe Balbi dma_addr_t ep0_trb_addr; 1071905dc04eSFelipe Balbi dma_addr_t bounce_addr; 10720ffcaf37SFelipe Balbi dma_addr_t scratch_addr; 1073e0ce0b0aSSebastian Andrzej Siewior struct dwc3_request ep0_usb_req; 1074bb014736SBaolin Wang struct completion ep0_in_setup; 1075789451f6SFelipe Balbi 107672246da4SFelipe Balbi /* device lock */ 107772246da4SFelipe Balbi spinlock_t lock; 1078789451f6SFelipe Balbi 107972246da4SFelipe Balbi struct device *dev; 1080d64ff406SArnd Bergmann struct device *sysdev; 108172246da4SFelipe Balbi 1082d07e8819SFelipe Balbi struct platform_device *xhci; 108351249dcaSIdo Shayevitz struct resource xhci_resources[DWC3_XHCI_RESOURCES_NUM]; 1084d07e8819SFelipe Balbi 1085696c8b12SFelipe Balbi struct dwc3_event_buffer *ev_buf; 108672246da4SFelipe Balbi struct dwc3_ep *eps[DWC3_ENDPOINTS_NUM]; 108772246da4SFelipe Balbi 1088e81a7018SPeter Chen struct usb_gadget *gadget; 108972246da4SFelipe Balbi struct usb_gadget_driver *gadget_driver; 109072246da4SFelipe Balbi 1091fe8abf33SMasahiro Yamada struct clk_bulk_data *clks; 1092fe8abf33SMasahiro Yamada int num_clks; 1093fe8abf33SMasahiro Yamada 1094fe8abf33SMasahiro Yamada struct reset_control *reset; 1095fe8abf33SMasahiro Yamada 109651e1e7bcSFelipe Balbi struct usb_phy *usb2_phy; 109751e1e7bcSFelipe Balbi struct usb_phy *usb3_phy; 109851e1e7bcSFelipe Balbi 109957303488SKishon Vijay Abraham I struct phy *usb2_generic_phy; 110057303488SKishon Vijay Abraham I struct phy *usb3_generic_phy; 110157303488SKishon Vijay Abraham I 110298112041SRoger Quadros bool phys_ready; 110398112041SRoger Quadros 110488bc9d19SHeikki Krogerus struct ulpi *ulpi; 110598112041SRoger Quadros bool ulpi_ready; 110688bc9d19SHeikki Krogerus 110772246da4SFelipe Balbi void __iomem *regs; 110872246da4SFelipe Balbi size_t regs_size; 110972246da4SFelipe Balbi 1110a45c82b8SRuchika Kharwar enum usb_dr_mode dr_mode; 11116b3261a2SRoger Quadros u32 current_dr_role; 111241ce1456SRoger Quadros u32 desired_dr_role; 11139840354fSRoger Quadros struct extcon_dev *edev; 11149840354fSRoger Quadros struct notifier_block edev_nb; 111532f2ed86SWilliam Wu enum usb_phy_interface hsphy_mode; 11168a0a1379SYu Chen struct usb_role_switch *role_sw; 111798ed256aSJohn Stultz enum usb_dr_mode role_switch_default_mode; 1118a45c82b8SRuchika Kharwar 1119bcdb3272SFelipe Balbi u32 fladj; 11203f308d17SFelipe Balbi u32 irq_gadget; 1121f09cc79bSRoger Quadros u32 otg_irq; 1122f09cc79bSRoger Quadros u32 current_otg_role; 1123f09cc79bSRoger Quadros u32 desired_otg_role; 1124f09cc79bSRoger Quadros bool otg_restart_host; 11250ffcaf37SFelipe Balbi u32 nr_scratch; 1126fae2b904SFelipe Balbi u32 u1u2; 11276c167fc9SFelipe Balbi u32 maximum_speed; 1128690fb371SJohn Youn 11299af21dd6SThinh Nguyen u32 ip; 11309af21dd6SThinh Nguyen 11319af21dd6SThinh Nguyen #define DWC3_IP 0x5533 11329af21dd6SThinh Nguyen #define DWC31_IP 0x3331 11339af21dd6SThinh Nguyen #define DWC32_IP 0x3332 11349af21dd6SThinh Nguyen 113572246da4SFelipe Balbi u32 revision; 113672246da4SFelipe Balbi 11379af21dd6SThinh Nguyen #define DWC3_REVISION_ANY 0x0 113872246da4SFelipe Balbi #define DWC3_REVISION_173A 0x5533173a 113972246da4SFelipe Balbi #define DWC3_REVISION_175A 0x5533175a 114072246da4SFelipe Balbi #define DWC3_REVISION_180A 0x5533180a 114172246da4SFelipe Balbi #define DWC3_REVISION_183A 0x5533183a 114272246da4SFelipe Balbi #define DWC3_REVISION_185A 0x5533185a 11432c61a8efSPaul Zimmerman #define DWC3_REVISION_187A 0x5533187a 114472246da4SFelipe Balbi #define DWC3_REVISION_188A 0x5533188a 114572246da4SFelipe Balbi #define DWC3_REVISION_190A 0x5533190a 11462c61a8efSPaul Zimmerman #define DWC3_REVISION_194A 0x5533194a 11471522d703SFelipe Balbi #define DWC3_REVISION_200A 0x5533200a 11481522d703SFelipe Balbi #define DWC3_REVISION_202A 0x5533202a 11491522d703SFelipe Balbi #define DWC3_REVISION_210A 0x5533210a 11501522d703SFelipe Balbi #define DWC3_REVISION_220A 0x5533220a 11517ac6a593SFelipe Balbi #define DWC3_REVISION_230A 0x5533230a 11527ac6a593SFelipe Balbi #define DWC3_REVISION_240A 0x5533240a 11537ac6a593SFelipe Balbi #define DWC3_REVISION_250A 0x5533250a 1154dbf5aaf7SFelipe Balbi #define DWC3_REVISION_260A 0x5533260a 1155dbf5aaf7SFelipe Balbi #define DWC3_REVISION_270A 0x5533270a 1156dbf5aaf7SFelipe Balbi #define DWC3_REVISION_280A 0x5533280a 11570bb39ca1SJohn Youn #define DWC3_REVISION_290A 0x5533290a 1158512e4757SJohn Youn #define DWC3_REVISION_300A 0x5533300a 1159512e4757SJohn Youn #define DWC3_REVISION_310A 0x5533310a 116089a9cc47SThinh Nguyen #define DWC3_REVISION_330A 0x5533330a 116172246da4SFelipe Balbi 11629af21dd6SThinh Nguyen #define DWC31_REVISION_ANY 0x0 11639af21dd6SThinh Nguyen #define DWC31_REVISION_110A 0x3131302a 11649af21dd6SThinh Nguyen #define DWC31_REVISION_120A 0x3132302a 11659af21dd6SThinh Nguyen #define DWC31_REVISION_160A 0x3136302a 11669af21dd6SThinh Nguyen #define DWC31_REVISION_170A 0x3137302a 11679af21dd6SThinh Nguyen #define DWC31_REVISION_180A 0x3138302a 11689af21dd6SThinh Nguyen #define DWC31_REVISION_190A 0x3139302a 1169690fb371SJohn Youn 1170b10e1c25SThinh Nguyen #define DWC32_REVISION_ANY 0x0 1171b10e1c25SThinh Nguyen #define DWC32_REVISION_100A 0x3130302a 1172b10e1c25SThinh Nguyen 1173475d8e01SThinh Nguyen u32 version_type; 1174475d8e01SThinh Nguyen 11759af21dd6SThinh Nguyen #define DWC31_VERSIONTYPE_ANY 0x0 1176475d8e01SThinh Nguyen #define DWC31_VERSIONTYPE_EA01 0x65613031 1177475d8e01SThinh Nguyen #define DWC31_VERSIONTYPE_EA02 0x65613032 1178475d8e01SThinh Nguyen #define DWC31_VERSIONTYPE_EA03 0x65613033 1179475d8e01SThinh Nguyen #define DWC31_VERSIONTYPE_EA04 0x65613034 1180475d8e01SThinh Nguyen #define DWC31_VERSIONTYPE_EA05 0x65613035 1181475d8e01SThinh Nguyen #define DWC31_VERSIONTYPE_EA06 0x65613036 1182475d8e01SThinh Nguyen 1183b53c772dSFelipe Balbi enum dwc3_ep0_next ep0_next_event; 118472246da4SFelipe Balbi enum dwc3_ep0_state ep0state; 118572246da4SFelipe Balbi enum dwc3_link_state link_state; 118672246da4SFelipe Balbi 1187865e09e7SFelipe Balbi u16 u2sel; 1188865e09e7SFelipe Balbi u16 u2pel; 1189865e09e7SFelipe Balbi u8 u1sel; 1190865e09e7SFelipe Balbi u8 u1pel; 1191865e09e7SFelipe Balbi 119272246da4SFelipe Balbi u8 speed; 1193865e09e7SFelipe Balbi 119447d3946eSBryan O'Donoghue u8 num_eps; 1195789451f6SFelipe Balbi 1196a3299499SFelipe Balbi struct dwc3_hwparams hwparams; 119772246da4SFelipe Balbi struct dentry *root; 1198d7668024SFelipe Balbi struct debugfs_regset32 *regset; 11993b637367SGerard Cauvy 120062ba09d6SThinh Nguyen u32 dbg_lsp_select; 120162ba09d6SThinh Nguyen 12023b637367SGerard Cauvy u8 test_mode; 12033b637367SGerard Cauvy u8 test_mode_nr; 120480caf7d2SHuang Rui u8 lpm_nyet_threshold; 1205460d098cSHuang Rui u8 hird_threshold; 1206938a5ad1SThinh Nguyen u8 rx_thr_num_pkt_prd; 1207938a5ad1SThinh Nguyen u8 rx_max_burst_prd; 1208938a5ad1SThinh Nguyen u8 tx_thr_num_pkt_prd; 1209938a5ad1SThinh Nguyen u8 tx_max_burst_prd; 1210f2b685d5SFelipe Balbi 12113e10a2ceSHeikki Krogerus const char *hsphy_interface; 12123e10a2ceSHeikki Krogerus 1213fc8bb91bSFelipe Balbi unsigned connected:1; 1214f2b685d5SFelipe Balbi unsigned delayed_status:1; 1215f2b685d5SFelipe Balbi unsigned ep0_bounced:1; 1216f2b685d5SFelipe Balbi unsigned ep0_expect_in:1; 121781bc5599SFelipe Balbi unsigned has_hibernation:1; 1218d64ff406SArnd Bergmann unsigned sysdev_is_parent:1; 121980caf7d2SHuang Rui unsigned has_lpm_erratum:1; 1220460d098cSHuang Rui unsigned is_utmi_l1_suspend:1; 1221946bd579SHuang Rui unsigned is_fpga:1; 1222fc8bb91bSFelipe Balbi unsigned pending_events:1; 1223f2b685d5SFelipe Balbi unsigned pullups_connected:1; 1224f2b685d5SFelipe Balbi unsigned setup_packet_pending:1; 1225f2b685d5SFelipe Balbi unsigned three_stage_setup:1; 1226d92021f6SThinh Nguyen unsigned dis_start_transfer_quirk:1; 1227eac68e8fSRobert Baldyga unsigned usb3_lpm_capable:1; 1228022a0208SThinh Nguyen unsigned usb2_lpm_disable:1; 12293b81221aSHuang Rui 12303b81221aSHuang Rui unsigned disable_scramble_quirk:1; 12319a5b2f31SHuang Rui unsigned u2exit_lfps_quirk:1; 1232b5a65c40SHuang Rui unsigned u2ss_inp3_quirk:1; 1233df31f5b3SHuang Rui unsigned req_p1p2p3_quirk:1; 1234a2a1d0f5SHuang Rui unsigned del_p1p2p3_quirk:1; 123541c06ffdSHuang Rui unsigned del_phy_power_chg_quirk:1; 1236fb67afcaSHuang Rui unsigned lfps_filter_quirk:1; 123714f4ac53SHuang Rui unsigned rx_detect_poll_quirk:1; 123859acfa20SHuang Rui unsigned dis_u3_susphy_quirk:1; 12390effe0a3SHuang Rui unsigned dis_u2_susphy_quirk:1; 1240ec791d14SJohn Youn unsigned dis_enblslpm_quirk:1; 1241729dcffdSAnurag Kumar Vulisha unsigned dis_u1_entry_quirk:1; 1242729dcffdSAnurag Kumar Vulisha unsigned dis_u2_entry_quirk:1; 1243e58dd357SRajesh Bhagat unsigned dis_rxdet_inp3_quirk:1; 124416199f33SWilliam Wu unsigned dis_u2_freeclk_exists_quirk:1; 124500fe081dSWilliam Wu unsigned dis_del_phy_power_chg_quirk:1; 124665db7a0cSWilliam Wu unsigned dis_tx_ipgap_linecheck_quirk:1; 12477ba6b09fSNeil Armstrong unsigned parkmode_disable_ss_quirk:1; 12486b6a0c9aSHuang Rui 12496b6a0c9aSHuang Rui unsigned tx_de_emphasis_quirk:1; 12506b6a0c9aSHuang Rui unsigned tx_de_emphasis:2; 1251cf40b86bSJohn Youn 125242bf02ecSRoger Quadros unsigned dis_metastability_quirk:1; 125342bf02ecSRoger Quadros 1254f580170fSYu Chen unsigned dis_split_quirk:1; 1255f580170fSYu Chen 1256cf40b86bSJohn Youn u16 imod_interval; 125772246da4SFelipe Balbi }; 125872246da4SFelipe Balbi 1259d9612c2fSPengbo Mu #define INCRX_BURST_MODE 0 1260d9612c2fSPengbo Mu #define INCRX_UNDEF_LENGTH_BURST_MODE 1 1261d9612c2fSPengbo Mu 126241ce1456SRoger Quadros #define work_to_dwc(w) (container_of((w), struct dwc3, drd_work)) 126372246da4SFelipe Balbi 126472246da4SFelipe Balbi /* -------------------------------------------------------------------------- */ 126572246da4SFelipe Balbi 126672246da4SFelipe Balbi struct dwc3_event_type { 126772246da4SFelipe Balbi u32 is_devspec:1; 12681974d494SHuang Rui u32 type:7; 12691974d494SHuang Rui u32 reserved8_31:24; 127072246da4SFelipe Balbi } __packed; 127172246da4SFelipe Balbi 127272246da4SFelipe Balbi #define DWC3_DEPEVT_XFERCOMPLETE 0x01 127372246da4SFelipe Balbi #define DWC3_DEPEVT_XFERINPROGRESS 0x02 127472246da4SFelipe Balbi #define DWC3_DEPEVT_XFERNOTREADY 0x03 127572246da4SFelipe Balbi #define DWC3_DEPEVT_RXTXFIFOEVT 0x04 127672246da4SFelipe Balbi #define DWC3_DEPEVT_STREAMEVT 0x06 127772246da4SFelipe Balbi #define DWC3_DEPEVT_EPCMDCMPLT 0x07 127872246da4SFelipe Balbi 127972246da4SFelipe Balbi /** 128072246da4SFelipe Balbi * struct dwc3_event_depvt - Device Endpoint Events 128172246da4SFelipe Balbi * @one_bit: indicates this is an endpoint event (not used) 128272246da4SFelipe Balbi * @endpoint_number: number of the endpoint 128372246da4SFelipe Balbi * @endpoint_event: The event we have: 128472246da4SFelipe Balbi * 0x00 - Reserved 128572246da4SFelipe Balbi * 0x01 - XferComplete 128672246da4SFelipe Balbi * 0x02 - XferInProgress 128772246da4SFelipe Balbi * 0x03 - XferNotReady 128872246da4SFelipe Balbi * 0x04 - RxTxFifoEvt (IN->Underrun, OUT->Overrun) 128972246da4SFelipe Balbi * 0x05 - Reserved 129072246da4SFelipe Balbi * 0x06 - StreamEvt 129172246da4SFelipe Balbi * 0x07 - EPCmdCmplt 129272246da4SFelipe Balbi * @reserved11_10: Reserved, don't use. 129372246da4SFelipe Balbi * @status: Indicates the status of the event. Refer to databook for 129472246da4SFelipe Balbi * more information. 129572246da4SFelipe Balbi * @parameters: Parameters of the current event. Refer to databook for 129672246da4SFelipe Balbi * more information. 129772246da4SFelipe Balbi */ 129872246da4SFelipe Balbi struct dwc3_event_depevt { 129972246da4SFelipe Balbi u32 one_bit:1; 130072246da4SFelipe Balbi u32 endpoint_number:5; 130172246da4SFelipe Balbi u32 endpoint_event:4; 130272246da4SFelipe Balbi u32 reserved11_10:2; 130372246da4SFelipe Balbi u32 status:4; 130440aa41fbSFelipe Balbi 130540aa41fbSFelipe Balbi /* Within XferNotReady */ 1306ff3f0789SRoger Quadros #define DEPEVT_STATUS_TRANSFER_ACTIVE BIT(3) 130740aa41fbSFelipe Balbi 13086d8a0196SFelipe Balbi /* Within XferComplete or XferInProgress */ 1309ff3f0789SRoger Quadros #define DEPEVT_STATUS_BUSERR BIT(0) 1310ff3f0789SRoger Quadros #define DEPEVT_STATUS_SHORT BIT(1) 1311ff3f0789SRoger Quadros #define DEPEVT_STATUS_IOC BIT(2) 13126d8a0196SFelipe Balbi #define DEPEVT_STATUS_LST BIT(3) /* XferComplete */ 13136d8a0196SFelipe Balbi #define DEPEVT_STATUS_MISSED_ISOC BIT(3) /* XferInProgress */ 1314dc137f01SFelipe Balbi 1315879631aaSFelipe Balbi /* Stream event only */ 1316879631aaSFelipe Balbi #define DEPEVT_STREAMEVT_FOUND 1 1317879631aaSFelipe Balbi #define DEPEVT_STREAMEVT_NOTFOUND 2 1318879631aaSFelipe Balbi 1319140ca4cfSThinh Nguyen /* Stream event parameter */ 1320140ca4cfSThinh Nguyen #define DEPEVT_STREAM_PRIME 0xfffe 1321140ca4cfSThinh Nguyen #define DEPEVT_STREAM_NOSTREAM 0x0 1322140ca4cfSThinh Nguyen 1323dc137f01SFelipe Balbi /* Control-only Status */ 1324dc137f01SFelipe Balbi #define DEPEVT_STATUS_CONTROL_DATA 1 1325dc137f01SFelipe Balbi #define DEPEVT_STATUS_CONTROL_STATUS 2 132645a2af2fSFelipe Balbi #define DEPEVT_STATUS_CONTROL_PHASE(n) ((n) & 3) 1327dc137f01SFelipe Balbi 13287b9cc7a2SKonrad Leszczynski /* In response to Start Transfer */ 13297b9cc7a2SKonrad Leszczynski #define DEPEVT_TRANSFER_NO_RESOURCE 1 13307b9cc7a2SKonrad Leszczynski #define DEPEVT_TRANSFER_BUS_EXPIRY 2 13317b9cc7a2SKonrad Leszczynski 133272246da4SFelipe Balbi u32 parameters:16; 133376a638f8SBaolin Wang 133476a638f8SBaolin Wang /* For Command Complete Events */ 133576a638f8SBaolin Wang #define DEPEVT_PARAMETER_CMD(n) (((n) & (0xf << 8)) >> 8) 133672246da4SFelipe Balbi } __packed; 133772246da4SFelipe Balbi 133872246da4SFelipe Balbi /** 133972246da4SFelipe Balbi * struct dwc3_event_devt - Device Events 134072246da4SFelipe Balbi * @one_bit: indicates this is a non-endpoint event (not used) 134172246da4SFelipe Balbi * @device_event: indicates it's a device event. Should read as 0x00 134272246da4SFelipe Balbi * @type: indicates the type of device event. 134372246da4SFelipe Balbi * 0 - DisconnEvt 134472246da4SFelipe Balbi * 1 - USBRst 134572246da4SFelipe Balbi * 2 - ConnectDone 134672246da4SFelipe Balbi * 3 - ULStChng 134772246da4SFelipe Balbi * 4 - WkUpEvt 134872246da4SFelipe Balbi * 5 - Reserved 134972246da4SFelipe Balbi * 6 - EOPF 135072246da4SFelipe Balbi * 7 - SOF 135172246da4SFelipe Balbi * 8 - Reserved 135272246da4SFelipe Balbi * 9 - ErrticErr 135372246da4SFelipe Balbi * 10 - CmdCmplt 135472246da4SFelipe Balbi * 11 - EvntOverflow 135572246da4SFelipe Balbi * 12 - VndrDevTstRcved 135672246da4SFelipe Balbi * @reserved15_12: Reserved, not used 135772246da4SFelipe Balbi * @event_info: Information about this event 135806f9b6e5SHuang Rui * @reserved31_25: Reserved, not used 135972246da4SFelipe Balbi */ 136072246da4SFelipe Balbi struct dwc3_event_devt { 136172246da4SFelipe Balbi u32 one_bit:1; 136272246da4SFelipe Balbi u32 device_event:7; 136372246da4SFelipe Balbi u32 type:4; 136472246da4SFelipe Balbi u32 reserved15_12:4; 136506f9b6e5SHuang Rui u32 event_info:9; 136606f9b6e5SHuang Rui u32 reserved31_25:7; 136772246da4SFelipe Balbi } __packed; 136872246da4SFelipe Balbi 136972246da4SFelipe Balbi /** 137072246da4SFelipe Balbi * struct dwc3_event_gevt - Other Core Events 137172246da4SFelipe Balbi * @one_bit: indicates this is a non-endpoint event (not used) 137272246da4SFelipe Balbi * @device_event: indicates it's (0x03) Carkit or (0x04) I2C event. 137372246da4SFelipe Balbi * @phy_port_number: self-explanatory 137472246da4SFelipe Balbi * @reserved31_12: Reserved, not used. 137572246da4SFelipe Balbi */ 137672246da4SFelipe Balbi struct dwc3_event_gevt { 137772246da4SFelipe Balbi u32 one_bit:1; 137872246da4SFelipe Balbi u32 device_event:7; 137972246da4SFelipe Balbi u32 phy_port_number:4; 138072246da4SFelipe Balbi u32 reserved31_12:20; 138172246da4SFelipe Balbi } __packed; 138272246da4SFelipe Balbi 138372246da4SFelipe Balbi /** 138472246da4SFelipe Balbi * union dwc3_event - representation of Event Buffer contents 138572246da4SFelipe Balbi * @raw: raw 32-bit event 138672246da4SFelipe Balbi * @type: the type of the event 138772246da4SFelipe Balbi * @depevt: Device Endpoint Event 138872246da4SFelipe Balbi * @devt: Device Event 138972246da4SFelipe Balbi * @gevt: Global Event 139072246da4SFelipe Balbi */ 139172246da4SFelipe Balbi union dwc3_event { 139272246da4SFelipe Balbi u32 raw; 139372246da4SFelipe Balbi struct dwc3_event_type type; 139472246da4SFelipe Balbi struct dwc3_event_depevt depevt; 139572246da4SFelipe Balbi struct dwc3_event_devt devt; 139672246da4SFelipe Balbi struct dwc3_event_gevt gevt; 139772246da4SFelipe Balbi }; 139872246da4SFelipe Balbi 139961018305SFelipe Balbi /** 140061018305SFelipe Balbi * struct dwc3_gadget_ep_cmd_params - representation of endpoint command 140161018305SFelipe Balbi * parameters 140261018305SFelipe Balbi * @param2: third parameter 140361018305SFelipe Balbi * @param1: second parameter 140461018305SFelipe Balbi * @param0: first parameter 140561018305SFelipe Balbi */ 140661018305SFelipe Balbi struct dwc3_gadget_ep_cmd_params { 140761018305SFelipe Balbi u32 param2; 140861018305SFelipe Balbi u32 param1; 140961018305SFelipe Balbi u32 param0; 141061018305SFelipe Balbi }; 141161018305SFelipe Balbi 141272246da4SFelipe Balbi /* 141372246da4SFelipe Balbi * DWC3 Features to be used as Driver Data 141472246da4SFelipe Balbi */ 141572246da4SFelipe Balbi 141672246da4SFelipe Balbi #define DWC3_HAS_PERIPHERAL BIT(0) 141772246da4SFelipe Balbi #define DWC3_HAS_XHCI BIT(1) 141872246da4SFelipe Balbi #define DWC3_HAS_OTG BIT(3) 141972246da4SFelipe Balbi 1420d07e8819SFelipe Balbi /* prototypes */ 1421f09cc79bSRoger Quadros void dwc3_set_prtcap(struct dwc3 *dwc, u32 mode); 14223140e8cbSSebastian Andrzej Siewior void dwc3_set_mode(struct dwc3 *dwc, u32 mode); 1423cf6d867dSFelipe Balbi u32 dwc3_core_fifo_space(struct dwc3_ep *dep, u8 type); 14243140e8cbSSebastian Andrzej Siewior 14259af21dd6SThinh Nguyen #define DWC3_IP_IS(_ip) \ 14269af21dd6SThinh Nguyen (dwc->ip == _ip##_IP) 1427a987a906SJohn Youn 14289af21dd6SThinh Nguyen #define DWC3_VER_IS(_ip, _ver) \ 14299af21dd6SThinh Nguyen (DWC3_IP_IS(_ip) && dwc->revision == _ip##_REVISION_##_ver) 14309af21dd6SThinh Nguyen 14319af21dd6SThinh Nguyen #define DWC3_VER_IS_PRIOR(_ip, _ver) \ 14329af21dd6SThinh Nguyen (DWC3_IP_IS(_ip) && dwc->revision < _ip##_REVISION_##_ver) 14339af21dd6SThinh Nguyen 14349af21dd6SThinh Nguyen #define DWC3_VER_IS_WITHIN(_ip, _from, _to) \ 14359af21dd6SThinh Nguyen (DWC3_IP_IS(_ip) && \ 14369af21dd6SThinh Nguyen dwc->revision >= _ip##_REVISION_##_from && \ 14379af21dd6SThinh Nguyen (!(_ip##_REVISION_##_to) || \ 14389af21dd6SThinh Nguyen dwc->revision <= _ip##_REVISION_##_to)) 14399af21dd6SThinh Nguyen 14409af21dd6SThinh Nguyen #define DWC3_VER_TYPE_IS_WITHIN(_ip, _ver, _from, _to) \ 14419af21dd6SThinh Nguyen (DWC3_VER_IS(_ip, _ver) && \ 14429af21dd6SThinh Nguyen dwc->version_type >= _ip##_VERSIONTYPE_##_from && \ 14439af21dd6SThinh Nguyen (!(_ip##_VERSIONTYPE_##_to) || \ 14449af21dd6SThinh Nguyen dwc->version_type <= _ip##_VERSIONTYPE_##_to)) 1445c4137a9cSJohn Youn 1446cf40b86bSJohn Youn bool dwc3_has_imod(struct dwc3 *dwc); 1447cf40b86bSJohn Youn 1448f09cc79bSRoger Quadros int dwc3_event_buffers_setup(struct dwc3 *dwc); 1449f09cc79bSRoger Quadros void dwc3_event_buffers_cleanup(struct dwc3 *dwc); 1450f09cc79bSRoger Quadros 1451388e5c51SVivek Gautam #if IS_ENABLED(CONFIG_USB_DWC3_HOST) || IS_ENABLED(CONFIG_USB_DWC3_DUAL_ROLE) 1452d07e8819SFelipe Balbi int dwc3_host_init(struct dwc3 *dwc); 1453d07e8819SFelipe Balbi void dwc3_host_exit(struct dwc3 *dwc); 1454388e5c51SVivek Gautam #else 1455388e5c51SVivek Gautam static inline int dwc3_host_init(struct dwc3 *dwc) 1456388e5c51SVivek Gautam { return 0; } 1457388e5c51SVivek Gautam static inline void dwc3_host_exit(struct dwc3 *dwc) 1458388e5c51SVivek Gautam { } 1459388e5c51SVivek Gautam #endif 1460d07e8819SFelipe Balbi 1461388e5c51SVivek Gautam #if IS_ENABLED(CONFIG_USB_DWC3_GADGET) || IS_ENABLED(CONFIG_USB_DWC3_DUAL_ROLE) 1462f80b45e7SFelipe Balbi int dwc3_gadget_init(struct dwc3 *dwc); 1463f80b45e7SFelipe Balbi void dwc3_gadget_exit(struct dwc3 *dwc); 146461018305SFelipe Balbi int dwc3_gadget_set_test_mode(struct dwc3 *dwc, int mode); 146561018305SFelipe Balbi int dwc3_gadget_get_link_state(struct dwc3 *dwc); 146661018305SFelipe Balbi int dwc3_gadget_set_link_state(struct dwc3 *dwc, enum dwc3_link_state state); 146787b923a2SFelipe Balbi int dwc3_send_gadget_ep_cmd(struct dwc3_ep *dep, unsigned int cmd, 14682cd4718dSFelipe Balbi struct dwc3_gadget_ep_cmd_params *params); 146987b923a2SFelipe Balbi int dwc3_send_gadget_generic_command(struct dwc3 *dwc, unsigned int cmd, 147087b923a2SFelipe Balbi u32 param); 1471388e5c51SVivek Gautam #else 1472388e5c51SVivek Gautam static inline int dwc3_gadget_init(struct dwc3 *dwc) 1473388e5c51SVivek Gautam { return 0; } 1474388e5c51SVivek Gautam static inline void dwc3_gadget_exit(struct dwc3 *dwc) 1475388e5c51SVivek Gautam { } 147661018305SFelipe Balbi static inline int dwc3_gadget_set_test_mode(struct dwc3 *dwc, int mode) 147761018305SFelipe Balbi { return 0; } 147861018305SFelipe Balbi static inline int dwc3_gadget_get_link_state(struct dwc3 *dwc) 147961018305SFelipe Balbi { return 0; } 148061018305SFelipe Balbi static inline int dwc3_gadget_set_link_state(struct dwc3 *dwc, 148161018305SFelipe Balbi enum dwc3_link_state state) 148261018305SFelipe Balbi { return 0; } 148361018305SFelipe Balbi 148487b923a2SFelipe Balbi static inline int dwc3_send_gadget_ep_cmd(struct dwc3_ep *dep, unsigned int cmd, 14852cd4718dSFelipe Balbi struct dwc3_gadget_ep_cmd_params *params) 148661018305SFelipe Balbi { return 0; } 148761018305SFelipe Balbi static inline int dwc3_send_gadget_generic_command(struct dwc3 *dwc, 148861018305SFelipe Balbi int cmd, u32 param) 148961018305SFelipe Balbi { return 0; } 1490388e5c51SVivek Gautam #endif 1491f80b45e7SFelipe Balbi 14929840354fSRoger Quadros #if IS_ENABLED(CONFIG_USB_DWC3_DUAL_ROLE) 14939840354fSRoger Quadros int dwc3_drd_init(struct dwc3 *dwc); 14949840354fSRoger Quadros void dwc3_drd_exit(struct dwc3 *dwc); 1495f09cc79bSRoger Quadros void dwc3_otg_init(struct dwc3 *dwc); 1496f09cc79bSRoger Quadros void dwc3_otg_exit(struct dwc3 *dwc); 1497f09cc79bSRoger Quadros void dwc3_otg_update(struct dwc3 *dwc, bool ignore_idstatus); 1498f09cc79bSRoger Quadros void dwc3_otg_host_init(struct dwc3 *dwc); 14999840354fSRoger Quadros #else 15009840354fSRoger Quadros static inline int dwc3_drd_init(struct dwc3 *dwc) 15019840354fSRoger Quadros { return 0; } 15029840354fSRoger Quadros static inline void dwc3_drd_exit(struct dwc3 *dwc) 15039840354fSRoger Quadros { } 1504f09cc79bSRoger Quadros static inline void dwc3_otg_init(struct dwc3 *dwc) 1505f09cc79bSRoger Quadros { } 1506f09cc79bSRoger Quadros static inline void dwc3_otg_exit(struct dwc3 *dwc) 1507f09cc79bSRoger Quadros { } 1508f09cc79bSRoger Quadros static inline void dwc3_otg_update(struct dwc3 *dwc, bool ignore_idstatus) 1509f09cc79bSRoger Quadros { } 1510f09cc79bSRoger Quadros static inline void dwc3_otg_host_init(struct dwc3 *dwc) 1511f09cc79bSRoger Quadros { } 15129840354fSRoger Quadros #endif 15139840354fSRoger Quadros 15147415f17cSFelipe Balbi /* power management interface */ 15157415f17cSFelipe Balbi #if !IS_ENABLED(CONFIG_USB_DWC3_HOST) 15167415f17cSFelipe Balbi int dwc3_gadget_suspend(struct dwc3 *dwc); 15177415f17cSFelipe Balbi int dwc3_gadget_resume(struct dwc3 *dwc); 1518fc8bb91bSFelipe Balbi void dwc3_gadget_process_pending_events(struct dwc3 *dwc); 15197415f17cSFelipe Balbi #else 15207415f17cSFelipe Balbi static inline int dwc3_gadget_suspend(struct dwc3 *dwc) 15217415f17cSFelipe Balbi { 15227415f17cSFelipe Balbi return 0; 15237415f17cSFelipe Balbi } 15247415f17cSFelipe Balbi 15257415f17cSFelipe Balbi static inline int dwc3_gadget_resume(struct dwc3 *dwc) 15267415f17cSFelipe Balbi { 15277415f17cSFelipe Balbi return 0; 15287415f17cSFelipe Balbi } 1529fc8bb91bSFelipe Balbi 1530fc8bb91bSFelipe Balbi static inline void dwc3_gadget_process_pending_events(struct dwc3 *dwc) 1531fc8bb91bSFelipe Balbi { 1532fc8bb91bSFelipe Balbi } 15337415f17cSFelipe Balbi #endif /* !IS_ENABLED(CONFIG_USB_DWC3_HOST) */ 15347415f17cSFelipe Balbi 153588bc9d19SHeikki Krogerus #if IS_ENABLED(CONFIG_USB_DWC3_ULPI) 153688bc9d19SHeikki Krogerus int dwc3_ulpi_init(struct dwc3 *dwc); 153788bc9d19SHeikki Krogerus void dwc3_ulpi_exit(struct dwc3 *dwc); 153888bc9d19SHeikki Krogerus #else 153988bc9d19SHeikki Krogerus static inline int dwc3_ulpi_init(struct dwc3 *dwc) 154088bc9d19SHeikki Krogerus { return 0; } 154188bc9d19SHeikki Krogerus static inline void dwc3_ulpi_exit(struct dwc3 *dwc) 154288bc9d19SHeikki Krogerus { } 154388bc9d19SHeikki Krogerus #endif 154488bc9d19SHeikki Krogerus 154572246da4SFelipe Balbi #endif /* __DRIVERS_USB_DWC3_CORE_H */ 1546