15fd54aceSGreg Kroah-Hartman // SPDX-License-Identifier: GPL-2.0 2bfad65eeSFelipe Balbi /* 372246da4SFelipe Balbi * core.h - DesignWare USB3 DRD Core Header 472246da4SFelipe Balbi * 572246da4SFelipe Balbi * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com 672246da4SFelipe Balbi * 772246da4SFelipe Balbi * Authors: Felipe Balbi <balbi@ti.com>, 872246da4SFelipe Balbi * Sebastian Andrzej Siewior <bigeasy@linutronix.de> 972246da4SFelipe Balbi */ 1072246da4SFelipe Balbi 1172246da4SFelipe Balbi #ifndef __DRIVERS_USB_DWC3_CORE_H 1272246da4SFelipe Balbi #define __DRIVERS_USB_DWC3_CORE_H 1372246da4SFelipe Balbi 1472246da4SFelipe Balbi #include <linux/device.h> 1572246da4SFelipe Balbi #include <linux/spinlock.h> 16d07e8819SFelipe Balbi #include <linux/ioport.h> 1772246da4SFelipe Balbi #include <linux/list.h> 18ff3f0789SRoger Quadros #include <linux/bitops.h> 1972246da4SFelipe Balbi #include <linux/dma-mapping.h> 2072246da4SFelipe Balbi #include <linux/mm.h> 2172246da4SFelipe Balbi #include <linux/debugfs.h> 2276a638f8SBaolin Wang #include <linux/wait.h> 2341ce1456SRoger Quadros #include <linux/workqueue.h> 2472246da4SFelipe Balbi 2572246da4SFelipe Balbi #include <linux/usb/ch9.h> 2672246da4SFelipe Balbi #include <linux/usb/gadget.h> 27a45c82b8SRuchika Kharwar #include <linux/usb/otg.h> 2888bc9d19SHeikki Krogerus #include <linux/ulpi/interface.h> 2972246da4SFelipe Balbi 3057303488SKishon Vijay Abraham I #include <linux/phy/phy.h> 3157303488SKishon Vijay Abraham I 322c4cbe6eSFelipe Balbi #define DWC3_MSG_MAX 500 332c4cbe6eSFelipe Balbi 3472246da4SFelipe Balbi /* Global constants */ 35bb014736SBaolin Wang #define DWC3_PULL_UP_TIMEOUT 500 /* ms */ 36905dc04eSFelipe Balbi #define DWC3_BOUNCE_SIZE 1024 /* size of a superspeed bulk */ 374199c5f8SFelipe Balbi #define DWC3_EP0_SETUP_SIZE 512 3872246da4SFelipe Balbi #define DWC3_ENDPOINTS_NUM 32 3951249dcaSIdo Shayevitz #define DWC3_XHCI_RESOURCES_NUM 2 4072246da4SFelipe Balbi 410ffcaf37SFelipe Balbi #define DWC3_SCRATCHBUF_SIZE 4096 /* each buffer is assumed to be 4KiB */ 42e71d363dSFelipe Balbi #define DWC3_EVENT_BUFFERS_SIZE 4096 4372246da4SFelipe Balbi #define DWC3_EVENT_TYPE_MASK 0xfe 4472246da4SFelipe Balbi 4572246da4SFelipe Balbi #define DWC3_EVENT_TYPE_DEV 0 4672246da4SFelipe Balbi #define DWC3_EVENT_TYPE_CARKIT 3 4772246da4SFelipe Balbi #define DWC3_EVENT_TYPE_I2C 4 4872246da4SFelipe Balbi 4972246da4SFelipe Balbi #define DWC3_DEVICE_EVENT_DISCONNECT 0 5072246da4SFelipe Balbi #define DWC3_DEVICE_EVENT_RESET 1 5172246da4SFelipe Balbi #define DWC3_DEVICE_EVENT_CONNECT_DONE 2 5272246da4SFelipe Balbi #define DWC3_DEVICE_EVENT_LINK_STATUS_CHANGE 3 5372246da4SFelipe Balbi #define DWC3_DEVICE_EVENT_WAKEUP 4 542c61a8efSPaul Zimmerman #define DWC3_DEVICE_EVENT_HIBER_REQ 5 5572246da4SFelipe Balbi #define DWC3_DEVICE_EVENT_EOPF 6 5672246da4SFelipe Balbi #define DWC3_DEVICE_EVENT_SOF 7 5772246da4SFelipe Balbi #define DWC3_DEVICE_EVENT_ERRATIC_ERROR 9 5872246da4SFelipe Balbi #define DWC3_DEVICE_EVENT_CMD_CMPL 10 5972246da4SFelipe Balbi #define DWC3_DEVICE_EVENT_OVERFLOW 11 6072246da4SFelipe Balbi 61*f09cc79bSRoger Quadros /* Controller's role while using the OTG block */ 62*f09cc79bSRoger Quadros #define DWC3_OTG_ROLE_IDLE 0 63*f09cc79bSRoger Quadros #define DWC3_OTG_ROLE_HOST 1 64*f09cc79bSRoger Quadros #define DWC3_OTG_ROLE_DEVICE 2 65*f09cc79bSRoger Quadros 6672246da4SFelipe Balbi #define DWC3_GEVNTCOUNT_MASK 0xfffc 67ff3f0789SRoger Quadros #define DWC3_GEVNTCOUNT_EHB BIT(31) 6872246da4SFelipe Balbi #define DWC3_GSNPSID_MASK 0xffff0000 6972246da4SFelipe Balbi #define DWC3_GSNPSREV_MASK 0xffff 7072246da4SFelipe Balbi 7151249dcaSIdo Shayevitz /* DWC3 registers memory space boundries */ 7251249dcaSIdo Shayevitz #define DWC3_XHCI_REGS_START 0x0 7351249dcaSIdo Shayevitz #define DWC3_XHCI_REGS_END 0x7fff 7451249dcaSIdo Shayevitz #define DWC3_GLOBALS_REGS_START 0xc100 7551249dcaSIdo Shayevitz #define DWC3_GLOBALS_REGS_END 0xc6ff 7651249dcaSIdo Shayevitz #define DWC3_DEVICE_REGS_START 0xc700 7751249dcaSIdo Shayevitz #define DWC3_DEVICE_REGS_END 0xcbff 7851249dcaSIdo Shayevitz #define DWC3_OTG_REGS_START 0xcc00 7951249dcaSIdo Shayevitz #define DWC3_OTG_REGS_END 0xccff 8051249dcaSIdo Shayevitz 8172246da4SFelipe Balbi /* Global Registers */ 8272246da4SFelipe Balbi #define DWC3_GSBUSCFG0 0xc100 8372246da4SFelipe Balbi #define DWC3_GSBUSCFG1 0xc104 8472246da4SFelipe Balbi #define DWC3_GTXTHRCFG 0xc108 8572246da4SFelipe Balbi #define DWC3_GRXTHRCFG 0xc10c 8672246da4SFelipe Balbi #define DWC3_GCTL 0xc110 8772246da4SFelipe Balbi #define DWC3_GEVTEN 0xc114 8872246da4SFelipe Balbi #define DWC3_GSTS 0xc118 89475c8bebSWilliam Wu #define DWC3_GUCTL1 0xc11c 9072246da4SFelipe Balbi #define DWC3_GSNPSID 0xc120 9172246da4SFelipe Balbi #define DWC3_GGPIO 0xc124 9272246da4SFelipe Balbi #define DWC3_GUID 0xc128 9372246da4SFelipe Balbi #define DWC3_GUCTL 0xc12c 9472246da4SFelipe Balbi #define DWC3_GBUSERRADDR0 0xc130 9572246da4SFelipe Balbi #define DWC3_GBUSERRADDR1 0xc134 9672246da4SFelipe Balbi #define DWC3_GPRTBIMAP0 0xc138 9772246da4SFelipe Balbi #define DWC3_GPRTBIMAP1 0xc13c 9872246da4SFelipe Balbi #define DWC3_GHWPARAMS0 0xc140 9972246da4SFelipe Balbi #define DWC3_GHWPARAMS1 0xc144 10072246da4SFelipe Balbi #define DWC3_GHWPARAMS2 0xc148 10172246da4SFelipe Balbi #define DWC3_GHWPARAMS3 0xc14c 10272246da4SFelipe Balbi #define DWC3_GHWPARAMS4 0xc150 10372246da4SFelipe Balbi #define DWC3_GHWPARAMS5 0xc154 10472246da4SFelipe Balbi #define DWC3_GHWPARAMS6 0xc158 10572246da4SFelipe Balbi #define DWC3_GHWPARAMS7 0xc15c 10672246da4SFelipe Balbi #define DWC3_GDBGFIFOSPACE 0xc160 10772246da4SFelipe Balbi #define DWC3_GDBGLTSSM 0xc164 10872246da4SFelipe Balbi #define DWC3_GPRTBIMAP_HS0 0xc180 10972246da4SFelipe Balbi #define DWC3_GPRTBIMAP_HS1 0xc184 11072246da4SFelipe Balbi #define DWC3_GPRTBIMAP_FS0 0xc188 11172246da4SFelipe Balbi #define DWC3_GPRTBIMAP_FS1 0xc18c 11206281d46SJohn Youn #define DWC3_GUCTL2 0xc19c 11372246da4SFelipe Balbi 114690fb371SJohn Youn #define DWC3_VER_NUMBER 0xc1a0 115690fb371SJohn Youn #define DWC3_VER_TYPE 0xc1a4 116690fb371SJohn Youn 1178261bd4eSRoger Quadros #define DWC3_GUSB2PHYCFG(n) (0xc200 + ((n) * 0x04)) 1188261bd4eSRoger Quadros #define DWC3_GUSB2I2CCTL(n) (0xc240 + ((n) * 0x04)) 11972246da4SFelipe Balbi 1208261bd4eSRoger Quadros #define DWC3_GUSB2PHYACC(n) (0xc280 + ((n) * 0x04)) 12172246da4SFelipe Balbi 1228261bd4eSRoger Quadros #define DWC3_GUSB3PIPECTL(n) (0xc2c0 + ((n) * 0x04)) 12372246da4SFelipe Balbi 1248261bd4eSRoger Quadros #define DWC3_GTXFIFOSIZ(n) (0xc300 + ((n) * 0x04)) 1258261bd4eSRoger Quadros #define DWC3_GRXFIFOSIZ(n) (0xc380 + ((n) * 0x04)) 12672246da4SFelipe Balbi 1278261bd4eSRoger Quadros #define DWC3_GEVNTADRLO(n) (0xc400 + ((n) * 0x10)) 1288261bd4eSRoger Quadros #define DWC3_GEVNTADRHI(n) (0xc404 + ((n) * 0x10)) 1298261bd4eSRoger Quadros #define DWC3_GEVNTSIZ(n) (0xc408 + ((n) * 0x10)) 1308261bd4eSRoger Quadros #define DWC3_GEVNTCOUNT(n) (0xc40c + ((n) * 0x10)) 13172246da4SFelipe Balbi 13272246da4SFelipe Balbi #define DWC3_GHWPARAMS8 0xc600 133db2be4e9SNikhil Badola #define DWC3_GFLADJ 0xc630 13472246da4SFelipe Balbi 13572246da4SFelipe Balbi /* Device Registers */ 13672246da4SFelipe Balbi #define DWC3_DCFG 0xc700 13772246da4SFelipe Balbi #define DWC3_DCTL 0xc704 13872246da4SFelipe Balbi #define DWC3_DEVTEN 0xc708 13972246da4SFelipe Balbi #define DWC3_DSTS 0xc70c 14072246da4SFelipe Balbi #define DWC3_DGCMDPAR 0xc710 14172246da4SFelipe Balbi #define DWC3_DGCMD 0xc714 14272246da4SFelipe Balbi #define DWC3_DALEPENA 0xc720 1432eb88016SFelipe Balbi 1448261bd4eSRoger Quadros #define DWC3_DEP_BASE(n) (0xc800 + ((n) * 0x10)) 1452eb88016SFelipe Balbi #define DWC3_DEPCMDPAR2 0x00 1462eb88016SFelipe Balbi #define DWC3_DEPCMDPAR1 0x04 1472eb88016SFelipe Balbi #define DWC3_DEPCMDPAR0 0x08 1482eb88016SFelipe Balbi #define DWC3_DEPCMD 0x0c 14972246da4SFelipe Balbi 1508261bd4eSRoger Quadros #define DWC3_DEV_IMOD(n) (0xca00 + ((n) * 0x4)) 151cf40b86bSJohn Youn 15272246da4SFelipe Balbi /* OTG Registers */ 15372246da4SFelipe Balbi #define DWC3_OCFG 0xcc00 15472246da4SFelipe Balbi #define DWC3_OCTL 0xcc04 155d4436c3aSGeorge Cherian #define DWC3_OEVT 0xcc08 156d4436c3aSGeorge Cherian #define DWC3_OEVTEN 0xcc0C 157d4436c3aSGeorge Cherian #define DWC3_OSTS 0xcc10 15872246da4SFelipe Balbi 15972246da4SFelipe Balbi /* Bit fields */ 16072246da4SFelipe Balbi 161cf6d867dSFelipe Balbi /* Global Debug Queue/FIFO Space Available Register */ 162cf6d867dSFelipe Balbi #define DWC3_GDBGFIFOSPACE_NUM(n) ((n) & 0x1f) 163cf6d867dSFelipe Balbi #define DWC3_GDBGFIFOSPACE_TYPE(n) (((n) << 5) & 0x1e0) 164cf6d867dSFelipe Balbi #define DWC3_GDBGFIFOSPACE_SPACE_AVAILABLE(n) (((n) >> 16) & 0xffff) 165cf6d867dSFelipe Balbi 166b16ea8b9SThinh Nguyen #define DWC3_TXFIFOQ 0 167b16ea8b9SThinh Nguyen #define DWC3_RXFIFOQ 1 168b16ea8b9SThinh Nguyen #define DWC3_TXREQQ 2 169b16ea8b9SThinh Nguyen #define DWC3_RXREQQ 3 170b16ea8b9SThinh Nguyen #define DWC3_RXINFOQ 4 171b16ea8b9SThinh Nguyen #define DWC3_PSTATQ 5 172b16ea8b9SThinh Nguyen #define DWC3_DESCFETCHQ 6 173b16ea8b9SThinh Nguyen #define DWC3_EVENTQ 7 174b16ea8b9SThinh Nguyen #define DWC3_AUXEVENTQ 8 175cf6d867dSFelipe Balbi 1762a58f9c1SFelipe Balbi /* Global RX Threshold Configuration Register */ 1772a58f9c1SFelipe Balbi #define DWC3_GRXTHRCFG_MAXRXBURSTSIZE(n) (((n) & 0x1f) << 19) 1782a58f9c1SFelipe Balbi #define DWC3_GRXTHRCFG_RXPKTCNT(n) (((n) & 0xf) << 24) 179ff3f0789SRoger Quadros #define DWC3_GRXTHRCFG_PKTCNTSEL BIT(29) 1802a58f9c1SFelipe Balbi 18172246da4SFelipe Balbi /* Global Configuration Register */ 1821d046793SPaul Zimmerman #define DWC3_GCTL_PWRDNSCALE(n) ((n) << 19) 183ff3f0789SRoger Quadros #define DWC3_GCTL_U2RSTECN BIT(16) 1841d046793SPaul Zimmerman #define DWC3_GCTL_RAMCLKSEL(x) (((x) & DWC3_GCTL_CLK_MASK) << 6) 18572246da4SFelipe Balbi #define DWC3_GCTL_CLK_BUS (0) 18672246da4SFelipe Balbi #define DWC3_GCTL_CLK_PIPE (1) 18772246da4SFelipe Balbi #define DWC3_GCTL_CLK_PIPEHALF (2) 18872246da4SFelipe Balbi #define DWC3_GCTL_CLK_MASK (3) 18972246da4SFelipe Balbi 1900b9fe32dSFelipe Balbi #define DWC3_GCTL_PRTCAP(n) (((n) & (3 << 12)) >> 12) 1911d046793SPaul Zimmerman #define DWC3_GCTL_PRTCAPDIR(n) ((n) << 12) 19272246da4SFelipe Balbi #define DWC3_GCTL_PRTCAP_HOST 1 19372246da4SFelipe Balbi #define DWC3_GCTL_PRTCAP_DEVICE 2 19472246da4SFelipe Balbi #define DWC3_GCTL_PRTCAP_OTG 3 19572246da4SFelipe Balbi 196ff3f0789SRoger Quadros #define DWC3_GCTL_CORESOFTRESET BIT(11) 197ff3f0789SRoger Quadros #define DWC3_GCTL_SOFITPSYNC BIT(10) 1981d046793SPaul Zimmerman #define DWC3_GCTL_SCALEDOWN(n) ((n) << 4) 1993e87c42aSPaul Zimmerman #define DWC3_GCTL_SCALEDOWN_MASK DWC3_GCTL_SCALEDOWN(3) 200ff3f0789SRoger Quadros #define DWC3_GCTL_DISSCRAMBLE BIT(3) 201ff3f0789SRoger Quadros #define DWC3_GCTL_U2EXIT_LFPS BIT(2) 202ff3f0789SRoger Quadros #define DWC3_GCTL_GBLHIBERNATIONEN BIT(1) 203ff3f0789SRoger Quadros #define DWC3_GCTL_DSBLCLKGTNG BIT(0) 20472246da4SFelipe Balbi 2050bb39ca1SJohn Youn /* Global User Control 1 Register */ 20665db7a0cSWilliam Wu #define DWC3_GUCTL1_TX_IPGAP_LINECHECK_DIS BIT(28) 207ff3f0789SRoger Quadros #define DWC3_GUCTL1_DEV_L1_EXIT_BY_HW BIT(24) 2080bb39ca1SJohn Youn 2094cff75c7SRoger Quadros /* Global Status Register */ 2104cff75c7SRoger Quadros #define DWC3_GSTS_OTG_IP BIT(10) 2114cff75c7SRoger Quadros #define DWC3_GSTS_BC_IP BIT(9) 2124cff75c7SRoger Quadros #define DWC3_GSTS_ADP_IP BIT(8) 2134cff75c7SRoger Quadros #define DWC3_GSTS_HOST_IP BIT(7) 2144cff75c7SRoger Quadros #define DWC3_GSTS_DEVICE_IP BIT(6) 2154cff75c7SRoger Quadros #define DWC3_GSTS_CSR_TIMEOUT BIT(5) 2164cff75c7SRoger Quadros #define DWC3_GSTS_BUS_ERR_ADDR_VLD BIT(4) 2174cff75c7SRoger Quadros 21872246da4SFelipe Balbi /* Global USB2 PHY Configuration Register */ 219ff3f0789SRoger Quadros #define DWC3_GUSB2PHYCFG_PHYSOFTRST BIT(31) 220ff3f0789SRoger Quadros #define DWC3_GUSB2PHYCFG_U2_FREECLK_EXISTS BIT(30) 221ff3f0789SRoger Quadros #define DWC3_GUSB2PHYCFG_SUSPHY BIT(6) 222ff3f0789SRoger Quadros #define DWC3_GUSB2PHYCFG_ULPI_UTMI BIT(4) 223ff3f0789SRoger Quadros #define DWC3_GUSB2PHYCFG_ENBLSLPM BIT(8) 22432f2ed86SWilliam Wu #define DWC3_GUSB2PHYCFG_PHYIF(n) (n << 3) 22532f2ed86SWilliam Wu #define DWC3_GUSB2PHYCFG_PHYIF_MASK DWC3_GUSB2PHYCFG_PHYIF(1) 22632f2ed86SWilliam Wu #define DWC3_GUSB2PHYCFG_USBTRDTIM(n) (n << 10) 22732f2ed86SWilliam Wu #define DWC3_GUSB2PHYCFG_USBTRDTIM_MASK DWC3_GUSB2PHYCFG_USBTRDTIM(0xf) 22832f2ed86SWilliam Wu #define USBTRDTIM_UTMI_8_BIT 9 22932f2ed86SWilliam Wu #define USBTRDTIM_UTMI_16_BIT 5 23032f2ed86SWilliam Wu #define UTMI_PHYIF_16_BIT 1 23132f2ed86SWilliam Wu #define UTMI_PHYIF_8_BIT 0 23272246da4SFelipe Balbi 233b5699eeeSHeikki Krogerus /* Global USB2 PHY Vendor Control Register */ 234ff3f0789SRoger Quadros #define DWC3_GUSB2PHYACC_NEWREGREQ BIT(25) 235ff3f0789SRoger Quadros #define DWC3_GUSB2PHYACC_BUSY BIT(23) 236ff3f0789SRoger Quadros #define DWC3_GUSB2PHYACC_WRITE BIT(22) 237b5699eeeSHeikki Krogerus #define DWC3_GUSB2PHYACC_ADDR(n) (n << 16) 238b5699eeeSHeikki Krogerus #define DWC3_GUSB2PHYACC_EXTEND_ADDR(n) (n << 8) 239b5699eeeSHeikki Krogerus #define DWC3_GUSB2PHYACC_DATA(n) (n & 0xff) 240b5699eeeSHeikki Krogerus 24172246da4SFelipe Balbi /* Global USB3 PIPE Control Register */ 242ff3f0789SRoger Quadros #define DWC3_GUSB3PIPECTL_PHYSOFTRST BIT(31) 243ff3f0789SRoger Quadros #define DWC3_GUSB3PIPECTL_U2SSINP3OK BIT(29) 244ff3f0789SRoger Quadros #define DWC3_GUSB3PIPECTL_DISRXDETINP3 BIT(28) 245ff3f0789SRoger Quadros #define DWC3_GUSB3PIPECTL_UX_EXIT_PX BIT(27) 246ff3f0789SRoger Quadros #define DWC3_GUSB3PIPECTL_REQP1P2P3 BIT(24) 247a2a1d0f5SHuang Rui #define DWC3_GUSB3PIPECTL_DEP1P2P3(n) ((n) << 19) 248a2a1d0f5SHuang Rui #define DWC3_GUSB3PIPECTL_DEP1P2P3_MASK DWC3_GUSB3PIPECTL_DEP1P2P3(7) 249a2a1d0f5SHuang Rui #define DWC3_GUSB3PIPECTL_DEP1P2P3_EN DWC3_GUSB3PIPECTL_DEP1P2P3(1) 250ff3f0789SRoger Quadros #define DWC3_GUSB3PIPECTL_DEPOCHANGE BIT(18) 251ff3f0789SRoger Quadros #define DWC3_GUSB3PIPECTL_SUSPHY BIT(17) 252ff3f0789SRoger Quadros #define DWC3_GUSB3PIPECTL_LFPSFILT BIT(9) 253ff3f0789SRoger Quadros #define DWC3_GUSB3PIPECTL_RX_DETOPOLL BIT(8) 2546b6a0c9aSHuang Rui #define DWC3_GUSB3PIPECTL_TX_DEEPH_MASK DWC3_GUSB3PIPECTL_TX_DEEPH(3) 2556b6a0c9aSHuang Rui #define DWC3_GUSB3PIPECTL_TX_DEEPH(n) ((n) << 1) 25672246da4SFelipe Balbi 257457e84b6SFelipe Balbi /* Global TX Fifo Size Register */ 258457e84b6SFelipe Balbi #define DWC3_GTXFIFOSIZ_TXFDEF(n) ((n) & 0xffff) 259457e84b6SFelipe Balbi #define DWC3_GTXFIFOSIZ_TXFSTADDR(n) ((n) & 0xffff0000) 260457e84b6SFelipe Balbi 26168d6a01bSFelipe Balbi /* Global Event Size Registers */ 262ff3f0789SRoger Quadros #define DWC3_GEVNTSIZ_INTMASK BIT(31) 26368d6a01bSFelipe Balbi #define DWC3_GEVNTSIZ_SIZE(n) ((n) & 0xffff) 26468d6a01bSFelipe Balbi 2654e99472bSFelipe Balbi /* Global HWPARAMS0 Register */ 2669d6173e1SThinh Nguyen #define DWC3_GHWPARAMS0_MODE(n) ((n) & 0x3) 2679d6173e1SThinh Nguyen #define DWC3_GHWPARAMS0_MODE_GADGET 0 2689d6173e1SThinh Nguyen #define DWC3_GHWPARAMS0_MODE_HOST 1 2699d6173e1SThinh Nguyen #define DWC3_GHWPARAMS0_MODE_DRD 2 2704e99472bSFelipe Balbi #define DWC3_GHWPARAMS0_MBUS_TYPE(n) (((n) >> 3) & 0x7) 2714e99472bSFelipe Balbi #define DWC3_GHWPARAMS0_SBUS_TYPE(n) (((n) >> 6) & 0x3) 2724e99472bSFelipe Balbi #define DWC3_GHWPARAMS0_MDWIDTH(n) (((n) >> 8) & 0xff) 2734e99472bSFelipe Balbi #define DWC3_GHWPARAMS0_SDWIDTH(n) (((n) >> 16) & 0xff) 2744e99472bSFelipe Balbi #define DWC3_GHWPARAMS0_AWIDTH(n) (((n) >> 24) & 0xff) 2754e99472bSFelipe Balbi 276aabb7075SFelipe Balbi /* Global HWPARAMS1 Register */ 2771d046793SPaul Zimmerman #define DWC3_GHWPARAMS1_EN_PWROPT(n) (((n) & (3 << 24)) >> 24) 278aabb7075SFelipe Balbi #define DWC3_GHWPARAMS1_EN_PWROPT_NO 0 279aabb7075SFelipe Balbi #define DWC3_GHWPARAMS1_EN_PWROPT_CLK 1 2802c61a8efSPaul Zimmerman #define DWC3_GHWPARAMS1_EN_PWROPT_HIB 2 2812c61a8efSPaul Zimmerman #define DWC3_GHWPARAMS1_PWROPT(n) ((n) << 24) 2822c61a8efSPaul Zimmerman #define DWC3_GHWPARAMS1_PWROPT_MASK DWC3_GHWPARAMS1_PWROPT(3) 2832c61a8efSPaul Zimmerman 2840e1e5c47SPaul Zimmerman /* Global HWPARAMS3 Register */ 2850e1e5c47SPaul Zimmerman #define DWC3_GHWPARAMS3_SSPHY_IFC(n) ((n) & 3) 2860e1e5c47SPaul Zimmerman #define DWC3_GHWPARAMS3_SSPHY_IFC_DIS 0 2871f38f88aSJohn Youn #define DWC3_GHWPARAMS3_SSPHY_IFC_GEN1 1 2881f38f88aSJohn Youn #define DWC3_GHWPARAMS3_SSPHY_IFC_GEN2 2 /* DWC_usb31 only */ 2890e1e5c47SPaul Zimmerman #define DWC3_GHWPARAMS3_HSPHY_IFC(n) (((n) & (3 << 2)) >> 2) 2900e1e5c47SPaul Zimmerman #define DWC3_GHWPARAMS3_HSPHY_IFC_DIS 0 2910e1e5c47SPaul Zimmerman #define DWC3_GHWPARAMS3_HSPHY_IFC_UTMI 1 2920e1e5c47SPaul Zimmerman #define DWC3_GHWPARAMS3_HSPHY_IFC_ULPI 2 2930e1e5c47SPaul Zimmerman #define DWC3_GHWPARAMS3_HSPHY_IFC_UTMI_ULPI 3 2940e1e5c47SPaul Zimmerman #define DWC3_GHWPARAMS3_FSPHY_IFC(n) (((n) & (3 << 4)) >> 4) 2950e1e5c47SPaul Zimmerman #define DWC3_GHWPARAMS3_FSPHY_IFC_DIS 0 2960e1e5c47SPaul Zimmerman #define DWC3_GHWPARAMS3_FSPHY_IFC_ENA 1 2970e1e5c47SPaul Zimmerman 2982c61a8efSPaul Zimmerman /* Global HWPARAMS4 Register */ 2992c61a8efSPaul Zimmerman #define DWC3_GHWPARAMS4_HIBER_SCRATCHBUFS(n) (((n) & (0x0f << 13)) >> 13) 3002c61a8efSPaul Zimmerman #define DWC3_MAX_HIBER_SCRATCHBUFS 15 301aabb7075SFelipe Balbi 302946bd579SHuang Rui /* Global HWPARAMS6 Register */ 3034cff75c7SRoger Quadros #define DWC3_GHWPARAMS6_BCSUPPORT BIT(14) 3044cff75c7SRoger Quadros #define DWC3_GHWPARAMS6_OTG3SUPPORT BIT(13) 3054cff75c7SRoger Quadros #define DWC3_GHWPARAMS6_ADPSUPPORT BIT(12) 3064cff75c7SRoger Quadros #define DWC3_GHWPARAMS6_HNPSUPPORT BIT(11) 3074cff75c7SRoger Quadros #define DWC3_GHWPARAMS6_SRPSUPPORT BIT(10) 308ff3f0789SRoger Quadros #define DWC3_GHWPARAMS6_EN_FPGA BIT(7) 309946bd579SHuang Rui 3104e99472bSFelipe Balbi /* Global HWPARAMS7 Register */ 3114e99472bSFelipe Balbi #define DWC3_GHWPARAMS7_RAM1_DEPTH(n) ((n) & 0xffff) 3124e99472bSFelipe Balbi #define DWC3_GHWPARAMS7_RAM2_DEPTH(n) (((n) >> 16) & 0xffff) 3134e99472bSFelipe Balbi 314db2be4e9SNikhil Badola /* Global Frame Length Adjustment Register */ 315ff3f0789SRoger Quadros #define DWC3_GFLADJ_30MHZ_SDBND_SEL BIT(7) 316db2be4e9SNikhil Badola #define DWC3_GFLADJ_30MHZ_MASK 0x3f 317db2be4e9SNikhil Badola 31806281d46SJohn Youn /* Global User Control Register 2 */ 319ff3f0789SRoger Quadros #define DWC3_GUCTL2_RST_ACTBITLATER BIT(14) 32006281d46SJohn Youn 32172246da4SFelipe Balbi /* Device Configuration Register */ 32272246da4SFelipe Balbi #define DWC3_DCFG_DEVADDR(addr) ((addr) << 3) 32372246da4SFelipe Balbi #define DWC3_DCFG_DEVADDR_MASK DWC3_DCFG_DEVADDR(0x7f) 32472246da4SFelipe Balbi 32572246da4SFelipe Balbi #define DWC3_DCFG_SPEED_MASK (7 << 0) 3261f38f88aSJohn Youn #define DWC3_DCFG_SUPERSPEED_PLUS (5 << 0) /* DWC_usb31 only */ 32772246da4SFelipe Balbi #define DWC3_DCFG_SUPERSPEED (4 << 0) 32872246da4SFelipe Balbi #define DWC3_DCFG_HIGHSPEED (0 << 0) 329ff3f0789SRoger Quadros #define DWC3_DCFG_FULLSPEED BIT(0) 33072246da4SFelipe Balbi #define DWC3_DCFG_LOWSPEED (2 << 0) 33172246da4SFelipe Balbi 332676e3497SFelipe Balbi #define DWC3_DCFG_NUMP_SHIFT 17 33397398612SDan Carpenter #define DWC3_DCFG_NUMP(n) (((n) >> DWC3_DCFG_NUMP_SHIFT) & 0x1f) 334676e3497SFelipe Balbi #define DWC3_DCFG_NUMP_MASK (0x1f << DWC3_DCFG_NUMP_SHIFT) 335ff3f0789SRoger Quadros #define DWC3_DCFG_LPM_CAP BIT(22) 3362c61a8efSPaul Zimmerman 33772246da4SFelipe Balbi /* Device Control Register */ 338ff3f0789SRoger Quadros #define DWC3_DCTL_RUN_STOP BIT(31) 339ff3f0789SRoger Quadros #define DWC3_DCTL_CSFTRST BIT(30) 340ff3f0789SRoger Quadros #define DWC3_DCTL_LSFTRST BIT(29) 34172246da4SFelipe Balbi 34272246da4SFelipe Balbi #define DWC3_DCTL_HIRD_THRES_MASK (0x1f << 24) 3437e39b817SPratyush Anand #define DWC3_DCTL_HIRD_THRES(n) ((n) << 24) 34472246da4SFelipe Balbi 345ff3f0789SRoger Quadros #define DWC3_DCTL_APPL1RES BIT(23) 34672246da4SFelipe Balbi 3472c61a8efSPaul Zimmerman /* These apply for core versions 1.87a and earlier */ 3488db7ed15SFelipe Balbi #define DWC3_DCTL_TRGTULST_MASK (0x0f << 17) 3498db7ed15SFelipe Balbi #define DWC3_DCTL_TRGTULST(n) ((n) << 17) 3508db7ed15SFelipe Balbi #define DWC3_DCTL_TRGTULST_U2 (DWC3_DCTL_TRGTULST(2)) 3518db7ed15SFelipe Balbi #define DWC3_DCTL_TRGTULST_U3 (DWC3_DCTL_TRGTULST(3)) 3528db7ed15SFelipe Balbi #define DWC3_DCTL_TRGTULST_SS_DIS (DWC3_DCTL_TRGTULST(4)) 3538db7ed15SFelipe Balbi #define DWC3_DCTL_TRGTULST_RX_DET (DWC3_DCTL_TRGTULST(5)) 3548db7ed15SFelipe Balbi #define DWC3_DCTL_TRGTULST_SS_INACT (DWC3_DCTL_TRGTULST(6)) 3558db7ed15SFelipe Balbi 3562c61a8efSPaul Zimmerman /* These apply for core versions 1.94a and later */ 35780caf7d2SHuang Rui #define DWC3_DCTL_LPM_ERRATA_MASK DWC3_DCTL_LPM_ERRATA(0xf) 35880caf7d2SHuang Rui #define DWC3_DCTL_LPM_ERRATA(n) ((n) << 20) 35980caf7d2SHuang Rui 360ff3f0789SRoger Quadros #define DWC3_DCTL_KEEP_CONNECT BIT(19) 361ff3f0789SRoger Quadros #define DWC3_DCTL_L1_HIBER_EN BIT(18) 362ff3f0789SRoger Quadros #define DWC3_DCTL_CRS BIT(17) 363ff3f0789SRoger Quadros #define DWC3_DCTL_CSS BIT(16) 3642c61a8efSPaul Zimmerman 365ff3f0789SRoger Quadros #define DWC3_DCTL_INITU2ENA BIT(12) 366ff3f0789SRoger Quadros #define DWC3_DCTL_ACCEPTU2ENA BIT(11) 367ff3f0789SRoger Quadros #define DWC3_DCTL_INITU1ENA BIT(10) 368ff3f0789SRoger Quadros #define DWC3_DCTL_ACCEPTU1ENA BIT(9) 36972246da4SFelipe Balbi #define DWC3_DCTL_TSTCTRL_MASK (0xf << 1) 37072246da4SFelipe Balbi 37172246da4SFelipe Balbi #define DWC3_DCTL_ULSTCHNGREQ_MASK (0x0f << 5) 37272246da4SFelipe Balbi #define DWC3_DCTL_ULSTCHNGREQ(n) (((n) << 5) & DWC3_DCTL_ULSTCHNGREQ_MASK) 37372246da4SFelipe Balbi 37472246da4SFelipe Balbi #define DWC3_DCTL_ULSTCHNG_NO_ACTION (DWC3_DCTL_ULSTCHNGREQ(0)) 37572246da4SFelipe Balbi #define DWC3_DCTL_ULSTCHNG_SS_DISABLED (DWC3_DCTL_ULSTCHNGREQ(4)) 37672246da4SFelipe Balbi #define DWC3_DCTL_ULSTCHNG_RX_DETECT (DWC3_DCTL_ULSTCHNGREQ(5)) 37772246da4SFelipe Balbi #define DWC3_DCTL_ULSTCHNG_SS_INACTIVE (DWC3_DCTL_ULSTCHNGREQ(6)) 37872246da4SFelipe Balbi #define DWC3_DCTL_ULSTCHNG_RECOVERY (DWC3_DCTL_ULSTCHNGREQ(8)) 37972246da4SFelipe Balbi #define DWC3_DCTL_ULSTCHNG_COMPLIANCE (DWC3_DCTL_ULSTCHNGREQ(10)) 38072246da4SFelipe Balbi #define DWC3_DCTL_ULSTCHNG_LOOPBACK (DWC3_DCTL_ULSTCHNGREQ(11)) 38172246da4SFelipe Balbi 38272246da4SFelipe Balbi /* Device Event Enable Register */ 383ff3f0789SRoger Quadros #define DWC3_DEVTEN_VNDRDEVTSTRCVEDEN BIT(12) 384ff3f0789SRoger Quadros #define DWC3_DEVTEN_EVNTOVERFLOWEN BIT(11) 385ff3f0789SRoger Quadros #define DWC3_DEVTEN_CMDCMPLTEN BIT(10) 386ff3f0789SRoger Quadros #define DWC3_DEVTEN_ERRTICERREN BIT(9) 387ff3f0789SRoger Quadros #define DWC3_DEVTEN_SOFEN BIT(7) 388ff3f0789SRoger Quadros #define DWC3_DEVTEN_EOPFEN BIT(6) 389ff3f0789SRoger Quadros #define DWC3_DEVTEN_HIBERNATIONREQEVTEN BIT(5) 390ff3f0789SRoger Quadros #define DWC3_DEVTEN_WKUPEVTEN BIT(4) 391ff3f0789SRoger Quadros #define DWC3_DEVTEN_ULSTCNGEN BIT(3) 392ff3f0789SRoger Quadros #define DWC3_DEVTEN_CONNECTDONEEN BIT(2) 393ff3f0789SRoger Quadros #define DWC3_DEVTEN_USBRSTEN BIT(1) 394ff3f0789SRoger Quadros #define DWC3_DEVTEN_DISCONNEVTEN BIT(0) 39572246da4SFelipe Balbi 39672246da4SFelipe Balbi /* Device Status Register */ 397ff3f0789SRoger Quadros #define DWC3_DSTS_DCNRD BIT(29) 3982c61a8efSPaul Zimmerman 3992c61a8efSPaul Zimmerman /* This applies for core versions 1.87a and earlier */ 400ff3f0789SRoger Quadros #define DWC3_DSTS_PWRUPREQ BIT(24) 4012c61a8efSPaul Zimmerman 4022c61a8efSPaul Zimmerman /* These apply for core versions 1.94a and later */ 403ff3f0789SRoger Quadros #define DWC3_DSTS_RSS BIT(25) 404ff3f0789SRoger Quadros #define DWC3_DSTS_SSS BIT(24) 4052c61a8efSPaul Zimmerman 406ff3f0789SRoger Quadros #define DWC3_DSTS_COREIDLE BIT(23) 407ff3f0789SRoger Quadros #define DWC3_DSTS_DEVCTRLHLT BIT(22) 40872246da4SFelipe Balbi 40972246da4SFelipe Balbi #define DWC3_DSTS_USBLNKST_MASK (0x0f << 18) 41072246da4SFelipe Balbi #define DWC3_DSTS_USBLNKST(n) (((n) & DWC3_DSTS_USBLNKST_MASK) >> 18) 41172246da4SFelipe Balbi 412ff3f0789SRoger Quadros #define DWC3_DSTS_RXFIFOEMPTY BIT(17) 41372246da4SFelipe Balbi 414d05b8182SPratyush Anand #define DWC3_DSTS_SOFFN_MASK (0x3fff << 3) 41572246da4SFelipe Balbi #define DWC3_DSTS_SOFFN(n) (((n) & DWC3_DSTS_SOFFN_MASK) >> 3) 41672246da4SFelipe Balbi 41772246da4SFelipe Balbi #define DWC3_DSTS_CONNECTSPD (7 << 0) 41872246da4SFelipe Balbi 4191f38f88aSJohn Youn #define DWC3_DSTS_SUPERSPEED_PLUS (5 << 0) /* DWC_usb31 only */ 42072246da4SFelipe Balbi #define DWC3_DSTS_SUPERSPEED (4 << 0) 42172246da4SFelipe Balbi #define DWC3_DSTS_HIGHSPEED (0 << 0) 422ff3f0789SRoger Quadros #define DWC3_DSTS_FULLSPEED BIT(0) 42372246da4SFelipe Balbi #define DWC3_DSTS_LOWSPEED (2 << 0) 42472246da4SFelipe Balbi 42572246da4SFelipe Balbi /* Device Generic Command Register */ 42672246da4SFelipe Balbi #define DWC3_DGCMD_SET_LMP 0x01 42772246da4SFelipe Balbi #define DWC3_DGCMD_SET_PERIODIC_PAR 0x02 42872246da4SFelipe Balbi #define DWC3_DGCMD_XMIT_FUNCTION 0x03 4292c61a8efSPaul Zimmerman 4302c61a8efSPaul Zimmerman /* These apply for core versions 1.94a and later */ 4312c61a8efSPaul Zimmerman #define DWC3_DGCMD_SET_SCRATCHPAD_ADDR_LO 0x04 4322c61a8efSPaul Zimmerman #define DWC3_DGCMD_SET_SCRATCHPAD_ADDR_HI 0x05 4332c61a8efSPaul Zimmerman 43472246da4SFelipe Balbi #define DWC3_DGCMD_SELECTED_FIFO_FLUSH 0x09 43572246da4SFelipe Balbi #define DWC3_DGCMD_ALL_FIFO_FLUSH 0x0a 43672246da4SFelipe Balbi #define DWC3_DGCMD_SET_ENDPOINT_NRDY 0x0c 43772246da4SFelipe Balbi #define DWC3_DGCMD_RUN_SOC_BUS_LOOPBACK 0x10 43872246da4SFelipe Balbi 439459e210cSSubbaraya Sundeep Bhatta #define DWC3_DGCMD_STATUS(n) (((n) >> 12) & 0x0F) 440ff3f0789SRoger Quadros #define DWC3_DGCMD_CMDACT BIT(10) 441ff3f0789SRoger Quadros #define DWC3_DGCMD_CMDIOC BIT(8) 4422c61a8efSPaul Zimmerman 4432c61a8efSPaul Zimmerman /* Device Generic Command Parameter Register */ 444ff3f0789SRoger Quadros #define DWC3_DGCMDPAR_FORCE_LINKPM_ACCEPT BIT(0) 4452c61a8efSPaul Zimmerman #define DWC3_DGCMDPAR_FIFO_NUM(n) ((n) << 0) 4462c61a8efSPaul Zimmerman #define DWC3_DGCMDPAR_RX_FIFO (0 << 5) 447ff3f0789SRoger Quadros #define DWC3_DGCMDPAR_TX_FIFO BIT(5) 4482c61a8efSPaul Zimmerman #define DWC3_DGCMDPAR_LOOPBACK_DIS (0 << 0) 449ff3f0789SRoger Quadros #define DWC3_DGCMDPAR_LOOPBACK_ENA BIT(0) 450b09bb642SFelipe Balbi 45172246da4SFelipe Balbi /* Device Endpoint Command Register */ 45272246da4SFelipe Balbi #define DWC3_DEPCMD_PARAM_SHIFT 16 4531d046793SPaul Zimmerman #define DWC3_DEPCMD_PARAM(x) ((x) << DWC3_DEPCMD_PARAM_SHIFT) 4541d046793SPaul Zimmerman #define DWC3_DEPCMD_GET_RSC_IDX(x) (((x) >> DWC3_DEPCMD_PARAM_SHIFT) & 0x7f) 455459e210cSSubbaraya Sundeep Bhatta #define DWC3_DEPCMD_STATUS(x) (((x) >> 12) & 0x0F) 456ff3f0789SRoger Quadros #define DWC3_DEPCMD_HIPRI_FORCERM BIT(11) 457ff3f0789SRoger Quadros #define DWC3_DEPCMD_CLEARPENDIN BIT(11) 458ff3f0789SRoger Quadros #define DWC3_DEPCMD_CMDACT BIT(10) 459ff3f0789SRoger Quadros #define DWC3_DEPCMD_CMDIOC BIT(8) 46072246da4SFelipe Balbi 46172246da4SFelipe Balbi #define DWC3_DEPCMD_DEPSTARTCFG (0x09 << 0) 46272246da4SFelipe Balbi #define DWC3_DEPCMD_ENDTRANSFER (0x08 << 0) 46372246da4SFelipe Balbi #define DWC3_DEPCMD_UPDATETRANSFER (0x07 << 0) 46472246da4SFelipe Balbi #define DWC3_DEPCMD_STARTTRANSFER (0x06 << 0) 46572246da4SFelipe Balbi #define DWC3_DEPCMD_CLEARSTALL (0x05 << 0) 46672246da4SFelipe Balbi #define DWC3_DEPCMD_SETSTALL (0x04 << 0) 4672c61a8efSPaul Zimmerman /* This applies for core versions 1.90a and earlier */ 46872246da4SFelipe Balbi #define DWC3_DEPCMD_GETSEQNUMBER (0x03 << 0) 4692c61a8efSPaul Zimmerman /* This applies for core versions 1.94a and later */ 4702c61a8efSPaul Zimmerman #define DWC3_DEPCMD_GETEPSTATE (0x03 << 0) 47172246da4SFelipe Balbi #define DWC3_DEPCMD_SETTRANSFRESOURCE (0x02 << 0) 47272246da4SFelipe Balbi #define DWC3_DEPCMD_SETEPCONFIG (0x01 << 0) 47372246da4SFelipe Balbi 4745999914fSFelipe Balbi #define DWC3_DEPCMD_CMD(x) ((x) & 0xf) 4755999914fSFelipe Balbi 47672246da4SFelipe Balbi /* The EP number goes 0..31 so ep0 is always out and ep1 is always in */ 477ff3f0789SRoger Quadros #define DWC3_DALEPENA_EP(n) BIT(n) 47872246da4SFelipe Balbi 47972246da4SFelipe Balbi #define DWC3_DEPCMD_TYPE_CONTROL 0 48072246da4SFelipe Balbi #define DWC3_DEPCMD_TYPE_ISOC 1 48172246da4SFelipe Balbi #define DWC3_DEPCMD_TYPE_BULK 2 48272246da4SFelipe Balbi #define DWC3_DEPCMD_TYPE_INTR 3 48372246da4SFelipe Balbi 484cf40b86bSJohn Youn #define DWC3_DEV_IMOD_COUNT_SHIFT 16 485cf40b86bSJohn Youn #define DWC3_DEV_IMOD_COUNT_MASK (0xffff << 16) 486cf40b86bSJohn Youn #define DWC3_DEV_IMOD_INTERVAL_SHIFT 0 487cf40b86bSJohn Youn #define DWC3_DEV_IMOD_INTERVAL_MASK (0xffff << 0) 488cf40b86bSJohn Youn 4894cff75c7SRoger Quadros /* OTG Configuration Register */ 4904cff75c7SRoger Quadros #define DWC3_OCFG_DISPWRCUTTOFF BIT(5) 4914cff75c7SRoger Quadros #define DWC3_OCFG_HIBDISMASK BIT(4) 4924cff75c7SRoger Quadros #define DWC3_OCFG_SFTRSTMASK BIT(3) 4934cff75c7SRoger Quadros #define DWC3_OCFG_OTGVERSION BIT(2) 4944cff75c7SRoger Quadros #define DWC3_OCFG_HNPCAP BIT(1) 4954cff75c7SRoger Quadros #define DWC3_OCFG_SRPCAP BIT(0) 4964cff75c7SRoger Quadros 4974cff75c7SRoger Quadros /* OTG CTL Register */ 4984cff75c7SRoger Quadros #define DWC3_OCTL_OTG3GOERR BIT(7) 4994cff75c7SRoger Quadros #define DWC3_OCTL_PERIMODE BIT(6) 5004cff75c7SRoger Quadros #define DWC3_OCTL_PRTPWRCTL BIT(5) 5014cff75c7SRoger Quadros #define DWC3_OCTL_HNPREQ BIT(4) 5024cff75c7SRoger Quadros #define DWC3_OCTL_SESREQ BIT(3) 5034cff75c7SRoger Quadros #define DWC3_OCTL_TERMSELIDPULSE BIT(2) 5044cff75c7SRoger Quadros #define DWC3_OCTL_DEVSETHNPEN BIT(1) 5054cff75c7SRoger Quadros #define DWC3_OCTL_HSTSETHNPEN BIT(0) 5064cff75c7SRoger Quadros 5074cff75c7SRoger Quadros /* OTG Event Register */ 5084cff75c7SRoger Quadros #define DWC3_OEVT_DEVICEMODE BIT(31) 5094cff75c7SRoger Quadros #define DWC3_OEVT_XHCIRUNSTPSET BIT(27) 5104cff75c7SRoger Quadros #define DWC3_OEVT_DEVRUNSTPSET BIT(26) 5114cff75c7SRoger Quadros #define DWC3_OEVT_HIBENTRY BIT(25) 5124cff75c7SRoger Quadros #define DWC3_OEVT_CONIDSTSCHNG BIT(24) 5134cff75c7SRoger Quadros #define DWC3_OEVT_HRRCONFNOTIF BIT(23) 5144cff75c7SRoger Quadros #define DWC3_OEVT_HRRINITNOTIF BIT(22) 5154cff75c7SRoger Quadros #define DWC3_OEVT_ADEVIDLE BIT(21) 5164cff75c7SRoger Quadros #define DWC3_OEVT_ADEVBHOSTEND BIT(20) 5174cff75c7SRoger Quadros #define DWC3_OEVT_ADEVHOST BIT(19) 5184cff75c7SRoger Quadros #define DWC3_OEVT_ADEVHNPCHNG BIT(18) 5194cff75c7SRoger Quadros #define DWC3_OEVT_ADEVSRPDET BIT(17) 5204cff75c7SRoger Quadros #define DWC3_OEVT_ADEVSESSENDDET BIT(16) 5214cff75c7SRoger Quadros #define DWC3_OEVT_BDEVBHOSTEND BIT(11) 5224cff75c7SRoger Quadros #define DWC3_OEVT_BDEVHNPCHNG BIT(10) 5234cff75c7SRoger Quadros #define DWC3_OEVT_BDEVSESSVLDDET BIT(9) 5244cff75c7SRoger Quadros #define DWC3_OEVT_BDEVVBUSCHNG BIT(8) 5254cff75c7SRoger Quadros #define DWC3_OEVT_BSESSVLD BIT(3) 5264cff75c7SRoger Quadros #define DWC3_OEVT_HSTNEGSTS BIT(2) 5274cff75c7SRoger Quadros #define DWC3_OEVT_SESREQSTS BIT(1) 5284cff75c7SRoger Quadros #define DWC3_OEVT_ERROR BIT(0) 5294cff75c7SRoger Quadros 5304cff75c7SRoger Quadros /* OTG Event Enable Register */ 5314cff75c7SRoger Quadros #define DWC3_OEVTEN_XHCIRUNSTPSETEN BIT(27) 5324cff75c7SRoger Quadros #define DWC3_OEVTEN_DEVRUNSTPSETEN BIT(26) 5334cff75c7SRoger Quadros #define DWC3_OEVTEN_HIBENTRYEN BIT(25) 5344cff75c7SRoger Quadros #define DWC3_OEVTEN_CONIDSTSCHNGEN BIT(24) 5354cff75c7SRoger Quadros #define DWC3_OEVTEN_HRRCONFNOTIFEN BIT(23) 5364cff75c7SRoger Quadros #define DWC3_OEVTEN_HRRINITNOTIFEN BIT(22) 5374cff75c7SRoger Quadros #define DWC3_OEVTEN_ADEVIDLEEN BIT(21) 5384cff75c7SRoger Quadros #define DWC3_OEVTEN_ADEVBHOSTENDEN BIT(20) 5394cff75c7SRoger Quadros #define DWC3_OEVTEN_ADEVHOSTEN BIT(19) 5404cff75c7SRoger Quadros #define DWC3_OEVTEN_ADEVHNPCHNGEN BIT(18) 5414cff75c7SRoger Quadros #define DWC3_OEVTEN_ADEVSRPDETEN BIT(17) 5424cff75c7SRoger Quadros #define DWC3_OEVTEN_ADEVSESSENDDETEN BIT(16) 5434cff75c7SRoger Quadros #define DWC3_OEVTEN_BDEVBHOSTENDEN BIT(11) 5444cff75c7SRoger Quadros #define DWC3_OEVTEN_BDEVHNPCHNGEN BIT(10) 5454cff75c7SRoger Quadros #define DWC3_OEVTEN_BDEVSESSVLDDETEN BIT(9) 5464cff75c7SRoger Quadros #define DWC3_OEVTEN_BDEVVBUSCHNGEN BIT(8) 5474cff75c7SRoger Quadros 5484cff75c7SRoger Quadros /* OTG Status Register */ 5494cff75c7SRoger Quadros #define DWC3_OSTS_DEVRUNSTP BIT(13) 5504cff75c7SRoger Quadros #define DWC3_OSTS_XHCIRUNSTP BIT(12) 5514cff75c7SRoger Quadros #define DWC3_OSTS_PERIPHERALSTATE BIT(4) 5524cff75c7SRoger Quadros #define DWC3_OSTS_XHCIPRTPOWER BIT(3) 5534cff75c7SRoger Quadros #define DWC3_OSTS_BSESVLD BIT(2) 5544cff75c7SRoger Quadros #define DWC3_OSTS_VBUSVLD BIT(1) 5554cff75c7SRoger Quadros #define DWC3_OSTS_CONIDSTS BIT(0) 5564cff75c7SRoger Quadros 55772246da4SFelipe Balbi /* Structures */ 55872246da4SFelipe Balbi 559f6bafc6aSFelipe Balbi struct dwc3_trb; 56072246da4SFelipe Balbi 56172246da4SFelipe Balbi /** 56272246da4SFelipe Balbi * struct dwc3_event_buffer - Software event buffer representation 56372246da4SFelipe Balbi * @buf: _THE_ buffer 564d9fa4c63SJohn Youn * @cache: The buffer cache used in the threaded interrupt 56572246da4SFelipe Balbi * @length: size of this buffer 566abed4118SFelipe Balbi * @lpos: event offset 56760d04bbeSFelipe Balbi * @count: cache of last read event count register 568abed4118SFelipe Balbi * @flags: flags related to this event buffer 56972246da4SFelipe Balbi * @dma: dma_addr_t 57072246da4SFelipe Balbi * @dwc: pointer to DWC controller 57172246da4SFelipe Balbi */ 57272246da4SFelipe Balbi struct dwc3_event_buffer { 57372246da4SFelipe Balbi void *buf; 574d9fa4c63SJohn Youn void *cache; 57572246da4SFelipe Balbi unsigned length; 57672246da4SFelipe Balbi unsigned int lpos; 57760d04bbeSFelipe Balbi unsigned int count; 578abed4118SFelipe Balbi unsigned int flags; 579abed4118SFelipe Balbi 580abed4118SFelipe Balbi #define DWC3_EVENT_PENDING BIT(0) 58172246da4SFelipe Balbi 58272246da4SFelipe Balbi dma_addr_t dma; 58372246da4SFelipe Balbi 58472246da4SFelipe Balbi struct dwc3 *dwc; 58572246da4SFelipe Balbi }; 58672246da4SFelipe Balbi 587ff3f0789SRoger Quadros #define DWC3_EP_FLAG_STALLED BIT(0) 588ff3f0789SRoger Quadros #define DWC3_EP_FLAG_WEDGED BIT(1) 58972246da4SFelipe Balbi 59072246da4SFelipe Balbi #define DWC3_EP_DIRECTION_TX true 59172246da4SFelipe Balbi #define DWC3_EP_DIRECTION_RX false 59272246da4SFelipe Balbi 5938495036eSFelipe Balbi #define DWC3_TRB_NUM 256 59472246da4SFelipe Balbi 59572246da4SFelipe Balbi /** 59672246da4SFelipe Balbi * struct dwc3_ep - device side endpoint representation 59772246da4SFelipe Balbi * @endpoint: usb endpoint 598aa3342c8SFelipe Balbi * @pending_list: list of pending requests for this endpoint 599aa3342c8SFelipe Balbi * @started_list: list of started requests on this endpoint 60076a638f8SBaolin Wang * @wait_end_transfer: wait_queue_head_t for waiting on End Transfer complete 60174674cbfSFelipe Balbi * @lock: spinlock for endpoint request queue traversal 6022eb88016SFelipe Balbi * @regs: pointer to first endpoint register 60372246da4SFelipe Balbi * @trb_pool: array of transaction buffers 60472246da4SFelipe Balbi * @trb_pool_dma: dma address of @trb_pool 60553fd8818SFelipe Balbi * @trb_enqueue: enqueue 'pointer' into TRB array 60653fd8818SFelipe Balbi * @trb_dequeue: dequeue 'pointer' into TRB array 60772246da4SFelipe Balbi * @dwc: pointer to DWC controller 6084cfcf876SPaul Zimmerman * @saved_state: ep state saved during hibernation 60972246da4SFelipe Balbi * @flags: endpoint flags (wedged, stalled, ...) 61072246da4SFelipe Balbi * @number: endpoint number (1 - 15) 61172246da4SFelipe Balbi * @type: set to bmAttributes & USB_ENDPOINT_XFERTYPE_MASK 612b4996a86SFelipe Balbi * @resource_index: Resource transfer index 613502a37b9SFelipe Balbi * @frame_number: set to the frame number we want this transfer to start (ISOC) 614c75f52fbSHuang Rui * @interval: the interval on which the ISOC transfer is started 61568d34c8aSFelipe Balbi * @allocated_requests: number of requests allocated 61668d34c8aSFelipe Balbi * @queued_requests: number of requests queued for transfer 61772246da4SFelipe Balbi * @name: a human readable name e.g. ep1out-bulk 61872246da4SFelipe Balbi * @direction: true for TX, false for RX 619879631aaSFelipe Balbi * @stream_capable: true when streams are enabled 62072246da4SFelipe Balbi */ 62172246da4SFelipe Balbi struct dwc3_ep { 62272246da4SFelipe Balbi struct usb_ep endpoint; 623aa3342c8SFelipe Balbi struct list_head pending_list; 624aa3342c8SFelipe Balbi struct list_head started_list; 62572246da4SFelipe Balbi 62676a638f8SBaolin Wang wait_queue_head_t wait_end_transfer; 62776a638f8SBaolin Wang 62874674cbfSFelipe Balbi spinlock_t lock; 6292eb88016SFelipe Balbi void __iomem *regs; 6302eb88016SFelipe Balbi 631f6bafc6aSFelipe Balbi struct dwc3_trb *trb_pool; 63272246da4SFelipe Balbi dma_addr_t trb_pool_dma; 63372246da4SFelipe Balbi struct dwc3 *dwc; 63472246da4SFelipe Balbi 6354cfcf876SPaul Zimmerman u32 saved_state; 63672246da4SFelipe Balbi unsigned flags; 637ff3f0789SRoger Quadros #define DWC3_EP_ENABLED BIT(0) 638ff3f0789SRoger Quadros #define DWC3_EP_STALL BIT(1) 639ff3f0789SRoger Quadros #define DWC3_EP_WEDGE BIT(2) 640ff3f0789SRoger Quadros #define DWC3_EP_BUSY BIT(4) 641ff3f0789SRoger Quadros #define DWC3_EP_PENDING_REQUEST BIT(5) 642ff3f0789SRoger Quadros #define DWC3_EP_MISSED_ISOC BIT(6) 643ff3f0789SRoger Quadros #define DWC3_EP_END_TRANSFER_PENDING BIT(7) 644ff3f0789SRoger Quadros #define DWC3_EP_TRANSFER_STARTED BIT(8) 64572246da4SFelipe Balbi 646984f66a6SFelipe Balbi /* This last one is specific to EP0 */ 647ff3f0789SRoger Quadros #define DWC3_EP0_DIR_IN BIT(31) 648984f66a6SFelipe Balbi 649c28f8259SFelipe Balbi /* 650c28f8259SFelipe Balbi * IMPORTANT: we *know* we have 256 TRBs in our @trb_pool, so we will 651c28f8259SFelipe Balbi * use a u8 type here. If anybody decides to increase number of TRBs to 652c28f8259SFelipe Balbi * anything larger than 256 - I can't see why people would want to do 653c28f8259SFelipe Balbi * this though - then this type needs to be changed. 654c28f8259SFelipe Balbi * 655c28f8259SFelipe Balbi * By using u8 types we ensure that our % operator when incrementing 656c28f8259SFelipe Balbi * enqueue and dequeue get optimized away by the compiler. 657c28f8259SFelipe Balbi */ 658c28f8259SFelipe Balbi u8 trb_enqueue; 659c28f8259SFelipe Balbi u8 trb_dequeue; 660c28f8259SFelipe Balbi 66172246da4SFelipe Balbi u8 number; 66272246da4SFelipe Balbi u8 type; 663b4996a86SFelipe Balbi u8 resource_index; 66468d34c8aSFelipe Balbi u32 allocated_requests; 66568d34c8aSFelipe Balbi u32 queued_requests; 666502a37b9SFelipe Balbi u32 frame_number; 66772246da4SFelipe Balbi u32 interval; 66872246da4SFelipe Balbi 66972246da4SFelipe Balbi char name[20]; 67072246da4SFelipe Balbi 67172246da4SFelipe Balbi unsigned direction:1; 672879631aaSFelipe Balbi unsigned stream_capable:1; 67372246da4SFelipe Balbi }; 67472246da4SFelipe Balbi 67572246da4SFelipe Balbi enum dwc3_phy { 67672246da4SFelipe Balbi DWC3_PHY_UNKNOWN = 0, 67772246da4SFelipe Balbi DWC3_PHY_USB3, 67872246da4SFelipe Balbi DWC3_PHY_USB2, 67972246da4SFelipe Balbi }; 68072246da4SFelipe Balbi 681b53c772dSFelipe Balbi enum dwc3_ep0_next { 682b53c772dSFelipe Balbi DWC3_EP0_UNKNOWN = 0, 683b53c772dSFelipe Balbi DWC3_EP0_COMPLETE, 684b53c772dSFelipe Balbi DWC3_EP0_NRDY_DATA, 685b53c772dSFelipe Balbi DWC3_EP0_NRDY_STATUS, 686b53c772dSFelipe Balbi }; 687b53c772dSFelipe Balbi 68872246da4SFelipe Balbi enum dwc3_ep0_state { 68972246da4SFelipe Balbi EP0_UNCONNECTED = 0, 690c7fcdeb2SFelipe Balbi EP0_SETUP_PHASE, 691c7fcdeb2SFelipe Balbi EP0_DATA_PHASE, 692c7fcdeb2SFelipe Balbi EP0_STATUS_PHASE, 69372246da4SFelipe Balbi }; 69472246da4SFelipe Balbi 69572246da4SFelipe Balbi enum dwc3_link_state { 69672246da4SFelipe Balbi /* In SuperSpeed */ 69772246da4SFelipe Balbi DWC3_LINK_STATE_U0 = 0x00, /* in HS, means ON */ 69872246da4SFelipe Balbi DWC3_LINK_STATE_U1 = 0x01, 69972246da4SFelipe Balbi DWC3_LINK_STATE_U2 = 0x02, /* in HS, means SLEEP */ 70072246da4SFelipe Balbi DWC3_LINK_STATE_U3 = 0x03, /* in HS, means SUSPEND */ 70172246da4SFelipe Balbi DWC3_LINK_STATE_SS_DIS = 0x04, 70272246da4SFelipe Balbi DWC3_LINK_STATE_RX_DET = 0x05, /* in HS, means Early Suspend */ 70372246da4SFelipe Balbi DWC3_LINK_STATE_SS_INACT = 0x06, 70472246da4SFelipe Balbi DWC3_LINK_STATE_POLL = 0x07, 70572246da4SFelipe Balbi DWC3_LINK_STATE_RECOV = 0x08, 70672246da4SFelipe Balbi DWC3_LINK_STATE_HRESET = 0x09, 70772246da4SFelipe Balbi DWC3_LINK_STATE_CMPLY = 0x0a, 70872246da4SFelipe Balbi DWC3_LINK_STATE_LPBK = 0x0b, 7092c61a8efSPaul Zimmerman DWC3_LINK_STATE_RESET = 0x0e, 7102c61a8efSPaul Zimmerman DWC3_LINK_STATE_RESUME = 0x0f, 71172246da4SFelipe Balbi DWC3_LINK_STATE_MASK = 0x0f, 71272246da4SFelipe Balbi }; 71372246da4SFelipe Balbi 714f6bafc6aSFelipe Balbi /* TRB Length, PCM and Status */ 715f6bafc6aSFelipe Balbi #define DWC3_TRB_SIZE_MASK (0x00ffffff) 716f6bafc6aSFelipe Balbi #define DWC3_TRB_SIZE_LENGTH(n) ((n) & DWC3_TRB_SIZE_MASK) 717f6bafc6aSFelipe Balbi #define DWC3_TRB_SIZE_PCM1(n) (((n) & 0x03) << 24) 718389f2828SPratyush Anand #define DWC3_TRB_SIZE_TRBSTS(n) (((n) & (0x0f << 28)) >> 28) 71972246da4SFelipe Balbi 720f6bafc6aSFelipe Balbi #define DWC3_TRBSTS_OK 0 721f6bafc6aSFelipe Balbi #define DWC3_TRBSTS_MISSED_ISOC 1 722f6bafc6aSFelipe Balbi #define DWC3_TRBSTS_SETUP_PENDING 2 7232c61a8efSPaul Zimmerman #define DWC3_TRB_STS_XFER_IN_PROG 4 72472246da4SFelipe Balbi 725f6bafc6aSFelipe Balbi /* TRB Control */ 726ff3f0789SRoger Quadros #define DWC3_TRB_CTRL_HWO BIT(0) 727ff3f0789SRoger Quadros #define DWC3_TRB_CTRL_LST BIT(1) 728ff3f0789SRoger Quadros #define DWC3_TRB_CTRL_CHN BIT(2) 729ff3f0789SRoger Quadros #define DWC3_TRB_CTRL_CSP BIT(3) 730f6bafc6aSFelipe Balbi #define DWC3_TRB_CTRL_TRBCTL(n) (((n) & 0x3f) << 4) 731ff3f0789SRoger Quadros #define DWC3_TRB_CTRL_ISP_IMI BIT(10) 732ff3f0789SRoger Quadros #define DWC3_TRB_CTRL_IOC BIT(11) 733f6bafc6aSFelipe Balbi #define DWC3_TRB_CTRL_SID_SOFN(n) (((n) & 0xffff) << 14) 734f6bafc6aSFelipe Balbi 735b058f3e8SFelipe Balbi #define DWC3_TRBCTL_TYPE(n) ((n) & (0x3f << 4)) 736f6bafc6aSFelipe Balbi #define DWC3_TRBCTL_NORMAL DWC3_TRB_CTRL_TRBCTL(1) 737f6bafc6aSFelipe Balbi #define DWC3_TRBCTL_CONTROL_SETUP DWC3_TRB_CTRL_TRBCTL(2) 738f6bafc6aSFelipe Balbi #define DWC3_TRBCTL_CONTROL_STATUS2 DWC3_TRB_CTRL_TRBCTL(3) 739f6bafc6aSFelipe Balbi #define DWC3_TRBCTL_CONTROL_STATUS3 DWC3_TRB_CTRL_TRBCTL(4) 740f6bafc6aSFelipe Balbi #define DWC3_TRBCTL_CONTROL_DATA DWC3_TRB_CTRL_TRBCTL(5) 741f6bafc6aSFelipe Balbi #define DWC3_TRBCTL_ISOCHRONOUS_FIRST DWC3_TRB_CTRL_TRBCTL(6) 742f6bafc6aSFelipe Balbi #define DWC3_TRBCTL_ISOCHRONOUS DWC3_TRB_CTRL_TRBCTL(7) 743f6bafc6aSFelipe Balbi #define DWC3_TRBCTL_LINK_TRB DWC3_TRB_CTRL_TRBCTL(8) 74472246da4SFelipe Balbi 74572246da4SFelipe Balbi /** 746f6bafc6aSFelipe Balbi * struct dwc3_trb - transfer request block (hw format) 74772246da4SFelipe Balbi * @bpl: DW0-3 74872246da4SFelipe Balbi * @bph: DW4-7 74972246da4SFelipe Balbi * @size: DW8-B 750bfad65eeSFelipe Balbi * @ctrl: DWC-F 75172246da4SFelipe Balbi */ 752f6bafc6aSFelipe Balbi struct dwc3_trb { 753f6bafc6aSFelipe Balbi u32 bpl; 754f6bafc6aSFelipe Balbi u32 bph; 755f6bafc6aSFelipe Balbi u32 size; 756f6bafc6aSFelipe Balbi u32 ctrl; 75772246da4SFelipe Balbi } __packed; 75872246da4SFelipe Balbi 75972246da4SFelipe Balbi /** 760bfad65eeSFelipe Balbi * struct dwc3_hwparams - copy of HWPARAMS registers 761bfad65eeSFelipe Balbi * @hwparams0: GHWPARAMS0 762bfad65eeSFelipe Balbi * @hwparams1: GHWPARAMS1 763bfad65eeSFelipe Balbi * @hwparams2: GHWPARAMS2 764bfad65eeSFelipe Balbi * @hwparams3: GHWPARAMS3 765bfad65eeSFelipe Balbi * @hwparams4: GHWPARAMS4 766bfad65eeSFelipe Balbi * @hwparams5: GHWPARAMS5 767bfad65eeSFelipe Balbi * @hwparams6: GHWPARAMS6 768bfad65eeSFelipe Balbi * @hwparams7: GHWPARAMS7 769bfad65eeSFelipe Balbi * @hwparams8: GHWPARAMS8 770a3299499SFelipe Balbi */ 771a3299499SFelipe Balbi struct dwc3_hwparams { 772a3299499SFelipe Balbi u32 hwparams0; 773a3299499SFelipe Balbi u32 hwparams1; 774a3299499SFelipe Balbi u32 hwparams2; 775a3299499SFelipe Balbi u32 hwparams3; 776a3299499SFelipe Balbi u32 hwparams4; 777a3299499SFelipe Balbi u32 hwparams5; 778a3299499SFelipe Balbi u32 hwparams6; 779a3299499SFelipe Balbi u32 hwparams7; 780a3299499SFelipe Balbi u32 hwparams8; 781a3299499SFelipe Balbi }; 782a3299499SFelipe Balbi 7830949e99bSFelipe Balbi /* HWPARAMS0 */ 7840949e99bSFelipe Balbi #define DWC3_MODE(n) ((n) & 0x7) 7850949e99bSFelipe Balbi 786457e84b6SFelipe Balbi #define DWC3_MDWIDTH(n) (((n) & 0xff00) >> 8) 787457e84b6SFelipe Balbi 7880949e99bSFelipe Balbi /* HWPARAMS1 */ 7899f622b2aSFelipe Balbi #define DWC3_NUM_INT(n) (((n) & (0x3f << 15)) >> 15) 7909f622b2aSFelipe Balbi 791789451f6SFelipe Balbi /* HWPARAMS3 */ 792789451f6SFelipe Balbi #define DWC3_NUM_IN_EPS_MASK (0x1f << 18) 793789451f6SFelipe Balbi #define DWC3_NUM_EPS_MASK (0x3f << 12) 794789451f6SFelipe Balbi #define DWC3_NUM_EPS(p) (((p)->hwparams3 & \ 795789451f6SFelipe Balbi (DWC3_NUM_EPS_MASK)) >> 12) 796789451f6SFelipe Balbi #define DWC3_NUM_IN_EPS(p) (((p)->hwparams3 & \ 797789451f6SFelipe Balbi (DWC3_NUM_IN_EPS_MASK)) >> 18) 798789451f6SFelipe Balbi 799457e84b6SFelipe Balbi /* HWPARAMS7 */ 800457e84b6SFelipe Balbi #define DWC3_RAM1_DEPTH(n) ((n) & 0xffff) 801457e84b6SFelipe Balbi 8025ef68c56SFelipe Balbi /** 8035ef68c56SFelipe Balbi * struct dwc3_request - representation of a transfer request 8045ef68c56SFelipe Balbi * @request: struct usb_request to be transferred 8055ef68c56SFelipe Balbi * @list: a list_head used for request queueing 8065ef68c56SFelipe Balbi * @dep: struct dwc3_ep owning this request 8070b3e4af3SFelipe Balbi * @sg: pointer to first incomplete sg 8080b3e4af3SFelipe Balbi * @num_pending_sgs: counter to pending sgs 809e62c5bc5SFelipe Balbi * @remaining: amount of data remaining 8105ef68c56SFelipe Balbi * @epnum: endpoint number to which this request refers 8115ef68c56SFelipe Balbi * @trb: pointer to struct dwc3_trb 8125ef68c56SFelipe Balbi * @trb_dma: DMA address of @trb 813c6267a51SFelipe Balbi * @unaligned: true for OUT endpoints with length not divisible by maxp 8145ef68c56SFelipe Balbi * @direction: IN or OUT direction flag 8155ef68c56SFelipe Balbi * @mapped: true when request has been dma-mapped 816bfad65eeSFelipe Balbi * @started: request is started 817bfad65eeSFelipe Balbi * @zero: wants a ZLP 8185ef68c56SFelipe Balbi */ 819e0ce0b0aSSebastian Andrzej Siewior struct dwc3_request { 820e0ce0b0aSSebastian Andrzej Siewior struct usb_request request; 821e0ce0b0aSSebastian Andrzej Siewior struct list_head list; 822e0ce0b0aSSebastian Andrzej Siewior struct dwc3_ep *dep; 8230b3e4af3SFelipe Balbi struct scatterlist *sg; 824e0ce0b0aSSebastian Andrzej Siewior 8250b3e4af3SFelipe Balbi unsigned num_pending_sgs; 826e62c5bc5SFelipe Balbi unsigned remaining; 827e0ce0b0aSSebastian Andrzej Siewior u8 epnum; 828f6bafc6aSFelipe Balbi struct dwc3_trb *trb; 829e0ce0b0aSSebastian Andrzej Siewior dma_addr_t trb_dma; 830e0ce0b0aSSebastian Andrzej Siewior 831c6267a51SFelipe Balbi unsigned unaligned:1; 832e0ce0b0aSSebastian Andrzej Siewior unsigned direction:1; 833e0ce0b0aSSebastian Andrzej Siewior unsigned mapped:1; 834aa3342c8SFelipe Balbi unsigned started:1; 835d6e5a549SFelipe Balbi unsigned zero:1; 836e0ce0b0aSSebastian Andrzej Siewior }; 837e0ce0b0aSSebastian Andrzej Siewior 8382c61a8efSPaul Zimmerman /* 8392c61a8efSPaul Zimmerman * struct dwc3_scratchpad_array - hibernation scratchpad array 8402c61a8efSPaul Zimmerman * (format defined by hw) 8412c61a8efSPaul Zimmerman */ 8422c61a8efSPaul Zimmerman struct dwc3_scratchpad_array { 8432c61a8efSPaul Zimmerman __le64 dma_adr[DWC3_MAX_HIBER_SCRATCHBUFS]; 8442c61a8efSPaul Zimmerman }; 8452c61a8efSPaul Zimmerman 846a3299499SFelipe Balbi /** 84772246da4SFelipe Balbi * struct dwc3 - representation of our controller 848bfad65eeSFelipe Balbi * @drd_work: workqueue used for role swapping 84991db07dcSFelipe Balbi * @ep0_trb: trb which is used for the ctrl_req 850bfad65eeSFelipe Balbi * @bounce: address of bounce buffer 851bfad65eeSFelipe Balbi * @scratchbuf: address of scratch buffer 85291db07dcSFelipe Balbi * @setup_buf: used while precessing STD USB requests 853bfad65eeSFelipe Balbi * @ep0_trb_addr: dma address of @ep0_trb 854bfad65eeSFelipe Balbi * @bounce_addr: dma address of @bounce 85591db07dcSFelipe Balbi * @ep0_usb_req: dummy req used while handling STD USB requests 8560ffcaf37SFelipe Balbi * @scratch_addr: dma address of scratchbuf 857bb014736SBaolin Wang * @ep0_in_setup: one control transfer is completed and enter setup phase 85872246da4SFelipe Balbi * @lock: for synchronizing 85972246da4SFelipe Balbi * @dev: pointer to our struct device 860bfad65eeSFelipe Balbi * @sysdev: pointer to the DMA-capable device 861d07e8819SFelipe Balbi * @xhci: pointer to our xHCI child 862bfad65eeSFelipe Balbi * @xhci_resources: struct resources for our @xhci child 863bfad65eeSFelipe Balbi * @ev_buf: struct dwc3_event_buffer pointer 864bfad65eeSFelipe Balbi * @eps: endpoint array 86572246da4SFelipe Balbi * @gadget: device side representation of the peripheral controller 86672246da4SFelipe Balbi * @gadget_driver: pointer to the gadget driver 86772246da4SFelipe Balbi * @regs: base address for our registers 86872246da4SFelipe Balbi * @regs_size: address space size 869bcdb3272SFelipe Balbi * @fladj: frame length adjustment 8703f308d17SFelipe Balbi * @irq_gadget: peripheral controller's IRQ number 871*f09cc79bSRoger Quadros * @otg_irq: IRQ number for OTG IRQs 872*f09cc79bSRoger Quadros * @current_otg_role: current role of operation while using the OTG block 873*f09cc79bSRoger Quadros * @desired_otg_role: desired role of operation while using the OTG block 874*f09cc79bSRoger Quadros * @otg_restart_host: flag that OTG controller needs to restart host 8750ffcaf37SFelipe Balbi * @nr_scratch: number of scratch buffers 876fae2b904SFelipe Balbi * @u1u2: only used on revisions <1.83a for workaround 8776c167fc9SFelipe Balbi * @maximum_speed: maximum speed requested (mainly for testing purposes) 87872246da4SFelipe Balbi * @revision: revision register contents 879a45c82b8SRuchika Kharwar * @dr_mode: requested mode of operation 8806b3261a2SRoger Quadros * @current_dr_role: current role of operation when in dual-role mode 88141ce1456SRoger Quadros * @desired_dr_role: desired role of operation when in dual-role mode 8829840354fSRoger Quadros * @edev: extcon handle 8839840354fSRoger Quadros * @edev_nb: extcon notifier 88432f2ed86SWilliam Wu * @hsphy_mode: UTMI phy mode, one of following: 88532f2ed86SWilliam Wu * - USBPHY_INTERFACE_MODE_UTMI 88632f2ed86SWilliam Wu * - USBPHY_INTERFACE_MODE_UTMIW 88751e1e7bcSFelipe Balbi * @usb2_phy: pointer to USB2 PHY 88851e1e7bcSFelipe Balbi * @usb3_phy: pointer to USB3 PHY 88957303488SKishon Vijay Abraham I * @usb2_generic_phy: pointer to USB2 PHY 89057303488SKishon Vijay Abraham I * @usb3_generic_phy: pointer to USB3 PHY 89198112041SRoger Quadros * @phys_ready: flag to indicate that PHYs are ready 89288bc9d19SHeikki Krogerus * @ulpi: pointer to ulpi interface 89398112041SRoger Quadros * @ulpi_ready: flag to indicate that ULPI is initialized 894865e09e7SFelipe Balbi * @u2sel: parameter from Set SEL request. 895865e09e7SFelipe Balbi * @u2pel: parameter from Set SEL request. 896865e09e7SFelipe Balbi * @u1sel: parameter from Set SEL request. 897865e09e7SFelipe Balbi * @u1pel: parameter from Set SEL request. 89847d3946eSBryan O'Donoghue * @num_eps: number of endpoints 899b53c772dSFelipe Balbi * @ep0_next_event: hold the next expected event 90072246da4SFelipe Balbi * @ep0state: state of endpoint zero 90172246da4SFelipe Balbi * @link_state: link state 90272246da4SFelipe Balbi * @speed: device speed (super, high, full, low) 903a3299499SFelipe Balbi * @hwparams: copy of hwparams registers 90472246da4SFelipe Balbi * @root: debugfs root folder pointer 905f2b685d5SFelipe Balbi * @regset: debugfs pointer to regdump file 906f2b685d5SFelipe Balbi * @test_mode: true when we're entering a USB test mode 907f2b685d5SFelipe Balbi * @test_mode_nr: test feature selector 90880caf7d2SHuang Rui * @lpm_nyet_threshold: LPM NYET response threshold 909460d098cSHuang Rui * @hird_threshold: HIRD threshold 9103e10a2ceSHeikki Krogerus * @hsphy_interface: "utmi" or "ulpi" 911fc8bb91bSFelipe Balbi * @connected: true when we're connected to a host, false otherwise 912f2b685d5SFelipe Balbi * @delayed_status: true when gadget driver asks for delayed status 913f2b685d5SFelipe Balbi * @ep0_bounced: true when we used bounce buffer 914f2b685d5SFelipe Balbi * @ep0_expect_in: true when we expect a DATA IN transfer 91581bc5599SFelipe Balbi * @has_hibernation: true when dwc3 was configured with Hibernation 916d64ff406SArnd Bergmann * @sysdev_is_parent: true when dwc3 device has a parent driver 91780caf7d2SHuang Rui * @has_lpm_erratum: true when core was configured with LPM Erratum. Note that 91880caf7d2SHuang Rui * there's now way for software to detect this in runtime. 919460d098cSHuang Rui * @is_utmi_l1_suspend: the core asserts output signal 920460d098cSHuang Rui * 0 - utmi_sleep_n 921460d098cSHuang Rui * 1 - utmi_l1_suspend_n 922946bd579SHuang Rui * @is_fpga: true when we are using the FPGA board 923fc8bb91bSFelipe Balbi * @pending_events: true when we have pending IRQs to be handled 924f2b685d5SFelipe Balbi * @pullups_connected: true when Run/Stop bit is set 925f2b685d5SFelipe Balbi * @setup_packet_pending: true when there's a Setup Packet in FIFO. Workaround 926f2b685d5SFelipe Balbi * @three_stage_setup: set if we perform a three phase setup 927eac68e8fSRobert Baldyga * @usb3_lpm_capable: set if hadrware supports Link Power Management 9283b81221aSHuang Rui * @disable_scramble_quirk: set if we enable the disable scramble quirk 9299a5b2f31SHuang Rui * @u2exit_lfps_quirk: set if we enable u2exit lfps quirk 930b5a65c40SHuang Rui * @u2ss_inp3_quirk: set if we enable P3 OK for U2/SS Inactive quirk 931df31f5b3SHuang Rui * @req_p1p2p3_quirk: set if we enable request p1p2p3 quirk 932a2a1d0f5SHuang Rui * @del_p1p2p3_quirk: set if we enable delay p1p2p3 quirk 93341c06ffdSHuang Rui * @del_phy_power_chg_quirk: set if we enable delay phy power change quirk 934fb67afcaSHuang Rui * @lfps_filter_quirk: set if we enable LFPS filter quirk 93514f4ac53SHuang Rui * @rx_detect_poll_quirk: set if we enable rx_detect to polling lfps quirk 93659acfa20SHuang Rui * @dis_u3_susphy_quirk: set if we disable usb3 suspend phy 9370effe0a3SHuang Rui * @dis_u2_susphy_quirk: set if we disable usb2 suspend phy 938ec791d14SJohn Youn * @dis_enblslpm_quirk: set if we clear enblslpm in GUSB2PHYCFG, 939ec791d14SJohn Youn * disabling the suspend signal to the PHY. 940bfad65eeSFelipe Balbi * @dis_rxdet_inp3_quirk: set if we disable Rx.Detect in P3 94116199f33SWilliam Wu * @dis_u2_freeclk_exists_quirk : set if we clear u2_freeclk_exists 94216199f33SWilliam Wu * in GUSB2PHYCFG, specify that USB2 PHY doesn't 94316199f33SWilliam Wu * provide a free-running PHY clock. 94400fe081dSWilliam Wu * @dis_del_phy_power_chg_quirk: set if we disable delay phy power 94500fe081dSWilliam Wu * change quirk. 94665db7a0cSWilliam Wu * @dis_tx_ipgap_linecheck_quirk: set if we disable u2mac linestate 94765db7a0cSWilliam Wu * check during HS transmit. 9486b6a0c9aSHuang Rui * @tx_de_emphasis_quirk: set if we enable Tx de-emphasis quirk 9496b6a0c9aSHuang Rui * @tx_de_emphasis: Tx de-emphasis value 9506b6a0c9aSHuang Rui * 0 - -6dB de-emphasis 9516b6a0c9aSHuang Rui * 1 - -3.5dB de-emphasis 9526b6a0c9aSHuang Rui * 2 - No de-emphasis 9536b6a0c9aSHuang Rui * 3 - Reserved 95442bf02ecSRoger Quadros * @dis_metastability_quirk: set to disable metastability quirk. 955cf40b86bSJohn Youn * @imod_interval: set the interrupt moderation interval in 250ns 956cf40b86bSJohn Youn * increments or 0 to disable. 95772246da4SFelipe Balbi */ 95872246da4SFelipe Balbi struct dwc3 { 95941ce1456SRoger Quadros struct work_struct drd_work; 960f6bafc6aSFelipe Balbi struct dwc3_trb *ep0_trb; 961905dc04eSFelipe Balbi void *bounce; 9620ffcaf37SFelipe Balbi void *scratchbuf; 96372246da4SFelipe Balbi u8 *setup_buf; 96472246da4SFelipe Balbi dma_addr_t ep0_trb_addr; 965905dc04eSFelipe Balbi dma_addr_t bounce_addr; 9660ffcaf37SFelipe Balbi dma_addr_t scratch_addr; 967e0ce0b0aSSebastian Andrzej Siewior struct dwc3_request ep0_usb_req; 968bb014736SBaolin Wang struct completion ep0_in_setup; 969789451f6SFelipe Balbi 97072246da4SFelipe Balbi /* device lock */ 97172246da4SFelipe Balbi spinlock_t lock; 972789451f6SFelipe Balbi 97372246da4SFelipe Balbi struct device *dev; 974d64ff406SArnd Bergmann struct device *sysdev; 97572246da4SFelipe Balbi 976d07e8819SFelipe Balbi struct platform_device *xhci; 97751249dcaSIdo Shayevitz struct resource xhci_resources[DWC3_XHCI_RESOURCES_NUM]; 978d07e8819SFelipe Balbi 979696c8b12SFelipe Balbi struct dwc3_event_buffer *ev_buf; 98072246da4SFelipe Balbi struct dwc3_ep *eps[DWC3_ENDPOINTS_NUM]; 98172246da4SFelipe Balbi 98272246da4SFelipe Balbi struct usb_gadget gadget; 98372246da4SFelipe Balbi struct usb_gadget_driver *gadget_driver; 98472246da4SFelipe Balbi 98551e1e7bcSFelipe Balbi struct usb_phy *usb2_phy; 98651e1e7bcSFelipe Balbi struct usb_phy *usb3_phy; 98751e1e7bcSFelipe Balbi 98857303488SKishon Vijay Abraham I struct phy *usb2_generic_phy; 98957303488SKishon Vijay Abraham I struct phy *usb3_generic_phy; 99057303488SKishon Vijay Abraham I 99198112041SRoger Quadros bool phys_ready; 99298112041SRoger Quadros 99388bc9d19SHeikki Krogerus struct ulpi *ulpi; 99498112041SRoger Quadros bool ulpi_ready; 99588bc9d19SHeikki Krogerus 99672246da4SFelipe Balbi void __iomem *regs; 99772246da4SFelipe Balbi size_t regs_size; 99872246da4SFelipe Balbi 999a45c82b8SRuchika Kharwar enum usb_dr_mode dr_mode; 10006b3261a2SRoger Quadros u32 current_dr_role; 100141ce1456SRoger Quadros u32 desired_dr_role; 10029840354fSRoger Quadros struct extcon_dev *edev; 10039840354fSRoger Quadros struct notifier_block edev_nb; 100432f2ed86SWilliam Wu enum usb_phy_interface hsphy_mode; 1005a45c82b8SRuchika Kharwar 1006bcdb3272SFelipe Balbi u32 fladj; 10073f308d17SFelipe Balbi u32 irq_gadget; 1008*f09cc79bSRoger Quadros u32 otg_irq; 1009*f09cc79bSRoger Quadros u32 current_otg_role; 1010*f09cc79bSRoger Quadros u32 desired_otg_role; 1011*f09cc79bSRoger Quadros bool otg_restart_host; 10120ffcaf37SFelipe Balbi u32 nr_scratch; 1013fae2b904SFelipe Balbi u32 u1u2; 10146c167fc9SFelipe Balbi u32 maximum_speed; 1015690fb371SJohn Youn 1016690fb371SJohn Youn /* 1017690fb371SJohn Youn * All 3.1 IP version constants are greater than the 3.0 IP 1018690fb371SJohn Youn * version constants. This works for most version checks in 1019690fb371SJohn Youn * dwc3. However, in the future, this may not apply as 1020690fb371SJohn Youn * features may be developed on newer versions of the 3.0 IP 1021690fb371SJohn Youn * that are not in the 3.1 IP. 1022690fb371SJohn Youn */ 102372246da4SFelipe Balbi u32 revision; 102472246da4SFelipe Balbi 102572246da4SFelipe Balbi #define DWC3_REVISION_173A 0x5533173a 102672246da4SFelipe Balbi #define DWC3_REVISION_175A 0x5533175a 102772246da4SFelipe Balbi #define DWC3_REVISION_180A 0x5533180a 102872246da4SFelipe Balbi #define DWC3_REVISION_183A 0x5533183a 102972246da4SFelipe Balbi #define DWC3_REVISION_185A 0x5533185a 10302c61a8efSPaul Zimmerman #define DWC3_REVISION_187A 0x5533187a 103172246da4SFelipe Balbi #define DWC3_REVISION_188A 0x5533188a 103272246da4SFelipe Balbi #define DWC3_REVISION_190A 0x5533190a 10332c61a8efSPaul Zimmerman #define DWC3_REVISION_194A 0x5533194a 10341522d703SFelipe Balbi #define DWC3_REVISION_200A 0x5533200a 10351522d703SFelipe Balbi #define DWC3_REVISION_202A 0x5533202a 10361522d703SFelipe Balbi #define DWC3_REVISION_210A 0x5533210a 10371522d703SFelipe Balbi #define DWC3_REVISION_220A 0x5533220a 10387ac6a593SFelipe Balbi #define DWC3_REVISION_230A 0x5533230a 10397ac6a593SFelipe Balbi #define DWC3_REVISION_240A 0x5533240a 10407ac6a593SFelipe Balbi #define DWC3_REVISION_250A 0x5533250a 1041dbf5aaf7SFelipe Balbi #define DWC3_REVISION_260A 0x5533260a 1042dbf5aaf7SFelipe Balbi #define DWC3_REVISION_270A 0x5533270a 1043dbf5aaf7SFelipe Balbi #define DWC3_REVISION_280A 0x5533280a 10440bb39ca1SJohn Youn #define DWC3_REVISION_290A 0x5533290a 1045512e4757SJohn Youn #define DWC3_REVISION_300A 0x5533300a 1046512e4757SJohn Youn #define DWC3_REVISION_310A 0x5533310a 104772246da4SFelipe Balbi 1048690fb371SJohn Youn /* 1049690fb371SJohn Youn * NOTICE: we're using bit 31 as a "is usb 3.1" flag. This is really 1050690fb371SJohn Youn * just so dwc31 revisions are always larger than dwc3. 1051690fb371SJohn Youn */ 1052690fb371SJohn Youn #define DWC3_REVISION_IS_DWC31 0x80000000 1053e77c5614SJohn Youn #define DWC3_USB31_REVISION_110A (0x3131302a | DWC3_REVISION_IS_DWC31) 1054cf40b86bSJohn Youn #define DWC3_USB31_REVISION_120A (0x3132302a | DWC3_REVISION_IS_DWC31) 1055690fb371SJohn Youn 1056b53c772dSFelipe Balbi enum dwc3_ep0_next ep0_next_event; 105772246da4SFelipe Balbi enum dwc3_ep0_state ep0state; 105872246da4SFelipe Balbi enum dwc3_link_state link_state; 105972246da4SFelipe Balbi 1060865e09e7SFelipe Balbi u16 u2sel; 1061865e09e7SFelipe Balbi u16 u2pel; 1062865e09e7SFelipe Balbi u8 u1sel; 1063865e09e7SFelipe Balbi u8 u1pel; 1064865e09e7SFelipe Balbi 106572246da4SFelipe Balbi u8 speed; 1066865e09e7SFelipe Balbi 106747d3946eSBryan O'Donoghue u8 num_eps; 1068789451f6SFelipe Balbi 1069a3299499SFelipe Balbi struct dwc3_hwparams hwparams; 107072246da4SFelipe Balbi struct dentry *root; 1071d7668024SFelipe Balbi struct debugfs_regset32 *regset; 10723b637367SGerard Cauvy 10733b637367SGerard Cauvy u8 test_mode; 10743b637367SGerard Cauvy u8 test_mode_nr; 107580caf7d2SHuang Rui u8 lpm_nyet_threshold; 1076460d098cSHuang Rui u8 hird_threshold; 1077f2b685d5SFelipe Balbi 10783e10a2ceSHeikki Krogerus const char *hsphy_interface; 10793e10a2ceSHeikki Krogerus 1080fc8bb91bSFelipe Balbi unsigned connected:1; 1081f2b685d5SFelipe Balbi unsigned delayed_status:1; 1082f2b685d5SFelipe Balbi unsigned ep0_bounced:1; 1083f2b685d5SFelipe Balbi unsigned ep0_expect_in:1; 108481bc5599SFelipe Balbi unsigned has_hibernation:1; 1085d64ff406SArnd Bergmann unsigned sysdev_is_parent:1; 108680caf7d2SHuang Rui unsigned has_lpm_erratum:1; 1087460d098cSHuang Rui unsigned is_utmi_l1_suspend:1; 1088946bd579SHuang Rui unsigned is_fpga:1; 1089fc8bb91bSFelipe Balbi unsigned pending_events:1; 1090f2b685d5SFelipe Balbi unsigned pullups_connected:1; 1091f2b685d5SFelipe Balbi unsigned setup_packet_pending:1; 1092f2b685d5SFelipe Balbi unsigned three_stage_setup:1; 1093eac68e8fSRobert Baldyga unsigned usb3_lpm_capable:1; 10943b81221aSHuang Rui 10953b81221aSHuang Rui unsigned disable_scramble_quirk:1; 10969a5b2f31SHuang Rui unsigned u2exit_lfps_quirk:1; 1097b5a65c40SHuang Rui unsigned u2ss_inp3_quirk:1; 1098df31f5b3SHuang Rui unsigned req_p1p2p3_quirk:1; 1099a2a1d0f5SHuang Rui unsigned del_p1p2p3_quirk:1; 110041c06ffdSHuang Rui unsigned del_phy_power_chg_quirk:1; 1101fb67afcaSHuang Rui unsigned lfps_filter_quirk:1; 110214f4ac53SHuang Rui unsigned rx_detect_poll_quirk:1; 110359acfa20SHuang Rui unsigned dis_u3_susphy_quirk:1; 11040effe0a3SHuang Rui unsigned dis_u2_susphy_quirk:1; 1105ec791d14SJohn Youn unsigned dis_enblslpm_quirk:1; 1106e58dd357SRajesh Bhagat unsigned dis_rxdet_inp3_quirk:1; 110716199f33SWilliam Wu unsigned dis_u2_freeclk_exists_quirk:1; 110800fe081dSWilliam Wu unsigned dis_del_phy_power_chg_quirk:1; 110965db7a0cSWilliam Wu unsigned dis_tx_ipgap_linecheck_quirk:1; 11106b6a0c9aSHuang Rui 11116b6a0c9aSHuang Rui unsigned tx_de_emphasis_quirk:1; 11126b6a0c9aSHuang Rui unsigned tx_de_emphasis:2; 1113cf40b86bSJohn Youn 111442bf02ecSRoger Quadros unsigned dis_metastability_quirk:1; 111542bf02ecSRoger Quadros 1116cf40b86bSJohn Youn u16 imod_interval; 111772246da4SFelipe Balbi }; 111872246da4SFelipe Balbi 111941ce1456SRoger Quadros #define work_to_dwc(w) (container_of((w), struct dwc3, drd_work)) 112072246da4SFelipe Balbi 112172246da4SFelipe Balbi /* -------------------------------------------------------------------------- */ 112272246da4SFelipe Balbi 112372246da4SFelipe Balbi struct dwc3_event_type { 112472246da4SFelipe Balbi u32 is_devspec:1; 11251974d494SHuang Rui u32 type:7; 11261974d494SHuang Rui u32 reserved8_31:24; 112772246da4SFelipe Balbi } __packed; 112872246da4SFelipe Balbi 112972246da4SFelipe Balbi #define DWC3_DEPEVT_XFERCOMPLETE 0x01 113072246da4SFelipe Balbi #define DWC3_DEPEVT_XFERINPROGRESS 0x02 113172246da4SFelipe Balbi #define DWC3_DEPEVT_XFERNOTREADY 0x03 113272246da4SFelipe Balbi #define DWC3_DEPEVT_RXTXFIFOEVT 0x04 113372246da4SFelipe Balbi #define DWC3_DEPEVT_STREAMEVT 0x06 113472246da4SFelipe Balbi #define DWC3_DEPEVT_EPCMDCMPLT 0x07 113572246da4SFelipe Balbi 113672246da4SFelipe Balbi /** 113772246da4SFelipe Balbi * struct dwc3_event_depvt - Device Endpoint Events 113872246da4SFelipe Balbi * @one_bit: indicates this is an endpoint event (not used) 113972246da4SFelipe Balbi * @endpoint_number: number of the endpoint 114072246da4SFelipe Balbi * @endpoint_event: The event we have: 114172246da4SFelipe Balbi * 0x00 - Reserved 114272246da4SFelipe Balbi * 0x01 - XferComplete 114372246da4SFelipe Balbi * 0x02 - XferInProgress 114472246da4SFelipe Balbi * 0x03 - XferNotReady 114572246da4SFelipe Balbi * 0x04 - RxTxFifoEvt (IN->Underrun, OUT->Overrun) 114672246da4SFelipe Balbi * 0x05 - Reserved 114772246da4SFelipe Balbi * 0x06 - StreamEvt 114872246da4SFelipe Balbi * 0x07 - EPCmdCmplt 114972246da4SFelipe Balbi * @reserved11_10: Reserved, don't use. 115072246da4SFelipe Balbi * @status: Indicates the status of the event. Refer to databook for 115172246da4SFelipe Balbi * more information. 115272246da4SFelipe Balbi * @parameters: Parameters of the current event. Refer to databook for 115372246da4SFelipe Balbi * more information. 115472246da4SFelipe Balbi */ 115572246da4SFelipe Balbi struct dwc3_event_depevt { 115672246da4SFelipe Balbi u32 one_bit:1; 115772246da4SFelipe Balbi u32 endpoint_number:5; 115872246da4SFelipe Balbi u32 endpoint_event:4; 115972246da4SFelipe Balbi u32 reserved11_10:2; 116072246da4SFelipe Balbi u32 status:4; 116140aa41fbSFelipe Balbi 116240aa41fbSFelipe Balbi /* Within XferNotReady */ 1163ff3f0789SRoger Quadros #define DEPEVT_STATUS_TRANSFER_ACTIVE BIT(3) 116440aa41fbSFelipe Balbi 116540aa41fbSFelipe Balbi /* Within XferComplete */ 1166ff3f0789SRoger Quadros #define DEPEVT_STATUS_BUSERR BIT(0) 1167ff3f0789SRoger Quadros #define DEPEVT_STATUS_SHORT BIT(1) 1168ff3f0789SRoger Quadros #define DEPEVT_STATUS_IOC BIT(2) 1169ff3f0789SRoger Quadros #define DEPEVT_STATUS_LST BIT(3) 1170dc137f01SFelipe Balbi 1171879631aaSFelipe Balbi /* Stream event only */ 1172879631aaSFelipe Balbi #define DEPEVT_STREAMEVT_FOUND 1 1173879631aaSFelipe Balbi #define DEPEVT_STREAMEVT_NOTFOUND 2 1174879631aaSFelipe Balbi 1175dc137f01SFelipe Balbi /* Control-only Status */ 1176dc137f01SFelipe Balbi #define DEPEVT_STATUS_CONTROL_DATA 1 1177dc137f01SFelipe Balbi #define DEPEVT_STATUS_CONTROL_STATUS 2 117845a2af2fSFelipe Balbi #define DEPEVT_STATUS_CONTROL_PHASE(n) ((n) & 3) 1179dc137f01SFelipe Balbi 11807b9cc7a2SKonrad Leszczynski /* In response to Start Transfer */ 11817b9cc7a2SKonrad Leszczynski #define DEPEVT_TRANSFER_NO_RESOURCE 1 11827b9cc7a2SKonrad Leszczynski #define DEPEVT_TRANSFER_BUS_EXPIRY 2 11837b9cc7a2SKonrad Leszczynski 118472246da4SFelipe Balbi u32 parameters:16; 118576a638f8SBaolin Wang 118676a638f8SBaolin Wang /* For Command Complete Events */ 118776a638f8SBaolin Wang #define DEPEVT_PARAMETER_CMD(n) (((n) & (0xf << 8)) >> 8) 118872246da4SFelipe Balbi } __packed; 118972246da4SFelipe Balbi 119072246da4SFelipe Balbi /** 119172246da4SFelipe Balbi * struct dwc3_event_devt - Device Events 119272246da4SFelipe Balbi * @one_bit: indicates this is a non-endpoint event (not used) 119372246da4SFelipe Balbi * @device_event: indicates it's a device event. Should read as 0x00 119472246da4SFelipe Balbi * @type: indicates the type of device event. 119572246da4SFelipe Balbi * 0 - DisconnEvt 119672246da4SFelipe Balbi * 1 - USBRst 119772246da4SFelipe Balbi * 2 - ConnectDone 119872246da4SFelipe Balbi * 3 - ULStChng 119972246da4SFelipe Balbi * 4 - WkUpEvt 120072246da4SFelipe Balbi * 5 - Reserved 120172246da4SFelipe Balbi * 6 - EOPF 120272246da4SFelipe Balbi * 7 - SOF 120372246da4SFelipe Balbi * 8 - Reserved 120472246da4SFelipe Balbi * 9 - ErrticErr 120572246da4SFelipe Balbi * 10 - CmdCmplt 120672246da4SFelipe Balbi * 11 - EvntOverflow 120772246da4SFelipe Balbi * 12 - VndrDevTstRcved 120872246da4SFelipe Balbi * @reserved15_12: Reserved, not used 120972246da4SFelipe Balbi * @event_info: Information about this event 121006f9b6e5SHuang Rui * @reserved31_25: Reserved, not used 121172246da4SFelipe Balbi */ 121272246da4SFelipe Balbi struct dwc3_event_devt { 121372246da4SFelipe Balbi u32 one_bit:1; 121472246da4SFelipe Balbi u32 device_event:7; 121572246da4SFelipe Balbi u32 type:4; 121672246da4SFelipe Balbi u32 reserved15_12:4; 121706f9b6e5SHuang Rui u32 event_info:9; 121806f9b6e5SHuang Rui u32 reserved31_25:7; 121972246da4SFelipe Balbi } __packed; 122072246da4SFelipe Balbi 122172246da4SFelipe Balbi /** 122272246da4SFelipe Balbi * struct dwc3_event_gevt - Other Core Events 122372246da4SFelipe Balbi * @one_bit: indicates this is a non-endpoint event (not used) 122472246da4SFelipe Balbi * @device_event: indicates it's (0x03) Carkit or (0x04) I2C event. 122572246da4SFelipe Balbi * @phy_port_number: self-explanatory 122672246da4SFelipe Balbi * @reserved31_12: Reserved, not used. 122772246da4SFelipe Balbi */ 122872246da4SFelipe Balbi struct dwc3_event_gevt { 122972246da4SFelipe Balbi u32 one_bit:1; 123072246da4SFelipe Balbi u32 device_event:7; 123172246da4SFelipe Balbi u32 phy_port_number:4; 123272246da4SFelipe Balbi u32 reserved31_12:20; 123372246da4SFelipe Balbi } __packed; 123472246da4SFelipe Balbi 123572246da4SFelipe Balbi /** 123672246da4SFelipe Balbi * union dwc3_event - representation of Event Buffer contents 123772246da4SFelipe Balbi * @raw: raw 32-bit event 123872246da4SFelipe Balbi * @type: the type of the event 123972246da4SFelipe Balbi * @depevt: Device Endpoint Event 124072246da4SFelipe Balbi * @devt: Device Event 124172246da4SFelipe Balbi * @gevt: Global Event 124272246da4SFelipe Balbi */ 124372246da4SFelipe Balbi union dwc3_event { 124472246da4SFelipe Balbi u32 raw; 124572246da4SFelipe Balbi struct dwc3_event_type type; 124672246da4SFelipe Balbi struct dwc3_event_depevt depevt; 124772246da4SFelipe Balbi struct dwc3_event_devt devt; 124872246da4SFelipe Balbi struct dwc3_event_gevt gevt; 124972246da4SFelipe Balbi }; 125072246da4SFelipe Balbi 125161018305SFelipe Balbi /** 125261018305SFelipe Balbi * struct dwc3_gadget_ep_cmd_params - representation of endpoint command 125361018305SFelipe Balbi * parameters 125461018305SFelipe Balbi * @param2: third parameter 125561018305SFelipe Balbi * @param1: second parameter 125661018305SFelipe Balbi * @param0: first parameter 125761018305SFelipe Balbi */ 125861018305SFelipe Balbi struct dwc3_gadget_ep_cmd_params { 125961018305SFelipe Balbi u32 param2; 126061018305SFelipe Balbi u32 param1; 126161018305SFelipe Balbi u32 param0; 126261018305SFelipe Balbi }; 126361018305SFelipe Balbi 126472246da4SFelipe Balbi /* 126572246da4SFelipe Balbi * DWC3 Features to be used as Driver Data 126672246da4SFelipe Balbi */ 126772246da4SFelipe Balbi 126872246da4SFelipe Balbi #define DWC3_HAS_PERIPHERAL BIT(0) 126972246da4SFelipe Balbi #define DWC3_HAS_XHCI BIT(1) 127072246da4SFelipe Balbi #define DWC3_HAS_OTG BIT(3) 127172246da4SFelipe Balbi 1272d07e8819SFelipe Balbi /* prototypes */ 1273*f09cc79bSRoger Quadros void dwc3_set_prtcap(struct dwc3 *dwc, u32 mode); 12743140e8cbSSebastian Andrzej Siewior void dwc3_set_mode(struct dwc3 *dwc, u32 mode); 1275cf6d867dSFelipe Balbi u32 dwc3_core_fifo_space(struct dwc3_ep *dep, u8 type); 12763140e8cbSSebastian Andrzej Siewior 1277a987a906SJohn Youn /* check whether we are on the DWC_usb3 core */ 1278a987a906SJohn Youn static inline bool dwc3_is_usb3(struct dwc3 *dwc) 1279a987a906SJohn Youn { 1280a987a906SJohn Youn return !(dwc->revision & DWC3_REVISION_IS_DWC31); 1281a987a906SJohn Youn } 1282a987a906SJohn Youn 1283c4137a9cSJohn Youn /* check whether we are on the DWC_usb31 core */ 1284c4137a9cSJohn Youn static inline bool dwc3_is_usb31(struct dwc3 *dwc) 1285c4137a9cSJohn Youn { 1286c4137a9cSJohn Youn return !!(dwc->revision & DWC3_REVISION_IS_DWC31); 1287c4137a9cSJohn Youn } 1288c4137a9cSJohn Youn 1289cf40b86bSJohn Youn bool dwc3_has_imod(struct dwc3 *dwc); 1290cf40b86bSJohn Youn 1291*f09cc79bSRoger Quadros int dwc3_event_buffers_setup(struct dwc3 *dwc); 1292*f09cc79bSRoger Quadros void dwc3_event_buffers_cleanup(struct dwc3 *dwc); 1293*f09cc79bSRoger Quadros 1294388e5c51SVivek Gautam #if IS_ENABLED(CONFIG_USB_DWC3_HOST) || IS_ENABLED(CONFIG_USB_DWC3_DUAL_ROLE) 1295d07e8819SFelipe Balbi int dwc3_host_init(struct dwc3 *dwc); 1296d07e8819SFelipe Balbi void dwc3_host_exit(struct dwc3 *dwc); 1297388e5c51SVivek Gautam #else 1298388e5c51SVivek Gautam static inline int dwc3_host_init(struct dwc3 *dwc) 1299388e5c51SVivek Gautam { return 0; } 1300388e5c51SVivek Gautam static inline void dwc3_host_exit(struct dwc3 *dwc) 1301388e5c51SVivek Gautam { } 1302388e5c51SVivek Gautam #endif 1303d07e8819SFelipe Balbi 1304388e5c51SVivek Gautam #if IS_ENABLED(CONFIG_USB_DWC3_GADGET) || IS_ENABLED(CONFIG_USB_DWC3_DUAL_ROLE) 1305f80b45e7SFelipe Balbi int dwc3_gadget_init(struct dwc3 *dwc); 1306f80b45e7SFelipe Balbi void dwc3_gadget_exit(struct dwc3 *dwc); 130761018305SFelipe Balbi int dwc3_gadget_set_test_mode(struct dwc3 *dwc, int mode); 130861018305SFelipe Balbi int dwc3_gadget_get_link_state(struct dwc3 *dwc); 130961018305SFelipe Balbi int dwc3_gadget_set_link_state(struct dwc3 *dwc, enum dwc3_link_state state); 13102cd4718dSFelipe Balbi int dwc3_send_gadget_ep_cmd(struct dwc3_ep *dep, unsigned cmd, 13112cd4718dSFelipe Balbi struct dwc3_gadget_ep_cmd_params *params); 13123ece0ec4SFelipe Balbi int dwc3_send_gadget_generic_command(struct dwc3 *dwc, unsigned cmd, u32 param); 1313388e5c51SVivek Gautam #else 1314388e5c51SVivek Gautam static inline int dwc3_gadget_init(struct dwc3 *dwc) 1315388e5c51SVivek Gautam { return 0; } 1316388e5c51SVivek Gautam static inline void dwc3_gadget_exit(struct dwc3 *dwc) 1317388e5c51SVivek Gautam { } 131861018305SFelipe Balbi static inline int dwc3_gadget_set_test_mode(struct dwc3 *dwc, int mode) 131961018305SFelipe Balbi { return 0; } 132061018305SFelipe Balbi static inline int dwc3_gadget_get_link_state(struct dwc3 *dwc) 132161018305SFelipe Balbi { return 0; } 132261018305SFelipe Balbi static inline int dwc3_gadget_set_link_state(struct dwc3 *dwc, 132361018305SFelipe Balbi enum dwc3_link_state state) 132461018305SFelipe Balbi { return 0; } 132561018305SFelipe Balbi 13262cd4718dSFelipe Balbi static inline int dwc3_send_gadget_ep_cmd(struct dwc3_ep *dep, unsigned cmd, 13272cd4718dSFelipe Balbi struct dwc3_gadget_ep_cmd_params *params) 132861018305SFelipe Balbi { return 0; } 132961018305SFelipe Balbi static inline int dwc3_send_gadget_generic_command(struct dwc3 *dwc, 133061018305SFelipe Balbi int cmd, u32 param) 133161018305SFelipe Balbi { return 0; } 1332388e5c51SVivek Gautam #endif 1333f80b45e7SFelipe Balbi 13349840354fSRoger Quadros #if IS_ENABLED(CONFIG_USB_DWC3_DUAL_ROLE) 13359840354fSRoger Quadros int dwc3_drd_init(struct dwc3 *dwc); 13369840354fSRoger Quadros void dwc3_drd_exit(struct dwc3 *dwc); 1337*f09cc79bSRoger Quadros void dwc3_otg_init(struct dwc3 *dwc); 1338*f09cc79bSRoger Quadros void dwc3_otg_exit(struct dwc3 *dwc); 1339*f09cc79bSRoger Quadros void dwc3_otg_update(struct dwc3 *dwc, bool ignore_idstatus); 1340*f09cc79bSRoger Quadros void dwc3_otg_host_init(struct dwc3 *dwc); 13419840354fSRoger Quadros #else 13429840354fSRoger Quadros static inline int dwc3_drd_init(struct dwc3 *dwc) 13439840354fSRoger Quadros { return 0; } 13449840354fSRoger Quadros static inline void dwc3_drd_exit(struct dwc3 *dwc) 13459840354fSRoger Quadros { } 1346*f09cc79bSRoger Quadros static inline void dwc3_otg_init(struct dwc3 *dwc) 1347*f09cc79bSRoger Quadros { } 1348*f09cc79bSRoger Quadros static inline void dwc3_otg_exit(struct dwc3 *dwc) 1349*f09cc79bSRoger Quadros { } 1350*f09cc79bSRoger Quadros static inline void dwc3_otg_update(struct dwc3 *dwc, bool ignore_idstatus) 1351*f09cc79bSRoger Quadros { } 1352*f09cc79bSRoger Quadros static inline void dwc3_otg_host_init(struct dwc3 *dwc) 1353*f09cc79bSRoger Quadros { } 13549840354fSRoger Quadros #endif 13559840354fSRoger Quadros 13567415f17cSFelipe Balbi /* power management interface */ 13577415f17cSFelipe Balbi #if !IS_ENABLED(CONFIG_USB_DWC3_HOST) 13587415f17cSFelipe Balbi int dwc3_gadget_suspend(struct dwc3 *dwc); 13597415f17cSFelipe Balbi int dwc3_gadget_resume(struct dwc3 *dwc); 1360fc8bb91bSFelipe Balbi void dwc3_gadget_process_pending_events(struct dwc3 *dwc); 13617415f17cSFelipe Balbi #else 13627415f17cSFelipe Balbi static inline int dwc3_gadget_suspend(struct dwc3 *dwc) 13637415f17cSFelipe Balbi { 13647415f17cSFelipe Balbi return 0; 13657415f17cSFelipe Balbi } 13667415f17cSFelipe Balbi 13677415f17cSFelipe Balbi static inline int dwc3_gadget_resume(struct dwc3 *dwc) 13687415f17cSFelipe Balbi { 13697415f17cSFelipe Balbi return 0; 13707415f17cSFelipe Balbi } 1371fc8bb91bSFelipe Balbi 1372fc8bb91bSFelipe Balbi static inline void dwc3_gadget_process_pending_events(struct dwc3 *dwc) 1373fc8bb91bSFelipe Balbi { 1374fc8bb91bSFelipe Balbi } 13757415f17cSFelipe Balbi #endif /* !IS_ENABLED(CONFIG_USB_DWC3_HOST) */ 13767415f17cSFelipe Balbi 137788bc9d19SHeikki Krogerus #if IS_ENABLED(CONFIG_USB_DWC3_ULPI) 137888bc9d19SHeikki Krogerus int dwc3_ulpi_init(struct dwc3 *dwc); 137988bc9d19SHeikki Krogerus void dwc3_ulpi_exit(struct dwc3 *dwc); 138088bc9d19SHeikki Krogerus #else 138188bc9d19SHeikki Krogerus static inline int dwc3_ulpi_init(struct dwc3 *dwc) 138288bc9d19SHeikki Krogerus { return 0; } 138388bc9d19SHeikki Krogerus static inline void dwc3_ulpi_exit(struct dwc3 *dwc) 138488bc9d19SHeikki Krogerus { } 138588bc9d19SHeikki Krogerus #endif 138688bc9d19SHeikki Krogerus 138772246da4SFelipe Balbi #endif /* __DRIVERS_USB_DWC3_CORE_H */ 1388