172246da4SFelipe Balbi /** 272246da4SFelipe Balbi * core.h - DesignWare USB3 DRD Core Header 372246da4SFelipe Balbi * 472246da4SFelipe Balbi * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com 572246da4SFelipe Balbi * 672246da4SFelipe Balbi * Authors: Felipe Balbi <balbi@ti.com>, 772246da4SFelipe Balbi * Sebastian Andrzej Siewior <bigeasy@linutronix.de> 872246da4SFelipe Balbi * 972246da4SFelipe Balbi * Redistribution and use in source and binary forms, with or without 1072246da4SFelipe Balbi * modification, are permitted provided that the following conditions 1172246da4SFelipe Balbi * are met: 1272246da4SFelipe Balbi * 1. Redistributions of source code must retain the above copyright 1372246da4SFelipe Balbi * notice, this list of conditions, and the following disclaimer, 1472246da4SFelipe Balbi * without modification. 1572246da4SFelipe Balbi * 2. Redistributions in binary form must reproduce the above copyright 1672246da4SFelipe Balbi * notice, this list of conditions and the following disclaimer in the 1772246da4SFelipe Balbi * documentation and/or other materials provided with the distribution. 1872246da4SFelipe Balbi * 3. The names of the above-listed copyright holders may not be used 1972246da4SFelipe Balbi * to endorse or promote products derived from this software without 2072246da4SFelipe Balbi * specific prior written permission. 2172246da4SFelipe Balbi * 2272246da4SFelipe Balbi * ALTERNATIVELY, this software may be distributed under the terms of the 2372246da4SFelipe Balbi * GNU General Public License ("GPL") version 2, as published by the Free 2472246da4SFelipe Balbi * Software Foundation. 2572246da4SFelipe Balbi * 2672246da4SFelipe Balbi * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS 2772246da4SFelipe Balbi * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 2872246da4SFelipe Balbi * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 2972246da4SFelipe Balbi * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR 3072246da4SFelipe Balbi * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 3172246da4SFelipe Balbi * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 3272246da4SFelipe Balbi * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 3372246da4SFelipe Balbi * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF 3472246da4SFelipe Balbi * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING 3572246da4SFelipe Balbi * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 3672246da4SFelipe Balbi * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 3772246da4SFelipe Balbi */ 3872246da4SFelipe Balbi 3972246da4SFelipe Balbi #ifndef __DRIVERS_USB_DWC3_CORE_H 4072246da4SFelipe Balbi #define __DRIVERS_USB_DWC3_CORE_H 4172246da4SFelipe Balbi 4272246da4SFelipe Balbi #include <linux/device.h> 4372246da4SFelipe Balbi #include <linux/spinlock.h> 44d07e8819SFelipe Balbi #include <linux/ioport.h> 4572246da4SFelipe Balbi #include <linux/list.h> 4672246da4SFelipe Balbi #include <linux/dma-mapping.h> 4772246da4SFelipe Balbi #include <linux/mm.h> 4872246da4SFelipe Balbi #include <linux/debugfs.h> 4972246da4SFelipe Balbi 5072246da4SFelipe Balbi #include <linux/usb/ch9.h> 5172246da4SFelipe Balbi #include <linux/usb/gadget.h> 5272246da4SFelipe Balbi 5372246da4SFelipe Balbi /* Global constants */ 5472246da4SFelipe Balbi #define DWC3_ENDPOINTS_NUM 32 5551249dcaSIdo Shayevitz #define DWC3_XHCI_RESOURCES_NUM 2 5672246da4SFelipe Balbi 5772246da4SFelipe Balbi #define DWC3_EVENT_BUFFERS_SIZE PAGE_SIZE 5872246da4SFelipe Balbi #define DWC3_EVENT_TYPE_MASK 0xfe 5972246da4SFelipe Balbi 6072246da4SFelipe Balbi #define DWC3_EVENT_TYPE_DEV 0 6172246da4SFelipe Balbi #define DWC3_EVENT_TYPE_CARKIT 3 6272246da4SFelipe Balbi #define DWC3_EVENT_TYPE_I2C 4 6372246da4SFelipe Balbi 6472246da4SFelipe Balbi #define DWC3_DEVICE_EVENT_DISCONNECT 0 6572246da4SFelipe Balbi #define DWC3_DEVICE_EVENT_RESET 1 6672246da4SFelipe Balbi #define DWC3_DEVICE_EVENT_CONNECT_DONE 2 6772246da4SFelipe Balbi #define DWC3_DEVICE_EVENT_LINK_STATUS_CHANGE 3 6872246da4SFelipe Balbi #define DWC3_DEVICE_EVENT_WAKEUP 4 6972246da4SFelipe Balbi #define DWC3_DEVICE_EVENT_EOPF 6 7072246da4SFelipe Balbi #define DWC3_DEVICE_EVENT_SOF 7 7172246da4SFelipe Balbi #define DWC3_DEVICE_EVENT_ERRATIC_ERROR 9 7272246da4SFelipe Balbi #define DWC3_DEVICE_EVENT_CMD_CMPL 10 7372246da4SFelipe Balbi #define DWC3_DEVICE_EVENT_OVERFLOW 11 7472246da4SFelipe Balbi 7572246da4SFelipe Balbi #define DWC3_GEVNTCOUNT_MASK 0xfffc 7672246da4SFelipe Balbi #define DWC3_GSNPSID_MASK 0xffff0000 7772246da4SFelipe Balbi #define DWC3_GSNPSREV_MASK 0xffff 7872246da4SFelipe Balbi 7951249dcaSIdo Shayevitz /* DWC3 registers memory space boundries */ 8051249dcaSIdo Shayevitz #define DWC3_XHCI_REGS_START 0x0 8151249dcaSIdo Shayevitz #define DWC3_XHCI_REGS_END 0x7fff 8251249dcaSIdo Shayevitz #define DWC3_GLOBALS_REGS_START 0xc100 8351249dcaSIdo Shayevitz #define DWC3_GLOBALS_REGS_END 0xc6ff 8451249dcaSIdo Shayevitz #define DWC3_DEVICE_REGS_START 0xc700 8551249dcaSIdo Shayevitz #define DWC3_DEVICE_REGS_END 0xcbff 8651249dcaSIdo Shayevitz #define DWC3_OTG_REGS_START 0xcc00 8751249dcaSIdo Shayevitz #define DWC3_OTG_REGS_END 0xccff 8851249dcaSIdo Shayevitz 8972246da4SFelipe Balbi /* Global Registers */ 9072246da4SFelipe Balbi #define DWC3_GSBUSCFG0 0xc100 9172246da4SFelipe Balbi #define DWC3_GSBUSCFG1 0xc104 9272246da4SFelipe Balbi #define DWC3_GTXTHRCFG 0xc108 9372246da4SFelipe Balbi #define DWC3_GRXTHRCFG 0xc10c 9472246da4SFelipe Balbi #define DWC3_GCTL 0xc110 9572246da4SFelipe Balbi #define DWC3_GEVTEN 0xc114 9672246da4SFelipe Balbi #define DWC3_GSTS 0xc118 9772246da4SFelipe Balbi #define DWC3_GSNPSID 0xc120 9872246da4SFelipe Balbi #define DWC3_GGPIO 0xc124 9972246da4SFelipe Balbi #define DWC3_GUID 0xc128 10072246da4SFelipe Balbi #define DWC3_GUCTL 0xc12c 10172246da4SFelipe Balbi #define DWC3_GBUSERRADDR0 0xc130 10272246da4SFelipe Balbi #define DWC3_GBUSERRADDR1 0xc134 10372246da4SFelipe Balbi #define DWC3_GPRTBIMAP0 0xc138 10472246da4SFelipe Balbi #define DWC3_GPRTBIMAP1 0xc13c 10572246da4SFelipe Balbi #define DWC3_GHWPARAMS0 0xc140 10672246da4SFelipe Balbi #define DWC3_GHWPARAMS1 0xc144 10772246da4SFelipe Balbi #define DWC3_GHWPARAMS2 0xc148 10872246da4SFelipe Balbi #define DWC3_GHWPARAMS3 0xc14c 10972246da4SFelipe Balbi #define DWC3_GHWPARAMS4 0xc150 11072246da4SFelipe Balbi #define DWC3_GHWPARAMS5 0xc154 11172246da4SFelipe Balbi #define DWC3_GHWPARAMS6 0xc158 11272246da4SFelipe Balbi #define DWC3_GHWPARAMS7 0xc15c 11372246da4SFelipe Balbi #define DWC3_GDBGFIFOSPACE 0xc160 11472246da4SFelipe Balbi #define DWC3_GDBGLTSSM 0xc164 11572246da4SFelipe Balbi #define DWC3_GPRTBIMAP_HS0 0xc180 11672246da4SFelipe Balbi #define DWC3_GPRTBIMAP_HS1 0xc184 11772246da4SFelipe Balbi #define DWC3_GPRTBIMAP_FS0 0xc188 11872246da4SFelipe Balbi #define DWC3_GPRTBIMAP_FS1 0xc18c 11972246da4SFelipe Balbi 12072246da4SFelipe Balbi #define DWC3_GUSB2PHYCFG(n) (0xc200 + (n * 0x04)) 12172246da4SFelipe Balbi #define DWC3_GUSB2I2CCTL(n) (0xc240 + (n * 0x04)) 12272246da4SFelipe Balbi 12372246da4SFelipe Balbi #define DWC3_GUSB2PHYACC(n) (0xc280 + (n * 0x04)) 12472246da4SFelipe Balbi 12572246da4SFelipe Balbi #define DWC3_GUSB3PIPECTL(n) (0xc2c0 + (n * 0x04)) 12672246da4SFelipe Balbi 12772246da4SFelipe Balbi #define DWC3_GTXFIFOSIZ(n) (0xc300 + (n * 0x04)) 12872246da4SFelipe Balbi #define DWC3_GRXFIFOSIZ(n) (0xc380 + (n * 0x04)) 12972246da4SFelipe Balbi 13072246da4SFelipe Balbi #define DWC3_GEVNTADRLO(n) (0xc400 + (n * 0x10)) 13172246da4SFelipe Balbi #define DWC3_GEVNTADRHI(n) (0xc404 + (n * 0x10)) 13272246da4SFelipe Balbi #define DWC3_GEVNTSIZ(n) (0xc408 + (n * 0x10)) 13372246da4SFelipe Balbi #define DWC3_GEVNTCOUNT(n) (0xc40c + (n * 0x10)) 13472246da4SFelipe Balbi 13572246da4SFelipe Balbi #define DWC3_GHWPARAMS8 0xc600 13672246da4SFelipe Balbi 13772246da4SFelipe Balbi /* Device Registers */ 13872246da4SFelipe Balbi #define DWC3_DCFG 0xc700 13972246da4SFelipe Balbi #define DWC3_DCTL 0xc704 14072246da4SFelipe Balbi #define DWC3_DEVTEN 0xc708 14172246da4SFelipe Balbi #define DWC3_DSTS 0xc70c 14272246da4SFelipe Balbi #define DWC3_DGCMDPAR 0xc710 14372246da4SFelipe Balbi #define DWC3_DGCMD 0xc714 14472246da4SFelipe Balbi #define DWC3_DALEPENA 0xc720 14572246da4SFelipe Balbi #define DWC3_DEPCMDPAR2(n) (0xc800 + (n * 0x10)) 14672246da4SFelipe Balbi #define DWC3_DEPCMDPAR1(n) (0xc804 + (n * 0x10)) 14772246da4SFelipe Balbi #define DWC3_DEPCMDPAR0(n) (0xc808 + (n * 0x10)) 14872246da4SFelipe Balbi #define DWC3_DEPCMD(n) (0xc80c + (n * 0x10)) 14972246da4SFelipe Balbi 15072246da4SFelipe Balbi /* OTG Registers */ 15172246da4SFelipe Balbi #define DWC3_OCFG 0xcc00 15272246da4SFelipe Balbi #define DWC3_OCTL 0xcc04 15372246da4SFelipe Balbi #define DWC3_OEVTEN 0xcc08 15472246da4SFelipe Balbi #define DWC3_OSTS 0xcc0C 15572246da4SFelipe Balbi 15672246da4SFelipe Balbi /* Bit fields */ 15772246da4SFelipe Balbi 15872246da4SFelipe Balbi /* Global Configuration Register */ 1591d046793SPaul Zimmerman #define DWC3_GCTL_PWRDNSCALE(n) ((n) << 19) 160f4aadbe4SFelipe Balbi #define DWC3_GCTL_U2RSTECN (1 << 16) 1611d046793SPaul Zimmerman #define DWC3_GCTL_RAMCLKSEL(x) (((x) & DWC3_GCTL_CLK_MASK) << 6) 16272246da4SFelipe Balbi #define DWC3_GCTL_CLK_BUS (0) 16372246da4SFelipe Balbi #define DWC3_GCTL_CLK_PIPE (1) 16472246da4SFelipe Balbi #define DWC3_GCTL_CLK_PIPEHALF (2) 16572246da4SFelipe Balbi #define DWC3_GCTL_CLK_MASK (3) 16672246da4SFelipe Balbi 1670b9fe32dSFelipe Balbi #define DWC3_GCTL_PRTCAP(n) (((n) & (3 << 12)) >> 12) 1681d046793SPaul Zimmerman #define DWC3_GCTL_PRTCAPDIR(n) ((n) << 12) 16972246da4SFelipe Balbi #define DWC3_GCTL_PRTCAP_HOST 1 17072246da4SFelipe Balbi #define DWC3_GCTL_PRTCAP_DEVICE 2 17172246da4SFelipe Balbi #define DWC3_GCTL_PRTCAP_OTG 3 17272246da4SFelipe Balbi 17372246da4SFelipe Balbi #define DWC3_GCTL_CORESOFTRESET (1 << 11) 1741d046793SPaul Zimmerman #define DWC3_GCTL_SCALEDOWN(n) ((n) << 4) 1753e87c42aSPaul Zimmerman #define DWC3_GCTL_SCALEDOWN_MASK DWC3_GCTL_SCALEDOWN(3) 17672246da4SFelipe Balbi #define DWC3_GCTL_DISSCRAMBLE (1 << 3) 177aabb7075SFelipe Balbi #define DWC3_GCTL_DSBLCLKGTNG (1 << 0) 17872246da4SFelipe Balbi 17972246da4SFelipe Balbi /* Global USB2 PHY Configuration Register */ 18072246da4SFelipe Balbi #define DWC3_GUSB2PHYCFG_PHYSOFTRST (1 << 31) 18172246da4SFelipe Balbi #define DWC3_GUSB2PHYCFG_SUSPHY (1 << 6) 18272246da4SFelipe Balbi 18372246da4SFelipe Balbi /* Global USB3 PIPE Control Register */ 18472246da4SFelipe Balbi #define DWC3_GUSB3PIPECTL_PHYSOFTRST (1 << 31) 18572246da4SFelipe Balbi #define DWC3_GUSB3PIPECTL_SUSPHY (1 << 17) 18672246da4SFelipe Balbi 187457e84b6SFelipe Balbi /* Global TX Fifo Size Register */ 188457e84b6SFelipe Balbi #define DWC3_GTXFIFOSIZ_TXFDEF(n) ((n) & 0xffff) 189457e84b6SFelipe Balbi #define DWC3_GTXFIFOSIZ_TXFSTADDR(n) ((n) & 0xffff0000) 190457e84b6SFelipe Balbi 191aabb7075SFelipe Balbi /* Global HWPARAMS1 Register */ 1921d046793SPaul Zimmerman #define DWC3_GHWPARAMS1_EN_PWROPT(n) (((n) & (3 << 24)) >> 24) 193aabb7075SFelipe Balbi #define DWC3_GHWPARAMS1_EN_PWROPT_NO 0 194aabb7075SFelipe Balbi #define DWC3_GHWPARAMS1_EN_PWROPT_CLK 1 195aabb7075SFelipe Balbi 19672246da4SFelipe Balbi /* Device Configuration Register */ 197e6a3b5e2SSebastian Andrzej Siewior #define DWC3_DCFG_LPM_CAP (1 << 22) 19872246da4SFelipe Balbi #define DWC3_DCFG_DEVADDR(addr) ((addr) << 3) 19972246da4SFelipe Balbi #define DWC3_DCFG_DEVADDR_MASK DWC3_DCFG_DEVADDR(0x7f) 20072246da4SFelipe Balbi 20172246da4SFelipe Balbi #define DWC3_DCFG_SPEED_MASK (7 << 0) 20272246da4SFelipe Balbi #define DWC3_DCFG_SUPERSPEED (4 << 0) 20372246da4SFelipe Balbi #define DWC3_DCFG_HIGHSPEED (0 << 0) 20472246da4SFelipe Balbi #define DWC3_DCFG_FULLSPEED2 (1 << 0) 20572246da4SFelipe Balbi #define DWC3_DCFG_LOWSPEED (2 << 0) 20672246da4SFelipe Balbi #define DWC3_DCFG_FULLSPEED1 (3 << 0) 20772246da4SFelipe Balbi 20872246da4SFelipe Balbi /* Device Control Register */ 20972246da4SFelipe Balbi #define DWC3_DCTL_RUN_STOP (1 << 31) 21072246da4SFelipe Balbi #define DWC3_DCTL_CSFTRST (1 << 30) 21172246da4SFelipe Balbi #define DWC3_DCTL_LSFTRST (1 << 29) 21272246da4SFelipe Balbi 21372246da4SFelipe Balbi #define DWC3_DCTL_HIRD_THRES_MASK (0x1f << 24) 21472246da4SFelipe Balbi #define DWC3_DCTL_HIRD_THRES(n) (((n) & DWC3_DCTL_HIRD_THRES_MASK) >> 24) 21572246da4SFelipe Balbi 21672246da4SFelipe Balbi #define DWC3_DCTL_APPL1RES (1 << 23) 21772246da4SFelipe Balbi 2188db7ed15SFelipe Balbi #define DWC3_DCTL_TRGTULST_MASK (0x0f << 17) 2198db7ed15SFelipe Balbi #define DWC3_DCTL_TRGTULST(n) ((n) << 17) 2208db7ed15SFelipe Balbi 2218db7ed15SFelipe Balbi #define DWC3_DCTL_TRGTULST_U2 (DWC3_DCTL_TRGTULST(2)) 2228db7ed15SFelipe Balbi #define DWC3_DCTL_TRGTULST_U3 (DWC3_DCTL_TRGTULST(3)) 2238db7ed15SFelipe Balbi #define DWC3_DCTL_TRGTULST_SS_DIS (DWC3_DCTL_TRGTULST(4)) 2248db7ed15SFelipe Balbi #define DWC3_DCTL_TRGTULST_RX_DET (DWC3_DCTL_TRGTULST(5)) 2258db7ed15SFelipe Balbi #define DWC3_DCTL_TRGTULST_SS_INACT (DWC3_DCTL_TRGTULST(6)) 2268db7ed15SFelipe Balbi 22772246da4SFelipe Balbi #define DWC3_DCTL_INITU2ENA (1 << 12) 22872246da4SFelipe Balbi #define DWC3_DCTL_ACCEPTU2ENA (1 << 11) 22972246da4SFelipe Balbi #define DWC3_DCTL_INITU1ENA (1 << 10) 23072246da4SFelipe Balbi #define DWC3_DCTL_ACCEPTU1ENA (1 << 9) 23172246da4SFelipe Balbi #define DWC3_DCTL_TSTCTRL_MASK (0xf << 1) 23272246da4SFelipe Balbi 23372246da4SFelipe Balbi #define DWC3_DCTL_ULSTCHNGREQ_MASK (0x0f << 5) 23472246da4SFelipe Balbi #define DWC3_DCTL_ULSTCHNGREQ(n) (((n) << 5) & DWC3_DCTL_ULSTCHNGREQ_MASK) 23572246da4SFelipe Balbi 23672246da4SFelipe Balbi #define DWC3_DCTL_ULSTCHNG_NO_ACTION (DWC3_DCTL_ULSTCHNGREQ(0)) 23772246da4SFelipe Balbi #define DWC3_DCTL_ULSTCHNG_SS_DISABLED (DWC3_DCTL_ULSTCHNGREQ(4)) 23872246da4SFelipe Balbi #define DWC3_DCTL_ULSTCHNG_RX_DETECT (DWC3_DCTL_ULSTCHNGREQ(5)) 23972246da4SFelipe Balbi #define DWC3_DCTL_ULSTCHNG_SS_INACTIVE (DWC3_DCTL_ULSTCHNGREQ(6)) 24072246da4SFelipe Balbi #define DWC3_DCTL_ULSTCHNG_RECOVERY (DWC3_DCTL_ULSTCHNGREQ(8)) 24172246da4SFelipe Balbi #define DWC3_DCTL_ULSTCHNG_COMPLIANCE (DWC3_DCTL_ULSTCHNGREQ(10)) 24272246da4SFelipe Balbi #define DWC3_DCTL_ULSTCHNG_LOOPBACK (DWC3_DCTL_ULSTCHNGREQ(11)) 24372246da4SFelipe Balbi 24472246da4SFelipe Balbi /* Device Event Enable Register */ 24572246da4SFelipe Balbi #define DWC3_DEVTEN_VNDRDEVTSTRCVEDEN (1 << 12) 24672246da4SFelipe Balbi #define DWC3_DEVTEN_EVNTOVERFLOWEN (1 << 11) 24772246da4SFelipe Balbi #define DWC3_DEVTEN_CMDCMPLTEN (1 << 10) 24872246da4SFelipe Balbi #define DWC3_DEVTEN_ERRTICERREN (1 << 9) 24972246da4SFelipe Balbi #define DWC3_DEVTEN_SOFEN (1 << 7) 25072246da4SFelipe Balbi #define DWC3_DEVTEN_EOPFEN (1 << 6) 25172246da4SFelipe Balbi #define DWC3_DEVTEN_WKUPEVTEN (1 << 4) 25272246da4SFelipe Balbi #define DWC3_DEVTEN_ULSTCNGEN (1 << 3) 25372246da4SFelipe Balbi #define DWC3_DEVTEN_CONNECTDONEEN (1 << 2) 25472246da4SFelipe Balbi #define DWC3_DEVTEN_USBRSTEN (1 << 1) 25572246da4SFelipe Balbi #define DWC3_DEVTEN_DISCONNEVTEN (1 << 0) 25672246da4SFelipe Balbi 25772246da4SFelipe Balbi /* Device Status Register */ 25872246da4SFelipe Balbi #define DWC3_DSTS_PWRUPREQ (1 << 24) 25972246da4SFelipe Balbi #define DWC3_DSTS_COREIDLE (1 << 23) 26072246da4SFelipe Balbi #define DWC3_DSTS_DEVCTRLHLT (1 << 22) 26172246da4SFelipe Balbi 26272246da4SFelipe Balbi #define DWC3_DSTS_USBLNKST_MASK (0x0f << 18) 26372246da4SFelipe Balbi #define DWC3_DSTS_USBLNKST(n) (((n) & DWC3_DSTS_USBLNKST_MASK) >> 18) 26472246da4SFelipe Balbi 26572246da4SFelipe Balbi #define DWC3_DSTS_RXFIFOEMPTY (1 << 17) 26672246da4SFelipe Balbi 26772246da4SFelipe Balbi #define DWC3_DSTS_SOFFN_MASK (0x3ff << 3) 26872246da4SFelipe Balbi #define DWC3_DSTS_SOFFN(n) (((n) & DWC3_DSTS_SOFFN_MASK) >> 3) 26972246da4SFelipe Balbi 27072246da4SFelipe Balbi #define DWC3_DSTS_CONNECTSPD (7 << 0) 27172246da4SFelipe Balbi 27272246da4SFelipe Balbi #define DWC3_DSTS_SUPERSPEED (4 << 0) 27372246da4SFelipe Balbi #define DWC3_DSTS_HIGHSPEED (0 << 0) 27472246da4SFelipe Balbi #define DWC3_DSTS_FULLSPEED2 (1 << 0) 27572246da4SFelipe Balbi #define DWC3_DSTS_LOWSPEED (2 << 0) 27672246da4SFelipe Balbi #define DWC3_DSTS_FULLSPEED1 (3 << 0) 27772246da4SFelipe Balbi 27872246da4SFelipe Balbi /* Device Generic Command Register */ 27972246da4SFelipe Balbi #define DWC3_DGCMD_SET_LMP 0x01 28072246da4SFelipe Balbi #define DWC3_DGCMD_SET_PERIODIC_PAR 0x02 28172246da4SFelipe Balbi #define DWC3_DGCMD_XMIT_FUNCTION 0x03 28272246da4SFelipe Balbi #define DWC3_DGCMD_SELECTED_FIFO_FLUSH 0x09 28372246da4SFelipe Balbi #define DWC3_DGCMD_ALL_FIFO_FLUSH 0x0a 28472246da4SFelipe Balbi #define DWC3_DGCMD_SET_ENDPOINT_NRDY 0x0c 28572246da4SFelipe Balbi #define DWC3_DGCMD_RUN_SOC_BUS_LOOPBACK 0x10 28672246da4SFelipe Balbi 287b09bb642SFelipe Balbi #define DWC3_DGCMD_STATUS(n) (((n) >> 15) & 1) 288b09bb642SFelipe Balbi #define DWC3_DGCMD_CMDACT (1 << 10) 289b09bb642SFelipe Balbi 29072246da4SFelipe Balbi /* Device Endpoint Command Register */ 29172246da4SFelipe Balbi #define DWC3_DEPCMD_PARAM_SHIFT 16 2921d046793SPaul Zimmerman #define DWC3_DEPCMD_PARAM(x) ((x) << DWC3_DEPCMD_PARAM_SHIFT) 2931d046793SPaul Zimmerman #define DWC3_DEPCMD_GET_RSC_IDX(x) (((x) >> DWC3_DEPCMD_PARAM_SHIFT) & 0x7f) 294b09bb642SFelipe Balbi #define DWC3_DEPCMD_STATUS(x) (((x) >> 15) & 1) 29572246da4SFelipe Balbi #define DWC3_DEPCMD_HIPRI_FORCERM (1 << 11) 29672246da4SFelipe Balbi #define DWC3_DEPCMD_CMDACT (1 << 10) 29772246da4SFelipe Balbi #define DWC3_DEPCMD_CMDIOC (1 << 8) 29872246da4SFelipe Balbi 29972246da4SFelipe Balbi #define DWC3_DEPCMD_DEPSTARTCFG (0x09 << 0) 30072246da4SFelipe Balbi #define DWC3_DEPCMD_ENDTRANSFER (0x08 << 0) 30172246da4SFelipe Balbi #define DWC3_DEPCMD_UPDATETRANSFER (0x07 << 0) 30272246da4SFelipe Balbi #define DWC3_DEPCMD_STARTTRANSFER (0x06 << 0) 30372246da4SFelipe Balbi #define DWC3_DEPCMD_CLEARSTALL (0x05 << 0) 30472246da4SFelipe Balbi #define DWC3_DEPCMD_SETSTALL (0x04 << 0) 30572246da4SFelipe Balbi #define DWC3_DEPCMD_GETSEQNUMBER (0x03 << 0) 30672246da4SFelipe Balbi #define DWC3_DEPCMD_SETTRANSFRESOURCE (0x02 << 0) 30772246da4SFelipe Balbi #define DWC3_DEPCMD_SETEPCONFIG (0x01 << 0) 30872246da4SFelipe Balbi 30972246da4SFelipe Balbi /* The EP number goes 0..31 so ep0 is always out and ep1 is always in */ 31072246da4SFelipe Balbi #define DWC3_DALEPENA_EP(n) (1 << n) 31172246da4SFelipe Balbi 31272246da4SFelipe Balbi #define DWC3_DEPCMD_TYPE_CONTROL 0 31372246da4SFelipe Balbi #define DWC3_DEPCMD_TYPE_ISOC 1 31472246da4SFelipe Balbi #define DWC3_DEPCMD_TYPE_BULK 2 31572246da4SFelipe Balbi #define DWC3_DEPCMD_TYPE_INTR 3 31672246da4SFelipe Balbi 31772246da4SFelipe Balbi /* Structures */ 31872246da4SFelipe Balbi 319f6bafc6aSFelipe Balbi struct dwc3_trb; 32072246da4SFelipe Balbi 32172246da4SFelipe Balbi /** 32272246da4SFelipe Balbi * struct dwc3_event_buffer - Software event buffer representation 32372246da4SFelipe Balbi * @list: a list of event buffers 32472246da4SFelipe Balbi * @buf: _THE_ buffer 32572246da4SFelipe Balbi * @length: size of this buffer 32672246da4SFelipe Balbi * @dma: dma_addr_t 32772246da4SFelipe Balbi * @dwc: pointer to DWC controller 32872246da4SFelipe Balbi */ 32972246da4SFelipe Balbi struct dwc3_event_buffer { 33072246da4SFelipe Balbi void *buf; 33172246da4SFelipe Balbi unsigned length; 33272246da4SFelipe Balbi unsigned int lpos; 33372246da4SFelipe Balbi 33472246da4SFelipe Balbi dma_addr_t dma; 33572246da4SFelipe Balbi 33672246da4SFelipe Balbi struct dwc3 *dwc; 33772246da4SFelipe Balbi }; 33872246da4SFelipe Balbi 33972246da4SFelipe Balbi #define DWC3_EP_FLAG_STALLED (1 << 0) 34072246da4SFelipe Balbi #define DWC3_EP_FLAG_WEDGED (1 << 1) 34172246da4SFelipe Balbi 34272246da4SFelipe Balbi #define DWC3_EP_DIRECTION_TX true 34372246da4SFelipe Balbi #define DWC3_EP_DIRECTION_RX false 34472246da4SFelipe Balbi 34572246da4SFelipe Balbi #define DWC3_TRB_NUM 32 34672246da4SFelipe Balbi #define DWC3_TRB_MASK (DWC3_TRB_NUM - 1) 34772246da4SFelipe Balbi 34872246da4SFelipe Balbi /** 34972246da4SFelipe Balbi * struct dwc3_ep - device side endpoint representation 35072246da4SFelipe Balbi * @endpoint: usb endpoint 35172246da4SFelipe Balbi * @request_list: list of requests for this endpoint 35272246da4SFelipe Balbi * @req_queued: list of requests on this ep which have TRBs setup 35372246da4SFelipe Balbi * @trb_pool: array of transaction buffers 35472246da4SFelipe Balbi * @trb_pool_dma: dma address of @trb_pool 35572246da4SFelipe Balbi * @free_slot: next slot which is going to be used 35672246da4SFelipe Balbi * @busy_slot: first slot which is owned by HW 35772246da4SFelipe Balbi * @desc: usb_endpoint_descriptor pointer 35872246da4SFelipe Balbi * @dwc: pointer to DWC controller 35972246da4SFelipe Balbi * @flags: endpoint flags (wedged, stalled, ...) 36072246da4SFelipe Balbi * @current_trb: index of current used trb 36172246da4SFelipe Balbi * @number: endpoint number (1 - 15) 36272246da4SFelipe Balbi * @type: set to bmAttributes & USB_ENDPOINT_XFERTYPE_MASK 36372246da4SFelipe Balbi * @res_trans_idx: Resource transfer index 36472246da4SFelipe Balbi * @interval: the intervall on which the ISOC transfer is started 36572246da4SFelipe Balbi * @name: a human readable name e.g. ep1out-bulk 36672246da4SFelipe Balbi * @direction: true for TX, false for RX 367879631aaSFelipe Balbi * @stream_capable: true when streams are enabled 36872246da4SFelipe Balbi */ 36972246da4SFelipe Balbi struct dwc3_ep { 37072246da4SFelipe Balbi struct usb_ep endpoint; 37172246da4SFelipe Balbi struct list_head request_list; 37272246da4SFelipe Balbi struct list_head req_queued; 37372246da4SFelipe Balbi 374f6bafc6aSFelipe Balbi struct dwc3_trb *trb_pool; 37572246da4SFelipe Balbi dma_addr_t trb_pool_dma; 37672246da4SFelipe Balbi u32 free_slot; 37772246da4SFelipe Balbi u32 busy_slot; 37872246da4SFelipe Balbi const struct usb_endpoint_descriptor *desc; 379c90bfaecSFelipe Balbi const struct usb_ss_ep_comp_descriptor *comp_desc; 38072246da4SFelipe Balbi struct dwc3 *dwc; 38172246da4SFelipe Balbi 38272246da4SFelipe Balbi unsigned flags; 38372246da4SFelipe Balbi #define DWC3_EP_ENABLED (1 << 0) 38472246da4SFelipe Balbi #define DWC3_EP_STALL (1 << 1) 38572246da4SFelipe Balbi #define DWC3_EP_WEDGE (1 << 2) 38672246da4SFelipe Balbi #define DWC3_EP_BUSY (1 << 4) 38772246da4SFelipe Balbi #define DWC3_EP_PENDING_REQUEST (1 << 5) 38872246da4SFelipe Balbi 389984f66a6SFelipe Balbi /* This last one is specific to EP0 */ 390984f66a6SFelipe Balbi #define DWC3_EP0_DIR_IN (1 << 31) 391984f66a6SFelipe Balbi 39272246da4SFelipe Balbi unsigned current_trb; 39372246da4SFelipe Balbi 39472246da4SFelipe Balbi u8 number; 39572246da4SFelipe Balbi u8 type; 39672246da4SFelipe Balbi u8 res_trans_idx; 39772246da4SFelipe Balbi u32 interval; 39872246da4SFelipe Balbi 39972246da4SFelipe Balbi char name[20]; 40072246da4SFelipe Balbi 40172246da4SFelipe Balbi unsigned direction:1; 402879631aaSFelipe Balbi unsigned stream_capable:1; 40372246da4SFelipe Balbi }; 40472246da4SFelipe Balbi 40572246da4SFelipe Balbi enum dwc3_phy { 40672246da4SFelipe Balbi DWC3_PHY_UNKNOWN = 0, 40772246da4SFelipe Balbi DWC3_PHY_USB3, 40872246da4SFelipe Balbi DWC3_PHY_USB2, 40972246da4SFelipe Balbi }; 41072246da4SFelipe Balbi 411b53c772dSFelipe Balbi enum dwc3_ep0_next { 412b53c772dSFelipe Balbi DWC3_EP0_UNKNOWN = 0, 413b53c772dSFelipe Balbi DWC3_EP0_COMPLETE, 414b53c772dSFelipe Balbi DWC3_EP0_NRDY_SETUP, 415b53c772dSFelipe Balbi DWC3_EP0_NRDY_DATA, 416b53c772dSFelipe Balbi DWC3_EP0_NRDY_STATUS, 417b53c772dSFelipe Balbi }; 418b53c772dSFelipe Balbi 41972246da4SFelipe Balbi enum dwc3_ep0_state { 42072246da4SFelipe Balbi EP0_UNCONNECTED = 0, 421c7fcdeb2SFelipe Balbi EP0_SETUP_PHASE, 422c7fcdeb2SFelipe Balbi EP0_DATA_PHASE, 423c7fcdeb2SFelipe Balbi EP0_STATUS_PHASE, 42472246da4SFelipe Balbi }; 42572246da4SFelipe Balbi 42672246da4SFelipe Balbi enum dwc3_link_state { 42772246da4SFelipe Balbi /* In SuperSpeed */ 42872246da4SFelipe Balbi DWC3_LINK_STATE_U0 = 0x00, /* in HS, means ON */ 42972246da4SFelipe Balbi DWC3_LINK_STATE_U1 = 0x01, 43072246da4SFelipe Balbi DWC3_LINK_STATE_U2 = 0x02, /* in HS, means SLEEP */ 43172246da4SFelipe Balbi DWC3_LINK_STATE_U3 = 0x03, /* in HS, means SUSPEND */ 43272246da4SFelipe Balbi DWC3_LINK_STATE_SS_DIS = 0x04, 43372246da4SFelipe Balbi DWC3_LINK_STATE_RX_DET = 0x05, /* in HS, means Early Suspend */ 43472246da4SFelipe Balbi DWC3_LINK_STATE_SS_INACT = 0x06, 43572246da4SFelipe Balbi DWC3_LINK_STATE_POLL = 0x07, 43672246da4SFelipe Balbi DWC3_LINK_STATE_RECOV = 0x08, 43772246da4SFelipe Balbi DWC3_LINK_STATE_HRESET = 0x09, 43872246da4SFelipe Balbi DWC3_LINK_STATE_CMPLY = 0x0a, 43972246da4SFelipe Balbi DWC3_LINK_STATE_LPBK = 0x0b, 44072246da4SFelipe Balbi DWC3_LINK_STATE_MASK = 0x0f, 44172246da4SFelipe Balbi }; 44272246da4SFelipe Balbi 44372246da4SFelipe Balbi enum dwc3_device_state { 44472246da4SFelipe Balbi DWC3_DEFAULT_STATE, 44572246da4SFelipe Balbi DWC3_ADDRESS_STATE, 44672246da4SFelipe Balbi DWC3_CONFIGURED_STATE, 44772246da4SFelipe Balbi }; 44872246da4SFelipe Balbi 449f6bafc6aSFelipe Balbi /* TRB Length, PCM and Status */ 450f6bafc6aSFelipe Balbi #define DWC3_TRB_SIZE_MASK (0x00ffffff) 451f6bafc6aSFelipe Balbi #define DWC3_TRB_SIZE_LENGTH(n) ((n) & DWC3_TRB_SIZE_MASK) 452f6bafc6aSFelipe Balbi #define DWC3_TRB_SIZE_PCM1(n) (((n) & 0x03) << 24) 453f6bafc6aSFelipe Balbi #define DWC3_TRB_SIZE_TRBSTS(n) (((n) & (0x0f << 28) >> 28)) 45472246da4SFelipe Balbi 455f6bafc6aSFelipe Balbi #define DWC3_TRBSTS_OK 0 456f6bafc6aSFelipe Balbi #define DWC3_TRBSTS_MISSED_ISOC 1 457f6bafc6aSFelipe Balbi #define DWC3_TRBSTS_SETUP_PENDING 2 45872246da4SFelipe Balbi 459f6bafc6aSFelipe Balbi /* TRB Control */ 460f6bafc6aSFelipe Balbi #define DWC3_TRB_CTRL_HWO (1 << 0) 461f6bafc6aSFelipe Balbi #define DWC3_TRB_CTRL_LST (1 << 1) 462f6bafc6aSFelipe Balbi #define DWC3_TRB_CTRL_CHN (1 << 2) 463f6bafc6aSFelipe Balbi #define DWC3_TRB_CTRL_CSP (1 << 3) 464f6bafc6aSFelipe Balbi #define DWC3_TRB_CTRL_TRBCTL(n) (((n) & 0x3f) << 4) 465f6bafc6aSFelipe Balbi #define DWC3_TRB_CTRL_ISP_IMI (1 << 10) 466f6bafc6aSFelipe Balbi #define DWC3_TRB_CTRL_IOC (1 << 11) 467f6bafc6aSFelipe Balbi #define DWC3_TRB_CTRL_SID_SOFN(n) (((n) & 0xffff) << 14) 468f6bafc6aSFelipe Balbi 469f6bafc6aSFelipe Balbi #define DWC3_TRBCTL_NORMAL DWC3_TRB_CTRL_TRBCTL(1) 470f6bafc6aSFelipe Balbi #define DWC3_TRBCTL_CONTROL_SETUP DWC3_TRB_CTRL_TRBCTL(2) 471f6bafc6aSFelipe Balbi #define DWC3_TRBCTL_CONTROL_STATUS2 DWC3_TRB_CTRL_TRBCTL(3) 472f6bafc6aSFelipe Balbi #define DWC3_TRBCTL_CONTROL_STATUS3 DWC3_TRB_CTRL_TRBCTL(4) 473f6bafc6aSFelipe Balbi #define DWC3_TRBCTL_CONTROL_DATA DWC3_TRB_CTRL_TRBCTL(5) 474f6bafc6aSFelipe Balbi #define DWC3_TRBCTL_ISOCHRONOUS_FIRST DWC3_TRB_CTRL_TRBCTL(6) 475f6bafc6aSFelipe Balbi #define DWC3_TRBCTL_ISOCHRONOUS DWC3_TRB_CTRL_TRBCTL(7) 476f6bafc6aSFelipe Balbi #define DWC3_TRBCTL_LINK_TRB DWC3_TRB_CTRL_TRBCTL(8) 47772246da4SFelipe Balbi 47872246da4SFelipe Balbi /** 479f6bafc6aSFelipe Balbi * struct dwc3_trb - transfer request block (hw format) 48072246da4SFelipe Balbi * @bpl: DW0-3 48172246da4SFelipe Balbi * @bph: DW4-7 48272246da4SFelipe Balbi * @size: DW8-B 48372246da4SFelipe Balbi * @trl: DWC-F 48472246da4SFelipe Balbi */ 485f6bafc6aSFelipe Balbi struct dwc3_trb { 486f6bafc6aSFelipe Balbi u32 bpl; 487f6bafc6aSFelipe Balbi u32 bph; 488f6bafc6aSFelipe Balbi u32 size; 489f6bafc6aSFelipe Balbi u32 ctrl; 49072246da4SFelipe Balbi } __packed; 49172246da4SFelipe Balbi 49272246da4SFelipe Balbi /** 493a3299499SFelipe Balbi * dwc3_hwparams - copy of HWPARAMS registers 494a3299499SFelipe Balbi * @hwparams0 - GHWPARAMS0 495a3299499SFelipe Balbi * @hwparams1 - GHWPARAMS1 496a3299499SFelipe Balbi * @hwparams2 - GHWPARAMS2 497a3299499SFelipe Balbi * @hwparams3 - GHWPARAMS3 498a3299499SFelipe Balbi * @hwparams4 - GHWPARAMS4 499a3299499SFelipe Balbi * @hwparams5 - GHWPARAMS5 500a3299499SFelipe Balbi * @hwparams6 - GHWPARAMS6 501a3299499SFelipe Balbi * @hwparams7 - GHWPARAMS7 502a3299499SFelipe Balbi * @hwparams8 - GHWPARAMS8 503a3299499SFelipe Balbi */ 504a3299499SFelipe Balbi struct dwc3_hwparams { 505a3299499SFelipe Balbi u32 hwparams0; 506a3299499SFelipe Balbi u32 hwparams1; 507a3299499SFelipe Balbi u32 hwparams2; 508a3299499SFelipe Balbi u32 hwparams3; 509a3299499SFelipe Balbi u32 hwparams4; 510a3299499SFelipe Balbi u32 hwparams5; 511a3299499SFelipe Balbi u32 hwparams6; 512a3299499SFelipe Balbi u32 hwparams7; 513a3299499SFelipe Balbi u32 hwparams8; 514a3299499SFelipe Balbi }; 515a3299499SFelipe Balbi 5160949e99bSFelipe Balbi /* HWPARAMS0 */ 5170949e99bSFelipe Balbi #define DWC3_MODE(n) ((n) & 0x7) 5180949e99bSFelipe Balbi 5190949e99bSFelipe Balbi #define DWC3_MODE_DEVICE 0 5200949e99bSFelipe Balbi #define DWC3_MODE_HOST 1 5210949e99bSFelipe Balbi #define DWC3_MODE_DRD 2 5220949e99bSFelipe Balbi #define DWC3_MODE_HUB 3 5230949e99bSFelipe Balbi 524457e84b6SFelipe Balbi #define DWC3_MDWIDTH(n) (((n) & 0xff00) >> 8) 525457e84b6SFelipe Balbi 5260949e99bSFelipe Balbi /* HWPARAMS1 */ 5279f622b2aSFelipe Balbi #define DWC3_NUM_INT(n) (((n) & (0x3f << 15)) >> 15) 5289f622b2aSFelipe Balbi 529457e84b6SFelipe Balbi /* HWPARAMS7 */ 530457e84b6SFelipe Balbi #define DWC3_RAM1_DEPTH(n) ((n) & 0xffff) 531457e84b6SFelipe Balbi 532e0ce0b0aSSebastian Andrzej Siewior struct dwc3_request { 533e0ce0b0aSSebastian Andrzej Siewior struct usb_request request; 534e0ce0b0aSSebastian Andrzej Siewior struct list_head list; 535e0ce0b0aSSebastian Andrzej Siewior struct dwc3_ep *dep; 536e0ce0b0aSSebastian Andrzej Siewior 537e0ce0b0aSSebastian Andrzej Siewior u8 epnum; 538f6bafc6aSFelipe Balbi struct dwc3_trb *trb; 539e0ce0b0aSSebastian Andrzej Siewior dma_addr_t trb_dma; 540e0ce0b0aSSebastian Andrzej Siewior 541e0ce0b0aSSebastian Andrzej Siewior unsigned direction:1; 542e0ce0b0aSSebastian Andrzej Siewior unsigned mapped:1; 543e0ce0b0aSSebastian Andrzej Siewior unsigned queued:1; 544e0ce0b0aSSebastian Andrzej Siewior }; 545e0ce0b0aSSebastian Andrzej Siewior 546a3299499SFelipe Balbi /** 54772246da4SFelipe Balbi * struct dwc3 - representation of our controller 54891db07dcSFelipe Balbi * @ctrl_req: usb control request which is used for ep0 54991db07dcSFelipe Balbi * @ep0_trb: trb which is used for the ctrl_req 5505812b1c2SFelipe Balbi * @ep0_bounce: bounce buffer for ep0 55191db07dcSFelipe Balbi * @setup_buf: used while precessing STD USB requests 55291db07dcSFelipe Balbi * @ctrl_req_addr: dma address of ctrl_req 55391db07dcSFelipe Balbi * @ep0_trb: dma address of ep0_trb 55491db07dcSFelipe Balbi * @ep0_usb_req: dummy req used while handling STD USB requests 5555812b1c2SFelipe Balbi * @ep0_bounce_addr: dma address of ep0_bounce 55672246da4SFelipe Balbi * @lock: for synchronizing 55772246da4SFelipe Balbi * @dev: pointer to our struct device 558d07e8819SFelipe Balbi * @xhci: pointer to our xHCI child 55972246da4SFelipe Balbi * @event_buffer_list: a list of event buffers 56072246da4SFelipe Balbi * @gadget: device side representation of the peripheral controller 56172246da4SFelipe Balbi * @gadget_driver: pointer to the gadget driver 56272246da4SFelipe Balbi * @regs: base address for our registers 56372246da4SFelipe Balbi * @regs_size: address space size 56472246da4SFelipe Balbi * @irq: IRQ number 5659f622b2aSFelipe Balbi * @num_event_buffers: calculated number of event buffers 566fae2b904SFelipe Balbi * @u1u2: only used on revisions <1.83a for workaround 5676c167fc9SFelipe Balbi * @maximum_speed: maximum speed requested (mainly for testing purposes) 56872246da4SFelipe Balbi * @revision: revision register contents 5690949e99bSFelipe Balbi * @mode: mode of operation 57072246da4SFelipe Balbi * @is_selfpowered: true when we are selfpowered 57172246da4SFelipe Balbi * @three_stage_setup: set if we perform a three phase setup 5725812b1c2SFelipe Balbi * @ep0_bounced: true when we used bounce buffer 57355f3fba6SFelipe Balbi * @ep0_expect_in: true when we expect a DATA IN transfer 574b23c8439SPaul Zimmerman * @start_config_issued: true when StartConfig command has been issued 575df62df56SFelipe Balbi * @setup_packet_pending: true when there's a Setup Packet in FIFO. Workaround 576457e84b6SFelipe Balbi * @needs_fifo_resize: not all users might want fifo resizing, flag it 577457e84b6SFelipe Balbi * @resize_fifos: tells us it's ok to reconfigure our TxFIFO sizes. 578*c12a0d86SFelipe Balbi * @isoch_delay: wValue from Set Isochronous Delay request; 579865e09e7SFelipe Balbi * @u2sel: parameter from Set SEL request. 580865e09e7SFelipe Balbi * @u2pel: parameter from Set SEL request. 581865e09e7SFelipe Balbi * @u1sel: parameter from Set SEL request. 582865e09e7SFelipe Balbi * @u1pel: parameter from Set SEL request. 583b53c772dSFelipe Balbi * @ep0_next_event: hold the next expected event 58472246da4SFelipe Balbi * @ep0state: state of endpoint zero 58572246da4SFelipe Balbi * @link_state: link state 58672246da4SFelipe Balbi * @speed: device speed (super, high, full, low) 58772246da4SFelipe Balbi * @mem: points to start of memory which is used for this struct. 588a3299499SFelipe Balbi * @hwparams: copy of hwparams registers 58972246da4SFelipe Balbi * @root: debugfs root folder pointer 59072246da4SFelipe Balbi */ 59172246da4SFelipe Balbi struct dwc3 { 59272246da4SFelipe Balbi struct usb_ctrlrequest *ctrl_req; 593f6bafc6aSFelipe Balbi struct dwc3_trb *ep0_trb; 5945812b1c2SFelipe Balbi void *ep0_bounce; 59572246da4SFelipe Balbi u8 *setup_buf; 59672246da4SFelipe Balbi dma_addr_t ctrl_req_addr; 59772246da4SFelipe Balbi dma_addr_t ep0_trb_addr; 5985812b1c2SFelipe Balbi dma_addr_t ep0_bounce_addr; 599e0ce0b0aSSebastian Andrzej Siewior struct dwc3_request ep0_usb_req; 60072246da4SFelipe Balbi /* device lock */ 60172246da4SFelipe Balbi spinlock_t lock; 60272246da4SFelipe Balbi struct device *dev; 60372246da4SFelipe Balbi 604d07e8819SFelipe Balbi struct platform_device *xhci; 60551249dcaSIdo Shayevitz struct resource xhci_resources[DWC3_XHCI_RESOURCES_NUM]; 606d07e8819SFelipe Balbi 607457d3f21SFelipe Balbi struct dwc3_event_buffer **ev_buffs; 60872246da4SFelipe Balbi struct dwc3_ep *eps[DWC3_ENDPOINTS_NUM]; 60972246da4SFelipe Balbi 61072246da4SFelipe Balbi struct usb_gadget gadget; 61172246da4SFelipe Balbi struct usb_gadget_driver *gadget_driver; 61272246da4SFelipe Balbi 61372246da4SFelipe Balbi void __iomem *regs; 61472246da4SFelipe Balbi size_t regs_size; 61572246da4SFelipe Balbi 6169f622b2aSFelipe Balbi u32 num_event_buffers; 617fae2b904SFelipe Balbi u32 u1u2; 6186c167fc9SFelipe Balbi u32 maximum_speed; 61972246da4SFelipe Balbi u32 revision; 6200949e99bSFelipe Balbi u32 mode; 62172246da4SFelipe Balbi 62272246da4SFelipe Balbi #define DWC3_REVISION_173A 0x5533173a 62372246da4SFelipe Balbi #define DWC3_REVISION_175A 0x5533175a 62472246da4SFelipe Balbi #define DWC3_REVISION_180A 0x5533180a 62572246da4SFelipe Balbi #define DWC3_REVISION_183A 0x5533183a 62672246da4SFelipe Balbi #define DWC3_REVISION_185A 0x5533185a 62772246da4SFelipe Balbi #define DWC3_REVISION_188A 0x5533188a 62872246da4SFelipe Balbi #define DWC3_REVISION_190A 0x5533190a 6291522d703SFelipe Balbi #define DWC3_REVISION_200A 0x5533200a 6301522d703SFelipe Balbi #define DWC3_REVISION_202A 0x5533202a 6311522d703SFelipe Balbi #define DWC3_REVISION_210A 0x5533210a 6321522d703SFelipe Balbi #define DWC3_REVISION_220A 0x5533220a 63372246da4SFelipe Balbi 63472246da4SFelipe Balbi unsigned is_selfpowered:1; 63572246da4SFelipe Balbi unsigned three_stage_setup:1; 6365812b1c2SFelipe Balbi unsigned ep0_bounced:1; 63755f3fba6SFelipe Balbi unsigned ep0_expect_in:1; 638b23c8439SPaul Zimmerman unsigned start_config_issued:1; 639df62df56SFelipe Balbi unsigned setup_packet_pending:1; 6405bdb1dccSSebastian Andrzej Siewior unsigned delayed_status:1; 641457e84b6SFelipe Balbi unsigned needs_fifo_resize:1; 642457e84b6SFelipe Balbi unsigned resize_fifos:1; 64372246da4SFelipe Balbi 644b53c772dSFelipe Balbi enum dwc3_ep0_next ep0_next_event; 64572246da4SFelipe Balbi enum dwc3_ep0_state ep0state; 64672246da4SFelipe Balbi enum dwc3_link_state link_state; 64772246da4SFelipe Balbi enum dwc3_device_state dev_state; 64872246da4SFelipe Balbi 649*c12a0d86SFelipe Balbi u16 isoch_delay; 650865e09e7SFelipe Balbi u16 u2sel; 651865e09e7SFelipe Balbi u16 u2pel; 652865e09e7SFelipe Balbi u8 u1sel; 653865e09e7SFelipe Balbi u8 u1pel; 654865e09e7SFelipe Balbi 65572246da4SFelipe Balbi u8 speed; 656865e09e7SFelipe Balbi 65772246da4SFelipe Balbi void *mem; 65872246da4SFelipe Balbi 659a3299499SFelipe Balbi struct dwc3_hwparams hwparams; 66072246da4SFelipe Balbi struct dentry *root; 6613b637367SGerard Cauvy 6623b637367SGerard Cauvy u8 test_mode; 6633b637367SGerard Cauvy u8 test_mode_nr; 66472246da4SFelipe Balbi }; 66572246da4SFelipe Balbi 66672246da4SFelipe Balbi /* -------------------------------------------------------------------------- */ 66772246da4SFelipe Balbi 66872246da4SFelipe Balbi /* -------------------------------------------------------------------------- */ 66972246da4SFelipe Balbi 67072246da4SFelipe Balbi struct dwc3_event_type { 67172246da4SFelipe Balbi u32 is_devspec:1; 67272246da4SFelipe Balbi u32 type:6; 67372246da4SFelipe Balbi u32 reserved8_31:25; 67472246da4SFelipe Balbi } __packed; 67572246da4SFelipe Balbi 67672246da4SFelipe Balbi #define DWC3_DEPEVT_XFERCOMPLETE 0x01 67772246da4SFelipe Balbi #define DWC3_DEPEVT_XFERINPROGRESS 0x02 67872246da4SFelipe Balbi #define DWC3_DEPEVT_XFERNOTREADY 0x03 67972246da4SFelipe Balbi #define DWC3_DEPEVT_RXTXFIFOEVT 0x04 68072246da4SFelipe Balbi #define DWC3_DEPEVT_STREAMEVT 0x06 68172246da4SFelipe Balbi #define DWC3_DEPEVT_EPCMDCMPLT 0x07 68272246da4SFelipe Balbi 68372246da4SFelipe Balbi /** 68472246da4SFelipe Balbi * struct dwc3_event_depvt - Device Endpoint Events 68572246da4SFelipe Balbi * @one_bit: indicates this is an endpoint event (not used) 68672246da4SFelipe Balbi * @endpoint_number: number of the endpoint 68772246da4SFelipe Balbi * @endpoint_event: The event we have: 68872246da4SFelipe Balbi * 0x00 - Reserved 68972246da4SFelipe Balbi * 0x01 - XferComplete 69072246da4SFelipe Balbi * 0x02 - XferInProgress 69172246da4SFelipe Balbi * 0x03 - XferNotReady 69272246da4SFelipe Balbi * 0x04 - RxTxFifoEvt (IN->Underrun, OUT->Overrun) 69372246da4SFelipe Balbi * 0x05 - Reserved 69472246da4SFelipe Balbi * 0x06 - StreamEvt 69572246da4SFelipe Balbi * 0x07 - EPCmdCmplt 69672246da4SFelipe Balbi * @reserved11_10: Reserved, don't use. 69772246da4SFelipe Balbi * @status: Indicates the status of the event. Refer to databook for 69872246da4SFelipe Balbi * more information. 69972246da4SFelipe Balbi * @parameters: Parameters of the current event. Refer to databook for 70072246da4SFelipe Balbi * more information. 70172246da4SFelipe Balbi */ 70272246da4SFelipe Balbi struct dwc3_event_depevt { 70372246da4SFelipe Balbi u32 one_bit:1; 70472246da4SFelipe Balbi u32 endpoint_number:5; 70572246da4SFelipe Balbi u32 endpoint_event:4; 70672246da4SFelipe Balbi u32 reserved11_10:2; 70772246da4SFelipe Balbi u32 status:4; 70840aa41fbSFelipe Balbi 70940aa41fbSFelipe Balbi /* Within XferNotReady */ 71040aa41fbSFelipe Balbi #define DEPEVT_STATUS_TRANSFER_ACTIVE (1 << 3) 71140aa41fbSFelipe Balbi 71240aa41fbSFelipe Balbi /* Within XferComplete */ 71372246da4SFelipe Balbi #define DEPEVT_STATUS_BUSERR (1 << 0) 71472246da4SFelipe Balbi #define DEPEVT_STATUS_SHORT (1 << 1) 71572246da4SFelipe Balbi #define DEPEVT_STATUS_IOC (1 << 2) 71672246da4SFelipe Balbi #define DEPEVT_STATUS_LST (1 << 3) 717dc137f01SFelipe Balbi 718879631aaSFelipe Balbi /* Stream event only */ 719879631aaSFelipe Balbi #define DEPEVT_STREAMEVT_FOUND 1 720879631aaSFelipe Balbi #define DEPEVT_STREAMEVT_NOTFOUND 2 721879631aaSFelipe Balbi 722dc137f01SFelipe Balbi /* Control-only Status */ 723dc137f01SFelipe Balbi #define DEPEVT_STATUS_CONTROL_SETUP 0 724dc137f01SFelipe Balbi #define DEPEVT_STATUS_CONTROL_DATA 1 725dc137f01SFelipe Balbi #define DEPEVT_STATUS_CONTROL_STATUS 2 726dc137f01SFelipe Balbi 72772246da4SFelipe Balbi u32 parameters:16; 72872246da4SFelipe Balbi } __packed; 72972246da4SFelipe Balbi 73072246da4SFelipe Balbi /** 73172246da4SFelipe Balbi * struct dwc3_event_devt - Device Events 73272246da4SFelipe Balbi * @one_bit: indicates this is a non-endpoint event (not used) 73372246da4SFelipe Balbi * @device_event: indicates it's a device event. Should read as 0x00 73472246da4SFelipe Balbi * @type: indicates the type of device event. 73572246da4SFelipe Balbi * 0 - DisconnEvt 73672246da4SFelipe Balbi * 1 - USBRst 73772246da4SFelipe Balbi * 2 - ConnectDone 73872246da4SFelipe Balbi * 3 - ULStChng 73972246da4SFelipe Balbi * 4 - WkUpEvt 74072246da4SFelipe Balbi * 5 - Reserved 74172246da4SFelipe Balbi * 6 - EOPF 74272246da4SFelipe Balbi * 7 - SOF 74372246da4SFelipe Balbi * 8 - Reserved 74472246da4SFelipe Balbi * 9 - ErrticErr 74572246da4SFelipe Balbi * 10 - CmdCmplt 74672246da4SFelipe Balbi * 11 - EvntOverflow 74772246da4SFelipe Balbi * 12 - VndrDevTstRcved 74872246da4SFelipe Balbi * @reserved15_12: Reserved, not used 74972246da4SFelipe Balbi * @event_info: Information about this event 75072246da4SFelipe Balbi * @reserved31_24: Reserved, not used 75172246da4SFelipe Balbi */ 75272246da4SFelipe Balbi struct dwc3_event_devt { 75372246da4SFelipe Balbi u32 one_bit:1; 75472246da4SFelipe Balbi u32 device_event:7; 75572246da4SFelipe Balbi u32 type:4; 75672246da4SFelipe Balbi u32 reserved15_12:4; 75772246da4SFelipe Balbi u32 event_info:8; 75872246da4SFelipe Balbi u32 reserved31_24:8; 75972246da4SFelipe Balbi } __packed; 76072246da4SFelipe Balbi 76172246da4SFelipe Balbi /** 76272246da4SFelipe Balbi * struct dwc3_event_gevt - Other Core Events 76372246da4SFelipe Balbi * @one_bit: indicates this is a non-endpoint event (not used) 76472246da4SFelipe Balbi * @device_event: indicates it's (0x03) Carkit or (0x04) I2C event. 76572246da4SFelipe Balbi * @phy_port_number: self-explanatory 76672246da4SFelipe Balbi * @reserved31_12: Reserved, not used. 76772246da4SFelipe Balbi */ 76872246da4SFelipe Balbi struct dwc3_event_gevt { 76972246da4SFelipe Balbi u32 one_bit:1; 77072246da4SFelipe Balbi u32 device_event:7; 77172246da4SFelipe Balbi u32 phy_port_number:4; 77272246da4SFelipe Balbi u32 reserved31_12:20; 77372246da4SFelipe Balbi } __packed; 77472246da4SFelipe Balbi 77572246da4SFelipe Balbi /** 77672246da4SFelipe Balbi * union dwc3_event - representation of Event Buffer contents 77772246da4SFelipe Balbi * @raw: raw 32-bit event 77872246da4SFelipe Balbi * @type: the type of the event 77972246da4SFelipe Balbi * @depevt: Device Endpoint Event 78072246da4SFelipe Balbi * @devt: Device Event 78172246da4SFelipe Balbi * @gevt: Global Event 78272246da4SFelipe Balbi */ 78372246da4SFelipe Balbi union dwc3_event { 78472246da4SFelipe Balbi u32 raw; 78572246da4SFelipe Balbi struct dwc3_event_type type; 78672246da4SFelipe Balbi struct dwc3_event_depevt depevt; 78772246da4SFelipe Balbi struct dwc3_event_devt devt; 78872246da4SFelipe Balbi struct dwc3_event_gevt gevt; 78972246da4SFelipe Balbi }; 79072246da4SFelipe Balbi 79172246da4SFelipe Balbi /* 79272246da4SFelipe Balbi * DWC3 Features to be used as Driver Data 79372246da4SFelipe Balbi */ 79472246da4SFelipe Balbi 79572246da4SFelipe Balbi #define DWC3_HAS_PERIPHERAL BIT(0) 79672246da4SFelipe Balbi #define DWC3_HAS_XHCI BIT(1) 79772246da4SFelipe Balbi #define DWC3_HAS_OTG BIT(3) 79872246da4SFelipe Balbi 799d07e8819SFelipe Balbi /* prototypes */ 8003140e8cbSSebastian Andrzej Siewior void dwc3_set_mode(struct dwc3 *dwc, u32 mode); 801457e84b6SFelipe Balbi int dwc3_gadget_resize_tx_fifos(struct dwc3 *dwc); 8023140e8cbSSebastian Andrzej Siewior 803d07e8819SFelipe Balbi int dwc3_host_init(struct dwc3 *dwc); 804d07e8819SFelipe Balbi void dwc3_host_exit(struct dwc3 *dwc); 805d07e8819SFelipe Balbi 806f80b45e7SFelipe Balbi int dwc3_gadget_init(struct dwc3 *dwc); 807f80b45e7SFelipe Balbi void dwc3_gadget_exit(struct dwc3 *dwc); 808f80b45e7SFelipe Balbi 8098300dd23SFelipe Balbi extern int dwc3_get_device_id(void); 8108300dd23SFelipe Balbi extern void dwc3_put_device_id(int id); 8118300dd23SFelipe Balbi 81272246da4SFelipe Balbi #endif /* __DRIVERS_USB_DWC3_CORE_H */ 813