1bfad65eeSFelipe Balbi /* 272246da4SFelipe Balbi * core.h - DesignWare USB3 DRD Core Header 372246da4SFelipe Balbi * 472246da4SFelipe Balbi * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com 572246da4SFelipe Balbi * 672246da4SFelipe Balbi * Authors: Felipe Balbi <balbi@ti.com>, 772246da4SFelipe Balbi * Sebastian Andrzej Siewior <bigeasy@linutronix.de> 872246da4SFelipe Balbi * 95945f789SFelipe Balbi * This program is free software: you can redistribute it and/or modify 105945f789SFelipe Balbi * it under the terms of the GNU General Public License version 2 of 115945f789SFelipe Balbi * the License as published by the Free Software Foundation. 1272246da4SFelipe Balbi * 135945f789SFelipe Balbi * This program is distributed in the hope that it will be useful, 145945f789SFelipe Balbi * but WITHOUT ANY WARRANTY; without even the implied warranty of 155945f789SFelipe Balbi * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 165945f789SFelipe Balbi * GNU General Public License for more details. 1772246da4SFelipe Balbi */ 1872246da4SFelipe Balbi 1972246da4SFelipe Balbi #ifndef __DRIVERS_USB_DWC3_CORE_H 2072246da4SFelipe Balbi #define __DRIVERS_USB_DWC3_CORE_H 2172246da4SFelipe Balbi 2272246da4SFelipe Balbi #include <linux/device.h> 2372246da4SFelipe Balbi #include <linux/spinlock.h> 24d07e8819SFelipe Balbi #include <linux/ioport.h> 2572246da4SFelipe Balbi #include <linux/list.h> 26ff3f0789SRoger Quadros #include <linux/bitops.h> 2772246da4SFelipe Balbi #include <linux/dma-mapping.h> 2872246da4SFelipe Balbi #include <linux/mm.h> 2972246da4SFelipe Balbi #include <linux/debugfs.h> 3076a638f8SBaolin Wang #include <linux/wait.h> 3141ce1456SRoger Quadros #include <linux/workqueue.h> 3272246da4SFelipe Balbi 3372246da4SFelipe Balbi #include <linux/usb/ch9.h> 3472246da4SFelipe Balbi #include <linux/usb/gadget.h> 35a45c82b8SRuchika Kharwar #include <linux/usb/otg.h> 3688bc9d19SHeikki Krogerus #include <linux/ulpi/interface.h> 3772246da4SFelipe Balbi 3857303488SKishon Vijay Abraham I #include <linux/phy/phy.h> 3957303488SKishon Vijay Abraham I 402c4cbe6eSFelipe Balbi #define DWC3_MSG_MAX 500 412c4cbe6eSFelipe Balbi 4272246da4SFelipe Balbi /* Global constants */ 43bb014736SBaolin Wang #define DWC3_PULL_UP_TIMEOUT 500 /* ms */ 44905dc04eSFelipe Balbi #define DWC3_BOUNCE_SIZE 1024 /* size of a superspeed bulk */ 454199c5f8SFelipe Balbi #define DWC3_EP0_SETUP_SIZE 512 4672246da4SFelipe Balbi #define DWC3_ENDPOINTS_NUM 32 4751249dcaSIdo Shayevitz #define DWC3_XHCI_RESOURCES_NUM 2 4872246da4SFelipe Balbi 490ffcaf37SFelipe Balbi #define DWC3_SCRATCHBUF_SIZE 4096 /* each buffer is assumed to be 4KiB */ 50e71d363dSFelipe Balbi #define DWC3_EVENT_BUFFERS_SIZE 4096 5172246da4SFelipe Balbi #define DWC3_EVENT_TYPE_MASK 0xfe 5272246da4SFelipe Balbi 5372246da4SFelipe Balbi #define DWC3_EVENT_TYPE_DEV 0 5472246da4SFelipe Balbi #define DWC3_EVENT_TYPE_CARKIT 3 5572246da4SFelipe Balbi #define DWC3_EVENT_TYPE_I2C 4 5672246da4SFelipe Balbi 5772246da4SFelipe Balbi #define DWC3_DEVICE_EVENT_DISCONNECT 0 5872246da4SFelipe Balbi #define DWC3_DEVICE_EVENT_RESET 1 5972246da4SFelipe Balbi #define DWC3_DEVICE_EVENT_CONNECT_DONE 2 6072246da4SFelipe Balbi #define DWC3_DEVICE_EVENT_LINK_STATUS_CHANGE 3 6172246da4SFelipe Balbi #define DWC3_DEVICE_EVENT_WAKEUP 4 622c61a8efSPaul Zimmerman #define DWC3_DEVICE_EVENT_HIBER_REQ 5 6372246da4SFelipe Balbi #define DWC3_DEVICE_EVENT_EOPF 6 6472246da4SFelipe Balbi #define DWC3_DEVICE_EVENT_SOF 7 6572246da4SFelipe Balbi #define DWC3_DEVICE_EVENT_ERRATIC_ERROR 9 6672246da4SFelipe Balbi #define DWC3_DEVICE_EVENT_CMD_CMPL 10 6772246da4SFelipe Balbi #define DWC3_DEVICE_EVENT_OVERFLOW 11 6872246da4SFelipe Balbi 6972246da4SFelipe Balbi #define DWC3_GEVNTCOUNT_MASK 0xfffc 70ff3f0789SRoger Quadros #define DWC3_GEVNTCOUNT_EHB BIT(31) 7172246da4SFelipe Balbi #define DWC3_GSNPSID_MASK 0xffff0000 7272246da4SFelipe Balbi #define DWC3_GSNPSREV_MASK 0xffff 7372246da4SFelipe Balbi 7451249dcaSIdo Shayevitz /* DWC3 registers memory space boundries */ 7551249dcaSIdo Shayevitz #define DWC3_XHCI_REGS_START 0x0 7651249dcaSIdo Shayevitz #define DWC3_XHCI_REGS_END 0x7fff 7751249dcaSIdo Shayevitz #define DWC3_GLOBALS_REGS_START 0xc100 7851249dcaSIdo Shayevitz #define DWC3_GLOBALS_REGS_END 0xc6ff 7951249dcaSIdo Shayevitz #define DWC3_DEVICE_REGS_START 0xc700 8051249dcaSIdo Shayevitz #define DWC3_DEVICE_REGS_END 0xcbff 8151249dcaSIdo Shayevitz #define DWC3_OTG_REGS_START 0xcc00 8251249dcaSIdo Shayevitz #define DWC3_OTG_REGS_END 0xccff 8351249dcaSIdo Shayevitz 8472246da4SFelipe Balbi /* Global Registers */ 8572246da4SFelipe Balbi #define DWC3_GSBUSCFG0 0xc100 8672246da4SFelipe Balbi #define DWC3_GSBUSCFG1 0xc104 8772246da4SFelipe Balbi #define DWC3_GTXTHRCFG 0xc108 8872246da4SFelipe Balbi #define DWC3_GRXTHRCFG 0xc10c 8972246da4SFelipe Balbi #define DWC3_GCTL 0xc110 9072246da4SFelipe Balbi #define DWC3_GEVTEN 0xc114 9172246da4SFelipe Balbi #define DWC3_GSTS 0xc118 92475c8bebSWilliam Wu #define DWC3_GUCTL1 0xc11c 9372246da4SFelipe Balbi #define DWC3_GSNPSID 0xc120 9472246da4SFelipe Balbi #define DWC3_GGPIO 0xc124 9572246da4SFelipe Balbi #define DWC3_GUID 0xc128 9672246da4SFelipe Balbi #define DWC3_GUCTL 0xc12c 9772246da4SFelipe Balbi #define DWC3_GBUSERRADDR0 0xc130 9872246da4SFelipe Balbi #define DWC3_GBUSERRADDR1 0xc134 9972246da4SFelipe Balbi #define DWC3_GPRTBIMAP0 0xc138 10072246da4SFelipe Balbi #define DWC3_GPRTBIMAP1 0xc13c 10172246da4SFelipe Balbi #define DWC3_GHWPARAMS0 0xc140 10272246da4SFelipe Balbi #define DWC3_GHWPARAMS1 0xc144 10372246da4SFelipe Balbi #define DWC3_GHWPARAMS2 0xc148 10472246da4SFelipe Balbi #define DWC3_GHWPARAMS3 0xc14c 10572246da4SFelipe Balbi #define DWC3_GHWPARAMS4 0xc150 10672246da4SFelipe Balbi #define DWC3_GHWPARAMS5 0xc154 10772246da4SFelipe Balbi #define DWC3_GHWPARAMS6 0xc158 10872246da4SFelipe Balbi #define DWC3_GHWPARAMS7 0xc15c 10972246da4SFelipe Balbi #define DWC3_GDBGFIFOSPACE 0xc160 11072246da4SFelipe Balbi #define DWC3_GDBGLTSSM 0xc164 11172246da4SFelipe Balbi #define DWC3_GPRTBIMAP_HS0 0xc180 11272246da4SFelipe Balbi #define DWC3_GPRTBIMAP_HS1 0xc184 11372246da4SFelipe Balbi #define DWC3_GPRTBIMAP_FS0 0xc188 11472246da4SFelipe Balbi #define DWC3_GPRTBIMAP_FS1 0xc18c 11506281d46SJohn Youn #define DWC3_GUCTL2 0xc19c 11672246da4SFelipe Balbi 117690fb371SJohn Youn #define DWC3_VER_NUMBER 0xc1a0 118690fb371SJohn Youn #define DWC3_VER_TYPE 0xc1a4 119690fb371SJohn Youn 1208261bd4eSRoger Quadros #define DWC3_GUSB2PHYCFG(n) (0xc200 + ((n) * 0x04)) 1218261bd4eSRoger Quadros #define DWC3_GUSB2I2CCTL(n) (0xc240 + ((n) * 0x04)) 12272246da4SFelipe Balbi 1238261bd4eSRoger Quadros #define DWC3_GUSB2PHYACC(n) (0xc280 + ((n) * 0x04)) 12472246da4SFelipe Balbi 1258261bd4eSRoger Quadros #define DWC3_GUSB3PIPECTL(n) (0xc2c0 + ((n) * 0x04)) 12672246da4SFelipe Balbi 1278261bd4eSRoger Quadros #define DWC3_GTXFIFOSIZ(n) (0xc300 + ((n) * 0x04)) 1288261bd4eSRoger Quadros #define DWC3_GRXFIFOSIZ(n) (0xc380 + ((n) * 0x04)) 12972246da4SFelipe Balbi 1308261bd4eSRoger Quadros #define DWC3_GEVNTADRLO(n) (0xc400 + ((n) * 0x10)) 1318261bd4eSRoger Quadros #define DWC3_GEVNTADRHI(n) (0xc404 + ((n) * 0x10)) 1328261bd4eSRoger Quadros #define DWC3_GEVNTSIZ(n) (0xc408 + ((n) * 0x10)) 1338261bd4eSRoger Quadros #define DWC3_GEVNTCOUNT(n) (0xc40c + ((n) * 0x10)) 13472246da4SFelipe Balbi 13572246da4SFelipe Balbi #define DWC3_GHWPARAMS8 0xc600 136db2be4e9SNikhil Badola #define DWC3_GFLADJ 0xc630 13772246da4SFelipe Balbi 13872246da4SFelipe Balbi /* Device Registers */ 13972246da4SFelipe Balbi #define DWC3_DCFG 0xc700 14072246da4SFelipe Balbi #define DWC3_DCTL 0xc704 14172246da4SFelipe Balbi #define DWC3_DEVTEN 0xc708 14272246da4SFelipe Balbi #define DWC3_DSTS 0xc70c 14372246da4SFelipe Balbi #define DWC3_DGCMDPAR 0xc710 14472246da4SFelipe Balbi #define DWC3_DGCMD 0xc714 14572246da4SFelipe Balbi #define DWC3_DALEPENA 0xc720 1462eb88016SFelipe Balbi 1478261bd4eSRoger Quadros #define DWC3_DEP_BASE(n) (0xc800 + ((n) * 0x10)) 1482eb88016SFelipe Balbi #define DWC3_DEPCMDPAR2 0x00 1492eb88016SFelipe Balbi #define DWC3_DEPCMDPAR1 0x04 1502eb88016SFelipe Balbi #define DWC3_DEPCMDPAR0 0x08 1512eb88016SFelipe Balbi #define DWC3_DEPCMD 0x0c 15272246da4SFelipe Balbi 1538261bd4eSRoger Quadros #define DWC3_DEV_IMOD(n) (0xca00 + ((n) * 0x4)) 154cf40b86bSJohn Youn 15572246da4SFelipe Balbi /* OTG Registers */ 15672246da4SFelipe Balbi #define DWC3_OCFG 0xcc00 15772246da4SFelipe Balbi #define DWC3_OCTL 0xcc04 158d4436c3aSGeorge Cherian #define DWC3_OEVT 0xcc08 159d4436c3aSGeorge Cherian #define DWC3_OEVTEN 0xcc0C 160d4436c3aSGeorge Cherian #define DWC3_OSTS 0xcc10 16172246da4SFelipe Balbi 16272246da4SFelipe Balbi /* Bit fields */ 16372246da4SFelipe Balbi 164cf6d867dSFelipe Balbi /* Global Debug Queue/FIFO Space Available Register */ 165cf6d867dSFelipe Balbi #define DWC3_GDBGFIFOSPACE_NUM(n) ((n) & 0x1f) 166cf6d867dSFelipe Balbi #define DWC3_GDBGFIFOSPACE_TYPE(n) (((n) << 5) & 0x1e0) 167cf6d867dSFelipe Balbi #define DWC3_GDBGFIFOSPACE_SPACE_AVAILABLE(n) (((n) >> 16) & 0xffff) 168cf6d867dSFelipe Balbi 169cf6d867dSFelipe Balbi #define DWC3_TXFIFOQ 1 170cf6d867dSFelipe Balbi #define DWC3_RXFIFOQ 3 171cf6d867dSFelipe Balbi #define DWC3_TXREQQ 5 172cf6d867dSFelipe Balbi #define DWC3_RXREQQ 7 173cf6d867dSFelipe Balbi #define DWC3_RXINFOQ 9 174cf6d867dSFelipe Balbi #define DWC3_DESCFETCHQ 13 175cf6d867dSFelipe Balbi #define DWC3_EVENTQ 15 176cf6d867dSFelipe Balbi 1772a58f9c1SFelipe Balbi /* Global RX Threshold Configuration Register */ 1782a58f9c1SFelipe Balbi #define DWC3_GRXTHRCFG_MAXRXBURSTSIZE(n) (((n) & 0x1f) << 19) 1792a58f9c1SFelipe Balbi #define DWC3_GRXTHRCFG_RXPKTCNT(n) (((n) & 0xf) << 24) 180ff3f0789SRoger Quadros #define DWC3_GRXTHRCFG_PKTCNTSEL BIT(29) 1812a58f9c1SFelipe Balbi 18272246da4SFelipe Balbi /* Global Configuration Register */ 1831d046793SPaul Zimmerman #define DWC3_GCTL_PWRDNSCALE(n) ((n) << 19) 184ff3f0789SRoger Quadros #define DWC3_GCTL_U2RSTECN BIT(16) 1851d046793SPaul Zimmerman #define DWC3_GCTL_RAMCLKSEL(x) (((x) & DWC3_GCTL_CLK_MASK) << 6) 18672246da4SFelipe Balbi #define DWC3_GCTL_CLK_BUS (0) 18772246da4SFelipe Balbi #define DWC3_GCTL_CLK_PIPE (1) 18872246da4SFelipe Balbi #define DWC3_GCTL_CLK_PIPEHALF (2) 18972246da4SFelipe Balbi #define DWC3_GCTL_CLK_MASK (3) 19072246da4SFelipe Balbi 1910b9fe32dSFelipe Balbi #define DWC3_GCTL_PRTCAP(n) (((n) & (3 << 12)) >> 12) 1921d046793SPaul Zimmerman #define DWC3_GCTL_PRTCAPDIR(n) ((n) << 12) 19372246da4SFelipe Balbi #define DWC3_GCTL_PRTCAP_HOST 1 19472246da4SFelipe Balbi #define DWC3_GCTL_PRTCAP_DEVICE 2 19572246da4SFelipe Balbi #define DWC3_GCTL_PRTCAP_OTG 3 19672246da4SFelipe Balbi 197ff3f0789SRoger Quadros #define DWC3_GCTL_CORESOFTRESET BIT(11) 198ff3f0789SRoger Quadros #define DWC3_GCTL_SOFITPSYNC BIT(10) 1991d046793SPaul Zimmerman #define DWC3_GCTL_SCALEDOWN(n) ((n) << 4) 2003e87c42aSPaul Zimmerman #define DWC3_GCTL_SCALEDOWN_MASK DWC3_GCTL_SCALEDOWN(3) 201ff3f0789SRoger Quadros #define DWC3_GCTL_DISSCRAMBLE BIT(3) 202ff3f0789SRoger Quadros #define DWC3_GCTL_U2EXIT_LFPS BIT(2) 203ff3f0789SRoger Quadros #define DWC3_GCTL_GBLHIBERNATIONEN BIT(1) 204ff3f0789SRoger Quadros #define DWC3_GCTL_DSBLCLKGTNG BIT(0) 20572246da4SFelipe Balbi 2060bb39ca1SJohn Youn /* Global User Control 1 Register */ 20765db7a0cSWilliam Wu #define DWC3_GUCTL1_TX_IPGAP_LINECHECK_DIS BIT(28) 208ff3f0789SRoger Quadros #define DWC3_GUCTL1_DEV_L1_EXIT_BY_HW BIT(24) 2090bb39ca1SJohn Youn 21072246da4SFelipe Balbi /* Global USB2 PHY Configuration Register */ 211ff3f0789SRoger Quadros #define DWC3_GUSB2PHYCFG_PHYSOFTRST BIT(31) 212ff3f0789SRoger Quadros #define DWC3_GUSB2PHYCFG_U2_FREECLK_EXISTS BIT(30) 213ff3f0789SRoger Quadros #define DWC3_GUSB2PHYCFG_SUSPHY BIT(6) 214ff3f0789SRoger Quadros #define DWC3_GUSB2PHYCFG_ULPI_UTMI BIT(4) 215ff3f0789SRoger Quadros #define DWC3_GUSB2PHYCFG_ENBLSLPM BIT(8) 21632f2ed86SWilliam Wu #define DWC3_GUSB2PHYCFG_PHYIF(n) (n << 3) 21732f2ed86SWilliam Wu #define DWC3_GUSB2PHYCFG_PHYIF_MASK DWC3_GUSB2PHYCFG_PHYIF(1) 21832f2ed86SWilliam Wu #define DWC3_GUSB2PHYCFG_USBTRDTIM(n) (n << 10) 21932f2ed86SWilliam Wu #define DWC3_GUSB2PHYCFG_USBTRDTIM_MASK DWC3_GUSB2PHYCFG_USBTRDTIM(0xf) 22032f2ed86SWilliam Wu #define USBTRDTIM_UTMI_8_BIT 9 22132f2ed86SWilliam Wu #define USBTRDTIM_UTMI_16_BIT 5 22232f2ed86SWilliam Wu #define UTMI_PHYIF_16_BIT 1 22332f2ed86SWilliam Wu #define UTMI_PHYIF_8_BIT 0 22472246da4SFelipe Balbi 225b5699eeeSHeikki Krogerus /* Global USB2 PHY Vendor Control Register */ 226ff3f0789SRoger Quadros #define DWC3_GUSB2PHYACC_NEWREGREQ BIT(25) 227ff3f0789SRoger Quadros #define DWC3_GUSB2PHYACC_BUSY BIT(23) 228ff3f0789SRoger Quadros #define DWC3_GUSB2PHYACC_WRITE BIT(22) 229b5699eeeSHeikki Krogerus #define DWC3_GUSB2PHYACC_ADDR(n) (n << 16) 230b5699eeeSHeikki Krogerus #define DWC3_GUSB2PHYACC_EXTEND_ADDR(n) (n << 8) 231b5699eeeSHeikki Krogerus #define DWC3_GUSB2PHYACC_DATA(n) (n & 0xff) 232b5699eeeSHeikki Krogerus 23372246da4SFelipe Balbi /* Global USB3 PIPE Control Register */ 234ff3f0789SRoger Quadros #define DWC3_GUSB3PIPECTL_PHYSOFTRST BIT(31) 235ff3f0789SRoger Quadros #define DWC3_GUSB3PIPECTL_U2SSINP3OK BIT(29) 236ff3f0789SRoger Quadros #define DWC3_GUSB3PIPECTL_DISRXDETINP3 BIT(28) 237ff3f0789SRoger Quadros #define DWC3_GUSB3PIPECTL_UX_EXIT_PX BIT(27) 238ff3f0789SRoger Quadros #define DWC3_GUSB3PIPECTL_REQP1P2P3 BIT(24) 239a2a1d0f5SHuang Rui #define DWC3_GUSB3PIPECTL_DEP1P2P3(n) ((n) << 19) 240a2a1d0f5SHuang Rui #define DWC3_GUSB3PIPECTL_DEP1P2P3_MASK DWC3_GUSB3PIPECTL_DEP1P2P3(7) 241a2a1d0f5SHuang Rui #define DWC3_GUSB3PIPECTL_DEP1P2P3_EN DWC3_GUSB3PIPECTL_DEP1P2P3(1) 242ff3f0789SRoger Quadros #define DWC3_GUSB3PIPECTL_DEPOCHANGE BIT(18) 243ff3f0789SRoger Quadros #define DWC3_GUSB3PIPECTL_SUSPHY BIT(17) 244ff3f0789SRoger Quadros #define DWC3_GUSB3PIPECTL_LFPSFILT BIT(9) 245ff3f0789SRoger Quadros #define DWC3_GUSB3PIPECTL_RX_DETOPOLL BIT(8) 2466b6a0c9aSHuang Rui #define DWC3_GUSB3PIPECTL_TX_DEEPH_MASK DWC3_GUSB3PIPECTL_TX_DEEPH(3) 2476b6a0c9aSHuang Rui #define DWC3_GUSB3PIPECTL_TX_DEEPH(n) ((n) << 1) 24872246da4SFelipe Balbi 249457e84b6SFelipe Balbi /* Global TX Fifo Size Register */ 250457e84b6SFelipe Balbi #define DWC3_GTXFIFOSIZ_TXFDEF(n) ((n) & 0xffff) 251457e84b6SFelipe Balbi #define DWC3_GTXFIFOSIZ_TXFSTADDR(n) ((n) & 0xffff0000) 252457e84b6SFelipe Balbi 25368d6a01bSFelipe Balbi /* Global Event Size Registers */ 254ff3f0789SRoger Quadros #define DWC3_GEVNTSIZ_INTMASK BIT(31) 25568d6a01bSFelipe Balbi #define DWC3_GEVNTSIZ_SIZE(n) ((n) & 0xffff) 25668d6a01bSFelipe Balbi 2574e99472bSFelipe Balbi /* Global HWPARAMS0 Register */ 2589d6173e1SThinh Nguyen #define DWC3_GHWPARAMS0_MODE(n) ((n) & 0x3) 2599d6173e1SThinh Nguyen #define DWC3_GHWPARAMS0_MODE_GADGET 0 2609d6173e1SThinh Nguyen #define DWC3_GHWPARAMS0_MODE_HOST 1 2619d6173e1SThinh Nguyen #define DWC3_GHWPARAMS0_MODE_DRD 2 2624e99472bSFelipe Balbi #define DWC3_GHWPARAMS0_MBUS_TYPE(n) (((n) >> 3) & 0x7) 2634e99472bSFelipe Balbi #define DWC3_GHWPARAMS0_SBUS_TYPE(n) (((n) >> 6) & 0x3) 2644e99472bSFelipe Balbi #define DWC3_GHWPARAMS0_MDWIDTH(n) (((n) >> 8) & 0xff) 2654e99472bSFelipe Balbi #define DWC3_GHWPARAMS0_SDWIDTH(n) (((n) >> 16) & 0xff) 2664e99472bSFelipe Balbi #define DWC3_GHWPARAMS0_AWIDTH(n) (((n) >> 24) & 0xff) 2674e99472bSFelipe Balbi 268aabb7075SFelipe Balbi /* Global HWPARAMS1 Register */ 2691d046793SPaul Zimmerman #define DWC3_GHWPARAMS1_EN_PWROPT(n) (((n) & (3 << 24)) >> 24) 270aabb7075SFelipe Balbi #define DWC3_GHWPARAMS1_EN_PWROPT_NO 0 271aabb7075SFelipe Balbi #define DWC3_GHWPARAMS1_EN_PWROPT_CLK 1 2722c61a8efSPaul Zimmerman #define DWC3_GHWPARAMS1_EN_PWROPT_HIB 2 2732c61a8efSPaul Zimmerman #define DWC3_GHWPARAMS1_PWROPT(n) ((n) << 24) 2742c61a8efSPaul Zimmerman #define DWC3_GHWPARAMS1_PWROPT_MASK DWC3_GHWPARAMS1_PWROPT(3) 2752c61a8efSPaul Zimmerman 2760e1e5c47SPaul Zimmerman /* Global HWPARAMS3 Register */ 2770e1e5c47SPaul Zimmerman #define DWC3_GHWPARAMS3_SSPHY_IFC(n) ((n) & 3) 2780e1e5c47SPaul Zimmerman #define DWC3_GHWPARAMS3_SSPHY_IFC_DIS 0 2791f38f88aSJohn Youn #define DWC3_GHWPARAMS3_SSPHY_IFC_GEN1 1 2801f38f88aSJohn Youn #define DWC3_GHWPARAMS3_SSPHY_IFC_GEN2 2 /* DWC_usb31 only */ 2810e1e5c47SPaul Zimmerman #define DWC3_GHWPARAMS3_HSPHY_IFC(n) (((n) & (3 << 2)) >> 2) 2820e1e5c47SPaul Zimmerman #define DWC3_GHWPARAMS3_HSPHY_IFC_DIS 0 2830e1e5c47SPaul Zimmerman #define DWC3_GHWPARAMS3_HSPHY_IFC_UTMI 1 2840e1e5c47SPaul Zimmerman #define DWC3_GHWPARAMS3_HSPHY_IFC_ULPI 2 2850e1e5c47SPaul Zimmerman #define DWC3_GHWPARAMS3_HSPHY_IFC_UTMI_ULPI 3 2860e1e5c47SPaul Zimmerman #define DWC3_GHWPARAMS3_FSPHY_IFC(n) (((n) & (3 << 4)) >> 4) 2870e1e5c47SPaul Zimmerman #define DWC3_GHWPARAMS3_FSPHY_IFC_DIS 0 2880e1e5c47SPaul Zimmerman #define DWC3_GHWPARAMS3_FSPHY_IFC_ENA 1 2890e1e5c47SPaul Zimmerman 2902c61a8efSPaul Zimmerman /* Global HWPARAMS4 Register */ 2912c61a8efSPaul Zimmerman #define DWC3_GHWPARAMS4_HIBER_SCRATCHBUFS(n) (((n) & (0x0f << 13)) >> 13) 2922c61a8efSPaul Zimmerman #define DWC3_MAX_HIBER_SCRATCHBUFS 15 293aabb7075SFelipe Balbi 294946bd579SHuang Rui /* Global HWPARAMS6 Register */ 295ff3f0789SRoger Quadros #define DWC3_GHWPARAMS6_EN_FPGA BIT(7) 296946bd579SHuang Rui 2974e99472bSFelipe Balbi /* Global HWPARAMS7 Register */ 2984e99472bSFelipe Balbi #define DWC3_GHWPARAMS7_RAM1_DEPTH(n) ((n) & 0xffff) 2994e99472bSFelipe Balbi #define DWC3_GHWPARAMS7_RAM2_DEPTH(n) (((n) >> 16) & 0xffff) 3004e99472bSFelipe Balbi 301db2be4e9SNikhil Badola /* Global Frame Length Adjustment Register */ 302ff3f0789SRoger Quadros #define DWC3_GFLADJ_30MHZ_SDBND_SEL BIT(7) 303db2be4e9SNikhil Badola #define DWC3_GFLADJ_30MHZ_MASK 0x3f 304db2be4e9SNikhil Badola 30506281d46SJohn Youn /* Global User Control Register 2 */ 306ff3f0789SRoger Quadros #define DWC3_GUCTL2_RST_ACTBITLATER BIT(14) 30706281d46SJohn Youn 30872246da4SFelipe Balbi /* Device Configuration Register */ 30972246da4SFelipe Balbi #define DWC3_DCFG_DEVADDR(addr) ((addr) << 3) 31072246da4SFelipe Balbi #define DWC3_DCFG_DEVADDR_MASK DWC3_DCFG_DEVADDR(0x7f) 31172246da4SFelipe Balbi 31272246da4SFelipe Balbi #define DWC3_DCFG_SPEED_MASK (7 << 0) 3131f38f88aSJohn Youn #define DWC3_DCFG_SUPERSPEED_PLUS (5 << 0) /* DWC_usb31 only */ 31472246da4SFelipe Balbi #define DWC3_DCFG_SUPERSPEED (4 << 0) 31572246da4SFelipe Balbi #define DWC3_DCFG_HIGHSPEED (0 << 0) 316ff3f0789SRoger Quadros #define DWC3_DCFG_FULLSPEED BIT(0) 31772246da4SFelipe Balbi #define DWC3_DCFG_LOWSPEED (2 << 0) 31872246da4SFelipe Balbi 319676e3497SFelipe Balbi #define DWC3_DCFG_NUMP_SHIFT 17 32097398612SDan Carpenter #define DWC3_DCFG_NUMP(n) (((n) >> DWC3_DCFG_NUMP_SHIFT) & 0x1f) 321676e3497SFelipe Balbi #define DWC3_DCFG_NUMP_MASK (0x1f << DWC3_DCFG_NUMP_SHIFT) 322ff3f0789SRoger Quadros #define DWC3_DCFG_LPM_CAP BIT(22) 3232c61a8efSPaul Zimmerman 32472246da4SFelipe Balbi /* Device Control Register */ 325ff3f0789SRoger Quadros #define DWC3_DCTL_RUN_STOP BIT(31) 326ff3f0789SRoger Quadros #define DWC3_DCTL_CSFTRST BIT(30) 327ff3f0789SRoger Quadros #define DWC3_DCTL_LSFTRST BIT(29) 32872246da4SFelipe Balbi 32972246da4SFelipe Balbi #define DWC3_DCTL_HIRD_THRES_MASK (0x1f << 24) 3307e39b817SPratyush Anand #define DWC3_DCTL_HIRD_THRES(n) ((n) << 24) 33172246da4SFelipe Balbi 332ff3f0789SRoger Quadros #define DWC3_DCTL_APPL1RES BIT(23) 33372246da4SFelipe Balbi 3342c61a8efSPaul Zimmerman /* These apply for core versions 1.87a and earlier */ 3358db7ed15SFelipe Balbi #define DWC3_DCTL_TRGTULST_MASK (0x0f << 17) 3368db7ed15SFelipe Balbi #define DWC3_DCTL_TRGTULST(n) ((n) << 17) 3378db7ed15SFelipe Balbi #define DWC3_DCTL_TRGTULST_U2 (DWC3_DCTL_TRGTULST(2)) 3388db7ed15SFelipe Balbi #define DWC3_DCTL_TRGTULST_U3 (DWC3_DCTL_TRGTULST(3)) 3398db7ed15SFelipe Balbi #define DWC3_DCTL_TRGTULST_SS_DIS (DWC3_DCTL_TRGTULST(4)) 3408db7ed15SFelipe Balbi #define DWC3_DCTL_TRGTULST_RX_DET (DWC3_DCTL_TRGTULST(5)) 3418db7ed15SFelipe Balbi #define DWC3_DCTL_TRGTULST_SS_INACT (DWC3_DCTL_TRGTULST(6)) 3428db7ed15SFelipe Balbi 3432c61a8efSPaul Zimmerman /* These apply for core versions 1.94a and later */ 34480caf7d2SHuang Rui #define DWC3_DCTL_LPM_ERRATA_MASK DWC3_DCTL_LPM_ERRATA(0xf) 34580caf7d2SHuang Rui #define DWC3_DCTL_LPM_ERRATA(n) ((n) << 20) 34680caf7d2SHuang Rui 347ff3f0789SRoger Quadros #define DWC3_DCTL_KEEP_CONNECT BIT(19) 348ff3f0789SRoger Quadros #define DWC3_DCTL_L1_HIBER_EN BIT(18) 349ff3f0789SRoger Quadros #define DWC3_DCTL_CRS BIT(17) 350ff3f0789SRoger Quadros #define DWC3_DCTL_CSS BIT(16) 3512c61a8efSPaul Zimmerman 352ff3f0789SRoger Quadros #define DWC3_DCTL_INITU2ENA BIT(12) 353ff3f0789SRoger Quadros #define DWC3_DCTL_ACCEPTU2ENA BIT(11) 354ff3f0789SRoger Quadros #define DWC3_DCTL_INITU1ENA BIT(10) 355ff3f0789SRoger Quadros #define DWC3_DCTL_ACCEPTU1ENA BIT(9) 35672246da4SFelipe Balbi #define DWC3_DCTL_TSTCTRL_MASK (0xf << 1) 35772246da4SFelipe Balbi 35872246da4SFelipe Balbi #define DWC3_DCTL_ULSTCHNGREQ_MASK (0x0f << 5) 35972246da4SFelipe Balbi #define DWC3_DCTL_ULSTCHNGREQ(n) (((n) << 5) & DWC3_DCTL_ULSTCHNGREQ_MASK) 36072246da4SFelipe Balbi 36172246da4SFelipe Balbi #define DWC3_DCTL_ULSTCHNG_NO_ACTION (DWC3_DCTL_ULSTCHNGREQ(0)) 36272246da4SFelipe Balbi #define DWC3_DCTL_ULSTCHNG_SS_DISABLED (DWC3_DCTL_ULSTCHNGREQ(4)) 36372246da4SFelipe Balbi #define DWC3_DCTL_ULSTCHNG_RX_DETECT (DWC3_DCTL_ULSTCHNGREQ(5)) 36472246da4SFelipe Balbi #define DWC3_DCTL_ULSTCHNG_SS_INACTIVE (DWC3_DCTL_ULSTCHNGREQ(6)) 36572246da4SFelipe Balbi #define DWC3_DCTL_ULSTCHNG_RECOVERY (DWC3_DCTL_ULSTCHNGREQ(8)) 36672246da4SFelipe Balbi #define DWC3_DCTL_ULSTCHNG_COMPLIANCE (DWC3_DCTL_ULSTCHNGREQ(10)) 36772246da4SFelipe Balbi #define DWC3_DCTL_ULSTCHNG_LOOPBACK (DWC3_DCTL_ULSTCHNGREQ(11)) 36872246da4SFelipe Balbi 36972246da4SFelipe Balbi /* Device Event Enable Register */ 370ff3f0789SRoger Quadros #define DWC3_DEVTEN_VNDRDEVTSTRCVEDEN BIT(12) 371ff3f0789SRoger Quadros #define DWC3_DEVTEN_EVNTOVERFLOWEN BIT(11) 372ff3f0789SRoger Quadros #define DWC3_DEVTEN_CMDCMPLTEN BIT(10) 373ff3f0789SRoger Quadros #define DWC3_DEVTEN_ERRTICERREN BIT(9) 374ff3f0789SRoger Quadros #define DWC3_DEVTEN_SOFEN BIT(7) 375ff3f0789SRoger Quadros #define DWC3_DEVTEN_EOPFEN BIT(6) 376ff3f0789SRoger Quadros #define DWC3_DEVTEN_HIBERNATIONREQEVTEN BIT(5) 377ff3f0789SRoger Quadros #define DWC3_DEVTEN_WKUPEVTEN BIT(4) 378ff3f0789SRoger Quadros #define DWC3_DEVTEN_ULSTCNGEN BIT(3) 379ff3f0789SRoger Quadros #define DWC3_DEVTEN_CONNECTDONEEN BIT(2) 380ff3f0789SRoger Quadros #define DWC3_DEVTEN_USBRSTEN BIT(1) 381ff3f0789SRoger Quadros #define DWC3_DEVTEN_DISCONNEVTEN BIT(0) 38272246da4SFelipe Balbi 38372246da4SFelipe Balbi /* Device Status Register */ 384ff3f0789SRoger Quadros #define DWC3_DSTS_DCNRD BIT(29) 3852c61a8efSPaul Zimmerman 3862c61a8efSPaul Zimmerman /* This applies for core versions 1.87a and earlier */ 387ff3f0789SRoger Quadros #define DWC3_DSTS_PWRUPREQ BIT(24) 3882c61a8efSPaul Zimmerman 3892c61a8efSPaul Zimmerman /* These apply for core versions 1.94a and later */ 390ff3f0789SRoger Quadros #define DWC3_DSTS_RSS BIT(25) 391ff3f0789SRoger Quadros #define DWC3_DSTS_SSS BIT(24) 3922c61a8efSPaul Zimmerman 393ff3f0789SRoger Quadros #define DWC3_DSTS_COREIDLE BIT(23) 394ff3f0789SRoger Quadros #define DWC3_DSTS_DEVCTRLHLT BIT(22) 39572246da4SFelipe Balbi 39672246da4SFelipe Balbi #define DWC3_DSTS_USBLNKST_MASK (0x0f << 18) 39772246da4SFelipe Balbi #define DWC3_DSTS_USBLNKST(n) (((n) & DWC3_DSTS_USBLNKST_MASK) >> 18) 39872246da4SFelipe Balbi 399ff3f0789SRoger Quadros #define DWC3_DSTS_RXFIFOEMPTY BIT(17) 40072246da4SFelipe Balbi 401d05b8182SPratyush Anand #define DWC3_DSTS_SOFFN_MASK (0x3fff << 3) 40272246da4SFelipe Balbi #define DWC3_DSTS_SOFFN(n) (((n) & DWC3_DSTS_SOFFN_MASK) >> 3) 40372246da4SFelipe Balbi 40472246da4SFelipe Balbi #define DWC3_DSTS_CONNECTSPD (7 << 0) 40572246da4SFelipe Balbi 4061f38f88aSJohn Youn #define DWC3_DSTS_SUPERSPEED_PLUS (5 << 0) /* DWC_usb31 only */ 40772246da4SFelipe Balbi #define DWC3_DSTS_SUPERSPEED (4 << 0) 40872246da4SFelipe Balbi #define DWC3_DSTS_HIGHSPEED (0 << 0) 409ff3f0789SRoger Quadros #define DWC3_DSTS_FULLSPEED BIT(0) 41072246da4SFelipe Balbi #define DWC3_DSTS_LOWSPEED (2 << 0) 41172246da4SFelipe Balbi 41272246da4SFelipe Balbi /* Device Generic Command Register */ 41372246da4SFelipe Balbi #define DWC3_DGCMD_SET_LMP 0x01 41472246da4SFelipe Balbi #define DWC3_DGCMD_SET_PERIODIC_PAR 0x02 41572246da4SFelipe Balbi #define DWC3_DGCMD_XMIT_FUNCTION 0x03 4162c61a8efSPaul Zimmerman 4172c61a8efSPaul Zimmerman /* These apply for core versions 1.94a and later */ 4182c61a8efSPaul Zimmerman #define DWC3_DGCMD_SET_SCRATCHPAD_ADDR_LO 0x04 4192c61a8efSPaul Zimmerman #define DWC3_DGCMD_SET_SCRATCHPAD_ADDR_HI 0x05 4202c61a8efSPaul Zimmerman 42172246da4SFelipe Balbi #define DWC3_DGCMD_SELECTED_FIFO_FLUSH 0x09 42272246da4SFelipe Balbi #define DWC3_DGCMD_ALL_FIFO_FLUSH 0x0a 42372246da4SFelipe Balbi #define DWC3_DGCMD_SET_ENDPOINT_NRDY 0x0c 42472246da4SFelipe Balbi #define DWC3_DGCMD_RUN_SOC_BUS_LOOPBACK 0x10 42572246da4SFelipe Balbi 426459e210cSSubbaraya Sundeep Bhatta #define DWC3_DGCMD_STATUS(n) (((n) >> 12) & 0x0F) 427ff3f0789SRoger Quadros #define DWC3_DGCMD_CMDACT BIT(10) 428ff3f0789SRoger Quadros #define DWC3_DGCMD_CMDIOC BIT(8) 4292c61a8efSPaul Zimmerman 4302c61a8efSPaul Zimmerman /* Device Generic Command Parameter Register */ 431ff3f0789SRoger Quadros #define DWC3_DGCMDPAR_FORCE_LINKPM_ACCEPT BIT(0) 4322c61a8efSPaul Zimmerman #define DWC3_DGCMDPAR_FIFO_NUM(n) ((n) << 0) 4332c61a8efSPaul Zimmerman #define DWC3_DGCMDPAR_RX_FIFO (0 << 5) 434ff3f0789SRoger Quadros #define DWC3_DGCMDPAR_TX_FIFO BIT(5) 4352c61a8efSPaul Zimmerman #define DWC3_DGCMDPAR_LOOPBACK_DIS (0 << 0) 436ff3f0789SRoger Quadros #define DWC3_DGCMDPAR_LOOPBACK_ENA BIT(0) 437b09bb642SFelipe Balbi 43872246da4SFelipe Balbi /* Device Endpoint Command Register */ 43972246da4SFelipe Balbi #define DWC3_DEPCMD_PARAM_SHIFT 16 4401d046793SPaul Zimmerman #define DWC3_DEPCMD_PARAM(x) ((x) << DWC3_DEPCMD_PARAM_SHIFT) 4411d046793SPaul Zimmerman #define DWC3_DEPCMD_GET_RSC_IDX(x) (((x) >> DWC3_DEPCMD_PARAM_SHIFT) & 0x7f) 442459e210cSSubbaraya Sundeep Bhatta #define DWC3_DEPCMD_STATUS(x) (((x) >> 12) & 0x0F) 443ff3f0789SRoger Quadros #define DWC3_DEPCMD_HIPRI_FORCERM BIT(11) 444ff3f0789SRoger Quadros #define DWC3_DEPCMD_CLEARPENDIN BIT(11) 445ff3f0789SRoger Quadros #define DWC3_DEPCMD_CMDACT BIT(10) 446ff3f0789SRoger Quadros #define DWC3_DEPCMD_CMDIOC BIT(8) 44772246da4SFelipe Balbi 44872246da4SFelipe Balbi #define DWC3_DEPCMD_DEPSTARTCFG (0x09 << 0) 44972246da4SFelipe Balbi #define DWC3_DEPCMD_ENDTRANSFER (0x08 << 0) 45072246da4SFelipe Balbi #define DWC3_DEPCMD_UPDATETRANSFER (0x07 << 0) 45172246da4SFelipe Balbi #define DWC3_DEPCMD_STARTTRANSFER (0x06 << 0) 45272246da4SFelipe Balbi #define DWC3_DEPCMD_CLEARSTALL (0x05 << 0) 45372246da4SFelipe Balbi #define DWC3_DEPCMD_SETSTALL (0x04 << 0) 4542c61a8efSPaul Zimmerman /* This applies for core versions 1.90a and earlier */ 45572246da4SFelipe Balbi #define DWC3_DEPCMD_GETSEQNUMBER (0x03 << 0) 4562c61a8efSPaul Zimmerman /* This applies for core versions 1.94a and later */ 4572c61a8efSPaul Zimmerman #define DWC3_DEPCMD_GETEPSTATE (0x03 << 0) 45872246da4SFelipe Balbi #define DWC3_DEPCMD_SETTRANSFRESOURCE (0x02 << 0) 45972246da4SFelipe Balbi #define DWC3_DEPCMD_SETEPCONFIG (0x01 << 0) 46072246da4SFelipe Balbi 4615999914fSFelipe Balbi #define DWC3_DEPCMD_CMD(x) ((x) & 0xf) 4625999914fSFelipe Balbi 46372246da4SFelipe Balbi /* The EP number goes 0..31 so ep0 is always out and ep1 is always in */ 464ff3f0789SRoger Quadros #define DWC3_DALEPENA_EP(n) BIT(n) 46572246da4SFelipe Balbi 46672246da4SFelipe Balbi #define DWC3_DEPCMD_TYPE_CONTROL 0 46772246da4SFelipe Balbi #define DWC3_DEPCMD_TYPE_ISOC 1 46872246da4SFelipe Balbi #define DWC3_DEPCMD_TYPE_BULK 2 46972246da4SFelipe Balbi #define DWC3_DEPCMD_TYPE_INTR 3 47072246da4SFelipe Balbi 471cf40b86bSJohn Youn #define DWC3_DEV_IMOD_COUNT_SHIFT 16 472cf40b86bSJohn Youn #define DWC3_DEV_IMOD_COUNT_MASK (0xffff << 16) 473cf40b86bSJohn Youn #define DWC3_DEV_IMOD_INTERVAL_SHIFT 0 474cf40b86bSJohn Youn #define DWC3_DEV_IMOD_INTERVAL_MASK (0xffff << 0) 475cf40b86bSJohn Youn 47672246da4SFelipe Balbi /* Structures */ 47772246da4SFelipe Balbi 478f6bafc6aSFelipe Balbi struct dwc3_trb; 47972246da4SFelipe Balbi 48072246da4SFelipe Balbi /** 48172246da4SFelipe Balbi * struct dwc3_event_buffer - Software event buffer representation 48272246da4SFelipe Balbi * @buf: _THE_ buffer 483d9fa4c63SJohn Youn * @cache: The buffer cache used in the threaded interrupt 48472246da4SFelipe Balbi * @length: size of this buffer 485abed4118SFelipe Balbi * @lpos: event offset 48660d04bbeSFelipe Balbi * @count: cache of last read event count register 487abed4118SFelipe Balbi * @flags: flags related to this event buffer 48872246da4SFelipe Balbi * @dma: dma_addr_t 48972246da4SFelipe Balbi * @dwc: pointer to DWC controller 49072246da4SFelipe Balbi */ 49172246da4SFelipe Balbi struct dwc3_event_buffer { 49272246da4SFelipe Balbi void *buf; 493d9fa4c63SJohn Youn void *cache; 49472246da4SFelipe Balbi unsigned length; 49572246da4SFelipe Balbi unsigned int lpos; 49660d04bbeSFelipe Balbi unsigned int count; 497abed4118SFelipe Balbi unsigned int flags; 498abed4118SFelipe Balbi 499abed4118SFelipe Balbi #define DWC3_EVENT_PENDING BIT(0) 50072246da4SFelipe Balbi 50172246da4SFelipe Balbi dma_addr_t dma; 50272246da4SFelipe Balbi 50372246da4SFelipe Balbi struct dwc3 *dwc; 50472246da4SFelipe Balbi }; 50572246da4SFelipe Balbi 506ff3f0789SRoger Quadros #define DWC3_EP_FLAG_STALLED BIT(0) 507ff3f0789SRoger Quadros #define DWC3_EP_FLAG_WEDGED BIT(1) 50872246da4SFelipe Balbi 50972246da4SFelipe Balbi #define DWC3_EP_DIRECTION_TX true 51072246da4SFelipe Balbi #define DWC3_EP_DIRECTION_RX false 51172246da4SFelipe Balbi 5128495036eSFelipe Balbi #define DWC3_TRB_NUM 256 51372246da4SFelipe Balbi 51472246da4SFelipe Balbi /** 51572246da4SFelipe Balbi * struct dwc3_ep - device side endpoint representation 51672246da4SFelipe Balbi * @endpoint: usb endpoint 517aa3342c8SFelipe Balbi * @pending_list: list of pending requests for this endpoint 518aa3342c8SFelipe Balbi * @started_list: list of started requests on this endpoint 51976a638f8SBaolin Wang * @wait_end_transfer: wait_queue_head_t for waiting on End Transfer complete 52074674cbfSFelipe Balbi * @lock: spinlock for endpoint request queue traversal 5212eb88016SFelipe Balbi * @regs: pointer to first endpoint register 52272246da4SFelipe Balbi * @trb_pool: array of transaction buffers 52372246da4SFelipe Balbi * @trb_pool_dma: dma address of @trb_pool 52453fd8818SFelipe Balbi * @trb_enqueue: enqueue 'pointer' into TRB array 52553fd8818SFelipe Balbi * @trb_dequeue: dequeue 'pointer' into TRB array 52672246da4SFelipe Balbi * @dwc: pointer to DWC controller 5274cfcf876SPaul Zimmerman * @saved_state: ep state saved during hibernation 52872246da4SFelipe Balbi * @flags: endpoint flags (wedged, stalled, ...) 52972246da4SFelipe Balbi * @number: endpoint number (1 - 15) 53072246da4SFelipe Balbi * @type: set to bmAttributes & USB_ENDPOINT_XFERTYPE_MASK 531b4996a86SFelipe Balbi * @resource_index: Resource transfer index 532c75f52fbSHuang Rui * @interval: the interval on which the ISOC transfer is started 53368d34c8aSFelipe Balbi * @allocated_requests: number of requests allocated 53468d34c8aSFelipe Balbi * @queued_requests: number of requests queued for transfer 53572246da4SFelipe Balbi * @name: a human readable name e.g. ep1out-bulk 53672246da4SFelipe Balbi * @direction: true for TX, false for RX 537879631aaSFelipe Balbi * @stream_capable: true when streams are enabled 53872246da4SFelipe Balbi */ 53972246da4SFelipe Balbi struct dwc3_ep { 54072246da4SFelipe Balbi struct usb_ep endpoint; 541aa3342c8SFelipe Balbi struct list_head pending_list; 542aa3342c8SFelipe Balbi struct list_head started_list; 54372246da4SFelipe Balbi 54476a638f8SBaolin Wang wait_queue_head_t wait_end_transfer; 54576a638f8SBaolin Wang 54674674cbfSFelipe Balbi spinlock_t lock; 5472eb88016SFelipe Balbi void __iomem *regs; 5482eb88016SFelipe Balbi 549f6bafc6aSFelipe Balbi struct dwc3_trb *trb_pool; 55072246da4SFelipe Balbi dma_addr_t trb_pool_dma; 55172246da4SFelipe Balbi struct dwc3 *dwc; 55272246da4SFelipe Balbi 5534cfcf876SPaul Zimmerman u32 saved_state; 55472246da4SFelipe Balbi unsigned flags; 555ff3f0789SRoger Quadros #define DWC3_EP_ENABLED BIT(0) 556ff3f0789SRoger Quadros #define DWC3_EP_STALL BIT(1) 557ff3f0789SRoger Quadros #define DWC3_EP_WEDGE BIT(2) 558ff3f0789SRoger Quadros #define DWC3_EP_BUSY BIT(4) 559ff3f0789SRoger Quadros #define DWC3_EP_PENDING_REQUEST BIT(5) 560ff3f0789SRoger Quadros #define DWC3_EP_MISSED_ISOC BIT(6) 561ff3f0789SRoger Quadros #define DWC3_EP_END_TRANSFER_PENDING BIT(7) 562ff3f0789SRoger Quadros #define DWC3_EP_TRANSFER_STARTED BIT(8) 56372246da4SFelipe Balbi 564984f66a6SFelipe Balbi /* This last one is specific to EP0 */ 565ff3f0789SRoger Quadros #define DWC3_EP0_DIR_IN BIT(31) 566984f66a6SFelipe Balbi 567c28f8259SFelipe Balbi /* 568c28f8259SFelipe Balbi * IMPORTANT: we *know* we have 256 TRBs in our @trb_pool, so we will 569c28f8259SFelipe Balbi * use a u8 type here. If anybody decides to increase number of TRBs to 570c28f8259SFelipe Balbi * anything larger than 256 - I can't see why people would want to do 571c28f8259SFelipe Balbi * this though - then this type needs to be changed. 572c28f8259SFelipe Balbi * 573c28f8259SFelipe Balbi * By using u8 types we ensure that our % operator when incrementing 574c28f8259SFelipe Balbi * enqueue and dequeue get optimized away by the compiler. 575c28f8259SFelipe Balbi */ 576c28f8259SFelipe Balbi u8 trb_enqueue; 577c28f8259SFelipe Balbi u8 trb_dequeue; 578c28f8259SFelipe Balbi 57972246da4SFelipe Balbi u8 number; 58072246da4SFelipe Balbi u8 type; 581b4996a86SFelipe Balbi u8 resource_index; 58268d34c8aSFelipe Balbi u32 allocated_requests; 58368d34c8aSFelipe Balbi u32 queued_requests; 58472246da4SFelipe Balbi u32 interval; 58572246da4SFelipe Balbi 58672246da4SFelipe Balbi char name[20]; 58772246da4SFelipe Balbi 58872246da4SFelipe Balbi unsigned direction:1; 589879631aaSFelipe Balbi unsigned stream_capable:1; 59072246da4SFelipe Balbi }; 59172246da4SFelipe Balbi 59272246da4SFelipe Balbi enum dwc3_phy { 59372246da4SFelipe Balbi DWC3_PHY_UNKNOWN = 0, 59472246da4SFelipe Balbi DWC3_PHY_USB3, 59572246da4SFelipe Balbi DWC3_PHY_USB2, 59672246da4SFelipe Balbi }; 59772246da4SFelipe Balbi 598b53c772dSFelipe Balbi enum dwc3_ep0_next { 599b53c772dSFelipe Balbi DWC3_EP0_UNKNOWN = 0, 600b53c772dSFelipe Balbi DWC3_EP0_COMPLETE, 601b53c772dSFelipe Balbi DWC3_EP0_NRDY_DATA, 602b53c772dSFelipe Balbi DWC3_EP0_NRDY_STATUS, 603b53c772dSFelipe Balbi }; 604b53c772dSFelipe Balbi 60572246da4SFelipe Balbi enum dwc3_ep0_state { 60672246da4SFelipe Balbi EP0_UNCONNECTED = 0, 607c7fcdeb2SFelipe Balbi EP0_SETUP_PHASE, 608c7fcdeb2SFelipe Balbi EP0_DATA_PHASE, 609c7fcdeb2SFelipe Balbi EP0_STATUS_PHASE, 61072246da4SFelipe Balbi }; 61172246da4SFelipe Balbi 61272246da4SFelipe Balbi enum dwc3_link_state { 61372246da4SFelipe Balbi /* In SuperSpeed */ 61472246da4SFelipe Balbi DWC3_LINK_STATE_U0 = 0x00, /* in HS, means ON */ 61572246da4SFelipe Balbi DWC3_LINK_STATE_U1 = 0x01, 61672246da4SFelipe Balbi DWC3_LINK_STATE_U2 = 0x02, /* in HS, means SLEEP */ 61772246da4SFelipe Balbi DWC3_LINK_STATE_U3 = 0x03, /* in HS, means SUSPEND */ 61872246da4SFelipe Balbi DWC3_LINK_STATE_SS_DIS = 0x04, 61972246da4SFelipe Balbi DWC3_LINK_STATE_RX_DET = 0x05, /* in HS, means Early Suspend */ 62072246da4SFelipe Balbi DWC3_LINK_STATE_SS_INACT = 0x06, 62172246da4SFelipe Balbi DWC3_LINK_STATE_POLL = 0x07, 62272246da4SFelipe Balbi DWC3_LINK_STATE_RECOV = 0x08, 62372246da4SFelipe Balbi DWC3_LINK_STATE_HRESET = 0x09, 62472246da4SFelipe Balbi DWC3_LINK_STATE_CMPLY = 0x0a, 62572246da4SFelipe Balbi DWC3_LINK_STATE_LPBK = 0x0b, 6262c61a8efSPaul Zimmerman DWC3_LINK_STATE_RESET = 0x0e, 6272c61a8efSPaul Zimmerman DWC3_LINK_STATE_RESUME = 0x0f, 62872246da4SFelipe Balbi DWC3_LINK_STATE_MASK = 0x0f, 62972246da4SFelipe Balbi }; 63072246da4SFelipe Balbi 631f6bafc6aSFelipe Balbi /* TRB Length, PCM and Status */ 632f6bafc6aSFelipe Balbi #define DWC3_TRB_SIZE_MASK (0x00ffffff) 633f6bafc6aSFelipe Balbi #define DWC3_TRB_SIZE_LENGTH(n) ((n) & DWC3_TRB_SIZE_MASK) 634f6bafc6aSFelipe Balbi #define DWC3_TRB_SIZE_PCM1(n) (((n) & 0x03) << 24) 635389f2828SPratyush Anand #define DWC3_TRB_SIZE_TRBSTS(n) (((n) & (0x0f << 28)) >> 28) 63672246da4SFelipe Balbi 637f6bafc6aSFelipe Balbi #define DWC3_TRBSTS_OK 0 638f6bafc6aSFelipe Balbi #define DWC3_TRBSTS_MISSED_ISOC 1 639f6bafc6aSFelipe Balbi #define DWC3_TRBSTS_SETUP_PENDING 2 6402c61a8efSPaul Zimmerman #define DWC3_TRB_STS_XFER_IN_PROG 4 64172246da4SFelipe Balbi 642f6bafc6aSFelipe Balbi /* TRB Control */ 643ff3f0789SRoger Quadros #define DWC3_TRB_CTRL_HWO BIT(0) 644ff3f0789SRoger Quadros #define DWC3_TRB_CTRL_LST BIT(1) 645ff3f0789SRoger Quadros #define DWC3_TRB_CTRL_CHN BIT(2) 646ff3f0789SRoger Quadros #define DWC3_TRB_CTRL_CSP BIT(3) 647f6bafc6aSFelipe Balbi #define DWC3_TRB_CTRL_TRBCTL(n) (((n) & 0x3f) << 4) 648ff3f0789SRoger Quadros #define DWC3_TRB_CTRL_ISP_IMI BIT(10) 649ff3f0789SRoger Quadros #define DWC3_TRB_CTRL_IOC BIT(11) 650f6bafc6aSFelipe Balbi #define DWC3_TRB_CTRL_SID_SOFN(n) (((n) & 0xffff) << 14) 651f6bafc6aSFelipe Balbi 652b058f3e8SFelipe Balbi #define DWC3_TRBCTL_TYPE(n) ((n) & (0x3f << 4)) 653f6bafc6aSFelipe Balbi #define DWC3_TRBCTL_NORMAL DWC3_TRB_CTRL_TRBCTL(1) 654f6bafc6aSFelipe Balbi #define DWC3_TRBCTL_CONTROL_SETUP DWC3_TRB_CTRL_TRBCTL(2) 655f6bafc6aSFelipe Balbi #define DWC3_TRBCTL_CONTROL_STATUS2 DWC3_TRB_CTRL_TRBCTL(3) 656f6bafc6aSFelipe Balbi #define DWC3_TRBCTL_CONTROL_STATUS3 DWC3_TRB_CTRL_TRBCTL(4) 657f6bafc6aSFelipe Balbi #define DWC3_TRBCTL_CONTROL_DATA DWC3_TRB_CTRL_TRBCTL(5) 658f6bafc6aSFelipe Balbi #define DWC3_TRBCTL_ISOCHRONOUS_FIRST DWC3_TRB_CTRL_TRBCTL(6) 659f6bafc6aSFelipe Balbi #define DWC3_TRBCTL_ISOCHRONOUS DWC3_TRB_CTRL_TRBCTL(7) 660f6bafc6aSFelipe Balbi #define DWC3_TRBCTL_LINK_TRB DWC3_TRB_CTRL_TRBCTL(8) 66172246da4SFelipe Balbi 66272246da4SFelipe Balbi /** 663f6bafc6aSFelipe Balbi * struct dwc3_trb - transfer request block (hw format) 66472246da4SFelipe Balbi * @bpl: DW0-3 66572246da4SFelipe Balbi * @bph: DW4-7 66672246da4SFelipe Balbi * @size: DW8-B 667bfad65eeSFelipe Balbi * @ctrl: DWC-F 66872246da4SFelipe Balbi */ 669f6bafc6aSFelipe Balbi struct dwc3_trb { 670f6bafc6aSFelipe Balbi u32 bpl; 671f6bafc6aSFelipe Balbi u32 bph; 672f6bafc6aSFelipe Balbi u32 size; 673f6bafc6aSFelipe Balbi u32 ctrl; 67472246da4SFelipe Balbi } __packed; 67572246da4SFelipe Balbi 67672246da4SFelipe Balbi /** 677bfad65eeSFelipe Balbi * struct dwc3_hwparams - copy of HWPARAMS registers 678bfad65eeSFelipe Balbi * @hwparams0: GHWPARAMS0 679bfad65eeSFelipe Balbi * @hwparams1: GHWPARAMS1 680bfad65eeSFelipe Balbi * @hwparams2: GHWPARAMS2 681bfad65eeSFelipe Balbi * @hwparams3: GHWPARAMS3 682bfad65eeSFelipe Balbi * @hwparams4: GHWPARAMS4 683bfad65eeSFelipe Balbi * @hwparams5: GHWPARAMS5 684bfad65eeSFelipe Balbi * @hwparams6: GHWPARAMS6 685bfad65eeSFelipe Balbi * @hwparams7: GHWPARAMS7 686bfad65eeSFelipe Balbi * @hwparams8: GHWPARAMS8 687a3299499SFelipe Balbi */ 688a3299499SFelipe Balbi struct dwc3_hwparams { 689a3299499SFelipe Balbi u32 hwparams0; 690a3299499SFelipe Balbi u32 hwparams1; 691a3299499SFelipe Balbi u32 hwparams2; 692a3299499SFelipe Balbi u32 hwparams3; 693a3299499SFelipe Balbi u32 hwparams4; 694a3299499SFelipe Balbi u32 hwparams5; 695a3299499SFelipe Balbi u32 hwparams6; 696a3299499SFelipe Balbi u32 hwparams7; 697a3299499SFelipe Balbi u32 hwparams8; 698a3299499SFelipe Balbi }; 699a3299499SFelipe Balbi 7000949e99bSFelipe Balbi /* HWPARAMS0 */ 7010949e99bSFelipe Balbi #define DWC3_MODE(n) ((n) & 0x7) 7020949e99bSFelipe Balbi 703457e84b6SFelipe Balbi #define DWC3_MDWIDTH(n) (((n) & 0xff00) >> 8) 704457e84b6SFelipe Balbi 7050949e99bSFelipe Balbi /* HWPARAMS1 */ 7069f622b2aSFelipe Balbi #define DWC3_NUM_INT(n) (((n) & (0x3f << 15)) >> 15) 7079f622b2aSFelipe Balbi 708789451f6SFelipe Balbi /* HWPARAMS3 */ 709789451f6SFelipe Balbi #define DWC3_NUM_IN_EPS_MASK (0x1f << 18) 710789451f6SFelipe Balbi #define DWC3_NUM_EPS_MASK (0x3f << 12) 711789451f6SFelipe Balbi #define DWC3_NUM_EPS(p) (((p)->hwparams3 & \ 712789451f6SFelipe Balbi (DWC3_NUM_EPS_MASK)) >> 12) 713789451f6SFelipe Balbi #define DWC3_NUM_IN_EPS(p) (((p)->hwparams3 & \ 714789451f6SFelipe Balbi (DWC3_NUM_IN_EPS_MASK)) >> 18) 715789451f6SFelipe Balbi 716457e84b6SFelipe Balbi /* HWPARAMS7 */ 717457e84b6SFelipe Balbi #define DWC3_RAM1_DEPTH(n) ((n) & 0xffff) 718457e84b6SFelipe Balbi 7195ef68c56SFelipe Balbi /** 7205ef68c56SFelipe Balbi * struct dwc3_request - representation of a transfer request 7215ef68c56SFelipe Balbi * @request: struct usb_request to be transferred 7225ef68c56SFelipe Balbi * @list: a list_head used for request queueing 7235ef68c56SFelipe Balbi * @dep: struct dwc3_ep owning this request 7240b3e4af3SFelipe Balbi * @sg: pointer to first incomplete sg 7250b3e4af3SFelipe Balbi * @num_pending_sgs: counter to pending sgs 726e62c5bc5SFelipe Balbi * @remaining: amount of data remaining 7275ef68c56SFelipe Balbi * @epnum: endpoint number to which this request refers 7285ef68c56SFelipe Balbi * @trb: pointer to struct dwc3_trb 7295ef68c56SFelipe Balbi * @trb_dma: DMA address of @trb 730c6267a51SFelipe Balbi * @unaligned: true for OUT endpoints with length not divisible by maxp 7315ef68c56SFelipe Balbi * @direction: IN or OUT direction flag 7325ef68c56SFelipe Balbi * @mapped: true when request has been dma-mapped 733bfad65eeSFelipe Balbi * @started: request is started 734bfad65eeSFelipe Balbi * @zero: wants a ZLP 7355ef68c56SFelipe Balbi */ 736e0ce0b0aSSebastian Andrzej Siewior struct dwc3_request { 737e0ce0b0aSSebastian Andrzej Siewior struct usb_request request; 738e0ce0b0aSSebastian Andrzej Siewior struct list_head list; 739e0ce0b0aSSebastian Andrzej Siewior struct dwc3_ep *dep; 7400b3e4af3SFelipe Balbi struct scatterlist *sg; 741e0ce0b0aSSebastian Andrzej Siewior 7420b3e4af3SFelipe Balbi unsigned num_pending_sgs; 743e62c5bc5SFelipe Balbi unsigned remaining; 744e0ce0b0aSSebastian Andrzej Siewior u8 epnum; 745f6bafc6aSFelipe Balbi struct dwc3_trb *trb; 746e0ce0b0aSSebastian Andrzej Siewior dma_addr_t trb_dma; 747e0ce0b0aSSebastian Andrzej Siewior 748c6267a51SFelipe Balbi unsigned unaligned:1; 749e0ce0b0aSSebastian Andrzej Siewior unsigned direction:1; 750e0ce0b0aSSebastian Andrzej Siewior unsigned mapped:1; 751aa3342c8SFelipe Balbi unsigned started:1; 752d6e5a549SFelipe Balbi unsigned zero:1; 753e0ce0b0aSSebastian Andrzej Siewior }; 754e0ce0b0aSSebastian Andrzej Siewior 7552c61a8efSPaul Zimmerman /* 7562c61a8efSPaul Zimmerman * struct dwc3_scratchpad_array - hibernation scratchpad array 7572c61a8efSPaul Zimmerman * (format defined by hw) 7582c61a8efSPaul Zimmerman */ 7592c61a8efSPaul Zimmerman struct dwc3_scratchpad_array { 7602c61a8efSPaul Zimmerman __le64 dma_adr[DWC3_MAX_HIBER_SCRATCHBUFS]; 7612c61a8efSPaul Zimmerman }; 7622c61a8efSPaul Zimmerman 763a3299499SFelipe Balbi /** 76472246da4SFelipe Balbi * struct dwc3 - representation of our controller 765bfad65eeSFelipe Balbi * @drd_work: workqueue used for role swapping 76691db07dcSFelipe Balbi * @ep0_trb: trb which is used for the ctrl_req 767bfad65eeSFelipe Balbi * @bounce: address of bounce buffer 768bfad65eeSFelipe Balbi * @scratchbuf: address of scratch buffer 76991db07dcSFelipe Balbi * @setup_buf: used while precessing STD USB requests 770bfad65eeSFelipe Balbi * @ep0_trb_addr: dma address of @ep0_trb 771bfad65eeSFelipe Balbi * @bounce_addr: dma address of @bounce 77291db07dcSFelipe Balbi * @ep0_usb_req: dummy req used while handling STD USB requests 7730ffcaf37SFelipe Balbi * @scratch_addr: dma address of scratchbuf 774bb014736SBaolin Wang * @ep0_in_setup: one control transfer is completed and enter setup phase 77572246da4SFelipe Balbi * @lock: for synchronizing 77672246da4SFelipe Balbi * @dev: pointer to our struct device 777bfad65eeSFelipe Balbi * @sysdev: pointer to the DMA-capable device 778d07e8819SFelipe Balbi * @xhci: pointer to our xHCI child 779bfad65eeSFelipe Balbi * @xhci_resources: struct resources for our @xhci child 780bfad65eeSFelipe Balbi * @ev_buf: struct dwc3_event_buffer pointer 781bfad65eeSFelipe Balbi * @eps: endpoint array 78272246da4SFelipe Balbi * @gadget: device side representation of the peripheral controller 78372246da4SFelipe Balbi * @gadget_driver: pointer to the gadget driver 78472246da4SFelipe Balbi * @regs: base address for our registers 78572246da4SFelipe Balbi * @regs_size: address space size 786bcdb3272SFelipe Balbi * @fladj: frame length adjustment 7873f308d17SFelipe Balbi * @irq_gadget: peripheral controller's IRQ number 7880ffcaf37SFelipe Balbi * @nr_scratch: number of scratch buffers 789fae2b904SFelipe Balbi * @u1u2: only used on revisions <1.83a for workaround 7906c167fc9SFelipe Balbi * @maximum_speed: maximum speed requested (mainly for testing purposes) 79172246da4SFelipe Balbi * @revision: revision register contents 792a45c82b8SRuchika Kharwar * @dr_mode: requested mode of operation 7936b3261a2SRoger Quadros * @current_dr_role: current role of operation when in dual-role mode 79441ce1456SRoger Quadros * @desired_dr_role: desired role of operation when in dual-role mode 7959840354fSRoger Quadros * @edev: extcon handle 7969840354fSRoger Quadros * @edev_nb: extcon notifier 79732f2ed86SWilliam Wu * @hsphy_mode: UTMI phy mode, one of following: 79832f2ed86SWilliam Wu * - USBPHY_INTERFACE_MODE_UTMI 79932f2ed86SWilliam Wu * - USBPHY_INTERFACE_MODE_UTMIW 80051e1e7bcSFelipe Balbi * @usb2_phy: pointer to USB2 PHY 80151e1e7bcSFelipe Balbi * @usb3_phy: pointer to USB3 PHY 80257303488SKishon Vijay Abraham I * @usb2_generic_phy: pointer to USB2 PHY 80357303488SKishon Vijay Abraham I * @usb3_generic_phy: pointer to USB3 PHY 80488bc9d19SHeikki Krogerus * @ulpi: pointer to ulpi interface 805c12a0d86SFelipe Balbi * @isoch_delay: wValue from Set Isochronous Delay request; 806865e09e7SFelipe Balbi * @u2sel: parameter from Set SEL request. 807865e09e7SFelipe Balbi * @u2pel: parameter from Set SEL request. 808865e09e7SFelipe Balbi * @u1sel: parameter from Set SEL request. 809865e09e7SFelipe Balbi * @u1pel: parameter from Set SEL request. 81047d3946eSBryan O'Donoghue * @num_eps: number of endpoints 811b53c772dSFelipe Balbi * @ep0_next_event: hold the next expected event 81272246da4SFelipe Balbi * @ep0state: state of endpoint zero 81372246da4SFelipe Balbi * @link_state: link state 81472246da4SFelipe Balbi * @speed: device speed (super, high, full, low) 815a3299499SFelipe Balbi * @hwparams: copy of hwparams registers 81672246da4SFelipe Balbi * @root: debugfs root folder pointer 817f2b685d5SFelipe Balbi * @regset: debugfs pointer to regdump file 818f2b685d5SFelipe Balbi * @test_mode: true when we're entering a USB test mode 819f2b685d5SFelipe Balbi * @test_mode_nr: test feature selector 82080caf7d2SHuang Rui * @lpm_nyet_threshold: LPM NYET response threshold 821460d098cSHuang Rui * @hird_threshold: HIRD threshold 8223e10a2ceSHeikki Krogerus * @hsphy_interface: "utmi" or "ulpi" 823fc8bb91bSFelipe Balbi * @connected: true when we're connected to a host, false otherwise 824f2b685d5SFelipe Balbi * @delayed_status: true when gadget driver asks for delayed status 825f2b685d5SFelipe Balbi * @ep0_bounced: true when we used bounce buffer 826f2b685d5SFelipe Balbi * @ep0_expect_in: true when we expect a DATA IN transfer 82781bc5599SFelipe Balbi * @has_hibernation: true when dwc3 was configured with Hibernation 828d64ff406SArnd Bergmann * @sysdev_is_parent: true when dwc3 device has a parent driver 82980caf7d2SHuang Rui * @has_lpm_erratum: true when core was configured with LPM Erratum. Note that 83080caf7d2SHuang Rui * there's now way for software to detect this in runtime. 831460d098cSHuang Rui * @is_utmi_l1_suspend: the core asserts output signal 832460d098cSHuang Rui * 0 - utmi_sleep_n 833460d098cSHuang Rui * 1 - utmi_l1_suspend_n 834946bd579SHuang Rui * @is_fpga: true when we are using the FPGA board 835fc8bb91bSFelipe Balbi * @pending_events: true when we have pending IRQs to be handled 836f2b685d5SFelipe Balbi * @pullups_connected: true when Run/Stop bit is set 837f2b685d5SFelipe Balbi * @setup_packet_pending: true when there's a Setup Packet in FIFO. Workaround 838f2b685d5SFelipe Balbi * @three_stage_setup: set if we perform a three phase setup 839eac68e8fSRobert Baldyga * @usb3_lpm_capable: set if hadrware supports Link Power Management 8403b81221aSHuang Rui * @disable_scramble_quirk: set if we enable the disable scramble quirk 8419a5b2f31SHuang Rui * @u2exit_lfps_quirk: set if we enable u2exit lfps quirk 842b5a65c40SHuang Rui * @u2ss_inp3_quirk: set if we enable P3 OK for U2/SS Inactive quirk 843df31f5b3SHuang Rui * @req_p1p2p3_quirk: set if we enable request p1p2p3 quirk 844a2a1d0f5SHuang Rui * @del_p1p2p3_quirk: set if we enable delay p1p2p3 quirk 84541c06ffdSHuang Rui * @del_phy_power_chg_quirk: set if we enable delay phy power change quirk 846fb67afcaSHuang Rui * @lfps_filter_quirk: set if we enable LFPS filter quirk 84714f4ac53SHuang Rui * @rx_detect_poll_quirk: set if we enable rx_detect to polling lfps quirk 84859acfa20SHuang Rui * @dis_u3_susphy_quirk: set if we disable usb3 suspend phy 8490effe0a3SHuang Rui * @dis_u2_susphy_quirk: set if we disable usb2 suspend phy 850ec791d14SJohn Youn * @dis_enblslpm_quirk: set if we clear enblslpm in GUSB2PHYCFG, 851ec791d14SJohn Youn * disabling the suspend signal to the PHY. 852bfad65eeSFelipe Balbi * @dis_rxdet_inp3_quirk: set if we disable Rx.Detect in P3 85316199f33SWilliam Wu * @dis_u2_freeclk_exists_quirk : set if we clear u2_freeclk_exists 85416199f33SWilliam Wu * in GUSB2PHYCFG, specify that USB2 PHY doesn't 85516199f33SWilliam Wu * provide a free-running PHY clock. 85600fe081dSWilliam Wu * @dis_del_phy_power_chg_quirk: set if we disable delay phy power 85700fe081dSWilliam Wu * change quirk. 85865db7a0cSWilliam Wu * @dis_tx_ipgap_linecheck_quirk: set if we disable u2mac linestate 85965db7a0cSWilliam Wu * check during HS transmit. 8606b6a0c9aSHuang Rui * @tx_de_emphasis_quirk: set if we enable Tx de-emphasis quirk 8616b6a0c9aSHuang Rui * @tx_de_emphasis: Tx de-emphasis value 8626b6a0c9aSHuang Rui * 0 - -6dB de-emphasis 8636b6a0c9aSHuang Rui * 1 - -3.5dB de-emphasis 8646b6a0c9aSHuang Rui * 2 - No de-emphasis 8656b6a0c9aSHuang Rui * 3 - Reserved 866cf40b86bSJohn Youn * @imod_interval: set the interrupt moderation interval in 250ns 867cf40b86bSJohn Youn * increments or 0 to disable. 86872246da4SFelipe Balbi */ 86972246da4SFelipe Balbi struct dwc3 { 87041ce1456SRoger Quadros struct work_struct drd_work; 871f6bafc6aSFelipe Balbi struct dwc3_trb *ep0_trb; 872905dc04eSFelipe Balbi void *bounce; 8730ffcaf37SFelipe Balbi void *scratchbuf; 87472246da4SFelipe Balbi u8 *setup_buf; 87572246da4SFelipe Balbi dma_addr_t ep0_trb_addr; 876905dc04eSFelipe Balbi dma_addr_t bounce_addr; 8770ffcaf37SFelipe Balbi dma_addr_t scratch_addr; 878e0ce0b0aSSebastian Andrzej Siewior struct dwc3_request ep0_usb_req; 879bb014736SBaolin Wang struct completion ep0_in_setup; 880789451f6SFelipe Balbi 88172246da4SFelipe Balbi /* device lock */ 88272246da4SFelipe Balbi spinlock_t lock; 883789451f6SFelipe Balbi 88472246da4SFelipe Balbi struct device *dev; 885d64ff406SArnd Bergmann struct device *sysdev; 88672246da4SFelipe Balbi 887d07e8819SFelipe Balbi struct platform_device *xhci; 88851249dcaSIdo Shayevitz struct resource xhci_resources[DWC3_XHCI_RESOURCES_NUM]; 889d07e8819SFelipe Balbi 890696c8b12SFelipe Balbi struct dwc3_event_buffer *ev_buf; 89172246da4SFelipe Balbi struct dwc3_ep *eps[DWC3_ENDPOINTS_NUM]; 89272246da4SFelipe Balbi 89372246da4SFelipe Balbi struct usb_gadget gadget; 89472246da4SFelipe Balbi struct usb_gadget_driver *gadget_driver; 89572246da4SFelipe Balbi 89651e1e7bcSFelipe Balbi struct usb_phy *usb2_phy; 89751e1e7bcSFelipe Balbi struct usb_phy *usb3_phy; 89851e1e7bcSFelipe Balbi 89957303488SKishon Vijay Abraham I struct phy *usb2_generic_phy; 90057303488SKishon Vijay Abraham I struct phy *usb3_generic_phy; 90157303488SKishon Vijay Abraham I 90288bc9d19SHeikki Krogerus struct ulpi *ulpi; 90388bc9d19SHeikki Krogerus 90472246da4SFelipe Balbi void __iomem *regs; 90572246da4SFelipe Balbi size_t regs_size; 90672246da4SFelipe Balbi 907a45c82b8SRuchika Kharwar enum usb_dr_mode dr_mode; 9086b3261a2SRoger Quadros u32 current_dr_role; 90941ce1456SRoger Quadros u32 desired_dr_role; 9109840354fSRoger Quadros struct extcon_dev *edev; 9119840354fSRoger Quadros struct notifier_block edev_nb; 91232f2ed86SWilliam Wu enum usb_phy_interface hsphy_mode; 913a45c82b8SRuchika Kharwar 914bcdb3272SFelipe Balbi u32 fladj; 9153f308d17SFelipe Balbi u32 irq_gadget; 9160ffcaf37SFelipe Balbi u32 nr_scratch; 917fae2b904SFelipe Balbi u32 u1u2; 9186c167fc9SFelipe Balbi u32 maximum_speed; 919690fb371SJohn Youn 920690fb371SJohn Youn /* 921690fb371SJohn Youn * All 3.1 IP version constants are greater than the 3.0 IP 922690fb371SJohn Youn * version constants. This works for most version checks in 923690fb371SJohn Youn * dwc3. However, in the future, this may not apply as 924690fb371SJohn Youn * features may be developed on newer versions of the 3.0 IP 925690fb371SJohn Youn * that are not in the 3.1 IP. 926690fb371SJohn Youn */ 92772246da4SFelipe Balbi u32 revision; 92872246da4SFelipe Balbi 92972246da4SFelipe Balbi #define DWC3_REVISION_173A 0x5533173a 93072246da4SFelipe Balbi #define DWC3_REVISION_175A 0x5533175a 93172246da4SFelipe Balbi #define DWC3_REVISION_180A 0x5533180a 93272246da4SFelipe Balbi #define DWC3_REVISION_183A 0x5533183a 93372246da4SFelipe Balbi #define DWC3_REVISION_185A 0x5533185a 9342c61a8efSPaul Zimmerman #define DWC3_REVISION_187A 0x5533187a 93572246da4SFelipe Balbi #define DWC3_REVISION_188A 0x5533188a 93672246da4SFelipe Balbi #define DWC3_REVISION_190A 0x5533190a 9372c61a8efSPaul Zimmerman #define DWC3_REVISION_194A 0x5533194a 9381522d703SFelipe Balbi #define DWC3_REVISION_200A 0x5533200a 9391522d703SFelipe Balbi #define DWC3_REVISION_202A 0x5533202a 9401522d703SFelipe Balbi #define DWC3_REVISION_210A 0x5533210a 9411522d703SFelipe Balbi #define DWC3_REVISION_220A 0x5533220a 9427ac6a593SFelipe Balbi #define DWC3_REVISION_230A 0x5533230a 9437ac6a593SFelipe Balbi #define DWC3_REVISION_240A 0x5533240a 9447ac6a593SFelipe Balbi #define DWC3_REVISION_250A 0x5533250a 945dbf5aaf7SFelipe Balbi #define DWC3_REVISION_260A 0x5533260a 946dbf5aaf7SFelipe Balbi #define DWC3_REVISION_270A 0x5533270a 947dbf5aaf7SFelipe Balbi #define DWC3_REVISION_280A 0x5533280a 9480bb39ca1SJohn Youn #define DWC3_REVISION_290A 0x5533290a 949512e4757SJohn Youn #define DWC3_REVISION_300A 0x5533300a 950512e4757SJohn Youn #define DWC3_REVISION_310A 0x5533310a 95172246da4SFelipe Balbi 952690fb371SJohn Youn /* 953690fb371SJohn Youn * NOTICE: we're using bit 31 as a "is usb 3.1" flag. This is really 954690fb371SJohn Youn * just so dwc31 revisions are always larger than dwc3. 955690fb371SJohn Youn */ 956690fb371SJohn Youn #define DWC3_REVISION_IS_DWC31 0x80000000 957e77c5614SJohn Youn #define DWC3_USB31_REVISION_110A (0x3131302a | DWC3_REVISION_IS_DWC31) 958cf40b86bSJohn Youn #define DWC3_USB31_REVISION_120A (0x3132302a | DWC3_REVISION_IS_DWC31) 959690fb371SJohn Youn 960b53c772dSFelipe Balbi enum dwc3_ep0_next ep0_next_event; 96172246da4SFelipe Balbi enum dwc3_ep0_state ep0state; 96272246da4SFelipe Balbi enum dwc3_link_state link_state; 96372246da4SFelipe Balbi 964c12a0d86SFelipe Balbi u16 isoch_delay; 965865e09e7SFelipe Balbi u16 u2sel; 966865e09e7SFelipe Balbi u16 u2pel; 967865e09e7SFelipe Balbi u8 u1sel; 968865e09e7SFelipe Balbi u8 u1pel; 969865e09e7SFelipe Balbi 97072246da4SFelipe Balbi u8 speed; 971865e09e7SFelipe Balbi 97247d3946eSBryan O'Donoghue u8 num_eps; 973789451f6SFelipe Balbi 974a3299499SFelipe Balbi struct dwc3_hwparams hwparams; 97572246da4SFelipe Balbi struct dentry *root; 976d7668024SFelipe Balbi struct debugfs_regset32 *regset; 9773b637367SGerard Cauvy 9783b637367SGerard Cauvy u8 test_mode; 9793b637367SGerard Cauvy u8 test_mode_nr; 98080caf7d2SHuang Rui u8 lpm_nyet_threshold; 981460d098cSHuang Rui u8 hird_threshold; 982f2b685d5SFelipe Balbi 9833e10a2ceSHeikki Krogerus const char *hsphy_interface; 9843e10a2ceSHeikki Krogerus 985fc8bb91bSFelipe Balbi unsigned connected:1; 986f2b685d5SFelipe Balbi unsigned delayed_status:1; 987f2b685d5SFelipe Balbi unsigned ep0_bounced:1; 988f2b685d5SFelipe Balbi unsigned ep0_expect_in:1; 98981bc5599SFelipe Balbi unsigned has_hibernation:1; 990d64ff406SArnd Bergmann unsigned sysdev_is_parent:1; 99180caf7d2SHuang Rui unsigned has_lpm_erratum:1; 992460d098cSHuang Rui unsigned is_utmi_l1_suspend:1; 993946bd579SHuang Rui unsigned is_fpga:1; 994fc8bb91bSFelipe Balbi unsigned pending_events:1; 995f2b685d5SFelipe Balbi unsigned pullups_connected:1; 996f2b685d5SFelipe Balbi unsigned setup_packet_pending:1; 997f2b685d5SFelipe Balbi unsigned three_stage_setup:1; 998eac68e8fSRobert Baldyga unsigned usb3_lpm_capable:1; 9993b81221aSHuang Rui 10003b81221aSHuang Rui unsigned disable_scramble_quirk:1; 10019a5b2f31SHuang Rui unsigned u2exit_lfps_quirk:1; 1002b5a65c40SHuang Rui unsigned u2ss_inp3_quirk:1; 1003df31f5b3SHuang Rui unsigned req_p1p2p3_quirk:1; 1004a2a1d0f5SHuang Rui unsigned del_p1p2p3_quirk:1; 100541c06ffdSHuang Rui unsigned del_phy_power_chg_quirk:1; 1006fb67afcaSHuang Rui unsigned lfps_filter_quirk:1; 100714f4ac53SHuang Rui unsigned rx_detect_poll_quirk:1; 100859acfa20SHuang Rui unsigned dis_u3_susphy_quirk:1; 10090effe0a3SHuang Rui unsigned dis_u2_susphy_quirk:1; 1010ec791d14SJohn Youn unsigned dis_enblslpm_quirk:1; 1011e58dd357SRajesh Bhagat unsigned dis_rxdet_inp3_quirk:1; 101216199f33SWilliam Wu unsigned dis_u2_freeclk_exists_quirk:1; 101300fe081dSWilliam Wu unsigned dis_del_phy_power_chg_quirk:1; 101465db7a0cSWilliam Wu unsigned dis_tx_ipgap_linecheck_quirk:1; 10156b6a0c9aSHuang Rui 10166b6a0c9aSHuang Rui unsigned tx_de_emphasis_quirk:1; 10176b6a0c9aSHuang Rui unsigned tx_de_emphasis:2; 1018cf40b86bSJohn Youn 1019cf40b86bSJohn Youn u16 imod_interval; 102072246da4SFelipe Balbi }; 102172246da4SFelipe Balbi 102241ce1456SRoger Quadros #define work_to_dwc(w) (container_of((w), struct dwc3, drd_work)) 102372246da4SFelipe Balbi 102472246da4SFelipe Balbi /* -------------------------------------------------------------------------- */ 102572246da4SFelipe Balbi 102672246da4SFelipe Balbi struct dwc3_event_type { 102772246da4SFelipe Balbi u32 is_devspec:1; 10281974d494SHuang Rui u32 type:7; 10291974d494SHuang Rui u32 reserved8_31:24; 103072246da4SFelipe Balbi } __packed; 103172246da4SFelipe Balbi 103272246da4SFelipe Balbi #define DWC3_DEPEVT_XFERCOMPLETE 0x01 103372246da4SFelipe Balbi #define DWC3_DEPEVT_XFERINPROGRESS 0x02 103472246da4SFelipe Balbi #define DWC3_DEPEVT_XFERNOTREADY 0x03 103572246da4SFelipe Balbi #define DWC3_DEPEVT_RXTXFIFOEVT 0x04 103672246da4SFelipe Balbi #define DWC3_DEPEVT_STREAMEVT 0x06 103772246da4SFelipe Balbi #define DWC3_DEPEVT_EPCMDCMPLT 0x07 103872246da4SFelipe Balbi 103972246da4SFelipe Balbi /** 104072246da4SFelipe Balbi * struct dwc3_event_depvt - Device Endpoint Events 104172246da4SFelipe Balbi * @one_bit: indicates this is an endpoint event (not used) 104272246da4SFelipe Balbi * @endpoint_number: number of the endpoint 104372246da4SFelipe Balbi * @endpoint_event: The event we have: 104472246da4SFelipe Balbi * 0x00 - Reserved 104572246da4SFelipe Balbi * 0x01 - XferComplete 104672246da4SFelipe Balbi * 0x02 - XferInProgress 104772246da4SFelipe Balbi * 0x03 - XferNotReady 104872246da4SFelipe Balbi * 0x04 - RxTxFifoEvt (IN->Underrun, OUT->Overrun) 104972246da4SFelipe Balbi * 0x05 - Reserved 105072246da4SFelipe Balbi * 0x06 - StreamEvt 105172246da4SFelipe Balbi * 0x07 - EPCmdCmplt 105272246da4SFelipe Balbi * @reserved11_10: Reserved, don't use. 105372246da4SFelipe Balbi * @status: Indicates the status of the event. Refer to databook for 105472246da4SFelipe Balbi * more information. 105572246da4SFelipe Balbi * @parameters: Parameters of the current event. Refer to databook for 105672246da4SFelipe Balbi * more information. 105772246da4SFelipe Balbi */ 105872246da4SFelipe Balbi struct dwc3_event_depevt { 105972246da4SFelipe Balbi u32 one_bit:1; 106072246da4SFelipe Balbi u32 endpoint_number:5; 106172246da4SFelipe Balbi u32 endpoint_event:4; 106272246da4SFelipe Balbi u32 reserved11_10:2; 106372246da4SFelipe Balbi u32 status:4; 106440aa41fbSFelipe Balbi 106540aa41fbSFelipe Balbi /* Within XferNotReady */ 1066ff3f0789SRoger Quadros #define DEPEVT_STATUS_TRANSFER_ACTIVE BIT(3) 106740aa41fbSFelipe Balbi 106840aa41fbSFelipe Balbi /* Within XferComplete */ 1069ff3f0789SRoger Quadros #define DEPEVT_STATUS_BUSERR BIT(0) 1070ff3f0789SRoger Quadros #define DEPEVT_STATUS_SHORT BIT(1) 1071ff3f0789SRoger Quadros #define DEPEVT_STATUS_IOC BIT(2) 1072ff3f0789SRoger Quadros #define DEPEVT_STATUS_LST BIT(3) 1073dc137f01SFelipe Balbi 1074879631aaSFelipe Balbi /* Stream event only */ 1075879631aaSFelipe Balbi #define DEPEVT_STREAMEVT_FOUND 1 1076879631aaSFelipe Balbi #define DEPEVT_STREAMEVT_NOTFOUND 2 1077879631aaSFelipe Balbi 1078dc137f01SFelipe Balbi /* Control-only Status */ 1079dc137f01SFelipe Balbi #define DEPEVT_STATUS_CONTROL_DATA 1 1080dc137f01SFelipe Balbi #define DEPEVT_STATUS_CONTROL_STATUS 2 108145a2af2fSFelipe Balbi #define DEPEVT_STATUS_CONTROL_PHASE(n) ((n) & 3) 1082dc137f01SFelipe Balbi 10837b9cc7a2SKonrad Leszczynski /* In response to Start Transfer */ 10847b9cc7a2SKonrad Leszczynski #define DEPEVT_TRANSFER_NO_RESOURCE 1 10857b9cc7a2SKonrad Leszczynski #define DEPEVT_TRANSFER_BUS_EXPIRY 2 10867b9cc7a2SKonrad Leszczynski 108772246da4SFelipe Balbi u32 parameters:16; 108876a638f8SBaolin Wang 108976a638f8SBaolin Wang /* For Command Complete Events */ 109076a638f8SBaolin Wang #define DEPEVT_PARAMETER_CMD(n) (((n) & (0xf << 8)) >> 8) 109172246da4SFelipe Balbi } __packed; 109272246da4SFelipe Balbi 109372246da4SFelipe Balbi /** 109472246da4SFelipe Balbi * struct dwc3_event_devt - Device Events 109572246da4SFelipe Balbi * @one_bit: indicates this is a non-endpoint event (not used) 109672246da4SFelipe Balbi * @device_event: indicates it's a device event. Should read as 0x00 109772246da4SFelipe Balbi * @type: indicates the type of device event. 109872246da4SFelipe Balbi * 0 - DisconnEvt 109972246da4SFelipe Balbi * 1 - USBRst 110072246da4SFelipe Balbi * 2 - ConnectDone 110172246da4SFelipe Balbi * 3 - ULStChng 110272246da4SFelipe Balbi * 4 - WkUpEvt 110372246da4SFelipe Balbi * 5 - Reserved 110472246da4SFelipe Balbi * 6 - EOPF 110572246da4SFelipe Balbi * 7 - SOF 110672246da4SFelipe Balbi * 8 - Reserved 110772246da4SFelipe Balbi * 9 - ErrticErr 110872246da4SFelipe Balbi * 10 - CmdCmplt 110972246da4SFelipe Balbi * 11 - EvntOverflow 111072246da4SFelipe Balbi * 12 - VndrDevTstRcved 111172246da4SFelipe Balbi * @reserved15_12: Reserved, not used 111272246da4SFelipe Balbi * @event_info: Information about this event 111306f9b6e5SHuang Rui * @reserved31_25: Reserved, not used 111472246da4SFelipe Balbi */ 111572246da4SFelipe Balbi struct dwc3_event_devt { 111672246da4SFelipe Balbi u32 one_bit:1; 111772246da4SFelipe Balbi u32 device_event:7; 111872246da4SFelipe Balbi u32 type:4; 111972246da4SFelipe Balbi u32 reserved15_12:4; 112006f9b6e5SHuang Rui u32 event_info:9; 112106f9b6e5SHuang Rui u32 reserved31_25:7; 112272246da4SFelipe Balbi } __packed; 112372246da4SFelipe Balbi 112472246da4SFelipe Balbi /** 112572246da4SFelipe Balbi * struct dwc3_event_gevt - Other Core Events 112672246da4SFelipe Balbi * @one_bit: indicates this is a non-endpoint event (not used) 112772246da4SFelipe Balbi * @device_event: indicates it's (0x03) Carkit or (0x04) I2C event. 112872246da4SFelipe Balbi * @phy_port_number: self-explanatory 112972246da4SFelipe Balbi * @reserved31_12: Reserved, not used. 113072246da4SFelipe Balbi */ 113172246da4SFelipe Balbi struct dwc3_event_gevt { 113272246da4SFelipe Balbi u32 one_bit:1; 113372246da4SFelipe Balbi u32 device_event:7; 113472246da4SFelipe Balbi u32 phy_port_number:4; 113572246da4SFelipe Balbi u32 reserved31_12:20; 113672246da4SFelipe Balbi } __packed; 113772246da4SFelipe Balbi 113872246da4SFelipe Balbi /** 113972246da4SFelipe Balbi * union dwc3_event - representation of Event Buffer contents 114072246da4SFelipe Balbi * @raw: raw 32-bit event 114172246da4SFelipe Balbi * @type: the type of the event 114272246da4SFelipe Balbi * @depevt: Device Endpoint Event 114372246da4SFelipe Balbi * @devt: Device Event 114472246da4SFelipe Balbi * @gevt: Global Event 114572246da4SFelipe Balbi */ 114672246da4SFelipe Balbi union dwc3_event { 114772246da4SFelipe Balbi u32 raw; 114872246da4SFelipe Balbi struct dwc3_event_type type; 114972246da4SFelipe Balbi struct dwc3_event_depevt depevt; 115072246da4SFelipe Balbi struct dwc3_event_devt devt; 115172246da4SFelipe Balbi struct dwc3_event_gevt gevt; 115272246da4SFelipe Balbi }; 115372246da4SFelipe Balbi 115461018305SFelipe Balbi /** 115561018305SFelipe Balbi * struct dwc3_gadget_ep_cmd_params - representation of endpoint command 115661018305SFelipe Balbi * parameters 115761018305SFelipe Balbi * @param2: third parameter 115861018305SFelipe Balbi * @param1: second parameter 115961018305SFelipe Balbi * @param0: first parameter 116061018305SFelipe Balbi */ 116161018305SFelipe Balbi struct dwc3_gadget_ep_cmd_params { 116261018305SFelipe Balbi u32 param2; 116361018305SFelipe Balbi u32 param1; 116461018305SFelipe Balbi u32 param0; 116561018305SFelipe Balbi }; 116661018305SFelipe Balbi 116772246da4SFelipe Balbi /* 116872246da4SFelipe Balbi * DWC3 Features to be used as Driver Data 116972246da4SFelipe Balbi */ 117072246da4SFelipe Balbi 117172246da4SFelipe Balbi #define DWC3_HAS_PERIPHERAL BIT(0) 117272246da4SFelipe Balbi #define DWC3_HAS_XHCI BIT(1) 117372246da4SFelipe Balbi #define DWC3_HAS_OTG BIT(3) 117472246da4SFelipe Balbi 1175d07e8819SFelipe Balbi /* prototypes */ 11763140e8cbSSebastian Andrzej Siewior void dwc3_set_mode(struct dwc3 *dwc, u32 mode); 1177cf6d867dSFelipe Balbi u32 dwc3_core_fifo_space(struct dwc3_ep *dep, u8 type); 11783140e8cbSSebastian Andrzej Siewior 1179a987a906SJohn Youn /* check whether we are on the DWC_usb3 core */ 1180a987a906SJohn Youn static inline bool dwc3_is_usb3(struct dwc3 *dwc) 1181a987a906SJohn Youn { 1182a987a906SJohn Youn return !(dwc->revision & DWC3_REVISION_IS_DWC31); 1183a987a906SJohn Youn } 1184a987a906SJohn Youn 1185c4137a9cSJohn Youn /* check whether we are on the DWC_usb31 core */ 1186c4137a9cSJohn Youn static inline bool dwc3_is_usb31(struct dwc3 *dwc) 1187c4137a9cSJohn Youn { 1188c4137a9cSJohn Youn return !!(dwc->revision & DWC3_REVISION_IS_DWC31); 1189c4137a9cSJohn Youn } 1190c4137a9cSJohn Youn 1191cf40b86bSJohn Youn bool dwc3_has_imod(struct dwc3 *dwc); 1192cf40b86bSJohn Youn 1193388e5c51SVivek Gautam #if IS_ENABLED(CONFIG_USB_DWC3_HOST) || IS_ENABLED(CONFIG_USB_DWC3_DUAL_ROLE) 1194d07e8819SFelipe Balbi int dwc3_host_init(struct dwc3 *dwc); 1195d07e8819SFelipe Balbi void dwc3_host_exit(struct dwc3 *dwc); 1196388e5c51SVivek Gautam #else 1197388e5c51SVivek Gautam static inline int dwc3_host_init(struct dwc3 *dwc) 1198388e5c51SVivek Gautam { return 0; } 1199388e5c51SVivek Gautam static inline void dwc3_host_exit(struct dwc3 *dwc) 1200388e5c51SVivek Gautam { } 1201388e5c51SVivek Gautam #endif 1202d07e8819SFelipe Balbi 1203388e5c51SVivek Gautam #if IS_ENABLED(CONFIG_USB_DWC3_GADGET) || IS_ENABLED(CONFIG_USB_DWC3_DUAL_ROLE) 1204f80b45e7SFelipe Balbi int dwc3_gadget_init(struct dwc3 *dwc); 1205f80b45e7SFelipe Balbi void dwc3_gadget_exit(struct dwc3 *dwc); 120661018305SFelipe Balbi int dwc3_gadget_set_test_mode(struct dwc3 *dwc, int mode); 120761018305SFelipe Balbi int dwc3_gadget_get_link_state(struct dwc3 *dwc); 120861018305SFelipe Balbi int dwc3_gadget_set_link_state(struct dwc3 *dwc, enum dwc3_link_state state); 12092cd4718dSFelipe Balbi int dwc3_send_gadget_ep_cmd(struct dwc3_ep *dep, unsigned cmd, 12102cd4718dSFelipe Balbi struct dwc3_gadget_ep_cmd_params *params); 12113ece0ec4SFelipe Balbi int dwc3_send_gadget_generic_command(struct dwc3 *dwc, unsigned cmd, u32 param); 1212388e5c51SVivek Gautam #else 1213388e5c51SVivek Gautam static inline int dwc3_gadget_init(struct dwc3 *dwc) 1214388e5c51SVivek Gautam { return 0; } 1215388e5c51SVivek Gautam static inline void dwc3_gadget_exit(struct dwc3 *dwc) 1216388e5c51SVivek Gautam { } 121761018305SFelipe Balbi static inline int dwc3_gadget_set_test_mode(struct dwc3 *dwc, int mode) 121861018305SFelipe Balbi { return 0; } 121961018305SFelipe Balbi static inline int dwc3_gadget_get_link_state(struct dwc3 *dwc) 122061018305SFelipe Balbi { return 0; } 122161018305SFelipe Balbi static inline int dwc3_gadget_set_link_state(struct dwc3 *dwc, 122261018305SFelipe Balbi enum dwc3_link_state state) 122361018305SFelipe Balbi { return 0; } 122461018305SFelipe Balbi 12252cd4718dSFelipe Balbi static inline int dwc3_send_gadget_ep_cmd(struct dwc3_ep *dep, unsigned cmd, 12262cd4718dSFelipe Balbi struct dwc3_gadget_ep_cmd_params *params) 122761018305SFelipe Balbi { return 0; } 122861018305SFelipe Balbi static inline int dwc3_send_gadget_generic_command(struct dwc3 *dwc, 122961018305SFelipe Balbi int cmd, u32 param) 123061018305SFelipe Balbi { return 0; } 1231388e5c51SVivek Gautam #endif 1232f80b45e7SFelipe Balbi 12339840354fSRoger Quadros #if IS_ENABLED(CONFIG_USB_DWC3_DUAL_ROLE) 12349840354fSRoger Quadros int dwc3_drd_init(struct dwc3 *dwc); 12359840354fSRoger Quadros void dwc3_drd_exit(struct dwc3 *dwc); 12369840354fSRoger Quadros #else 12379840354fSRoger Quadros static inline int dwc3_drd_init(struct dwc3 *dwc) 12389840354fSRoger Quadros { return 0; } 12399840354fSRoger Quadros static inline void dwc3_drd_exit(struct dwc3 *dwc) 12409840354fSRoger Quadros { } 12419840354fSRoger Quadros #endif 12429840354fSRoger Quadros 12437415f17cSFelipe Balbi /* power management interface */ 12447415f17cSFelipe Balbi #if !IS_ENABLED(CONFIG_USB_DWC3_HOST) 12457415f17cSFelipe Balbi int dwc3_gadget_suspend(struct dwc3 *dwc); 12467415f17cSFelipe Balbi int dwc3_gadget_resume(struct dwc3 *dwc); 1247fc8bb91bSFelipe Balbi void dwc3_gadget_process_pending_events(struct dwc3 *dwc); 12487415f17cSFelipe Balbi #else 12497415f17cSFelipe Balbi static inline int dwc3_gadget_suspend(struct dwc3 *dwc) 12507415f17cSFelipe Balbi { 12517415f17cSFelipe Balbi return 0; 12527415f17cSFelipe Balbi } 12537415f17cSFelipe Balbi 12547415f17cSFelipe Balbi static inline int dwc3_gadget_resume(struct dwc3 *dwc) 12557415f17cSFelipe Balbi { 12567415f17cSFelipe Balbi return 0; 12577415f17cSFelipe Balbi } 1258fc8bb91bSFelipe Balbi 1259fc8bb91bSFelipe Balbi static inline void dwc3_gadget_process_pending_events(struct dwc3 *dwc) 1260fc8bb91bSFelipe Balbi { 1261fc8bb91bSFelipe Balbi } 12627415f17cSFelipe Balbi #endif /* !IS_ENABLED(CONFIG_USB_DWC3_HOST) */ 12637415f17cSFelipe Balbi 126488bc9d19SHeikki Krogerus #if IS_ENABLED(CONFIG_USB_DWC3_ULPI) 126588bc9d19SHeikki Krogerus int dwc3_ulpi_init(struct dwc3 *dwc); 126688bc9d19SHeikki Krogerus void dwc3_ulpi_exit(struct dwc3 *dwc); 126788bc9d19SHeikki Krogerus #else 126888bc9d19SHeikki Krogerus static inline int dwc3_ulpi_init(struct dwc3 *dwc) 126988bc9d19SHeikki Krogerus { return 0; } 127088bc9d19SHeikki Krogerus static inline void dwc3_ulpi_exit(struct dwc3 *dwc) 127188bc9d19SHeikki Krogerus { } 127288bc9d19SHeikki Krogerus #endif 127388bc9d19SHeikki Krogerus 127472246da4SFelipe Balbi #endif /* __DRIVERS_USB_DWC3_CORE_H */ 1275