172246da4SFelipe Balbi /** 272246da4SFelipe Balbi * core.h - DesignWare USB3 DRD Core Header 372246da4SFelipe Balbi * 472246da4SFelipe Balbi * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com 572246da4SFelipe Balbi * 672246da4SFelipe Balbi * Authors: Felipe Balbi <balbi@ti.com>, 772246da4SFelipe Balbi * Sebastian Andrzej Siewior <bigeasy@linutronix.de> 872246da4SFelipe Balbi * 972246da4SFelipe Balbi * Redistribution and use in source and binary forms, with or without 1072246da4SFelipe Balbi * modification, are permitted provided that the following conditions 1172246da4SFelipe Balbi * are met: 1272246da4SFelipe Balbi * 1. Redistributions of source code must retain the above copyright 1372246da4SFelipe Balbi * notice, this list of conditions, and the following disclaimer, 1472246da4SFelipe Balbi * without modification. 1572246da4SFelipe Balbi * 2. Redistributions in binary form must reproduce the above copyright 1672246da4SFelipe Balbi * notice, this list of conditions and the following disclaimer in the 1772246da4SFelipe Balbi * documentation and/or other materials provided with the distribution. 1872246da4SFelipe Balbi * 3. The names of the above-listed copyright holders may not be used 1972246da4SFelipe Balbi * to endorse or promote products derived from this software without 2072246da4SFelipe Balbi * specific prior written permission. 2172246da4SFelipe Balbi * 2272246da4SFelipe Balbi * ALTERNATIVELY, this software may be distributed under the terms of the 2372246da4SFelipe Balbi * GNU General Public License ("GPL") version 2, as published by the Free 2472246da4SFelipe Balbi * Software Foundation. 2572246da4SFelipe Balbi * 2672246da4SFelipe Balbi * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS 2772246da4SFelipe Balbi * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 2872246da4SFelipe Balbi * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 2972246da4SFelipe Balbi * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR 3072246da4SFelipe Balbi * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 3172246da4SFelipe Balbi * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 3272246da4SFelipe Balbi * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 3372246da4SFelipe Balbi * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF 3472246da4SFelipe Balbi * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING 3572246da4SFelipe Balbi * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 3672246da4SFelipe Balbi * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 3772246da4SFelipe Balbi */ 3872246da4SFelipe Balbi 3972246da4SFelipe Balbi #ifndef __DRIVERS_USB_DWC3_CORE_H 4072246da4SFelipe Balbi #define __DRIVERS_USB_DWC3_CORE_H 4172246da4SFelipe Balbi 4272246da4SFelipe Balbi #include <linux/device.h> 4372246da4SFelipe Balbi #include <linux/spinlock.h> 44d07e8819SFelipe Balbi #include <linux/ioport.h> 4572246da4SFelipe Balbi #include <linux/list.h> 4672246da4SFelipe Balbi #include <linux/dma-mapping.h> 4772246da4SFelipe Balbi #include <linux/mm.h> 4872246da4SFelipe Balbi #include <linux/debugfs.h> 4972246da4SFelipe Balbi 5072246da4SFelipe Balbi #include <linux/usb/ch9.h> 5172246da4SFelipe Balbi #include <linux/usb/gadget.h> 5272246da4SFelipe Balbi 5372246da4SFelipe Balbi /* Global constants */ 543ef35fafSFelipe Balbi #define DWC3_EP0_BOUNCE_SIZE 512 5572246da4SFelipe Balbi #define DWC3_ENDPOINTS_NUM 32 5651249dcaSIdo Shayevitz #define DWC3_XHCI_RESOURCES_NUM 2 5772246da4SFelipe Balbi 585da93478SFelipe Balbi #define DWC3_EVENT_SIZE 4 /* bytes */ 595da93478SFelipe Balbi #define DWC3_EVENT_MAX_NUM 64 /* 2 events/endpoint */ 605da93478SFelipe Balbi #define DWC3_EVENT_BUFFERS_SIZE (DWC3_EVENT_SIZE * DWC3_EVENT_MAX_NUM) 6172246da4SFelipe Balbi #define DWC3_EVENT_TYPE_MASK 0xfe 6272246da4SFelipe Balbi 6372246da4SFelipe Balbi #define DWC3_EVENT_TYPE_DEV 0 6472246da4SFelipe Balbi #define DWC3_EVENT_TYPE_CARKIT 3 6572246da4SFelipe Balbi #define DWC3_EVENT_TYPE_I2C 4 6672246da4SFelipe Balbi 6772246da4SFelipe Balbi #define DWC3_DEVICE_EVENT_DISCONNECT 0 6872246da4SFelipe Balbi #define DWC3_DEVICE_EVENT_RESET 1 6972246da4SFelipe Balbi #define DWC3_DEVICE_EVENT_CONNECT_DONE 2 7072246da4SFelipe Balbi #define DWC3_DEVICE_EVENT_LINK_STATUS_CHANGE 3 7172246da4SFelipe Balbi #define DWC3_DEVICE_EVENT_WAKEUP 4 722c61a8efSPaul Zimmerman #define DWC3_DEVICE_EVENT_HIBER_REQ 5 7372246da4SFelipe Balbi #define DWC3_DEVICE_EVENT_EOPF 6 7472246da4SFelipe Balbi #define DWC3_DEVICE_EVENT_SOF 7 7572246da4SFelipe Balbi #define DWC3_DEVICE_EVENT_ERRATIC_ERROR 9 7672246da4SFelipe Balbi #define DWC3_DEVICE_EVENT_CMD_CMPL 10 7772246da4SFelipe Balbi #define DWC3_DEVICE_EVENT_OVERFLOW 11 7872246da4SFelipe Balbi 7972246da4SFelipe Balbi #define DWC3_GEVNTCOUNT_MASK 0xfffc 8072246da4SFelipe Balbi #define DWC3_GSNPSID_MASK 0xffff0000 8172246da4SFelipe Balbi #define DWC3_GSNPSREV_MASK 0xffff 8272246da4SFelipe Balbi 8351249dcaSIdo Shayevitz /* DWC3 registers memory space boundries */ 8451249dcaSIdo Shayevitz #define DWC3_XHCI_REGS_START 0x0 8551249dcaSIdo Shayevitz #define DWC3_XHCI_REGS_END 0x7fff 8651249dcaSIdo Shayevitz #define DWC3_GLOBALS_REGS_START 0xc100 8751249dcaSIdo Shayevitz #define DWC3_GLOBALS_REGS_END 0xc6ff 8851249dcaSIdo Shayevitz #define DWC3_DEVICE_REGS_START 0xc700 8951249dcaSIdo Shayevitz #define DWC3_DEVICE_REGS_END 0xcbff 9051249dcaSIdo Shayevitz #define DWC3_OTG_REGS_START 0xcc00 9151249dcaSIdo Shayevitz #define DWC3_OTG_REGS_END 0xccff 9251249dcaSIdo Shayevitz 9372246da4SFelipe Balbi /* Global Registers */ 9472246da4SFelipe Balbi #define DWC3_GSBUSCFG0 0xc100 9572246da4SFelipe Balbi #define DWC3_GSBUSCFG1 0xc104 9672246da4SFelipe Balbi #define DWC3_GTXTHRCFG 0xc108 9772246da4SFelipe Balbi #define DWC3_GRXTHRCFG 0xc10c 9872246da4SFelipe Balbi #define DWC3_GCTL 0xc110 9972246da4SFelipe Balbi #define DWC3_GEVTEN 0xc114 10072246da4SFelipe Balbi #define DWC3_GSTS 0xc118 10172246da4SFelipe Balbi #define DWC3_GSNPSID 0xc120 10272246da4SFelipe Balbi #define DWC3_GGPIO 0xc124 10372246da4SFelipe Balbi #define DWC3_GUID 0xc128 10472246da4SFelipe Balbi #define DWC3_GUCTL 0xc12c 10572246da4SFelipe Balbi #define DWC3_GBUSERRADDR0 0xc130 10672246da4SFelipe Balbi #define DWC3_GBUSERRADDR1 0xc134 10772246da4SFelipe Balbi #define DWC3_GPRTBIMAP0 0xc138 10872246da4SFelipe Balbi #define DWC3_GPRTBIMAP1 0xc13c 10972246da4SFelipe Balbi #define DWC3_GHWPARAMS0 0xc140 11072246da4SFelipe Balbi #define DWC3_GHWPARAMS1 0xc144 11172246da4SFelipe Balbi #define DWC3_GHWPARAMS2 0xc148 11272246da4SFelipe Balbi #define DWC3_GHWPARAMS3 0xc14c 11372246da4SFelipe Balbi #define DWC3_GHWPARAMS4 0xc150 11472246da4SFelipe Balbi #define DWC3_GHWPARAMS5 0xc154 11572246da4SFelipe Balbi #define DWC3_GHWPARAMS6 0xc158 11672246da4SFelipe Balbi #define DWC3_GHWPARAMS7 0xc15c 11772246da4SFelipe Balbi #define DWC3_GDBGFIFOSPACE 0xc160 11872246da4SFelipe Balbi #define DWC3_GDBGLTSSM 0xc164 11972246da4SFelipe Balbi #define DWC3_GPRTBIMAP_HS0 0xc180 12072246da4SFelipe Balbi #define DWC3_GPRTBIMAP_HS1 0xc184 12172246da4SFelipe Balbi #define DWC3_GPRTBIMAP_FS0 0xc188 12272246da4SFelipe Balbi #define DWC3_GPRTBIMAP_FS1 0xc18c 12372246da4SFelipe Balbi 12472246da4SFelipe Balbi #define DWC3_GUSB2PHYCFG(n) (0xc200 + (n * 0x04)) 12572246da4SFelipe Balbi #define DWC3_GUSB2I2CCTL(n) (0xc240 + (n * 0x04)) 12672246da4SFelipe Balbi 12772246da4SFelipe Balbi #define DWC3_GUSB2PHYACC(n) (0xc280 + (n * 0x04)) 12872246da4SFelipe Balbi 12972246da4SFelipe Balbi #define DWC3_GUSB3PIPECTL(n) (0xc2c0 + (n * 0x04)) 13072246da4SFelipe Balbi 13172246da4SFelipe Balbi #define DWC3_GTXFIFOSIZ(n) (0xc300 + (n * 0x04)) 13272246da4SFelipe Balbi #define DWC3_GRXFIFOSIZ(n) (0xc380 + (n * 0x04)) 13372246da4SFelipe Balbi 13472246da4SFelipe Balbi #define DWC3_GEVNTADRLO(n) (0xc400 + (n * 0x10)) 13572246da4SFelipe Balbi #define DWC3_GEVNTADRHI(n) (0xc404 + (n * 0x10)) 13672246da4SFelipe Balbi #define DWC3_GEVNTSIZ(n) (0xc408 + (n * 0x10)) 13772246da4SFelipe Balbi #define DWC3_GEVNTCOUNT(n) (0xc40c + (n * 0x10)) 13872246da4SFelipe Balbi 13972246da4SFelipe Balbi #define DWC3_GHWPARAMS8 0xc600 14072246da4SFelipe Balbi 14172246da4SFelipe Balbi /* Device Registers */ 14272246da4SFelipe Balbi #define DWC3_DCFG 0xc700 14372246da4SFelipe Balbi #define DWC3_DCTL 0xc704 14472246da4SFelipe Balbi #define DWC3_DEVTEN 0xc708 14572246da4SFelipe Balbi #define DWC3_DSTS 0xc70c 14672246da4SFelipe Balbi #define DWC3_DGCMDPAR 0xc710 14772246da4SFelipe Balbi #define DWC3_DGCMD 0xc714 14872246da4SFelipe Balbi #define DWC3_DALEPENA 0xc720 14972246da4SFelipe Balbi #define DWC3_DEPCMDPAR2(n) (0xc800 + (n * 0x10)) 15072246da4SFelipe Balbi #define DWC3_DEPCMDPAR1(n) (0xc804 + (n * 0x10)) 15172246da4SFelipe Balbi #define DWC3_DEPCMDPAR0(n) (0xc808 + (n * 0x10)) 15272246da4SFelipe Balbi #define DWC3_DEPCMD(n) (0xc80c + (n * 0x10)) 15372246da4SFelipe Balbi 15472246da4SFelipe Balbi /* OTG Registers */ 15572246da4SFelipe Balbi #define DWC3_OCFG 0xcc00 15672246da4SFelipe Balbi #define DWC3_OCTL 0xcc04 15772246da4SFelipe Balbi #define DWC3_OEVTEN 0xcc08 15872246da4SFelipe Balbi #define DWC3_OSTS 0xcc0C 15972246da4SFelipe Balbi 16072246da4SFelipe Balbi /* Bit fields */ 16172246da4SFelipe Balbi 16272246da4SFelipe Balbi /* Global Configuration Register */ 1631d046793SPaul Zimmerman #define DWC3_GCTL_PWRDNSCALE(n) ((n) << 19) 164f4aadbe4SFelipe Balbi #define DWC3_GCTL_U2RSTECN (1 << 16) 1651d046793SPaul Zimmerman #define DWC3_GCTL_RAMCLKSEL(x) (((x) & DWC3_GCTL_CLK_MASK) << 6) 16672246da4SFelipe Balbi #define DWC3_GCTL_CLK_BUS (0) 16772246da4SFelipe Balbi #define DWC3_GCTL_CLK_PIPE (1) 16872246da4SFelipe Balbi #define DWC3_GCTL_CLK_PIPEHALF (2) 16972246da4SFelipe Balbi #define DWC3_GCTL_CLK_MASK (3) 17072246da4SFelipe Balbi 1710b9fe32dSFelipe Balbi #define DWC3_GCTL_PRTCAP(n) (((n) & (3 << 12)) >> 12) 1721d046793SPaul Zimmerman #define DWC3_GCTL_PRTCAPDIR(n) ((n) << 12) 17372246da4SFelipe Balbi #define DWC3_GCTL_PRTCAP_HOST 1 17472246da4SFelipe Balbi #define DWC3_GCTL_PRTCAP_DEVICE 2 17572246da4SFelipe Balbi #define DWC3_GCTL_PRTCAP_OTG 3 17672246da4SFelipe Balbi 17772246da4SFelipe Balbi #define DWC3_GCTL_CORESOFTRESET (1 << 11) 1781d046793SPaul Zimmerman #define DWC3_GCTL_SCALEDOWN(n) ((n) << 4) 1793e87c42aSPaul Zimmerman #define DWC3_GCTL_SCALEDOWN_MASK DWC3_GCTL_SCALEDOWN(3) 18072246da4SFelipe Balbi #define DWC3_GCTL_DISSCRAMBLE (1 << 3) 1812c61a8efSPaul Zimmerman #define DWC3_GCTL_GBLHIBERNATIONEN (1 << 1) 182aabb7075SFelipe Balbi #define DWC3_GCTL_DSBLCLKGTNG (1 << 0) 18372246da4SFelipe Balbi 18472246da4SFelipe Balbi /* Global USB2 PHY Configuration Register */ 18572246da4SFelipe Balbi #define DWC3_GUSB2PHYCFG_PHYSOFTRST (1 << 31) 18672246da4SFelipe Balbi #define DWC3_GUSB2PHYCFG_SUSPHY (1 << 6) 18772246da4SFelipe Balbi 18872246da4SFelipe Balbi /* Global USB3 PIPE Control Register */ 18972246da4SFelipe Balbi #define DWC3_GUSB3PIPECTL_PHYSOFTRST (1 << 31) 19072246da4SFelipe Balbi #define DWC3_GUSB3PIPECTL_SUSPHY (1 << 17) 19172246da4SFelipe Balbi 192457e84b6SFelipe Balbi /* Global TX Fifo Size Register */ 193457e84b6SFelipe Balbi #define DWC3_GTXFIFOSIZ_TXFDEF(n) ((n) & 0xffff) 194457e84b6SFelipe Balbi #define DWC3_GTXFIFOSIZ_TXFSTADDR(n) ((n) & 0xffff0000) 195457e84b6SFelipe Balbi 196aabb7075SFelipe Balbi /* Global HWPARAMS1 Register */ 1971d046793SPaul Zimmerman #define DWC3_GHWPARAMS1_EN_PWROPT(n) (((n) & (3 << 24)) >> 24) 198aabb7075SFelipe Balbi #define DWC3_GHWPARAMS1_EN_PWROPT_NO 0 199aabb7075SFelipe Balbi #define DWC3_GHWPARAMS1_EN_PWROPT_CLK 1 2002c61a8efSPaul Zimmerman #define DWC3_GHWPARAMS1_EN_PWROPT_HIB 2 2012c61a8efSPaul Zimmerman #define DWC3_GHWPARAMS1_PWROPT(n) ((n) << 24) 2022c61a8efSPaul Zimmerman #define DWC3_GHWPARAMS1_PWROPT_MASK DWC3_GHWPARAMS1_PWROPT(3) 2032c61a8efSPaul Zimmerman 2042c61a8efSPaul Zimmerman /* Global HWPARAMS4 Register */ 2052c61a8efSPaul Zimmerman #define DWC3_GHWPARAMS4_HIBER_SCRATCHBUFS(n) (((n) & (0x0f << 13)) >> 13) 2062c61a8efSPaul Zimmerman #define DWC3_MAX_HIBER_SCRATCHBUFS 15 207aabb7075SFelipe Balbi 20872246da4SFelipe Balbi /* Device Configuration Register */ 209e6a3b5e2SSebastian Andrzej Siewior #define DWC3_DCFG_LPM_CAP (1 << 22) 21072246da4SFelipe Balbi #define DWC3_DCFG_DEVADDR(addr) ((addr) << 3) 21172246da4SFelipe Balbi #define DWC3_DCFG_DEVADDR_MASK DWC3_DCFG_DEVADDR(0x7f) 21272246da4SFelipe Balbi 21372246da4SFelipe Balbi #define DWC3_DCFG_SPEED_MASK (7 << 0) 21472246da4SFelipe Balbi #define DWC3_DCFG_SUPERSPEED (4 << 0) 21572246da4SFelipe Balbi #define DWC3_DCFG_HIGHSPEED (0 << 0) 21672246da4SFelipe Balbi #define DWC3_DCFG_FULLSPEED2 (1 << 0) 21772246da4SFelipe Balbi #define DWC3_DCFG_LOWSPEED (2 << 0) 21872246da4SFelipe Balbi #define DWC3_DCFG_FULLSPEED1 (3 << 0) 21972246da4SFelipe Balbi 2202c61a8efSPaul Zimmerman #define DWC3_DCFG_LPM_CAP (1 << 22) 2212c61a8efSPaul Zimmerman 22272246da4SFelipe Balbi /* Device Control Register */ 22372246da4SFelipe Balbi #define DWC3_DCTL_RUN_STOP (1 << 31) 22472246da4SFelipe Balbi #define DWC3_DCTL_CSFTRST (1 << 30) 22572246da4SFelipe Balbi #define DWC3_DCTL_LSFTRST (1 << 29) 22672246da4SFelipe Balbi 22772246da4SFelipe Balbi #define DWC3_DCTL_HIRD_THRES_MASK (0x1f << 24) 2287e39b817SPratyush Anand #define DWC3_DCTL_HIRD_THRES(n) ((n) << 24) 22972246da4SFelipe Balbi 23072246da4SFelipe Balbi #define DWC3_DCTL_APPL1RES (1 << 23) 23172246da4SFelipe Balbi 2322c61a8efSPaul Zimmerman /* These apply for core versions 1.87a and earlier */ 2338db7ed15SFelipe Balbi #define DWC3_DCTL_TRGTULST_MASK (0x0f << 17) 2348db7ed15SFelipe Balbi #define DWC3_DCTL_TRGTULST(n) ((n) << 17) 2358db7ed15SFelipe Balbi #define DWC3_DCTL_TRGTULST_U2 (DWC3_DCTL_TRGTULST(2)) 2368db7ed15SFelipe Balbi #define DWC3_DCTL_TRGTULST_U3 (DWC3_DCTL_TRGTULST(3)) 2378db7ed15SFelipe Balbi #define DWC3_DCTL_TRGTULST_SS_DIS (DWC3_DCTL_TRGTULST(4)) 2388db7ed15SFelipe Balbi #define DWC3_DCTL_TRGTULST_RX_DET (DWC3_DCTL_TRGTULST(5)) 2398db7ed15SFelipe Balbi #define DWC3_DCTL_TRGTULST_SS_INACT (DWC3_DCTL_TRGTULST(6)) 2408db7ed15SFelipe Balbi 2412c61a8efSPaul Zimmerman /* These apply for core versions 1.94a and later */ 2422c61a8efSPaul Zimmerman #define DWC3_DCTL_KEEP_CONNECT (1 << 19) 2432c61a8efSPaul Zimmerman #define DWC3_DCTL_L1_HIBER_EN (1 << 18) 2442c61a8efSPaul Zimmerman #define DWC3_DCTL_CRS (1 << 17) 2452c61a8efSPaul Zimmerman #define DWC3_DCTL_CSS (1 << 16) 2462c61a8efSPaul Zimmerman 24772246da4SFelipe Balbi #define DWC3_DCTL_INITU2ENA (1 << 12) 24872246da4SFelipe Balbi #define DWC3_DCTL_ACCEPTU2ENA (1 << 11) 24972246da4SFelipe Balbi #define DWC3_DCTL_INITU1ENA (1 << 10) 25072246da4SFelipe Balbi #define DWC3_DCTL_ACCEPTU1ENA (1 << 9) 25172246da4SFelipe Balbi #define DWC3_DCTL_TSTCTRL_MASK (0xf << 1) 25272246da4SFelipe Balbi 25372246da4SFelipe Balbi #define DWC3_DCTL_ULSTCHNGREQ_MASK (0x0f << 5) 25472246da4SFelipe Balbi #define DWC3_DCTL_ULSTCHNGREQ(n) (((n) << 5) & DWC3_DCTL_ULSTCHNGREQ_MASK) 25572246da4SFelipe Balbi 25672246da4SFelipe Balbi #define DWC3_DCTL_ULSTCHNG_NO_ACTION (DWC3_DCTL_ULSTCHNGREQ(0)) 25772246da4SFelipe Balbi #define DWC3_DCTL_ULSTCHNG_SS_DISABLED (DWC3_DCTL_ULSTCHNGREQ(4)) 25872246da4SFelipe Balbi #define DWC3_DCTL_ULSTCHNG_RX_DETECT (DWC3_DCTL_ULSTCHNGREQ(5)) 25972246da4SFelipe Balbi #define DWC3_DCTL_ULSTCHNG_SS_INACTIVE (DWC3_DCTL_ULSTCHNGREQ(6)) 26072246da4SFelipe Balbi #define DWC3_DCTL_ULSTCHNG_RECOVERY (DWC3_DCTL_ULSTCHNGREQ(8)) 26172246da4SFelipe Balbi #define DWC3_DCTL_ULSTCHNG_COMPLIANCE (DWC3_DCTL_ULSTCHNGREQ(10)) 26272246da4SFelipe Balbi #define DWC3_DCTL_ULSTCHNG_LOOPBACK (DWC3_DCTL_ULSTCHNGREQ(11)) 26372246da4SFelipe Balbi 26472246da4SFelipe Balbi /* Device Event Enable Register */ 26572246da4SFelipe Balbi #define DWC3_DEVTEN_VNDRDEVTSTRCVEDEN (1 << 12) 26672246da4SFelipe Balbi #define DWC3_DEVTEN_EVNTOVERFLOWEN (1 << 11) 26772246da4SFelipe Balbi #define DWC3_DEVTEN_CMDCMPLTEN (1 << 10) 26872246da4SFelipe Balbi #define DWC3_DEVTEN_ERRTICERREN (1 << 9) 26972246da4SFelipe Balbi #define DWC3_DEVTEN_SOFEN (1 << 7) 27072246da4SFelipe Balbi #define DWC3_DEVTEN_EOPFEN (1 << 6) 2712c61a8efSPaul Zimmerman #define DWC3_DEVTEN_HIBERNATIONREQEVTEN (1 << 5) 27272246da4SFelipe Balbi #define DWC3_DEVTEN_WKUPEVTEN (1 << 4) 27372246da4SFelipe Balbi #define DWC3_DEVTEN_ULSTCNGEN (1 << 3) 27472246da4SFelipe Balbi #define DWC3_DEVTEN_CONNECTDONEEN (1 << 2) 27572246da4SFelipe Balbi #define DWC3_DEVTEN_USBRSTEN (1 << 1) 27672246da4SFelipe Balbi #define DWC3_DEVTEN_DISCONNEVTEN (1 << 0) 27772246da4SFelipe Balbi 27872246da4SFelipe Balbi /* Device Status Register */ 2792c61a8efSPaul Zimmerman #define DWC3_DSTS_DCNRD (1 << 29) 2802c61a8efSPaul Zimmerman 2812c61a8efSPaul Zimmerman /* This applies for core versions 1.87a and earlier */ 28272246da4SFelipe Balbi #define DWC3_DSTS_PWRUPREQ (1 << 24) 2832c61a8efSPaul Zimmerman 2842c61a8efSPaul Zimmerman /* These apply for core versions 1.94a and later */ 2852c61a8efSPaul Zimmerman #define DWC3_DSTS_RSS (1 << 25) 2862c61a8efSPaul Zimmerman #define DWC3_DSTS_SSS (1 << 24) 2872c61a8efSPaul Zimmerman 28872246da4SFelipe Balbi #define DWC3_DSTS_COREIDLE (1 << 23) 28972246da4SFelipe Balbi #define DWC3_DSTS_DEVCTRLHLT (1 << 22) 29072246da4SFelipe Balbi 29172246da4SFelipe Balbi #define DWC3_DSTS_USBLNKST_MASK (0x0f << 18) 29272246da4SFelipe Balbi #define DWC3_DSTS_USBLNKST(n) (((n) & DWC3_DSTS_USBLNKST_MASK) >> 18) 29372246da4SFelipe Balbi 29472246da4SFelipe Balbi #define DWC3_DSTS_RXFIFOEMPTY (1 << 17) 29572246da4SFelipe Balbi 296d05b8182SPratyush Anand #define DWC3_DSTS_SOFFN_MASK (0x3fff << 3) 29772246da4SFelipe Balbi #define DWC3_DSTS_SOFFN(n) (((n) & DWC3_DSTS_SOFFN_MASK) >> 3) 29872246da4SFelipe Balbi 29972246da4SFelipe Balbi #define DWC3_DSTS_CONNECTSPD (7 << 0) 30072246da4SFelipe Balbi 30172246da4SFelipe Balbi #define DWC3_DSTS_SUPERSPEED (4 << 0) 30272246da4SFelipe Balbi #define DWC3_DSTS_HIGHSPEED (0 << 0) 30372246da4SFelipe Balbi #define DWC3_DSTS_FULLSPEED2 (1 << 0) 30472246da4SFelipe Balbi #define DWC3_DSTS_LOWSPEED (2 << 0) 30572246da4SFelipe Balbi #define DWC3_DSTS_FULLSPEED1 (3 << 0) 30672246da4SFelipe Balbi 30772246da4SFelipe Balbi /* Device Generic Command Register */ 30872246da4SFelipe Balbi #define DWC3_DGCMD_SET_LMP 0x01 30972246da4SFelipe Balbi #define DWC3_DGCMD_SET_PERIODIC_PAR 0x02 31072246da4SFelipe Balbi #define DWC3_DGCMD_XMIT_FUNCTION 0x03 3112c61a8efSPaul Zimmerman 3122c61a8efSPaul Zimmerman /* These apply for core versions 1.94a and later */ 3132c61a8efSPaul Zimmerman #define DWC3_DGCMD_SET_SCRATCHPAD_ADDR_LO 0x04 3142c61a8efSPaul Zimmerman #define DWC3_DGCMD_SET_SCRATCHPAD_ADDR_HI 0x05 3152c61a8efSPaul Zimmerman 31672246da4SFelipe Balbi #define DWC3_DGCMD_SELECTED_FIFO_FLUSH 0x09 31772246da4SFelipe Balbi #define DWC3_DGCMD_ALL_FIFO_FLUSH 0x0a 31872246da4SFelipe Balbi #define DWC3_DGCMD_SET_ENDPOINT_NRDY 0x0c 31972246da4SFelipe Balbi #define DWC3_DGCMD_RUN_SOC_BUS_LOOPBACK 0x10 32072246da4SFelipe Balbi 321b09bb642SFelipe Balbi #define DWC3_DGCMD_STATUS(n) (((n) >> 15) & 1) 322b09bb642SFelipe Balbi #define DWC3_DGCMD_CMDACT (1 << 10) 3232c61a8efSPaul Zimmerman #define DWC3_DGCMD_CMDIOC (1 << 8) 3242c61a8efSPaul Zimmerman 3252c61a8efSPaul Zimmerman /* Device Generic Command Parameter Register */ 3262c61a8efSPaul Zimmerman #define DWC3_DGCMDPAR_FORCE_LINKPM_ACCEPT (1 << 0) 3272c61a8efSPaul Zimmerman #define DWC3_DGCMDPAR_FIFO_NUM(n) ((n) << 0) 3282c61a8efSPaul Zimmerman #define DWC3_DGCMDPAR_RX_FIFO (0 << 5) 3292c61a8efSPaul Zimmerman #define DWC3_DGCMDPAR_TX_FIFO (1 << 5) 3302c61a8efSPaul Zimmerman #define DWC3_DGCMDPAR_LOOPBACK_DIS (0 << 0) 3312c61a8efSPaul Zimmerman #define DWC3_DGCMDPAR_LOOPBACK_ENA (1 << 0) 332b09bb642SFelipe Balbi 33372246da4SFelipe Balbi /* Device Endpoint Command Register */ 33472246da4SFelipe Balbi #define DWC3_DEPCMD_PARAM_SHIFT 16 3351d046793SPaul Zimmerman #define DWC3_DEPCMD_PARAM(x) ((x) << DWC3_DEPCMD_PARAM_SHIFT) 3361d046793SPaul Zimmerman #define DWC3_DEPCMD_GET_RSC_IDX(x) (((x) >> DWC3_DEPCMD_PARAM_SHIFT) & 0x7f) 337b09bb642SFelipe Balbi #define DWC3_DEPCMD_STATUS(x) (((x) >> 15) & 1) 33872246da4SFelipe Balbi #define DWC3_DEPCMD_HIPRI_FORCERM (1 << 11) 33972246da4SFelipe Balbi #define DWC3_DEPCMD_CMDACT (1 << 10) 34072246da4SFelipe Balbi #define DWC3_DEPCMD_CMDIOC (1 << 8) 34172246da4SFelipe Balbi 34272246da4SFelipe Balbi #define DWC3_DEPCMD_DEPSTARTCFG (0x09 << 0) 34372246da4SFelipe Balbi #define DWC3_DEPCMD_ENDTRANSFER (0x08 << 0) 34472246da4SFelipe Balbi #define DWC3_DEPCMD_UPDATETRANSFER (0x07 << 0) 34572246da4SFelipe Balbi #define DWC3_DEPCMD_STARTTRANSFER (0x06 << 0) 34672246da4SFelipe Balbi #define DWC3_DEPCMD_CLEARSTALL (0x05 << 0) 34772246da4SFelipe Balbi #define DWC3_DEPCMD_SETSTALL (0x04 << 0) 3482c61a8efSPaul Zimmerman /* This applies for core versions 1.90a and earlier */ 34972246da4SFelipe Balbi #define DWC3_DEPCMD_GETSEQNUMBER (0x03 << 0) 3502c61a8efSPaul Zimmerman /* This applies for core versions 1.94a and later */ 3512c61a8efSPaul Zimmerman #define DWC3_DEPCMD_GETEPSTATE (0x03 << 0) 35272246da4SFelipe Balbi #define DWC3_DEPCMD_SETTRANSFRESOURCE (0x02 << 0) 35372246da4SFelipe Balbi #define DWC3_DEPCMD_SETEPCONFIG (0x01 << 0) 35472246da4SFelipe Balbi 35572246da4SFelipe Balbi /* The EP number goes 0..31 so ep0 is always out and ep1 is always in */ 35672246da4SFelipe Balbi #define DWC3_DALEPENA_EP(n) (1 << n) 35772246da4SFelipe Balbi 35872246da4SFelipe Balbi #define DWC3_DEPCMD_TYPE_CONTROL 0 35972246da4SFelipe Balbi #define DWC3_DEPCMD_TYPE_ISOC 1 36072246da4SFelipe Balbi #define DWC3_DEPCMD_TYPE_BULK 2 36172246da4SFelipe Balbi #define DWC3_DEPCMD_TYPE_INTR 3 36272246da4SFelipe Balbi 36372246da4SFelipe Balbi /* Structures */ 36472246da4SFelipe Balbi 365f6bafc6aSFelipe Balbi struct dwc3_trb; 36672246da4SFelipe Balbi 36772246da4SFelipe Balbi /** 36872246da4SFelipe Balbi * struct dwc3_event_buffer - Software event buffer representation 36972246da4SFelipe Balbi * @list: a list of event buffers 37072246da4SFelipe Balbi * @buf: _THE_ buffer 37172246da4SFelipe Balbi * @length: size of this buffer 37272246da4SFelipe Balbi * @dma: dma_addr_t 37372246da4SFelipe Balbi * @dwc: pointer to DWC controller 37472246da4SFelipe Balbi */ 37572246da4SFelipe Balbi struct dwc3_event_buffer { 37672246da4SFelipe Balbi void *buf; 37772246da4SFelipe Balbi unsigned length; 37872246da4SFelipe Balbi unsigned int lpos; 37972246da4SFelipe Balbi 38072246da4SFelipe Balbi dma_addr_t dma; 38172246da4SFelipe Balbi 38272246da4SFelipe Balbi struct dwc3 *dwc; 38372246da4SFelipe Balbi }; 38472246da4SFelipe Balbi 38572246da4SFelipe Balbi #define DWC3_EP_FLAG_STALLED (1 << 0) 38672246da4SFelipe Balbi #define DWC3_EP_FLAG_WEDGED (1 << 1) 38772246da4SFelipe Balbi 38872246da4SFelipe Balbi #define DWC3_EP_DIRECTION_TX true 38972246da4SFelipe Balbi #define DWC3_EP_DIRECTION_RX false 39072246da4SFelipe Balbi 39172246da4SFelipe Balbi #define DWC3_TRB_NUM 32 39272246da4SFelipe Balbi #define DWC3_TRB_MASK (DWC3_TRB_NUM - 1) 39372246da4SFelipe Balbi 39472246da4SFelipe Balbi /** 39572246da4SFelipe Balbi * struct dwc3_ep - device side endpoint representation 39672246da4SFelipe Balbi * @endpoint: usb endpoint 39772246da4SFelipe Balbi * @request_list: list of requests for this endpoint 39872246da4SFelipe Balbi * @req_queued: list of requests on this ep which have TRBs setup 39972246da4SFelipe Balbi * @trb_pool: array of transaction buffers 40072246da4SFelipe Balbi * @trb_pool_dma: dma address of @trb_pool 40172246da4SFelipe Balbi * @free_slot: next slot which is going to be used 40272246da4SFelipe Balbi * @busy_slot: first slot which is owned by HW 40372246da4SFelipe Balbi * @desc: usb_endpoint_descriptor pointer 40472246da4SFelipe Balbi * @dwc: pointer to DWC controller 40572246da4SFelipe Balbi * @flags: endpoint flags (wedged, stalled, ...) 40672246da4SFelipe Balbi * @current_trb: index of current used trb 40772246da4SFelipe Balbi * @number: endpoint number (1 - 15) 40872246da4SFelipe Balbi * @type: set to bmAttributes & USB_ENDPOINT_XFERTYPE_MASK 409b4996a86SFelipe Balbi * @resource_index: Resource transfer index 41072246da4SFelipe Balbi * @interval: the intervall on which the ISOC transfer is started 41172246da4SFelipe Balbi * @name: a human readable name e.g. ep1out-bulk 41272246da4SFelipe Balbi * @direction: true for TX, false for RX 413879631aaSFelipe Balbi * @stream_capable: true when streams are enabled 41472246da4SFelipe Balbi */ 41572246da4SFelipe Balbi struct dwc3_ep { 41672246da4SFelipe Balbi struct usb_ep endpoint; 41772246da4SFelipe Balbi struct list_head request_list; 41872246da4SFelipe Balbi struct list_head req_queued; 41972246da4SFelipe Balbi 420f6bafc6aSFelipe Balbi struct dwc3_trb *trb_pool; 42172246da4SFelipe Balbi dma_addr_t trb_pool_dma; 42272246da4SFelipe Balbi u32 free_slot; 42372246da4SFelipe Balbi u32 busy_slot; 424c90bfaecSFelipe Balbi const struct usb_ss_ep_comp_descriptor *comp_desc; 42572246da4SFelipe Balbi struct dwc3 *dwc; 42672246da4SFelipe Balbi 42772246da4SFelipe Balbi unsigned flags; 42872246da4SFelipe Balbi #define DWC3_EP_ENABLED (1 << 0) 42972246da4SFelipe Balbi #define DWC3_EP_STALL (1 << 1) 43072246da4SFelipe Balbi #define DWC3_EP_WEDGE (1 << 2) 43172246da4SFelipe Balbi #define DWC3_EP_BUSY (1 << 4) 43272246da4SFelipe Balbi #define DWC3_EP_PENDING_REQUEST (1 << 5) 433d6d6ec7bSPratyush Anand #define DWC3_EP_MISSED_ISOC (1 << 6) 43472246da4SFelipe Balbi 435984f66a6SFelipe Balbi /* This last one is specific to EP0 */ 436984f66a6SFelipe Balbi #define DWC3_EP0_DIR_IN (1 << 31) 437984f66a6SFelipe Balbi 43872246da4SFelipe Balbi unsigned current_trb; 43972246da4SFelipe Balbi 44072246da4SFelipe Balbi u8 number; 44172246da4SFelipe Balbi u8 type; 442b4996a86SFelipe Balbi u8 resource_index; 44372246da4SFelipe Balbi u32 interval; 44472246da4SFelipe Balbi 44572246da4SFelipe Balbi char name[20]; 44672246da4SFelipe Balbi 44772246da4SFelipe Balbi unsigned direction:1; 448879631aaSFelipe Balbi unsigned stream_capable:1; 44972246da4SFelipe Balbi }; 45072246da4SFelipe Balbi 45172246da4SFelipe Balbi enum dwc3_phy { 45272246da4SFelipe Balbi DWC3_PHY_UNKNOWN = 0, 45372246da4SFelipe Balbi DWC3_PHY_USB3, 45472246da4SFelipe Balbi DWC3_PHY_USB2, 45572246da4SFelipe Balbi }; 45672246da4SFelipe Balbi 457b53c772dSFelipe Balbi enum dwc3_ep0_next { 458b53c772dSFelipe Balbi DWC3_EP0_UNKNOWN = 0, 459b53c772dSFelipe Balbi DWC3_EP0_COMPLETE, 460b53c772dSFelipe Balbi DWC3_EP0_NRDY_DATA, 461b53c772dSFelipe Balbi DWC3_EP0_NRDY_STATUS, 462b53c772dSFelipe Balbi }; 463b53c772dSFelipe Balbi 46472246da4SFelipe Balbi enum dwc3_ep0_state { 46572246da4SFelipe Balbi EP0_UNCONNECTED = 0, 466c7fcdeb2SFelipe Balbi EP0_SETUP_PHASE, 467c7fcdeb2SFelipe Balbi EP0_DATA_PHASE, 468c7fcdeb2SFelipe Balbi EP0_STATUS_PHASE, 46972246da4SFelipe Balbi }; 47072246da4SFelipe Balbi 47172246da4SFelipe Balbi enum dwc3_link_state { 47272246da4SFelipe Balbi /* In SuperSpeed */ 47372246da4SFelipe Balbi DWC3_LINK_STATE_U0 = 0x00, /* in HS, means ON */ 47472246da4SFelipe Balbi DWC3_LINK_STATE_U1 = 0x01, 47572246da4SFelipe Balbi DWC3_LINK_STATE_U2 = 0x02, /* in HS, means SLEEP */ 47672246da4SFelipe Balbi DWC3_LINK_STATE_U3 = 0x03, /* in HS, means SUSPEND */ 47772246da4SFelipe Balbi DWC3_LINK_STATE_SS_DIS = 0x04, 47872246da4SFelipe Balbi DWC3_LINK_STATE_RX_DET = 0x05, /* in HS, means Early Suspend */ 47972246da4SFelipe Balbi DWC3_LINK_STATE_SS_INACT = 0x06, 48072246da4SFelipe Balbi DWC3_LINK_STATE_POLL = 0x07, 48172246da4SFelipe Balbi DWC3_LINK_STATE_RECOV = 0x08, 48272246da4SFelipe Balbi DWC3_LINK_STATE_HRESET = 0x09, 48372246da4SFelipe Balbi DWC3_LINK_STATE_CMPLY = 0x0a, 48472246da4SFelipe Balbi DWC3_LINK_STATE_LPBK = 0x0b, 4852c61a8efSPaul Zimmerman DWC3_LINK_STATE_RESET = 0x0e, 4862c61a8efSPaul Zimmerman DWC3_LINK_STATE_RESUME = 0x0f, 48772246da4SFelipe Balbi DWC3_LINK_STATE_MASK = 0x0f, 48872246da4SFelipe Balbi }; 48972246da4SFelipe Balbi 49072246da4SFelipe Balbi enum dwc3_device_state { 49172246da4SFelipe Balbi DWC3_DEFAULT_STATE, 49272246da4SFelipe Balbi DWC3_ADDRESS_STATE, 49372246da4SFelipe Balbi DWC3_CONFIGURED_STATE, 49472246da4SFelipe Balbi }; 49572246da4SFelipe Balbi 496f6bafc6aSFelipe Balbi /* TRB Length, PCM and Status */ 497f6bafc6aSFelipe Balbi #define DWC3_TRB_SIZE_MASK (0x00ffffff) 498f6bafc6aSFelipe Balbi #define DWC3_TRB_SIZE_LENGTH(n) ((n) & DWC3_TRB_SIZE_MASK) 499f6bafc6aSFelipe Balbi #define DWC3_TRB_SIZE_PCM1(n) (((n) & 0x03) << 24) 500389f2828SPratyush Anand #define DWC3_TRB_SIZE_TRBSTS(n) (((n) & (0x0f << 28)) >> 28) 50172246da4SFelipe Balbi 502f6bafc6aSFelipe Balbi #define DWC3_TRBSTS_OK 0 503f6bafc6aSFelipe Balbi #define DWC3_TRBSTS_MISSED_ISOC 1 504f6bafc6aSFelipe Balbi #define DWC3_TRBSTS_SETUP_PENDING 2 5052c61a8efSPaul Zimmerman #define DWC3_TRB_STS_XFER_IN_PROG 4 50672246da4SFelipe Balbi 507f6bafc6aSFelipe Balbi /* TRB Control */ 508f6bafc6aSFelipe Balbi #define DWC3_TRB_CTRL_HWO (1 << 0) 509f6bafc6aSFelipe Balbi #define DWC3_TRB_CTRL_LST (1 << 1) 510f6bafc6aSFelipe Balbi #define DWC3_TRB_CTRL_CHN (1 << 2) 511f6bafc6aSFelipe Balbi #define DWC3_TRB_CTRL_CSP (1 << 3) 512f6bafc6aSFelipe Balbi #define DWC3_TRB_CTRL_TRBCTL(n) (((n) & 0x3f) << 4) 513f6bafc6aSFelipe Balbi #define DWC3_TRB_CTRL_ISP_IMI (1 << 10) 514f6bafc6aSFelipe Balbi #define DWC3_TRB_CTRL_IOC (1 << 11) 515f6bafc6aSFelipe Balbi #define DWC3_TRB_CTRL_SID_SOFN(n) (((n) & 0xffff) << 14) 516f6bafc6aSFelipe Balbi 517f6bafc6aSFelipe Balbi #define DWC3_TRBCTL_NORMAL DWC3_TRB_CTRL_TRBCTL(1) 518f6bafc6aSFelipe Balbi #define DWC3_TRBCTL_CONTROL_SETUP DWC3_TRB_CTRL_TRBCTL(2) 519f6bafc6aSFelipe Balbi #define DWC3_TRBCTL_CONTROL_STATUS2 DWC3_TRB_CTRL_TRBCTL(3) 520f6bafc6aSFelipe Balbi #define DWC3_TRBCTL_CONTROL_STATUS3 DWC3_TRB_CTRL_TRBCTL(4) 521f6bafc6aSFelipe Balbi #define DWC3_TRBCTL_CONTROL_DATA DWC3_TRB_CTRL_TRBCTL(5) 522f6bafc6aSFelipe Balbi #define DWC3_TRBCTL_ISOCHRONOUS_FIRST DWC3_TRB_CTRL_TRBCTL(6) 523f6bafc6aSFelipe Balbi #define DWC3_TRBCTL_ISOCHRONOUS DWC3_TRB_CTRL_TRBCTL(7) 524f6bafc6aSFelipe Balbi #define DWC3_TRBCTL_LINK_TRB DWC3_TRB_CTRL_TRBCTL(8) 52572246da4SFelipe Balbi 52672246da4SFelipe Balbi /** 527f6bafc6aSFelipe Balbi * struct dwc3_trb - transfer request block (hw format) 52872246da4SFelipe Balbi * @bpl: DW0-3 52972246da4SFelipe Balbi * @bph: DW4-7 53072246da4SFelipe Balbi * @size: DW8-B 53172246da4SFelipe Balbi * @trl: DWC-F 53272246da4SFelipe Balbi */ 533f6bafc6aSFelipe Balbi struct dwc3_trb { 534f6bafc6aSFelipe Balbi u32 bpl; 535f6bafc6aSFelipe Balbi u32 bph; 536f6bafc6aSFelipe Balbi u32 size; 537f6bafc6aSFelipe Balbi u32 ctrl; 53872246da4SFelipe Balbi } __packed; 53972246da4SFelipe Balbi 54072246da4SFelipe Balbi /** 541a3299499SFelipe Balbi * dwc3_hwparams - copy of HWPARAMS registers 542a3299499SFelipe Balbi * @hwparams0 - GHWPARAMS0 543a3299499SFelipe Balbi * @hwparams1 - GHWPARAMS1 544a3299499SFelipe Balbi * @hwparams2 - GHWPARAMS2 545a3299499SFelipe Balbi * @hwparams3 - GHWPARAMS3 546a3299499SFelipe Balbi * @hwparams4 - GHWPARAMS4 547a3299499SFelipe Balbi * @hwparams5 - GHWPARAMS5 548a3299499SFelipe Balbi * @hwparams6 - GHWPARAMS6 549a3299499SFelipe Balbi * @hwparams7 - GHWPARAMS7 550a3299499SFelipe Balbi * @hwparams8 - GHWPARAMS8 551a3299499SFelipe Balbi */ 552a3299499SFelipe Balbi struct dwc3_hwparams { 553a3299499SFelipe Balbi u32 hwparams0; 554a3299499SFelipe Balbi u32 hwparams1; 555a3299499SFelipe Balbi u32 hwparams2; 556a3299499SFelipe Balbi u32 hwparams3; 557a3299499SFelipe Balbi u32 hwparams4; 558a3299499SFelipe Balbi u32 hwparams5; 559a3299499SFelipe Balbi u32 hwparams6; 560a3299499SFelipe Balbi u32 hwparams7; 561a3299499SFelipe Balbi u32 hwparams8; 562a3299499SFelipe Balbi }; 563a3299499SFelipe Balbi 5640949e99bSFelipe Balbi /* HWPARAMS0 */ 5650949e99bSFelipe Balbi #define DWC3_MODE(n) ((n) & 0x7) 5660949e99bSFelipe Balbi 5670949e99bSFelipe Balbi #define DWC3_MODE_DEVICE 0 5680949e99bSFelipe Balbi #define DWC3_MODE_HOST 1 5690949e99bSFelipe Balbi #define DWC3_MODE_DRD 2 5700949e99bSFelipe Balbi #define DWC3_MODE_HUB 3 5710949e99bSFelipe Balbi 572457e84b6SFelipe Balbi #define DWC3_MDWIDTH(n) (((n) & 0xff00) >> 8) 573457e84b6SFelipe Balbi 5740949e99bSFelipe Balbi /* HWPARAMS1 */ 5759f622b2aSFelipe Balbi #define DWC3_NUM_INT(n) (((n) & (0x3f << 15)) >> 15) 5769f622b2aSFelipe Balbi 577457e84b6SFelipe Balbi /* HWPARAMS7 */ 578457e84b6SFelipe Balbi #define DWC3_RAM1_DEPTH(n) ((n) & 0xffff) 579457e84b6SFelipe Balbi 580e0ce0b0aSSebastian Andrzej Siewior struct dwc3_request { 581e0ce0b0aSSebastian Andrzej Siewior struct usb_request request; 582e0ce0b0aSSebastian Andrzej Siewior struct list_head list; 583e0ce0b0aSSebastian Andrzej Siewior struct dwc3_ep *dep; 584e5ba5ec8SPratyush Anand u32 start_slot; 585e0ce0b0aSSebastian Andrzej Siewior 586e0ce0b0aSSebastian Andrzej Siewior u8 epnum; 587f6bafc6aSFelipe Balbi struct dwc3_trb *trb; 588e0ce0b0aSSebastian Andrzej Siewior dma_addr_t trb_dma; 589e0ce0b0aSSebastian Andrzej Siewior 590e0ce0b0aSSebastian Andrzej Siewior unsigned direction:1; 591e0ce0b0aSSebastian Andrzej Siewior unsigned mapped:1; 592e0ce0b0aSSebastian Andrzej Siewior unsigned queued:1; 593e0ce0b0aSSebastian Andrzej Siewior }; 594e0ce0b0aSSebastian Andrzej Siewior 5952c61a8efSPaul Zimmerman /* 5962c61a8efSPaul Zimmerman * struct dwc3_scratchpad_array - hibernation scratchpad array 5972c61a8efSPaul Zimmerman * (format defined by hw) 5982c61a8efSPaul Zimmerman */ 5992c61a8efSPaul Zimmerman struct dwc3_scratchpad_array { 6002c61a8efSPaul Zimmerman __le64 dma_adr[DWC3_MAX_HIBER_SCRATCHBUFS]; 6012c61a8efSPaul Zimmerman }; 6022c61a8efSPaul Zimmerman 603a3299499SFelipe Balbi /** 60472246da4SFelipe Balbi * struct dwc3 - representation of our controller 60591db07dcSFelipe Balbi * @ctrl_req: usb control request which is used for ep0 60691db07dcSFelipe Balbi * @ep0_trb: trb which is used for the ctrl_req 6075812b1c2SFelipe Balbi * @ep0_bounce: bounce buffer for ep0 60891db07dcSFelipe Balbi * @setup_buf: used while precessing STD USB requests 60991db07dcSFelipe Balbi * @ctrl_req_addr: dma address of ctrl_req 61091db07dcSFelipe Balbi * @ep0_trb: dma address of ep0_trb 61191db07dcSFelipe Balbi * @ep0_usb_req: dummy req used while handling STD USB requests 6125812b1c2SFelipe Balbi * @ep0_bounce_addr: dma address of ep0_bounce 61372246da4SFelipe Balbi * @lock: for synchronizing 61472246da4SFelipe Balbi * @dev: pointer to our struct device 615d07e8819SFelipe Balbi * @xhci: pointer to our xHCI child 61672246da4SFelipe Balbi * @event_buffer_list: a list of event buffers 61772246da4SFelipe Balbi * @gadget: device side representation of the peripheral controller 61872246da4SFelipe Balbi * @gadget_driver: pointer to the gadget driver 61972246da4SFelipe Balbi * @regs: base address for our registers 62072246da4SFelipe Balbi * @regs_size: address space size 62172246da4SFelipe Balbi * @irq: IRQ number 6229f622b2aSFelipe Balbi * @num_event_buffers: calculated number of event buffers 623fae2b904SFelipe Balbi * @u1u2: only used on revisions <1.83a for workaround 6246c167fc9SFelipe Balbi * @maximum_speed: maximum speed requested (mainly for testing purposes) 62572246da4SFelipe Balbi * @revision: revision register contents 6260949e99bSFelipe Balbi * @mode: mode of operation 62751e1e7bcSFelipe Balbi * @usb2_phy: pointer to USB2 PHY 62851e1e7bcSFelipe Balbi * @usb3_phy: pointer to USB3 PHY 62972246da4SFelipe Balbi * @is_selfpowered: true when we are selfpowered 63072246da4SFelipe Balbi * @three_stage_setup: set if we perform a three phase setup 6315812b1c2SFelipe Balbi * @ep0_bounced: true when we used bounce buffer 63255f3fba6SFelipe Balbi * @ep0_expect_in: true when we expect a DATA IN transfer 633b23c8439SPaul Zimmerman * @start_config_issued: true when StartConfig command has been issued 634df62df56SFelipe Balbi * @setup_packet_pending: true when there's a Setup Packet in FIFO. Workaround 635457e84b6SFelipe Balbi * @needs_fifo_resize: not all users might want fifo resizing, flag it 636457e84b6SFelipe Balbi * @resize_fifos: tells us it's ok to reconfigure our TxFIFO sizes. 637c12a0d86SFelipe Balbi * @isoch_delay: wValue from Set Isochronous Delay request; 638865e09e7SFelipe Balbi * @u2sel: parameter from Set SEL request. 639865e09e7SFelipe Balbi * @u2pel: parameter from Set SEL request. 640865e09e7SFelipe Balbi * @u1sel: parameter from Set SEL request. 641865e09e7SFelipe Balbi * @u1pel: parameter from Set SEL request. 642b53c772dSFelipe Balbi * @ep0_next_event: hold the next expected event 64372246da4SFelipe Balbi * @ep0state: state of endpoint zero 64472246da4SFelipe Balbi * @link_state: link state 64572246da4SFelipe Balbi * @speed: device speed (super, high, full, low) 64672246da4SFelipe Balbi * @mem: points to start of memory which is used for this struct. 647a3299499SFelipe Balbi * @hwparams: copy of hwparams registers 64872246da4SFelipe Balbi * @root: debugfs root folder pointer 64972246da4SFelipe Balbi */ 65072246da4SFelipe Balbi struct dwc3 { 65172246da4SFelipe Balbi struct usb_ctrlrequest *ctrl_req; 652f6bafc6aSFelipe Balbi struct dwc3_trb *ep0_trb; 6535812b1c2SFelipe Balbi void *ep0_bounce; 65472246da4SFelipe Balbi u8 *setup_buf; 65572246da4SFelipe Balbi dma_addr_t ctrl_req_addr; 65672246da4SFelipe Balbi dma_addr_t ep0_trb_addr; 6575812b1c2SFelipe Balbi dma_addr_t ep0_bounce_addr; 658e0ce0b0aSSebastian Andrzej Siewior struct dwc3_request ep0_usb_req; 65972246da4SFelipe Balbi /* device lock */ 66072246da4SFelipe Balbi spinlock_t lock; 66172246da4SFelipe Balbi struct device *dev; 66272246da4SFelipe Balbi 663d07e8819SFelipe Balbi struct platform_device *xhci; 66451249dcaSIdo Shayevitz struct resource xhci_resources[DWC3_XHCI_RESOURCES_NUM]; 665d07e8819SFelipe Balbi 666457d3f21SFelipe Balbi struct dwc3_event_buffer **ev_buffs; 66772246da4SFelipe Balbi struct dwc3_ep *eps[DWC3_ENDPOINTS_NUM]; 66872246da4SFelipe Balbi 66972246da4SFelipe Balbi struct usb_gadget gadget; 67072246da4SFelipe Balbi struct usb_gadget_driver *gadget_driver; 67172246da4SFelipe Balbi 67251e1e7bcSFelipe Balbi struct usb_phy *usb2_phy; 67351e1e7bcSFelipe Balbi struct usb_phy *usb3_phy; 67451e1e7bcSFelipe Balbi 67572246da4SFelipe Balbi void __iomem *regs; 67672246da4SFelipe Balbi size_t regs_size; 67772246da4SFelipe Balbi 6789f622b2aSFelipe Balbi u32 num_event_buffers; 679fae2b904SFelipe Balbi u32 u1u2; 6806c167fc9SFelipe Balbi u32 maximum_speed; 68172246da4SFelipe Balbi u32 revision; 6820949e99bSFelipe Balbi u32 mode; 68372246da4SFelipe Balbi 68472246da4SFelipe Balbi #define DWC3_REVISION_173A 0x5533173a 68572246da4SFelipe Balbi #define DWC3_REVISION_175A 0x5533175a 68672246da4SFelipe Balbi #define DWC3_REVISION_180A 0x5533180a 68772246da4SFelipe Balbi #define DWC3_REVISION_183A 0x5533183a 68872246da4SFelipe Balbi #define DWC3_REVISION_185A 0x5533185a 6892c61a8efSPaul Zimmerman #define DWC3_REVISION_187A 0x5533187a 69072246da4SFelipe Balbi #define DWC3_REVISION_188A 0x5533188a 69172246da4SFelipe Balbi #define DWC3_REVISION_190A 0x5533190a 6922c61a8efSPaul Zimmerman #define DWC3_REVISION_194A 0x5533194a 6931522d703SFelipe Balbi #define DWC3_REVISION_200A 0x5533200a 6941522d703SFelipe Balbi #define DWC3_REVISION_202A 0x5533202a 6951522d703SFelipe Balbi #define DWC3_REVISION_210A 0x5533210a 6961522d703SFelipe Balbi #define DWC3_REVISION_220A 0x5533220a 69772246da4SFelipe Balbi 69872246da4SFelipe Balbi unsigned is_selfpowered:1; 69972246da4SFelipe Balbi unsigned three_stage_setup:1; 7005812b1c2SFelipe Balbi unsigned ep0_bounced:1; 70155f3fba6SFelipe Balbi unsigned ep0_expect_in:1; 702b23c8439SPaul Zimmerman unsigned start_config_issued:1; 703df62df56SFelipe Balbi unsigned setup_packet_pending:1; 7045bdb1dccSSebastian Andrzej Siewior unsigned delayed_status:1; 705457e84b6SFelipe Balbi unsigned needs_fifo_resize:1; 706457e84b6SFelipe Balbi unsigned resize_fifos:1; 707*9fcb3bd8SFelipe Balbi unsigned pullups_connected:1; 70872246da4SFelipe Balbi 709b53c772dSFelipe Balbi enum dwc3_ep0_next ep0_next_event; 71072246da4SFelipe Balbi enum dwc3_ep0_state ep0state; 71172246da4SFelipe Balbi enum dwc3_link_state link_state; 71272246da4SFelipe Balbi enum dwc3_device_state dev_state; 71372246da4SFelipe Balbi 714c12a0d86SFelipe Balbi u16 isoch_delay; 715865e09e7SFelipe Balbi u16 u2sel; 716865e09e7SFelipe Balbi u16 u2pel; 717865e09e7SFelipe Balbi u8 u1sel; 718865e09e7SFelipe Balbi u8 u1pel; 719865e09e7SFelipe Balbi 72072246da4SFelipe Balbi u8 speed; 721865e09e7SFelipe Balbi 72272246da4SFelipe Balbi void *mem; 72372246da4SFelipe Balbi 724a3299499SFelipe Balbi struct dwc3_hwparams hwparams; 72572246da4SFelipe Balbi struct dentry *root; 726d7668024SFelipe Balbi struct debugfs_regset32 *regset; 7273b637367SGerard Cauvy 7283b637367SGerard Cauvy u8 test_mode; 7293b637367SGerard Cauvy u8 test_mode_nr; 73072246da4SFelipe Balbi }; 73172246da4SFelipe Balbi 73272246da4SFelipe Balbi /* -------------------------------------------------------------------------- */ 73372246da4SFelipe Balbi 73472246da4SFelipe Balbi /* -------------------------------------------------------------------------- */ 73572246da4SFelipe Balbi 73672246da4SFelipe Balbi struct dwc3_event_type { 73772246da4SFelipe Balbi u32 is_devspec:1; 73872246da4SFelipe Balbi u32 type:6; 73972246da4SFelipe Balbi u32 reserved8_31:25; 74072246da4SFelipe Balbi } __packed; 74172246da4SFelipe Balbi 74272246da4SFelipe Balbi #define DWC3_DEPEVT_XFERCOMPLETE 0x01 74372246da4SFelipe Balbi #define DWC3_DEPEVT_XFERINPROGRESS 0x02 74472246da4SFelipe Balbi #define DWC3_DEPEVT_XFERNOTREADY 0x03 74572246da4SFelipe Balbi #define DWC3_DEPEVT_RXTXFIFOEVT 0x04 74672246da4SFelipe Balbi #define DWC3_DEPEVT_STREAMEVT 0x06 74772246da4SFelipe Balbi #define DWC3_DEPEVT_EPCMDCMPLT 0x07 74872246da4SFelipe Balbi 74972246da4SFelipe Balbi /** 75072246da4SFelipe Balbi * struct dwc3_event_depvt - Device Endpoint Events 75172246da4SFelipe Balbi * @one_bit: indicates this is an endpoint event (not used) 75272246da4SFelipe Balbi * @endpoint_number: number of the endpoint 75372246da4SFelipe Balbi * @endpoint_event: The event we have: 75472246da4SFelipe Balbi * 0x00 - Reserved 75572246da4SFelipe Balbi * 0x01 - XferComplete 75672246da4SFelipe Balbi * 0x02 - XferInProgress 75772246da4SFelipe Balbi * 0x03 - XferNotReady 75872246da4SFelipe Balbi * 0x04 - RxTxFifoEvt (IN->Underrun, OUT->Overrun) 75972246da4SFelipe Balbi * 0x05 - Reserved 76072246da4SFelipe Balbi * 0x06 - StreamEvt 76172246da4SFelipe Balbi * 0x07 - EPCmdCmplt 76272246da4SFelipe Balbi * @reserved11_10: Reserved, don't use. 76372246da4SFelipe Balbi * @status: Indicates the status of the event. Refer to databook for 76472246da4SFelipe Balbi * more information. 76572246da4SFelipe Balbi * @parameters: Parameters of the current event. Refer to databook for 76672246da4SFelipe Balbi * more information. 76772246da4SFelipe Balbi */ 76872246da4SFelipe Balbi struct dwc3_event_depevt { 76972246da4SFelipe Balbi u32 one_bit:1; 77072246da4SFelipe Balbi u32 endpoint_number:5; 77172246da4SFelipe Balbi u32 endpoint_event:4; 77272246da4SFelipe Balbi u32 reserved11_10:2; 77372246da4SFelipe Balbi u32 status:4; 77440aa41fbSFelipe Balbi 77540aa41fbSFelipe Balbi /* Within XferNotReady */ 77640aa41fbSFelipe Balbi #define DEPEVT_STATUS_TRANSFER_ACTIVE (1 << 3) 77740aa41fbSFelipe Balbi 77840aa41fbSFelipe Balbi /* Within XferComplete */ 77972246da4SFelipe Balbi #define DEPEVT_STATUS_BUSERR (1 << 0) 78072246da4SFelipe Balbi #define DEPEVT_STATUS_SHORT (1 << 1) 78172246da4SFelipe Balbi #define DEPEVT_STATUS_IOC (1 << 2) 78272246da4SFelipe Balbi #define DEPEVT_STATUS_LST (1 << 3) 783dc137f01SFelipe Balbi 784879631aaSFelipe Balbi /* Stream event only */ 785879631aaSFelipe Balbi #define DEPEVT_STREAMEVT_FOUND 1 786879631aaSFelipe Balbi #define DEPEVT_STREAMEVT_NOTFOUND 2 787879631aaSFelipe Balbi 788dc137f01SFelipe Balbi /* Control-only Status */ 789dc137f01SFelipe Balbi #define DEPEVT_STATUS_CONTROL_DATA 1 790dc137f01SFelipe Balbi #define DEPEVT_STATUS_CONTROL_STATUS 2 791dc137f01SFelipe Balbi 79272246da4SFelipe Balbi u32 parameters:16; 79372246da4SFelipe Balbi } __packed; 79472246da4SFelipe Balbi 79572246da4SFelipe Balbi /** 79672246da4SFelipe Balbi * struct dwc3_event_devt - Device Events 79772246da4SFelipe Balbi * @one_bit: indicates this is a non-endpoint event (not used) 79872246da4SFelipe Balbi * @device_event: indicates it's a device event. Should read as 0x00 79972246da4SFelipe Balbi * @type: indicates the type of device event. 80072246da4SFelipe Balbi * 0 - DisconnEvt 80172246da4SFelipe Balbi * 1 - USBRst 80272246da4SFelipe Balbi * 2 - ConnectDone 80372246da4SFelipe Balbi * 3 - ULStChng 80472246da4SFelipe Balbi * 4 - WkUpEvt 80572246da4SFelipe Balbi * 5 - Reserved 80672246da4SFelipe Balbi * 6 - EOPF 80772246da4SFelipe Balbi * 7 - SOF 80872246da4SFelipe Balbi * 8 - Reserved 80972246da4SFelipe Balbi * 9 - ErrticErr 81072246da4SFelipe Balbi * 10 - CmdCmplt 81172246da4SFelipe Balbi * 11 - EvntOverflow 81272246da4SFelipe Balbi * 12 - VndrDevTstRcved 81372246da4SFelipe Balbi * @reserved15_12: Reserved, not used 81472246da4SFelipe Balbi * @event_info: Information about this event 81572246da4SFelipe Balbi * @reserved31_24: Reserved, not used 81672246da4SFelipe Balbi */ 81772246da4SFelipe Balbi struct dwc3_event_devt { 81872246da4SFelipe Balbi u32 one_bit:1; 81972246da4SFelipe Balbi u32 device_event:7; 82072246da4SFelipe Balbi u32 type:4; 82172246da4SFelipe Balbi u32 reserved15_12:4; 82272246da4SFelipe Balbi u32 event_info:8; 82372246da4SFelipe Balbi u32 reserved31_24:8; 82472246da4SFelipe Balbi } __packed; 82572246da4SFelipe Balbi 82672246da4SFelipe Balbi /** 82772246da4SFelipe Balbi * struct dwc3_event_gevt - Other Core Events 82872246da4SFelipe Balbi * @one_bit: indicates this is a non-endpoint event (not used) 82972246da4SFelipe Balbi * @device_event: indicates it's (0x03) Carkit or (0x04) I2C event. 83072246da4SFelipe Balbi * @phy_port_number: self-explanatory 83172246da4SFelipe Balbi * @reserved31_12: Reserved, not used. 83272246da4SFelipe Balbi */ 83372246da4SFelipe Balbi struct dwc3_event_gevt { 83472246da4SFelipe Balbi u32 one_bit:1; 83572246da4SFelipe Balbi u32 device_event:7; 83672246da4SFelipe Balbi u32 phy_port_number:4; 83772246da4SFelipe Balbi u32 reserved31_12:20; 83872246da4SFelipe Balbi } __packed; 83972246da4SFelipe Balbi 84072246da4SFelipe Balbi /** 84172246da4SFelipe Balbi * union dwc3_event - representation of Event Buffer contents 84272246da4SFelipe Balbi * @raw: raw 32-bit event 84372246da4SFelipe Balbi * @type: the type of the event 84472246da4SFelipe Balbi * @depevt: Device Endpoint Event 84572246da4SFelipe Balbi * @devt: Device Event 84672246da4SFelipe Balbi * @gevt: Global Event 84772246da4SFelipe Balbi */ 84872246da4SFelipe Balbi union dwc3_event { 84972246da4SFelipe Balbi u32 raw; 85072246da4SFelipe Balbi struct dwc3_event_type type; 85172246da4SFelipe Balbi struct dwc3_event_depevt depevt; 85272246da4SFelipe Balbi struct dwc3_event_devt devt; 85372246da4SFelipe Balbi struct dwc3_event_gevt gevt; 85472246da4SFelipe Balbi }; 85572246da4SFelipe Balbi 85672246da4SFelipe Balbi /* 85772246da4SFelipe Balbi * DWC3 Features to be used as Driver Data 85872246da4SFelipe Balbi */ 85972246da4SFelipe Balbi 86072246da4SFelipe Balbi #define DWC3_HAS_PERIPHERAL BIT(0) 86172246da4SFelipe Balbi #define DWC3_HAS_XHCI BIT(1) 86272246da4SFelipe Balbi #define DWC3_HAS_OTG BIT(3) 86372246da4SFelipe Balbi 864d07e8819SFelipe Balbi /* prototypes */ 8653140e8cbSSebastian Andrzej Siewior void dwc3_set_mode(struct dwc3 *dwc, u32 mode); 866457e84b6SFelipe Balbi int dwc3_gadget_resize_tx_fifos(struct dwc3 *dwc); 8673140e8cbSSebastian Andrzej Siewior 868388e5c51SVivek Gautam #if IS_ENABLED(CONFIG_USB_DWC3_HOST) || IS_ENABLED(CONFIG_USB_DWC3_DUAL_ROLE) 869d07e8819SFelipe Balbi int dwc3_host_init(struct dwc3 *dwc); 870d07e8819SFelipe Balbi void dwc3_host_exit(struct dwc3 *dwc); 871388e5c51SVivek Gautam #else 872388e5c51SVivek Gautam static inline int dwc3_host_init(struct dwc3 *dwc) 873388e5c51SVivek Gautam { return 0; } 874388e5c51SVivek Gautam static inline void dwc3_host_exit(struct dwc3 *dwc) 875388e5c51SVivek Gautam { } 876388e5c51SVivek Gautam #endif 877d07e8819SFelipe Balbi 878388e5c51SVivek Gautam #if IS_ENABLED(CONFIG_USB_DWC3_GADGET) || IS_ENABLED(CONFIG_USB_DWC3_DUAL_ROLE) 879f80b45e7SFelipe Balbi int dwc3_gadget_init(struct dwc3 *dwc); 880f80b45e7SFelipe Balbi void dwc3_gadget_exit(struct dwc3 *dwc); 881388e5c51SVivek Gautam #else 882388e5c51SVivek Gautam static inline int dwc3_gadget_init(struct dwc3 *dwc) 883388e5c51SVivek Gautam { return 0; } 884388e5c51SVivek Gautam static inline void dwc3_gadget_exit(struct dwc3 *dwc) 885388e5c51SVivek Gautam { } 886388e5c51SVivek Gautam #endif 887f80b45e7SFelipe Balbi 88872246da4SFelipe Balbi #endif /* __DRIVERS_USB_DWC3_CORE_H */ 889