1b33f69f5SNishad Kamdar /* SPDX-License-Identifier: GPL-2.0 */ 2bfad65eeSFelipe Balbi /* 372246da4SFelipe Balbi * core.h - DesignWare USB3 DRD Core Header 472246da4SFelipe Balbi * 510623b87SAlexander A. Klimov * Copyright (C) 2010-2011 Texas Instruments Incorporated - https://www.ti.com 672246da4SFelipe Balbi * 772246da4SFelipe Balbi * Authors: Felipe Balbi <balbi@ti.com>, 872246da4SFelipe Balbi * Sebastian Andrzej Siewior <bigeasy@linutronix.de> 972246da4SFelipe Balbi */ 1072246da4SFelipe Balbi 1172246da4SFelipe Balbi #ifndef __DRIVERS_USB_DWC3_CORE_H 1272246da4SFelipe Balbi #define __DRIVERS_USB_DWC3_CORE_H 1372246da4SFelipe Balbi 1472246da4SFelipe Balbi #include <linux/device.h> 1572246da4SFelipe Balbi #include <linux/spinlock.h> 16f88359e1SYu Chen #include <linux/mutex.h> 17d07e8819SFelipe Balbi #include <linux/ioport.h> 1872246da4SFelipe Balbi #include <linux/list.h> 19ff3f0789SRoger Quadros #include <linux/bitops.h> 2072246da4SFelipe Balbi #include <linux/dma-mapping.h> 2172246da4SFelipe Balbi #include <linux/mm.h> 2272246da4SFelipe Balbi #include <linux/debugfs.h> 2376a638f8SBaolin Wang #include <linux/wait.h> 2441ce1456SRoger Quadros #include <linux/workqueue.h> 2572246da4SFelipe Balbi 2672246da4SFelipe Balbi #include <linux/usb/ch9.h> 2772246da4SFelipe Balbi #include <linux/usb/gadget.h> 28a45c82b8SRuchika Kharwar #include <linux/usb/otg.h> 298a0a1379SYu Chen #include <linux/usb/role.h> 3088bc9d19SHeikki Krogerus #include <linux/ulpi/interface.h> 3172246da4SFelipe Balbi 3257303488SKishon Vijay Abraham I #include <linux/phy/phy.h> 3357303488SKishon Vijay Abraham I 346f0764b5SRay Chi #include <linux/power_supply.h> 356f0764b5SRay Chi 362c4cbe6eSFelipe Balbi #define DWC3_MSG_MAX 500 372c4cbe6eSFelipe Balbi 3872246da4SFelipe Balbi /* Global constants */ 39bb014736SBaolin Wang #define DWC3_PULL_UP_TIMEOUT 500 /* ms */ 40905dc04eSFelipe Balbi #define DWC3_BOUNCE_SIZE 1024 /* size of a superspeed bulk */ 414199c5f8SFelipe Balbi #define DWC3_EP0_SETUP_SIZE 512 4272246da4SFelipe Balbi #define DWC3_ENDPOINTS_NUM 32 4351249dcaSIdo Shayevitz #define DWC3_XHCI_RESOURCES_NUM 2 44d5370106SFelipe Balbi #define DWC3_ISOC_MAX_RETRIES 5 4572246da4SFelipe Balbi 460ffcaf37SFelipe Balbi #define DWC3_SCRATCHBUF_SIZE 4096 /* each buffer is assumed to be 4KiB */ 47e71d363dSFelipe Balbi #define DWC3_EVENT_BUFFERS_SIZE 4096 4872246da4SFelipe Balbi #define DWC3_EVENT_TYPE_MASK 0xfe 4972246da4SFelipe Balbi 5072246da4SFelipe Balbi #define DWC3_EVENT_TYPE_DEV 0 5172246da4SFelipe Balbi #define DWC3_EVENT_TYPE_CARKIT 3 5272246da4SFelipe Balbi #define DWC3_EVENT_TYPE_I2C 4 5372246da4SFelipe Balbi 5472246da4SFelipe Balbi #define DWC3_DEVICE_EVENT_DISCONNECT 0 5572246da4SFelipe Balbi #define DWC3_DEVICE_EVENT_RESET 1 5672246da4SFelipe Balbi #define DWC3_DEVICE_EVENT_CONNECT_DONE 2 5772246da4SFelipe Balbi #define DWC3_DEVICE_EVENT_LINK_STATUS_CHANGE 3 5872246da4SFelipe Balbi #define DWC3_DEVICE_EVENT_WAKEUP 4 592c61a8efSPaul Zimmerman #define DWC3_DEVICE_EVENT_HIBER_REQ 5 606f26ebb7SJack Pham #define DWC3_DEVICE_EVENT_SUSPEND 6 6172246da4SFelipe Balbi #define DWC3_DEVICE_EVENT_SOF 7 6272246da4SFelipe Balbi #define DWC3_DEVICE_EVENT_ERRATIC_ERROR 9 6372246da4SFelipe Balbi #define DWC3_DEVICE_EVENT_CMD_CMPL 10 6472246da4SFelipe Balbi #define DWC3_DEVICE_EVENT_OVERFLOW 11 6572246da4SFelipe Balbi 66f09cc79bSRoger Quadros /* Controller's role while using the OTG block */ 67f09cc79bSRoger Quadros #define DWC3_OTG_ROLE_IDLE 0 68f09cc79bSRoger Quadros #define DWC3_OTG_ROLE_HOST 1 69f09cc79bSRoger Quadros #define DWC3_OTG_ROLE_DEVICE 2 70f09cc79bSRoger Quadros 7172246da4SFelipe Balbi #define DWC3_GEVNTCOUNT_MASK 0xfffc 72ff3f0789SRoger Quadros #define DWC3_GEVNTCOUNT_EHB BIT(31) 7372246da4SFelipe Balbi #define DWC3_GSNPSID_MASK 0xffff0000 7472246da4SFelipe Balbi #define DWC3_GSNPSREV_MASK 0xffff 759af21dd6SThinh Nguyen #define DWC3_GSNPS_ID(p) (((p) & DWC3_GSNPSID_MASK) >> 16) 7672246da4SFelipe Balbi 7751249dcaSIdo Shayevitz /* DWC3 registers memory space boundries */ 7851249dcaSIdo Shayevitz #define DWC3_XHCI_REGS_START 0x0 7951249dcaSIdo Shayevitz #define DWC3_XHCI_REGS_END 0x7fff 8051249dcaSIdo Shayevitz #define DWC3_GLOBALS_REGS_START 0xc100 8151249dcaSIdo Shayevitz #define DWC3_GLOBALS_REGS_END 0xc6ff 8251249dcaSIdo Shayevitz #define DWC3_DEVICE_REGS_START 0xc700 8351249dcaSIdo Shayevitz #define DWC3_DEVICE_REGS_END 0xcbff 8451249dcaSIdo Shayevitz #define DWC3_OTG_REGS_START 0xcc00 8551249dcaSIdo Shayevitz #define DWC3_OTG_REGS_END 0xccff 8651249dcaSIdo Shayevitz 8772246da4SFelipe Balbi /* Global Registers */ 8872246da4SFelipe Balbi #define DWC3_GSBUSCFG0 0xc100 8972246da4SFelipe Balbi #define DWC3_GSBUSCFG1 0xc104 9072246da4SFelipe Balbi #define DWC3_GTXTHRCFG 0xc108 9172246da4SFelipe Balbi #define DWC3_GRXTHRCFG 0xc10c 9272246da4SFelipe Balbi #define DWC3_GCTL 0xc110 9372246da4SFelipe Balbi #define DWC3_GEVTEN 0xc114 9472246da4SFelipe Balbi #define DWC3_GSTS 0xc118 95475c8bebSWilliam Wu #define DWC3_GUCTL1 0xc11c 9672246da4SFelipe Balbi #define DWC3_GSNPSID 0xc120 9772246da4SFelipe Balbi #define DWC3_GGPIO 0xc124 9872246da4SFelipe Balbi #define DWC3_GUID 0xc128 9972246da4SFelipe Balbi #define DWC3_GUCTL 0xc12c 10072246da4SFelipe Balbi #define DWC3_GBUSERRADDR0 0xc130 10172246da4SFelipe Balbi #define DWC3_GBUSERRADDR1 0xc134 10272246da4SFelipe Balbi #define DWC3_GPRTBIMAP0 0xc138 10372246da4SFelipe Balbi #define DWC3_GPRTBIMAP1 0xc13c 10472246da4SFelipe Balbi #define DWC3_GHWPARAMS0 0xc140 10572246da4SFelipe Balbi #define DWC3_GHWPARAMS1 0xc144 10672246da4SFelipe Balbi #define DWC3_GHWPARAMS2 0xc148 10772246da4SFelipe Balbi #define DWC3_GHWPARAMS3 0xc14c 10872246da4SFelipe Balbi #define DWC3_GHWPARAMS4 0xc150 10972246da4SFelipe Balbi #define DWC3_GHWPARAMS5 0xc154 11072246da4SFelipe Balbi #define DWC3_GHWPARAMS6 0xc158 11172246da4SFelipe Balbi #define DWC3_GHWPARAMS7 0xc15c 11272246da4SFelipe Balbi #define DWC3_GDBGFIFOSPACE 0xc160 11372246da4SFelipe Balbi #define DWC3_GDBGLTSSM 0xc164 11480b77634SThinh Nguyen #define DWC3_GDBGBMU 0xc16c 11580b77634SThinh Nguyen #define DWC3_GDBGLSPMUX 0xc170 11680b77634SThinh Nguyen #define DWC3_GDBGLSP 0xc174 11780b77634SThinh Nguyen #define DWC3_GDBGEPINFO0 0xc178 11880b77634SThinh Nguyen #define DWC3_GDBGEPINFO1 0xc17c 11972246da4SFelipe Balbi #define DWC3_GPRTBIMAP_HS0 0xc180 12072246da4SFelipe Balbi #define DWC3_GPRTBIMAP_HS1 0xc184 12172246da4SFelipe Balbi #define DWC3_GPRTBIMAP_FS0 0xc188 12272246da4SFelipe Balbi #define DWC3_GPRTBIMAP_FS1 0xc18c 12306281d46SJohn Youn #define DWC3_GUCTL2 0xc19c 12472246da4SFelipe Balbi 125690fb371SJohn Youn #define DWC3_VER_NUMBER 0xc1a0 126690fb371SJohn Youn #define DWC3_VER_TYPE 0xc1a4 127690fb371SJohn Youn 1288261bd4eSRoger Quadros #define DWC3_GUSB2PHYCFG(n) (0xc200 + ((n) * 0x04)) 1298261bd4eSRoger Quadros #define DWC3_GUSB2I2CCTL(n) (0xc240 + ((n) * 0x04)) 13072246da4SFelipe Balbi 1318261bd4eSRoger Quadros #define DWC3_GUSB2PHYACC(n) (0xc280 + ((n) * 0x04)) 13272246da4SFelipe Balbi 1338261bd4eSRoger Quadros #define DWC3_GUSB3PIPECTL(n) (0xc2c0 + ((n) * 0x04)) 13472246da4SFelipe Balbi 1358261bd4eSRoger Quadros #define DWC3_GTXFIFOSIZ(n) (0xc300 + ((n) * 0x04)) 1368261bd4eSRoger Quadros #define DWC3_GRXFIFOSIZ(n) (0xc380 + ((n) * 0x04)) 13772246da4SFelipe Balbi 1388261bd4eSRoger Quadros #define DWC3_GEVNTADRLO(n) (0xc400 + ((n) * 0x10)) 1398261bd4eSRoger Quadros #define DWC3_GEVNTADRHI(n) (0xc404 + ((n) * 0x10)) 1408261bd4eSRoger Quadros #define DWC3_GEVNTSIZ(n) (0xc408 + ((n) * 0x10)) 1418261bd4eSRoger Quadros #define DWC3_GEVNTCOUNT(n) (0xc40c + ((n) * 0x10)) 14272246da4SFelipe Balbi 14372246da4SFelipe Balbi #define DWC3_GHWPARAMS8 0xc600 144f580170fSYu Chen #define DWC3_GUCTL3 0xc60c 145db2be4e9SNikhil Badola #define DWC3_GFLADJ 0xc630 146250fdabeSThinh Nguyen #define DWC3_GHWPARAMS9 0xc6e0 14772246da4SFelipe Balbi 14872246da4SFelipe Balbi /* Device Registers */ 14972246da4SFelipe Balbi #define DWC3_DCFG 0xc700 15072246da4SFelipe Balbi #define DWC3_DCTL 0xc704 15172246da4SFelipe Balbi #define DWC3_DEVTEN 0xc708 15272246da4SFelipe Balbi #define DWC3_DSTS 0xc70c 15372246da4SFelipe Balbi #define DWC3_DGCMDPAR 0xc710 15472246da4SFelipe Balbi #define DWC3_DGCMD 0xc714 15572246da4SFelipe Balbi #define DWC3_DALEPENA 0xc720 156666f3de7SThinh Nguyen #define DWC3_DCFG1 0xc740 /* DWC_usb32 only */ 1572eb88016SFelipe Balbi 1588261bd4eSRoger Quadros #define DWC3_DEP_BASE(n) (0xc800 + ((n) * 0x10)) 1592eb88016SFelipe Balbi #define DWC3_DEPCMDPAR2 0x00 1602eb88016SFelipe Balbi #define DWC3_DEPCMDPAR1 0x04 1612eb88016SFelipe Balbi #define DWC3_DEPCMDPAR0 0x08 1622eb88016SFelipe Balbi #define DWC3_DEPCMD 0x0c 16372246da4SFelipe Balbi 1648261bd4eSRoger Quadros #define DWC3_DEV_IMOD(n) (0xca00 + ((n) * 0x4)) 165cf40b86bSJohn Youn 16672246da4SFelipe Balbi /* OTG Registers */ 16772246da4SFelipe Balbi #define DWC3_OCFG 0xcc00 16872246da4SFelipe Balbi #define DWC3_OCTL 0xcc04 169d4436c3aSGeorge Cherian #define DWC3_OEVT 0xcc08 170d4436c3aSGeorge Cherian #define DWC3_OEVTEN 0xcc0C 171d4436c3aSGeorge Cherian #define DWC3_OSTS 0xcc10 17272246da4SFelipe Balbi 17372246da4SFelipe Balbi /* Bit fields */ 17472246da4SFelipe Balbi 175d635db55SPengbo Mu /* Global SoC Bus Configuration INCRx Register 0 */ 176d635db55SPengbo Mu #define DWC3_GSBUSCFG0_INCR256BRSTENA (1 << 7) /* INCR256 burst */ 177d635db55SPengbo Mu #define DWC3_GSBUSCFG0_INCR128BRSTENA (1 << 6) /* INCR128 burst */ 178d635db55SPengbo Mu #define DWC3_GSBUSCFG0_INCR64BRSTENA (1 << 5) /* INCR64 burst */ 179d635db55SPengbo Mu #define DWC3_GSBUSCFG0_INCR32BRSTENA (1 << 4) /* INCR32 burst */ 180d635db55SPengbo Mu #define DWC3_GSBUSCFG0_INCR16BRSTENA (1 << 3) /* INCR16 burst */ 181d635db55SPengbo Mu #define DWC3_GSBUSCFG0_INCR8BRSTENA (1 << 2) /* INCR8 burst */ 182d635db55SPengbo Mu #define DWC3_GSBUSCFG0_INCR4BRSTENA (1 << 1) /* INCR4 burst */ 183d635db55SPengbo Mu #define DWC3_GSBUSCFG0_INCRBRSTENA (1 << 0) /* undefined length enable */ 184d635db55SPengbo Mu #define DWC3_GSBUSCFG0_INCRBRST_MASK 0xff 185d635db55SPengbo Mu 18662ba09d6SThinh Nguyen /* Global Debug LSP MUX Select */ 18762ba09d6SThinh Nguyen #define DWC3_GDBGLSPMUX_ENDBC BIT(15) /* Host only */ 18862ba09d6SThinh Nguyen #define DWC3_GDBGLSPMUX_HOSTSELECT(n) ((n) & 0x3fff) 18962ba09d6SThinh Nguyen #define DWC3_GDBGLSPMUX_DEVSELECT(n) (((n) & 0xf) << 4) 19062ba09d6SThinh Nguyen #define DWC3_GDBGLSPMUX_EPSELECT(n) ((n) & 0xf) 19162ba09d6SThinh Nguyen 192cf6d867dSFelipe Balbi /* Global Debug Queue/FIFO Space Available Register */ 193cf6d867dSFelipe Balbi #define DWC3_GDBGFIFOSPACE_NUM(n) ((n) & 0x1f) 194cf6d867dSFelipe Balbi #define DWC3_GDBGFIFOSPACE_TYPE(n) (((n) << 5) & 0x1e0) 195cf6d867dSFelipe Balbi #define DWC3_GDBGFIFOSPACE_SPACE_AVAILABLE(n) (((n) >> 16) & 0xffff) 196cf6d867dSFelipe Balbi 1972c85a181SThinh Nguyen #define DWC3_TXFIFO 0 1982c85a181SThinh Nguyen #define DWC3_RXFIFO 1 199b16ea8b9SThinh Nguyen #define DWC3_TXREQQ 2 200b16ea8b9SThinh Nguyen #define DWC3_RXREQQ 3 201b16ea8b9SThinh Nguyen #define DWC3_RXINFOQ 4 202b16ea8b9SThinh Nguyen #define DWC3_PSTATQ 5 203b16ea8b9SThinh Nguyen #define DWC3_DESCFETCHQ 6 204b16ea8b9SThinh Nguyen #define DWC3_EVENTQ 7 205b16ea8b9SThinh Nguyen #define DWC3_AUXEVENTQ 8 206cf6d867dSFelipe Balbi 2072a58f9c1SFelipe Balbi /* Global RX Threshold Configuration Register */ 2082a58f9c1SFelipe Balbi #define DWC3_GRXTHRCFG_MAXRXBURSTSIZE(n) (((n) & 0x1f) << 19) 2092a58f9c1SFelipe Balbi #define DWC3_GRXTHRCFG_RXPKTCNT(n) (((n) & 0xf) << 24) 210ff3f0789SRoger Quadros #define DWC3_GRXTHRCFG_PKTCNTSEL BIT(29) 2112a58f9c1SFelipe Balbi 2122fbc5bdcSThinh Nguyen /* Global RX Threshold Configuration Register for DWC_usb31 only */ 2132fbc5bdcSThinh Nguyen #define DWC31_GRXTHRCFG_MAXRXBURSTSIZE(n) (((n) & 0x1f) << 16) 2142fbc5bdcSThinh Nguyen #define DWC31_GRXTHRCFG_RXPKTCNT(n) (((n) & 0x1f) << 21) 2152fbc5bdcSThinh Nguyen #define DWC31_GRXTHRCFG_PKTCNTSEL BIT(26) 2162fbc5bdcSThinh Nguyen #define DWC31_RXTHRNUMPKTSEL_HS_PRD BIT(15) 2172fbc5bdcSThinh Nguyen #define DWC31_RXTHRNUMPKT_HS_PRD(n) (((n) & 0x3) << 13) 2182fbc5bdcSThinh Nguyen #define DWC31_RXTHRNUMPKTSEL_PRD BIT(10) 2192fbc5bdcSThinh Nguyen #define DWC31_RXTHRNUMPKT_PRD(n) (((n) & 0x1f) << 5) 2202fbc5bdcSThinh Nguyen #define DWC31_MAXRXBURSTSIZE_PRD(n) ((n) & 0x1f) 2212fbc5bdcSThinh Nguyen 2226743e817SThinh Nguyen /* Global TX Threshold Configuration Register for DWC_usb31 only */ 2236743e817SThinh Nguyen #define DWC31_GTXTHRCFG_MAXTXBURSTSIZE(n) (((n) & 0x1f) << 16) 2246743e817SThinh Nguyen #define DWC31_GTXTHRCFG_TXPKTCNT(n) (((n) & 0x1f) << 21) 2256743e817SThinh Nguyen #define DWC31_GTXTHRCFG_PKTCNTSEL BIT(26) 2266743e817SThinh Nguyen #define DWC31_TXTHRNUMPKTSEL_HS_PRD BIT(15) 2276743e817SThinh Nguyen #define DWC31_TXTHRNUMPKT_HS_PRD(n) (((n) & 0x3) << 13) 2286743e817SThinh Nguyen #define DWC31_TXTHRNUMPKTSEL_PRD BIT(10) 2296743e817SThinh Nguyen #define DWC31_TXTHRNUMPKT_PRD(n) (((n) & 0x1f) << 5) 2306743e817SThinh Nguyen #define DWC31_MAXTXBURSTSIZE_PRD(n) ((n) & 0x1f) 2316743e817SThinh Nguyen 23272246da4SFelipe Balbi /* Global Configuration Register */ 2331d046793SPaul Zimmerman #define DWC3_GCTL_PWRDNSCALE(n) ((n) << 19) 2343497b9a5SLi Jun #define DWC3_GCTL_PWRDNSCALE_MASK GENMASK(31, 19) 235ff3f0789SRoger Quadros #define DWC3_GCTL_U2RSTECN BIT(16) 2361d046793SPaul Zimmerman #define DWC3_GCTL_RAMCLKSEL(x) (((x) & DWC3_GCTL_CLK_MASK) << 6) 23772246da4SFelipe Balbi #define DWC3_GCTL_CLK_BUS (0) 23872246da4SFelipe Balbi #define DWC3_GCTL_CLK_PIPE (1) 23972246da4SFelipe Balbi #define DWC3_GCTL_CLK_PIPEHALF (2) 24072246da4SFelipe Balbi #define DWC3_GCTL_CLK_MASK (3) 24172246da4SFelipe Balbi 2420b9fe32dSFelipe Balbi #define DWC3_GCTL_PRTCAP(n) (((n) & (3 << 12)) >> 12) 2431d046793SPaul Zimmerman #define DWC3_GCTL_PRTCAPDIR(n) ((n) << 12) 24472246da4SFelipe Balbi #define DWC3_GCTL_PRTCAP_HOST 1 24572246da4SFelipe Balbi #define DWC3_GCTL_PRTCAP_DEVICE 2 24672246da4SFelipe Balbi #define DWC3_GCTL_PRTCAP_OTG 3 24772246da4SFelipe Balbi 248ff3f0789SRoger Quadros #define DWC3_GCTL_CORESOFTRESET BIT(11) 249ff3f0789SRoger Quadros #define DWC3_GCTL_SOFITPSYNC BIT(10) 2501d046793SPaul Zimmerman #define DWC3_GCTL_SCALEDOWN(n) ((n) << 4) 2513e87c42aSPaul Zimmerman #define DWC3_GCTL_SCALEDOWN_MASK DWC3_GCTL_SCALEDOWN(3) 252ff3f0789SRoger Quadros #define DWC3_GCTL_DISSCRAMBLE BIT(3) 253ff3f0789SRoger Quadros #define DWC3_GCTL_U2EXIT_LFPS BIT(2) 254ff3f0789SRoger Quadros #define DWC3_GCTL_GBLHIBERNATIONEN BIT(1) 255ff3f0789SRoger Quadros #define DWC3_GCTL_DSBLCLKGTNG BIT(0) 25672246da4SFelipe Balbi 257b138e23dSAnurag Kumar Vulisha /* Global User Control Register */ 258b138e23dSAnurag Kumar Vulisha #define DWC3_GUCTL_HSTINAUTORETRY BIT(14) 259b138e23dSAnurag Kumar Vulisha 2600bb39ca1SJohn Youn /* Global User Control 1 Register */ 261843714bbSJack Pham #define DWC3_GUCTL1_DEV_DECOUPLE_L1L2_EVT BIT(31) 26265db7a0cSWilliam Wu #define DWC3_GUCTL1_TX_IPGAP_LINECHECK_DIS BIT(28) 26362b20e6eSBin Yang #define DWC3_GUCTL1_DEV_FORCE_20_CLK_FOR_30_CLK BIT(26) 264ff3f0789SRoger Quadros #define DWC3_GUCTL1_DEV_L1_EXIT_BY_HW BIT(24) 265843714bbSJack Pham #define DWC3_GUCTL1_PARKMODE_DISABLE_SS BIT(17) 266d21a797aSStanley Chang #define DWC3_GUCTL1_PARKMODE_DISABLE_HS BIT(16) 26763d7f981SPiyush Mehta #define DWC3_GUCTL1_RESUME_OPMODE_HS_HOST BIT(10) 2680bb39ca1SJohn Youn 2694cff75c7SRoger Quadros /* Global Status Register */ 2704cff75c7SRoger Quadros #define DWC3_GSTS_OTG_IP BIT(10) 2714cff75c7SRoger Quadros #define DWC3_GSTS_BC_IP BIT(9) 2724cff75c7SRoger Quadros #define DWC3_GSTS_ADP_IP BIT(8) 2734cff75c7SRoger Quadros #define DWC3_GSTS_HOST_IP BIT(7) 2744cff75c7SRoger Quadros #define DWC3_GSTS_DEVICE_IP BIT(6) 2754cff75c7SRoger Quadros #define DWC3_GSTS_CSR_TIMEOUT BIT(5) 2764cff75c7SRoger Quadros #define DWC3_GSTS_BUS_ERR_ADDR_VLD BIT(4) 27762ba09d6SThinh Nguyen #define DWC3_GSTS_CURMOD(n) ((n) & 0x3) 27862ba09d6SThinh Nguyen #define DWC3_GSTS_CURMOD_DEVICE 0 27962ba09d6SThinh Nguyen #define DWC3_GSTS_CURMOD_HOST 1 2804cff75c7SRoger Quadros 28172246da4SFelipe Balbi /* Global USB2 PHY Configuration Register */ 282ff3f0789SRoger Quadros #define DWC3_GUSB2PHYCFG_PHYSOFTRST BIT(31) 283ff3f0789SRoger Quadros #define DWC3_GUSB2PHYCFG_U2_FREECLK_EXISTS BIT(30) 284b84ba26cSPiyush Mehta #define DWC3_GUSB2PHYCFG_ULPIEXTVBUSDRV BIT(17) 285ff3f0789SRoger Quadros #define DWC3_GUSB2PHYCFG_SUSPHY BIT(6) 286ff3f0789SRoger Quadros #define DWC3_GUSB2PHYCFG_ULPI_UTMI BIT(4) 287ff3f0789SRoger Quadros #define DWC3_GUSB2PHYCFG_ENBLSLPM BIT(8) 28832f2ed86SWilliam Wu #define DWC3_GUSB2PHYCFG_PHYIF(n) (n << 3) 28932f2ed86SWilliam Wu #define DWC3_GUSB2PHYCFG_PHYIF_MASK DWC3_GUSB2PHYCFG_PHYIF(1) 29032f2ed86SWilliam Wu #define DWC3_GUSB2PHYCFG_USBTRDTIM(n) (n << 10) 29132f2ed86SWilliam Wu #define DWC3_GUSB2PHYCFG_USBTRDTIM_MASK DWC3_GUSB2PHYCFG_USBTRDTIM(0xf) 29232f2ed86SWilliam Wu #define USBTRDTIM_UTMI_8_BIT 9 29332f2ed86SWilliam Wu #define USBTRDTIM_UTMI_16_BIT 5 29432f2ed86SWilliam Wu #define UTMI_PHYIF_16_BIT 1 29532f2ed86SWilliam Wu #define UTMI_PHYIF_8_BIT 0 29672246da4SFelipe Balbi 297b5699eeeSHeikki Krogerus /* Global USB2 PHY Vendor Control Register */ 298ff3f0789SRoger Quadros #define DWC3_GUSB2PHYACC_NEWREGREQ BIT(25) 299ce722da6SSerge Semin #define DWC3_GUSB2PHYACC_DONE BIT(24) 300ff3f0789SRoger Quadros #define DWC3_GUSB2PHYACC_BUSY BIT(23) 301ff3f0789SRoger Quadros #define DWC3_GUSB2PHYACC_WRITE BIT(22) 302b5699eeeSHeikki Krogerus #define DWC3_GUSB2PHYACC_ADDR(n) (n << 16) 303b5699eeeSHeikki Krogerus #define DWC3_GUSB2PHYACC_EXTEND_ADDR(n) (n << 8) 304b5699eeeSHeikki Krogerus #define DWC3_GUSB2PHYACC_DATA(n) (n & 0xff) 305b5699eeeSHeikki Krogerus 30672246da4SFelipe Balbi /* Global USB3 PIPE Control Register */ 307ff3f0789SRoger Quadros #define DWC3_GUSB3PIPECTL_PHYSOFTRST BIT(31) 308ff3f0789SRoger Quadros #define DWC3_GUSB3PIPECTL_U2SSINP3OK BIT(29) 309ff3f0789SRoger Quadros #define DWC3_GUSB3PIPECTL_DISRXDETINP3 BIT(28) 310ff3f0789SRoger Quadros #define DWC3_GUSB3PIPECTL_UX_EXIT_PX BIT(27) 311ff3f0789SRoger Quadros #define DWC3_GUSB3PIPECTL_REQP1P2P3 BIT(24) 312a2a1d0f5SHuang Rui #define DWC3_GUSB3PIPECTL_DEP1P2P3(n) ((n) << 19) 313a2a1d0f5SHuang Rui #define DWC3_GUSB3PIPECTL_DEP1P2P3_MASK DWC3_GUSB3PIPECTL_DEP1P2P3(7) 314a2a1d0f5SHuang Rui #define DWC3_GUSB3PIPECTL_DEP1P2P3_EN DWC3_GUSB3PIPECTL_DEP1P2P3(1) 315ff3f0789SRoger Quadros #define DWC3_GUSB3PIPECTL_DEPOCHANGE BIT(18) 316ff3f0789SRoger Quadros #define DWC3_GUSB3PIPECTL_SUSPHY BIT(17) 317ff3f0789SRoger Quadros #define DWC3_GUSB3PIPECTL_LFPSFILT BIT(9) 318ff3f0789SRoger Quadros #define DWC3_GUSB3PIPECTL_RX_DETOPOLL BIT(8) 3196b6a0c9aSHuang Rui #define DWC3_GUSB3PIPECTL_TX_DEEPH_MASK DWC3_GUSB3PIPECTL_TX_DEEPH(3) 3206b6a0c9aSHuang Rui #define DWC3_GUSB3PIPECTL_TX_DEEPH(n) ((n) << 1) 32172246da4SFelipe Balbi 322457e84b6SFelipe Balbi /* Global TX Fifo Size Register */ 3230cab8d26SThinh Nguyen #define DWC31_GTXFIFOSIZ_TXFRAMNUM BIT(15) /* DWC_usb31 only */ 324586f4335SThinh Nguyen #define DWC31_GTXFIFOSIZ_TXFDEP(n) ((n) & 0x7fff) /* DWC_usb31 only */ 325586f4335SThinh Nguyen #define DWC3_GTXFIFOSIZ_TXFDEP(n) ((n) & 0xffff) 326457e84b6SFelipe Balbi #define DWC3_GTXFIFOSIZ_TXFSTADDR(n) ((n) & 0xffff0000) 327457e84b6SFelipe Balbi 328d94ea531SThinh Nguyen /* Global RX Fifo Size Register */ 329d94ea531SThinh Nguyen #define DWC31_GRXFIFOSIZ_RXFDEP(n) ((n) & 0x7fff) /* DWC_usb31 only */ 330d94ea531SThinh Nguyen #define DWC3_GRXFIFOSIZ_RXFDEP(n) ((n) & 0xffff) 331d94ea531SThinh Nguyen 33268d6a01bSFelipe Balbi /* Global Event Size Registers */ 333ff3f0789SRoger Quadros #define DWC3_GEVNTSIZ_INTMASK BIT(31) 33468d6a01bSFelipe Balbi #define DWC3_GEVNTSIZ_SIZE(n) ((n) & 0xffff) 33568d6a01bSFelipe Balbi 3364e99472bSFelipe Balbi /* Global HWPARAMS0 Register */ 3379d6173e1SThinh Nguyen #define DWC3_GHWPARAMS0_MODE(n) ((n) & 0x3) 3389d6173e1SThinh Nguyen #define DWC3_GHWPARAMS0_MODE_GADGET 0 3399d6173e1SThinh Nguyen #define DWC3_GHWPARAMS0_MODE_HOST 1 3409d6173e1SThinh Nguyen #define DWC3_GHWPARAMS0_MODE_DRD 2 3414e99472bSFelipe Balbi #define DWC3_GHWPARAMS0_MBUS_TYPE(n) (((n) >> 3) & 0x7) 3424e99472bSFelipe Balbi #define DWC3_GHWPARAMS0_SBUS_TYPE(n) (((n) >> 6) & 0x3) 3434e99472bSFelipe Balbi #define DWC3_GHWPARAMS0_MDWIDTH(n) (((n) >> 8) & 0xff) 3444e99472bSFelipe Balbi #define DWC3_GHWPARAMS0_SDWIDTH(n) (((n) >> 16) & 0xff) 3454e99472bSFelipe Balbi #define DWC3_GHWPARAMS0_AWIDTH(n) (((n) >> 24) & 0xff) 3464e99472bSFelipe Balbi 347aabb7075SFelipe Balbi /* Global HWPARAMS1 Register */ 3481d046793SPaul Zimmerman #define DWC3_GHWPARAMS1_EN_PWROPT(n) (((n) & (3 << 24)) >> 24) 349aabb7075SFelipe Balbi #define DWC3_GHWPARAMS1_EN_PWROPT_NO 0 350aabb7075SFelipe Balbi #define DWC3_GHWPARAMS1_EN_PWROPT_CLK 1 3512c61a8efSPaul Zimmerman #define DWC3_GHWPARAMS1_EN_PWROPT_HIB 2 3522c61a8efSPaul Zimmerman #define DWC3_GHWPARAMS1_PWROPT(n) ((n) << 24) 3532c61a8efSPaul Zimmerman #define DWC3_GHWPARAMS1_PWROPT_MASK DWC3_GHWPARAMS1_PWROPT(3) 35462ba09d6SThinh Nguyen #define DWC3_GHWPARAMS1_ENDBC BIT(31) 3552c61a8efSPaul Zimmerman 3560e1e5c47SPaul Zimmerman /* Global HWPARAMS3 Register */ 3570e1e5c47SPaul Zimmerman #define DWC3_GHWPARAMS3_SSPHY_IFC(n) ((n) & 3) 3580e1e5c47SPaul Zimmerman #define DWC3_GHWPARAMS3_SSPHY_IFC_DIS 0 3591f38f88aSJohn Youn #define DWC3_GHWPARAMS3_SSPHY_IFC_GEN1 1 3601f38f88aSJohn Youn #define DWC3_GHWPARAMS3_SSPHY_IFC_GEN2 2 /* DWC_usb31 only */ 3610e1e5c47SPaul Zimmerman #define DWC3_GHWPARAMS3_HSPHY_IFC(n) (((n) & (3 << 2)) >> 2) 3620e1e5c47SPaul Zimmerman #define DWC3_GHWPARAMS3_HSPHY_IFC_DIS 0 3630e1e5c47SPaul Zimmerman #define DWC3_GHWPARAMS3_HSPHY_IFC_UTMI 1 3640e1e5c47SPaul Zimmerman #define DWC3_GHWPARAMS3_HSPHY_IFC_ULPI 2 3650e1e5c47SPaul Zimmerman #define DWC3_GHWPARAMS3_HSPHY_IFC_UTMI_ULPI 3 3660e1e5c47SPaul Zimmerman #define DWC3_GHWPARAMS3_FSPHY_IFC(n) (((n) & (3 << 4)) >> 4) 3670e1e5c47SPaul Zimmerman #define DWC3_GHWPARAMS3_FSPHY_IFC_DIS 0 3680e1e5c47SPaul Zimmerman #define DWC3_GHWPARAMS3_FSPHY_IFC_ENA 1 3690e1e5c47SPaul Zimmerman 3702c61a8efSPaul Zimmerman /* Global HWPARAMS4 Register */ 3712c61a8efSPaul Zimmerman #define DWC3_GHWPARAMS4_HIBER_SCRATCHBUFS(n) (((n) & (0x0f << 13)) >> 13) 3722c61a8efSPaul Zimmerman #define DWC3_MAX_HIBER_SCRATCHBUFS 15 373aabb7075SFelipe Balbi 374946bd579SHuang Rui /* Global HWPARAMS6 Register */ 3754cff75c7SRoger Quadros #define DWC3_GHWPARAMS6_BCSUPPORT BIT(14) 3764cff75c7SRoger Quadros #define DWC3_GHWPARAMS6_OTG3SUPPORT BIT(13) 3774cff75c7SRoger Quadros #define DWC3_GHWPARAMS6_ADPSUPPORT BIT(12) 3784cff75c7SRoger Quadros #define DWC3_GHWPARAMS6_HNPSUPPORT BIT(11) 3794cff75c7SRoger Quadros #define DWC3_GHWPARAMS6_SRPSUPPORT BIT(10) 380ff3f0789SRoger Quadros #define DWC3_GHWPARAMS6_EN_FPGA BIT(7) 381946bd579SHuang Rui 3824244ba02SThinh Nguyen /* DWC_usb32 only */ 3834244ba02SThinh Nguyen #define DWC3_GHWPARAMS6_MDWIDTH(n) ((n) & (0x3 << 8)) 3844244ba02SThinh Nguyen 3854e99472bSFelipe Balbi /* Global HWPARAMS7 Register */ 3864e99472bSFelipe Balbi #define DWC3_GHWPARAMS7_RAM1_DEPTH(n) ((n) & 0xffff) 3874e99472bSFelipe Balbi #define DWC3_GHWPARAMS7_RAM2_DEPTH(n) (((n) >> 16) & 0xffff) 3884e99472bSFelipe Balbi 389ddae7979SThinh Nguyen /* Global HWPARAMS9 Register */ 390ddae7979SThinh Nguyen #define DWC3_GHWPARAMS9_DEV_TXF_FLUSH_BYPASS BIT(0) 391666f3de7SThinh Nguyen #define DWC3_GHWPARAMS9_DEV_MST BIT(1) 392ddae7979SThinh Nguyen 393db2be4e9SNikhil Badola /* Global Frame Length Adjustment Register */ 394ff3f0789SRoger Quadros #define DWC3_GFLADJ_30MHZ_SDBND_SEL BIT(7) 395db2be4e9SNikhil Badola #define DWC3_GFLADJ_30MHZ_MASK 0x3f 396596c8785SSean Anderson #define DWC3_GFLADJ_REFCLK_FLADJ_MASK GENMASK(21, 8) 397a6fc2f1bSAlexander Stein #define DWC3_GFLADJ_REFCLK_LPM_SEL BIT(23) 398596c8785SSean Anderson #define DWC3_GFLADJ_240MHZDECR GENMASK(30, 24) 399596c8785SSean Anderson #define DWC3_GFLADJ_240MHZDECR_PLS1 BIT(31) 400db2be4e9SNikhil Badola 4017bee3188SBalaji Prakash J /* Global User Control Register*/ 4027bee3188SBalaji Prakash J #define DWC3_GUCTL_REFCLKPER_MASK 0xffc00000 4037bee3188SBalaji Prakash J #define DWC3_GUCTL_REFCLKPER_SEL 22 4047bee3188SBalaji Prakash J 40506281d46SJohn Youn /* Global User Control Register 2 */ 406ff3f0789SRoger Quadros #define DWC3_GUCTL2_RST_ACTBITLATER BIT(14) 40706281d46SJohn Youn 408f580170fSYu Chen /* Global User Control Register 3 */ 409f580170fSYu Chen #define DWC3_GUCTL3_SPLITDISABLE BIT(14) 410f580170fSYu Chen 41172246da4SFelipe Balbi /* Device Configuration Register */ 412072cab8aSThinh Nguyen #define DWC3_DCFG_NUMLANES(n) (((n) & 0x3) << 30) /* DWC_usb32 only */ 413072cab8aSThinh Nguyen 41472246da4SFelipe Balbi #define DWC3_DCFG_DEVADDR(addr) ((addr) << 3) 41572246da4SFelipe Balbi #define DWC3_DCFG_DEVADDR_MASK DWC3_DCFG_DEVADDR(0x7f) 41672246da4SFelipe Balbi 41772246da4SFelipe Balbi #define DWC3_DCFG_SPEED_MASK (7 << 0) 4181f38f88aSJohn Youn #define DWC3_DCFG_SUPERSPEED_PLUS (5 << 0) /* DWC_usb31 only */ 41972246da4SFelipe Balbi #define DWC3_DCFG_SUPERSPEED (4 << 0) 42072246da4SFelipe Balbi #define DWC3_DCFG_HIGHSPEED (0 << 0) 421ff3f0789SRoger Quadros #define DWC3_DCFG_FULLSPEED BIT(0) 42272246da4SFelipe Balbi 423676e3497SFelipe Balbi #define DWC3_DCFG_NUMP_SHIFT 17 42497398612SDan Carpenter #define DWC3_DCFG_NUMP(n) (((n) >> DWC3_DCFG_NUMP_SHIFT) & 0x1f) 425676e3497SFelipe Balbi #define DWC3_DCFG_NUMP_MASK (0x1f << DWC3_DCFG_NUMP_SHIFT) 426ff3f0789SRoger Quadros #define DWC3_DCFG_LPM_CAP BIT(22) 427e66bbfb0SThinh Nguyen #define DWC3_DCFG_IGNSTRMPP BIT(23) 4282c61a8efSPaul Zimmerman 42972246da4SFelipe Balbi /* Device Control Register */ 430ff3f0789SRoger Quadros #define DWC3_DCTL_RUN_STOP BIT(31) 431ff3f0789SRoger Quadros #define DWC3_DCTL_CSFTRST BIT(30) 432ff3f0789SRoger Quadros #define DWC3_DCTL_LSFTRST BIT(29) 43372246da4SFelipe Balbi 43472246da4SFelipe Balbi #define DWC3_DCTL_HIRD_THRES_MASK (0x1f << 24) 4357e39b817SPratyush Anand #define DWC3_DCTL_HIRD_THRES(n) ((n) << 24) 43672246da4SFelipe Balbi 437ff3f0789SRoger Quadros #define DWC3_DCTL_APPL1RES BIT(23) 43872246da4SFelipe Balbi 4392c61a8efSPaul Zimmerman /* These apply for core versions 1.87a and earlier */ 4408db7ed15SFelipe Balbi #define DWC3_DCTL_TRGTULST_MASK (0x0f << 17) 4418db7ed15SFelipe Balbi #define DWC3_DCTL_TRGTULST(n) ((n) << 17) 4428db7ed15SFelipe Balbi #define DWC3_DCTL_TRGTULST_U2 (DWC3_DCTL_TRGTULST(2)) 4438db7ed15SFelipe Balbi #define DWC3_DCTL_TRGTULST_U3 (DWC3_DCTL_TRGTULST(3)) 4448db7ed15SFelipe Balbi #define DWC3_DCTL_TRGTULST_SS_DIS (DWC3_DCTL_TRGTULST(4)) 4458db7ed15SFelipe Balbi #define DWC3_DCTL_TRGTULST_RX_DET (DWC3_DCTL_TRGTULST(5)) 4468db7ed15SFelipe Balbi #define DWC3_DCTL_TRGTULST_SS_INACT (DWC3_DCTL_TRGTULST(6)) 4478db7ed15SFelipe Balbi 4482c61a8efSPaul Zimmerman /* These apply for core versions 1.94a and later */ 4492e487d28SThinh Nguyen #define DWC3_DCTL_NYET_THRES(n) (((n) & 0xf) << 20) 45080caf7d2SHuang Rui 451ff3f0789SRoger Quadros #define DWC3_DCTL_KEEP_CONNECT BIT(19) 452ff3f0789SRoger Quadros #define DWC3_DCTL_L1_HIBER_EN BIT(18) 453ff3f0789SRoger Quadros #define DWC3_DCTL_CRS BIT(17) 454ff3f0789SRoger Quadros #define DWC3_DCTL_CSS BIT(16) 4552c61a8efSPaul Zimmerman 456ff3f0789SRoger Quadros #define DWC3_DCTL_INITU2ENA BIT(12) 457ff3f0789SRoger Quadros #define DWC3_DCTL_ACCEPTU2ENA BIT(11) 458ff3f0789SRoger Quadros #define DWC3_DCTL_INITU1ENA BIT(10) 459ff3f0789SRoger Quadros #define DWC3_DCTL_ACCEPTU1ENA BIT(9) 46072246da4SFelipe Balbi #define DWC3_DCTL_TSTCTRL_MASK (0xf << 1) 46172246da4SFelipe Balbi 46272246da4SFelipe Balbi #define DWC3_DCTL_ULSTCHNGREQ_MASK (0x0f << 5) 46372246da4SFelipe Balbi #define DWC3_DCTL_ULSTCHNGREQ(n) (((n) << 5) & DWC3_DCTL_ULSTCHNGREQ_MASK) 46472246da4SFelipe Balbi 46572246da4SFelipe Balbi #define DWC3_DCTL_ULSTCHNG_NO_ACTION (DWC3_DCTL_ULSTCHNGREQ(0)) 46672246da4SFelipe Balbi #define DWC3_DCTL_ULSTCHNG_SS_DISABLED (DWC3_DCTL_ULSTCHNGREQ(4)) 46772246da4SFelipe Balbi #define DWC3_DCTL_ULSTCHNG_RX_DETECT (DWC3_DCTL_ULSTCHNGREQ(5)) 46872246da4SFelipe Balbi #define DWC3_DCTL_ULSTCHNG_SS_INACTIVE (DWC3_DCTL_ULSTCHNGREQ(6)) 46972246da4SFelipe Balbi #define DWC3_DCTL_ULSTCHNG_RECOVERY (DWC3_DCTL_ULSTCHNGREQ(8)) 47072246da4SFelipe Balbi #define DWC3_DCTL_ULSTCHNG_COMPLIANCE (DWC3_DCTL_ULSTCHNGREQ(10)) 47172246da4SFelipe Balbi #define DWC3_DCTL_ULSTCHNG_LOOPBACK (DWC3_DCTL_ULSTCHNGREQ(11)) 47272246da4SFelipe Balbi 47372246da4SFelipe Balbi /* Device Event Enable Register */ 474ff3f0789SRoger Quadros #define DWC3_DEVTEN_VNDRDEVTSTRCVEDEN BIT(12) 475ff3f0789SRoger Quadros #define DWC3_DEVTEN_EVNTOVERFLOWEN BIT(11) 476ff3f0789SRoger Quadros #define DWC3_DEVTEN_CMDCMPLTEN BIT(10) 477ff3f0789SRoger Quadros #define DWC3_DEVTEN_ERRTICERREN BIT(9) 478ff3f0789SRoger Quadros #define DWC3_DEVTEN_SOFEN BIT(7) 4796f26ebb7SJack Pham #define DWC3_DEVTEN_U3L2L1SUSPEN BIT(6) 480ff3f0789SRoger Quadros #define DWC3_DEVTEN_HIBERNATIONREQEVTEN BIT(5) 481ff3f0789SRoger Quadros #define DWC3_DEVTEN_WKUPEVTEN BIT(4) 482ff3f0789SRoger Quadros #define DWC3_DEVTEN_ULSTCNGEN BIT(3) 483ff3f0789SRoger Quadros #define DWC3_DEVTEN_CONNECTDONEEN BIT(2) 484ff3f0789SRoger Quadros #define DWC3_DEVTEN_USBRSTEN BIT(1) 485ff3f0789SRoger Quadros #define DWC3_DEVTEN_DISCONNEVTEN BIT(0) 48672246da4SFelipe Balbi 487f551037cSThinh Nguyen #define DWC3_DSTS_CONNLANES(n) (((n) >> 30) & 0x3) /* DWC_usb32 only */ 488f551037cSThinh Nguyen 48972246da4SFelipe Balbi /* Device Status Register */ 490ff3f0789SRoger Quadros #define DWC3_DSTS_DCNRD BIT(29) 4912c61a8efSPaul Zimmerman 4922c61a8efSPaul Zimmerman /* This applies for core versions 1.87a and earlier */ 493ff3f0789SRoger Quadros #define DWC3_DSTS_PWRUPREQ BIT(24) 4942c61a8efSPaul Zimmerman 4952c61a8efSPaul Zimmerman /* These apply for core versions 1.94a and later */ 496ff3f0789SRoger Quadros #define DWC3_DSTS_RSS BIT(25) 497ff3f0789SRoger Quadros #define DWC3_DSTS_SSS BIT(24) 4982c61a8efSPaul Zimmerman 499ff3f0789SRoger Quadros #define DWC3_DSTS_COREIDLE BIT(23) 500ff3f0789SRoger Quadros #define DWC3_DSTS_DEVCTRLHLT BIT(22) 50172246da4SFelipe Balbi 50272246da4SFelipe Balbi #define DWC3_DSTS_USBLNKST_MASK (0x0f << 18) 50372246da4SFelipe Balbi #define DWC3_DSTS_USBLNKST(n) (((n) & DWC3_DSTS_USBLNKST_MASK) >> 18) 50472246da4SFelipe Balbi 505ff3f0789SRoger Quadros #define DWC3_DSTS_RXFIFOEMPTY BIT(17) 50672246da4SFelipe Balbi 507d05b8182SPratyush Anand #define DWC3_DSTS_SOFFN_MASK (0x3fff << 3) 50872246da4SFelipe Balbi #define DWC3_DSTS_SOFFN(n) (((n) & DWC3_DSTS_SOFFN_MASK) >> 3) 50972246da4SFelipe Balbi 51072246da4SFelipe Balbi #define DWC3_DSTS_CONNECTSPD (7 << 0) 51172246da4SFelipe Balbi 5121f38f88aSJohn Youn #define DWC3_DSTS_SUPERSPEED_PLUS (5 << 0) /* DWC_usb31 only */ 51372246da4SFelipe Balbi #define DWC3_DSTS_SUPERSPEED (4 << 0) 51472246da4SFelipe Balbi #define DWC3_DSTS_HIGHSPEED (0 << 0) 515ff3f0789SRoger Quadros #define DWC3_DSTS_FULLSPEED BIT(0) 51672246da4SFelipe Balbi 51772246da4SFelipe Balbi /* Device Generic Command Register */ 51872246da4SFelipe Balbi #define DWC3_DGCMD_SET_LMP 0x01 51972246da4SFelipe Balbi #define DWC3_DGCMD_SET_PERIODIC_PAR 0x02 52072246da4SFelipe Balbi #define DWC3_DGCMD_XMIT_FUNCTION 0x03 5212c61a8efSPaul Zimmerman 5222c61a8efSPaul Zimmerman /* These apply for core versions 1.94a and later */ 5232c61a8efSPaul Zimmerman #define DWC3_DGCMD_SET_SCRATCHPAD_ADDR_LO 0x04 5242c61a8efSPaul Zimmerman #define DWC3_DGCMD_SET_SCRATCHPAD_ADDR_HI 0x05 5252c61a8efSPaul Zimmerman 52672246da4SFelipe Balbi #define DWC3_DGCMD_SELECTED_FIFO_FLUSH 0x09 52772246da4SFelipe Balbi #define DWC3_DGCMD_ALL_FIFO_FLUSH 0x0a 52872246da4SFelipe Balbi #define DWC3_DGCMD_SET_ENDPOINT_NRDY 0x0c 529140ca4cfSThinh Nguyen #define DWC3_DGCMD_SET_ENDPOINT_PRIME 0x0d 53072246da4SFelipe Balbi #define DWC3_DGCMD_RUN_SOC_BUS_LOOPBACK 0x10 53192c08a84SElson Roy Serrao #define DWC3_DGCMD_DEV_NOTIFICATION 0x07 53272246da4SFelipe Balbi 533459e210cSSubbaraya Sundeep Bhatta #define DWC3_DGCMD_STATUS(n) (((n) >> 12) & 0x0F) 534ff3f0789SRoger Quadros #define DWC3_DGCMD_CMDACT BIT(10) 535ff3f0789SRoger Quadros #define DWC3_DGCMD_CMDIOC BIT(8) 5362c61a8efSPaul Zimmerman 5372c61a8efSPaul Zimmerman /* Device Generic Command Parameter Register */ 538ff3f0789SRoger Quadros #define DWC3_DGCMDPAR_FORCE_LINKPM_ACCEPT BIT(0) 5392c61a8efSPaul Zimmerman #define DWC3_DGCMDPAR_FIFO_NUM(n) ((n) << 0) 5402c61a8efSPaul Zimmerman #define DWC3_DGCMDPAR_RX_FIFO (0 << 5) 541ff3f0789SRoger Quadros #define DWC3_DGCMDPAR_TX_FIFO BIT(5) 5422c61a8efSPaul Zimmerman #define DWC3_DGCMDPAR_LOOPBACK_DIS (0 << 0) 543ff3f0789SRoger Quadros #define DWC3_DGCMDPAR_LOOPBACK_ENA BIT(0) 54492c08a84SElson Roy Serrao #define DWC3_DGCMDPAR_DN_FUNC_WAKE BIT(0) 54592c08a84SElson Roy Serrao #define DWC3_DGCMDPAR_INTF_SEL(n) ((n) << 4) 546b09bb642SFelipe Balbi 54772246da4SFelipe Balbi /* Device Endpoint Command Register */ 54872246da4SFelipe Balbi #define DWC3_DEPCMD_PARAM_SHIFT 16 5491d046793SPaul Zimmerman #define DWC3_DEPCMD_PARAM(x) ((x) << DWC3_DEPCMD_PARAM_SHIFT) 5501d046793SPaul Zimmerman #define DWC3_DEPCMD_GET_RSC_IDX(x) (((x) >> DWC3_DEPCMD_PARAM_SHIFT) & 0x7f) 551459e210cSSubbaraya Sundeep Bhatta #define DWC3_DEPCMD_STATUS(x) (((x) >> 12) & 0x0F) 552ff3f0789SRoger Quadros #define DWC3_DEPCMD_HIPRI_FORCERM BIT(11) 553ff3f0789SRoger Quadros #define DWC3_DEPCMD_CLEARPENDIN BIT(11) 554ff3f0789SRoger Quadros #define DWC3_DEPCMD_CMDACT BIT(10) 555ff3f0789SRoger Quadros #define DWC3_DEPCMD_CMDIOC BIT(8) 55672246da4SFelipe Balbi 55772246da4SFelipe Balbi #define DWC3_DEPCMD_DEPSTARTCFG (0x09 << 0) 55872246da4SFelipe Balbi #define DWC3_DEPCMD_ENDTRANSFER (0x08 << 0) 55972246da4SFelipe Balbi #define DWC3_DEPCMD_UPDATETRANSFER (0x07 << 0) 56072246da4SFelipe Balbi #define DWC3_DEPCMD_STARTTRANSFER (0x06 << 0) 56172246da4SFelipe Balbi #define DWC3_DEPCMD_CLEARSTALL (0x05 << 0) 56272246da4SFelipe Balbi #define DWC3_DEPCMD_SETSTALL (0x04 << 0) 5632c61a8efSPaul Zimmerman /* This applies for core versions 1.90a and earlier */ 56472246da4SFelipe Balbi #define DWC3_DEPCMD_GETSEQNUMBER (0x03 << 0) 5652c61a8efSPaul Zimmerman /* This applies for core versions 1.94a and later */ 5662c61a8efSPaul Zimmerman #define DWC3_DEPCMD_GETEPSTATE (0x03 << 0) 56772246da4SFelipe Balbi #define DWC3_DEPCMD_SETTRANSFRESOURCE (0x02 << 0) 56872246da4SFelipe Balbi #define DWC3_DEPCMD_SETEPCONFIG (0x01 << 0) 56972246da4SFelipe Balbi 5705999914fSFelipe Balbi #define DWC3_DEPCMD_CMD(x) ((x) & 0xf) 5715999914fSFelipe Balbi 57272246da4SFelipe Balbi /* The EP number goes 0..31 so ep0 is always out and ep1 is always in */ 573ff3f0789SRoger Quadros #define DWC3_DALEPENA_EP(n) BIT(n) 57472246da4SFelipe Balbi 575666f3de7SThinh Nguyen /* DWC_usb32 DCFG1 config */ 576666f3de7SThinh Nguyen #define DWC3_DCFG1_DIS_MST_ENH BIT(1) 577666f3de7SThinh Nguyen 57872246da4SFelipe Balbi #define DWC3_DEPCMD_TYPE_CONTROL 0 57972246da4SFelipe Balbi #define DWC3_DEPCMD_TYPE_ISOC 1 58072246da4SFelipe Balbi #define DWC3_DEPCMD_TYPE_BULK 2 58172246da4SFelipe Balbi #define DWC3_DEPCMD_TYPE_INTR 3 58272246da4SFelipe Balbi 583cf40b86bSJohn Youn #define DWC3_DEV_IMOD_COUNT_SHIFT 16 584cf40b86bSJohn Youn #define DWC3_DEV_IMOD_COUNT_MASK (0xffff << 16) 585cf40b86bSJohn Youn #define DWC3_DEV_IMOD_INTERVAL_SHIFT 0 586cf40b86bSJohn Youn #define DWC3_DEV_IMOD_INTERVAL_MASK (0xffff << 0) 587cf40b86bSJohn Youn 5884cff75c7SRoger Quadros /* OTG Configuration Register */ 5894cff75c7SRoger Quadros #define DWC3_OCFG_DISPWRCUTTOFF BIT(5) 5904cff75c7SRoger Quadros #define DWC3_OCFG_HIBDISMASK BIT(4) 5914cff75c7SRoger Quadros #define DWC3_OCFG_SFTRSTMASK BIT(3) 5924cff75c7SRoger Quadros #define DWC3_OCFG_OTGVERSION BIT(2) 5934cff75c7SRoger Quadros #define DWC3_OCFG_HNPCAP BIT(1) 5944cff75c7SRoger Quadros #define DWC3_OCFG_SRPCAP BIT(0) 5954cff75c7SRoger Quadros 5964cff75c7SRoger Quadros /* OTG CTL Register */ 5974cff75c7SRoger Quadros #define DWC3_OCTL_OTG3GOERR BIT(7) 5984cff75c7SRoger Quadros #define DWC3_OCTL_PERIMODE BIT(6) 5994cff75c7SRoger Quadros #define DWC3_OCTL_PRTPWRCTL BIT(5) 6004cff75c7SRoger Quadros #define DWC3_OCTL_HNPREQ BIT(4) 6014cff75c7SRoger Quadros #define DWC3_OCTL_SESREQ BIT(3) 6024cff75c7SRoger Quadros #define DWC3_OCTL_TERMSELIDPULSE BIT(2) 6034cff75c7SRoger Quadros #define DWC3_OCTL_DEVSETHNPEN BIT(1) 6044cff75c7SRoger Quadros #define DWC3_OCTL_HSTSETHNPEN BIT(0) 6054cff75c7SRoger Quadros 6064cff75c7SRoger Quadros /* OTG Event Register */ 6074cff75c7SRoger Quadros #define DWC3_OEVT_DEVICEMODE BIT(31) 6084cff75c7SRoger Quadros #define DWC3_OEVT_XHCIRUNSTPSET BIT(27) 6094cff75c7SRoger Quadros #define DWC3_OEVT_DEVRUNSTPSET BIT(26) 6104cff75c7SRoger Quadros #define DWC3_OEVT_HIBENTRY BIT(25) 6114cff75c7SRoger Quadros #define DWC3_OEVT_CONIDSTSCHNG BIT(24) 6124cff75c7SRoger Quadros #define DWC3_OEVT_HRRCONFNOTIF BIT(23) 6134cff75c7SRoger Quadros #define DWC3_OEVT_HRRINITNOTIF BIT(22) 6144cff75c7SRoger Quadros #define DWC3_OEVT_ADEVIDLE BIT(21) 6154cff75c7SRoger Quadros #define DWC3_OEVT_ADEVBHOSTEND BIT(20) 6164cff75c7SRoger Quadros #define DWC3_OEVT_ADEVHOST BIT(19) 6174cff75c7SRoger Quadros #define DWC3_OEVT_ADEVHNPCHNG BIT(18) 6184cff75c7SRoger Quadros #define DWC3_OEVT_ADEVSRPDET BIT(17) 6194cff75c7SRoger Quadros #define DWC3_OEVT_ADEVSESSENDDET BIT(16) 6204cff75c7SRoger Quadros #define DWC3_OEVT_BDEVBHOSTEND BIT(11) 6214cff75c7SRoger Quadros #define DWC3_OEVT_BDEVHNPCHNG BIT(10) 6224cff75c7SRoger Quadros #define DWC3_OEVT_BDEVSESSVLDDET BIT(9) 6234cff75c7SRoger Quadros #define DWC3_OEVT_BDEVVBUSCHNG BIT(8) 6244cff75c7SRoger Quadros #define DWC3_OEVT_BSESSVLD BIT(3) 6254cff75c7SRoger Quadros #define DWC3_OEVT_HSTNEGSTS BIT(2) 6264cff75c7SRoger Quadros #define DWC3_OEVT_SESREQSTS BIT(1) 6274cff75c7SRoger Quadros #define DWC3_OEVT_ERROR BIT(0) 6284cff75c7SRoger Quadros 6294cff75c7SRoger Quadros /* OTG Event Enable Register */ 6304cff75c7SRoger Quadros #define DWC3_OEVTEN_XHCIRUNSTPSETEN BIT(27) 6314cff75c7SRoger Quadros #define DWC3_OEVTEN_DEVRUNSTPSETEN BIT(26) 6324cff75c7SRoger Quadros #define DWC3_OEVTEN_HIBENTRYEN BIT(25) 6334cff75c7SRoger Quadros #define DWC3_OEVTEN_CONIDSTSCHNGEN BIT(24) 6344cff75c7SRoger Quadros #define DWC3_OEVTEN_HRRCONFNOTIFEN BIT(23) 6354cff75c7SRoger Quadros #define DWC3_OEVTEN_HRRINITNOTIFEN BIT(22) 6364cff75c7SRoger Quadros #define DWC3_OEVTEN_ADEVIDLEEN BIT(21) 6374cff75c7SRoger Quadros #define DWC3_OEVTEN_ADEVBHOSTENDEN BIT(20) 6384cff75c7SRoger Quadros #define DWC3_OEVTEN_ADEVHOSTEN BIT(19) 6394cff75c7SRoger Quadros #define DWC3_OEVTEN_ADEVHNPCHNGEN BIT(18) 6404cff75c7SRoger Quadros #define DWC3_OEVTEN_ADEVSRPDETEN BIT(17) 6414cff75c7SRoger Quadros #define DWC3_OEVTEN_ADEVSESSENDDETEN BIT(16) 6424cff75c7SRoger Quadros #define DWC3_OEVTEN_BDEVBHOSTENDEN BIT(11) 6434cff75c7SRoger Quadros #define DWC3_OEVTEN_BDEVHNPCHNGEN BIT(10) 6444cff75c7SRoger Quadros #define DWC3_OEVTEN_BDEVSESSVLDDETEN BIT(9) 6454cff75c7SRoger Quadros #define DWC3_OEVTEN_BDEVVBUSCHNGEN BIT(8) 6464cff75c7SRoger Quadros 6474cff75c7SRoger Quadros /* OTG Status Register */ 6484cff75c7SRoger Quadros #define DWC3_OSTS_DEVRUNSTP BIT(13) 6494cff75c7SRoger Quadros #define DWC3_OSTS_XHCIRUNSTP BIT(12) 6504cff75c7SRoger Quadros #define DWC3_OSTS_PERIPHERALSTATE BIT(4) 6514cff75c7SRoger Quadros #define DWC3_OSTS_XHCIPRTPOWER BIT(3) 6524cff75c7SRoger Quadros #define DWC3_OSTS_BSESVLD BIT(2) 6534cff75c7SRoger Quadros #define DWC3_OSTS_VBUSVLD BIT(1) 6544cff75c7SRoger Quadros #define DWC3_OSTS_CONIDSTS BIT(0) 6554cff75c7SRoger Quadros 65672246da4SFelipe Balbi /* Structures */ 65772246da4SFelipe Balbi 658f6bafc6aSFelipe Balbi struct dwc3_trb; 65972246da4SFelipe Balbi 66072246da4SFelipe Balbi /** 66172246da4SFelipe Balbi * struct dwc3_event_buffer - Software event buffer representation 66272246da4SFelipe Balbi * @buf: _THE_ buffer 663d9fa4c63SJohn Youn * @cache: The buffer cache used in the threaded interrupt 66472246da4SFelipe Balbi * @length: size of this buffer 665abed4118SFelipe Balbi * @lpos: event offset 66660d04bbeSFelipe Balbi * @count: cache of last read event count register 667abed4118SFelipe Balbi * @flags: flags related to this event buffer 66872246da4SFelipe Balbi * @dma: dma_addr_t 66972246da4SFelipe Balbi * @dwc: pointer to DWC controller 67072246da4SFelipe Balbi */ 67172246da4SFelipe Balbi struct dwc3_event_buffer { 67272246da4SFelipe Balbi void *buf; 673d9fa4c63SJohn Youn void *cache; 67487b923a2SFelipe Balbi unsigned int length; 67572246da4SFelipe Balbi unsigned int lpos; 67660d04bbeSFelipe Balbi unsigned int count; 677abed4118SFelipe Balbi unsigned int flags; 678abed4118SFelipe Balbi 679abed4118SFelipe Balbi #define DWC3_EVENT_PENDING BIT(0) 68072246da4SFelipe Balbi 68172246da4SFelipe Balbi dma_addr_t dma; 68272246da4SFelipe Balbi 68372246da4SFelipe Balbi struct dwc3 *dwc; 68472246da4SFelipe Balbi }; 68572246da4SFelipe Balbi 686ff3f0789SRoger Quadros #define DWC3_EP_FLAG_STALLED BIT(0) 687ff3f0789SRoger Quadros #define DWC3_EP_FLAG_WEDGED BIT(1) 68872246da4SFelipe Balbi 68972246da4SFelipe Balbi #define DWC3_EP_DIRECTION_TX true 69072246da4SFelipe Balbi #define DWC3_EP_DIRECTION_RX false 69172246da4SFelipe Balbi 6928495036eSFelipe Balbi #define DWC3_TRB_NUM 256 69372246da4SFelipe Balbi 69472246da4SFelipe Balbi /** 69572246da4SFelipe Balbi * struct dwc3_ep - device side endpoint representation 69672246da4SFelipe Balbi * @endpoint: usb endpoint 697d5443bbfSFelipe Balbi * @cancelled_list: list of cancelled requests for this endpoint 698aa3342c8SFelipe Balbi * @pending_list: list of pending requests for this endpoint 699aa3342c8SFelipe Balbi * @started_list: list of started requests on this endpoint 7002eb88016SFelipe Balbi * @regs: pointer to first endpoint register 70172246da4SFelipe Balbi * @trb_pool: array of transaction buffers 70272246da4SFelipe Balbi * @trb_pool_dma: dma address of @trb_pool 70353fd8818SFelipe Balbi * @trb_enqueue: enqueue 'pointer' into TRB array 70453fd8818SFelipe Balbi * @trb_dequeue: dequeue 'pointer' into TRB array 70572246da4SFelipe Balbi * @dwc: pointer to DWC controller 7064cfcf876SPaul Zimmerman * @saved_state: ep state saved during hibernation 70772246da4SFelipe Balbi * @flags: endpoint flags (wedged, stalled, ...) 70872246da4SFelipe Balbi * @number: endpoint number (1 - 15) 70972246da4SFelipe Balbi * @type: set to bmAttributes & USB_ENDPOINT_XFERTYPE_MASK 710b4996a86SFelipe Balbi * @resource_index: Resource transfer index 711502a37b9SFelipe Balbi * @frame_number: set to the frame number we want this transfer to start (ISOC) 712c75f52fbSHuang Rui * @interval: the interval on which the ISOC transfer is started 71372246da4SFelipe Balbi * @name: a human readable name e.g. ep1out-bulk 71472246da4SFelipe Balbi * @direction: true for TX, false for RX 715879631aaSFelipe Balbi * @stream_capable: true when streams are enabled 716d92021f6SThinh Nguyen * @combo_num: the test combination BIT[15:14] of the frame number to test 717d92021f6SThinh Nguyen * isochronous START TRANSFER command failure workaround 718d92021f6SThinh Nguyen * @start_cmd_status: the status of testing START TRANSFER command with 719d92021f6SThinh Nguyen * combo_num = 'b00 72072246da4SFelipe Balbi */ 72172246da4SFelipe Balbi struct dwc3_ep { 72272246da4SFelipe Balbi struct usb_ep endpoint; 723d5443bbfSFelipe Balbi struct list_head cancelled_list; 724aa3342c8SFelipe Balbi struct list_head pending_list; 725aa3342c8SFelipe Balbi struct list_head started_list; 72672246da4SFelipe Balbi 7272eb88016SFelipe Balbi void __iomem *regs; 7282eb88016SFelipe Balbi 729f6bafc6aSFelipe Balbi struct dwc3_trb *trb_pool; 73072246da4SFelipe Balbi dma_addr_t trb_pool_dma; 73172246da4SFelipe Balbi struct dwc3 *dwc; 73272246da4SFelipe Balbi 7334cfcf876SPaul Zimmerman u32 saved_state; 73487b923a2SFelipe Balbi unsigned int flags; 735ff3f0789SRoger Quadros #define DWC3_EP_ENABLED BIT(0) 736ff3f0789SRoger Quadros #define DWC3_EP_STALL BIT(1) 737ff3f0789SRoger Quadros #define DWC3_EP_WEDGE BIT(2) 7385f2e7975SFelipe Balbi #define DWC3_EP_TRANSFER_STARTED BIT(3) 739c58d8bfcSThinh Nguyen #define DWC3_EP_END_TRANSFER_PENDING BIT(4) 740ff3f0789SRoger Quadros #define DWC3_EP_PENDING_REQUEST BIT(5) 741da10bcddSThinh Nguyen #define DWC3_EP_DELAY_START BIT(6) 742e0d19563SThinh Nguyen #define DWC3_EP_WAIT_TRANSFER_COMPLETE BIT(7) 743140ca4cfSThinh Nguyen #define DWC3_EP_IGNORE_NEXT_NOSTREAM BIT(8) 744140ca4cfSThinh Nguyen #define DWC3_EP_FORCE_RESTART_STREAM BIT(9) 745140ca4cfSThinh Nguyen #define DWC3_EP_FIRST_STREAM_PRIMED BIT(10) 746d97c78a1SThinh Nguyen #define DWC3_EP_PENDING_CLEAR_STALL BIT(11) 747876a75cbSJack Pham #define DWC3_EP_TXFIFO_RESIZED BIT(12) 748e4cf6580SThinh Nguyen #define DWC3_EP_DELAY_STOP BIT(13) 74972246da4SFelipe Balbi 750984f66a6SFelipe Balbi /* This last one is specific to EP0 */ 751ff3f0789SRoger Quadros #define DWC3_EP0_DIR_IN BIT(31) 752984f66a6SFelipe Balbi 753c28f8259SFelipe Balbi /* 754c28f8259SFelipe Balbi * IMPORTANT: we *know* we have 256 TRBs in our @trb_pool, so we will 755c28f8259SFelipe Balbi * use a u8 type here. If anybody decides to increase number of TRBs to 756c28f8259SFelipe Balbi * anything larger than 256 - I can't see why people would want to do 757c28f8259SFelipe Balbi * this though - then this type needs to be changed. 758c28f8259SFelipe Balbi * 759c28f8259SFelipe Balbi * By using u8 types we ensure that our % operator when incrementing 760c28f8259SFelipe Balbi * enqueue and dequeue get optimized away by the compiler. 761c28f8259SFelipe Balbi */ 762c28f8259SFelipe Balbi u8 trb_enqueue; 763c28f8259SFelipe Balbi u8 trb_dequeue; 764c28f8259SFelipe Balbi 76572246da4SFelipe Balbi u8 number; 76672246da4SFelipe Balbi u8 type; 767b4996a86SFelipe Balbi u8 resource_index; 768502a37b9SFelipe Balbi u32 frame_number; 76972246da4SFelipe Balbi u32 interval; 77072246da4SFelipe Balbi 77172246da4SFelipe Balbi char name[20]; 77272246da4SFelipe Balbi 77372246da4SFelipe Balbi unsigned direction:1; 774879631aaSFelipe Balbi unsigned stream_capable:1; 775d92021f6SThinh Nguyen 776d92021f6SThinh Nguyen /* For isochronous START TRANSFER workaround only */ 777d92021f6SThinh Nguyen u8 combo_num; 778d92021f6SThinh Nguyen int start_cmd_status; 77972246da4SFelipe Balbi }; 78072246da4SFelipe Balbi 78172246da4SFelipe Balbi enum dwc3_phy { 78272246da4SFelipe Balbi DWC3_PHY_UNKNOWN = 0, 78372246da4SFelipe Balbi DWC3_PHY_USB3, 78472246da4SFelipe Balbi DWC3_PHY_USB2, 78572246da4SFelipe Balbi }; 78672246da4SFelipe Balbi 787b53c772dSFelipe Balbi enum dwc3_ep0_next { 788b53c772dSFelipe Balbi DWC3_EP0_UNKNOWN = 0, 789b53c772dSFelipe Balbi DWC3_EP0_COMPLETE, 790b53c772dSFelipe Balbi DWC3_EP0_NRDY_DATA, 791b53c772dSFelipe Balbi DWC3_EP0_NRDY_STATUS, 792b53c772dSFelipe Balbi }; 793b53c772dSFelipe Balbi 79472246da4SFelipe Balbi enum dwc3_ep0_state { 79572246da4SFelipe Balbi EP0_UNCONNECTED = 0, 796c7fcdeb2SFelipe Balbi EP0_SETUP_PHASE, 797c7fcdeb2SFelipe Balbi EP0_DATA_PHASE, 798c7fcdeb2SFelipe Balbi EP0_STATUS_PHASE, 79972246da4SFelipe Balbi }; 80072246da4SFelipe Balbi 80172246da4SFelipe Balbi enum dwc3_link_state { 80272246da4SFelipe Balbi /* In SuperSpeed */ 80372246da4SFelipe Balbi DWC3_LINK_STATE_U0 = 0x00, /* in HS, means ON */ 80472246da4SFelipe Balbi DWC3_LINK_STATE_U1 = 0x01, 80572246da4SFelipe Balbi DWC3_LINK_STATE_U2 = 0x02, /* in HS, means SLEEP */ 80672246da4SFelipe Balbi DWC3_LINK_STATE_U3 = 0x03, /* in HS, means SUSPEND */ 80772246da4SFelipe Balbi DWC3_LINK_STATE_SS_DIS = 0x04, 80872246da4SFelipe Balbi DWC3_LINK_STATE_RX_DET = 0x05, /* in HS, means Early Suspend */ 80972246da4SFelipe Balbi DWC3_LINK_STATE_SS_INACT = 0x06, 81072246da4SFelipe Balbi DWC3_LINK_STATE_POLL = 0x07, 81172246da4SFelipe Balbi DWC3_LINK_STATE_RECOV = 0x08, 81272246da4SFelipe Balbi DWC3_LINK_STATE_HRESET = 0x09, 81372246da4SFelipe Balbi DWC3_LINK_STATE_CMPLY = 0x0a, 81472246da4SFelipe Balbi DWC3_LINK_STATE_LPBK = 0x0b, 8152c61a8efSPaul Zimmerman DWC3_LINK_STATE_RESET = 0x0e, 8162c61a8efSPaul Zimmerman DWC3_LINK_STATE_RESUME = 0x0f, 81772246da4SFelipe Balbi DWC3_LINK_STATE_MASK = 0x0f, 81872246da4SFelipe Balbi }; 81972246da4SFelipe Balbi 820f6bafc6aSFelipe Balbi /* TRB Length, PCM and Status */ 821f6bafc6aSFelipe Balbi #define DWC3_TRB_SIZE_MASK (0x00ffffff) 822f6bafc6aSFelipe Balbi #define DWC3_TRB_SIZE_LENGTH(n) ((n) & DWC3_TRB_SIZE_MASK) 823f6bafc6aSFelipe Balbi #define DWC3_TRB_SIZE_PCM1(n) (((n) & 0x03) << 24) 824389f2828SPratyush Anand #define DWC3_TRB_SIZE_TRBSTS(n) (((n) & (0x0f << 28)) >> 28) 82572246da4SFelipe Balbi 826f6bafc6aSFelipe Balbi #define DWC3_TRBSTS_OK 0 827f6bafc6aSFelipe Balbi #define DWC3_TRBSTS_MISSED_ISOC 1 828f6bafc6aSFelipe Balbi #define DWC3_TRBSTS_SETUP_PENDING 2 8292c61a8efSPaul Zimmerman #define DWC3_TRB_STS_XFER_IN_PROG 4 83072246da4SFelipe Balbi 831f6bafc6aSFelipe Balbi /* TRB Control */ 832ff3f0789SRoger Quadros #define DWC3_TRB_CTRL_HWO BIT(0) 833ff3f0789SRoger Quadros #define DWC3_TRB_CTRL_LST BIT(1) 834ff3f0789SRoger Quadros #define DWC3_TRB_CTRL_CHN BIT(2) 835ff3f0789SRoger Quadros #define DWC3_TRB_CTRL_CSP BIT(3) 836f6bafc6aSFelipe Balbi #define DWC3_TRB_CTRL_TRBCTL(n) (((n) & 0x3f) << 4) 837ff3f0789SRoger Quadros #define DWC3_TRB_CTRL_ISP_IMI BIT(10) 838ff3f0789SRoger Quadros #define DWC3_TRB_CTRL_IOC BIT(11) 839f6bafc6aSFelipe Balbi #define DWC3_TRB_CTRL_SID_SOFN(n) (((n) & 0xffff) << 14) 8406abfa0f5SThinh Nguyen #define DWC3_TRB_CTRL_GET_SID_SOFN(n) (((n) & (0xffff << 14)) >> 14) 841f6bafc6aSFelipe Balbi 842b058f3e8SFelipe Balbi #define DWC3_TRBCTL_TYPE(n) ((n) & (0x3f << 4)) 843f6bafc6aSFelipe Balbi #define DWC3_TRBCTL_NORMAL DWC3_TRB_CTRL_TRBCTL(1) 844f6bafc6aSFelipe Balbi #define DWC3_TRBCTL_CONTROL_SETUP DWC3_TRB_CTRL_TRBCTL(2) 845f6bafc6aSFelipe Balbi #define DWC3_TRBCTL_CONTROL_STATUS2 DWC3_TRB_CTRL_TRBCTL(3) 846f6bafc6aSFelipe Balbi #define DWC3_TRBCTL_CONTROL_STATUS3 DWC3_TRB_CTRL_TRBCTL(4) 847f6bafc6aSFelipe Balbi #define DWC3_TRBCTL_CONTROL_DATA DWC3_TRB_CTRL_TRBCTL(5) 848f6bafc6aSFelipe Balbi #define DWC3_TRBCTL_ISOCHRONOUS_FIRST DWC3_TRB_CTRL_TRBCTL(6) 849f6bafc6aSFelipe Balbi #define DWC3_TRBCTL_ISOCHRONOUS DWC3_TRB_CTRL_TRBCTL(7) 850f6bafc6aSFelipe Balbi #define DWC3_TRBCTL_LINK_TRB DWC3_TRB_CTRL_TRBCTL(8) 85172246da4SFelipe Balbi 85272246da4SFelipe Balbi /** 853f6bafc6aSFelipe Balbi * struct dwc3_trb - transfer request block (hw format) 85472246da4SFelipe Balbi * @bpl: DW0-3 85572246da4SFelipe Balbi * @bph: DW4-7 85672246da4SFelipe Balbi * @size: DW8-B 857bfad65eeSFelipe Balbi * @ctrl: DWC-F 85872246da4SFelipe Balbi */ 859f6bafc6aSFelipe Balbi struct dwc3_trb { 860f6bafc6aSFelipe Balbi u32 bpl; 861f6bafc6aSFelipe Balbi u32 bph; 862f6bafc6aSFelipe Balbi u32 size; 863f6bafc6aSFelipe Balbi u32 ctrl; 86472246da4SFelipe Balbi } __packed; 86572246da4SFelipe Balbi 86672246da4SFelipe Balbi /** 867bfad65eeSFelipe Balbi * struct dwc3_hwparams - copy of HWPARAMS registers 868bfad65eeSFelipe Balbi * @hwparams0: GHWPARAMS0 869bfad65eeSFelipe Balbi * @hwparams1: GHWPARAMS1 870bfad65eeSFelipe Balbi * @hwparams2: GHWPARAMS2 871bfad65eeSFelipe Balbi * @hwparams3: GHWPARAMS3 872bfad65eeSFelipe Balbi * @hwparams4: GHWPARAMS4 873bfad65eeSFelipe Balbi * @hwparams5: GHWPARAMS5 874bfad65eeSFelipe Balbi * @hwparams6: GHWPARAMS6 875bfad65eeSFelipe Balbi * @hwparams7: GHWPARAMS7 876bfad65eeSFelipe Balbi * @hwparams8: GHWPARAMS8 8779cbc7eb1SThinh Nguyen * @hwparams9: GHWPARAMS9 878a3299499SFelipe Balbi */ 879a3299499SFelipe Balbi struct dwc3_hwparams { 880a3299499SFelipe Balbi u32 hwparams0; 881a3299499SFelipe Balbi u32 hwparams1; 882a3299499SFelipe Balbi u32 hwparams2; 883a3299499SFelipe Balbi u32 hwparams3; 884a3299499SFelipe Balbi u32 hwparams4; 885a3299499SFelipe Balbi u32 hwparams5; 886a3299499SFelipe Balbi u32 hwparams6; 887a3299499SFelipe Balbi u32 hwparams7; 888a3299499SFelipe Balbi u32 hwparams8; 88916710380SThinh Nguyen u32 hwparams9; 890a3299499SFelipe Balbi }; 891a3299499SFelipe Balbi 8920949e99bSFelipe Balbi /* HWPARAMS0 */ 8930949e99bSFelipe Balbi #define DWC3_MODE(n) ((n) & 0x7) 8940949e99bSFelipe Balbi 8950949e99bSFelipe Balbi /* HWPARAMS1 */ 8969f622b2aSFelipe Balbi #define DWC3_NUM_INT(n) (((n) & (0x3f << 15)) >> 15) 8979f622b2aSFelipe Balbi 898789451f6SFelipe Balbi /* HWPARAMS3 */ 899789451f6SFelipe Balbi #define DWC3_NUM_IN_EPS_MASK (0x1f << 18) 900789451f6SFelipe Balbi #define DWC3_NUM_EPS_MASK (0x3f << 12) 901789451f6SFelipe Balbi #define DWC3_NUM_EPS(p) (((p)->hwparams3 & \ 902789451f6SFelipe Balbi (DWC3_NUM_EPS_MASK)) >> 12) 903789451f6SFelipe Balbi #define DWC3_NUM_IN_EPS(p) (((p)->hwparams3 & \ 904789451f6SFelipe Balbi (DWC3_NUM_IN_EPS_MASK)) >> 18) 905789451f6SFelipe Balbi 906457e84b6SFelipe Balbi /* HWPARAMS7 */ 907457e84b6SFelipe Balbi #define DWC3_RAM1_DEPTH(n) ((n) & 0xffff) 908457e84b6SFelipe Balbi 909666f3de7SThinh Nguyen /* HWPARAMS9 */ 910666f3de7SThinh Nguyen #define DWC3_MST_CAPABLE(p) (!!((p)->hwparams9 & \ 911666f3de7SThinh Nguyen DWC3_GHWPARAMS9_DEV_MST)) 912666f3de7SThinh Nguyen 9135ef68c56SFelipe Balbi /** 9145ef68c56SFelipe Balbi * struct dwc3_request - representation of a transfer request 9155ef68c56SFelipe Balbi * @request: struct usb_request to be transferred 9165ef68c56SFelipe Balbi * @list: a list_head used for request queueing 9175ef68c56SFelipe Balbi * @dep: struct dwc3_ep owning this request 9180b3e4af3SFelipe Balbi * @sg: pointer to first incomplete sg 919a31e63b6SAnurag Kumar Vulisha * @start_sg: pointer to the sg which should be queued next 9200b3e4af3SFelipe Balbi * @num_pending_sgs: counter to pending sgs 921c96e6725SAnurag Kumar Vulisha * @num_queued_sgs: counter to the number of sgs which already got queued 922e62c5bc5SFelipe Balbi * @remaining: amount of data remaining 923a3af5e3aSFelipe Balbi * @status: internal dwc3 request status tracking 9245ef68c56SFelipe Balbi * @epnum: endpoint number to which this request refers 9255ef68c56SFelipe Balbi * @trb: pointer to struct dwc3_trb 9265ef68c56SFelipe Balbi * @trb_dma: DMA address of @trb 92709fe1f8dSFelipe Balbi * @num_trbs: number of TRBs used by this request 9281a22ec64SFelipe Balbi * @needs_extra_trb: true when request needs one extra TRB (either due to ZLP 9291a22ec64SFelipe Balbi * or unaligned OUT) 9305ef68c56SFelipe Balbi * @direction: IN or OUT direction flag 9315ef68c56SFelipe Balbi * @mapped: true when request has been dma-mapped 9325ef68c56SFelipe Balbi */ 933e0ce0b0aSSebastian Andrzej Siewior struct dwc3_request { 934e0ce0b0aSSebastian Andrzej Siewior struct usb_request request; 935e0ce0b0aSSebastian Andrzej Siewior struct list_head list; 936e0ce0b0aSSebastian Andrzej Siewior struct dwc3_ep *dep; 9370b3e4af3SFelipe Balbi struct scatterlist *sg; 938a31e63b6SAnurag Kumar Vulisha struct scatterlist *start_sg; 939e0ce0b0aSSebastian Andrzej Siewior 94087b923a2SFelipe Balbi unsigned int num_pending_sgs; 941c96e6725SAnurag Kumar Vulisha unsigned int num_queued_sgs; 94287b923a2SFelipe Balbi unsigned int remaining; 943a3af5e3aSFelipe Balbi 944a3af5e3aSFelipe Balbi unsigned int status; 945a3af5e3aSFelipe Balbi #define DWC3_REQUEST_STATUS_QUEUED 0 946a3af5e3aSFelipe Balbi #define DWC3_REQUEST_STATUS_STARTED 1 94704dd6e76SRay Chi #define DWC3_REQUEST_STATUS_DISCONNECTED 2 94804dd6e76SRay Chi #define DWC3_REQUEST_STATUS_DEQUEUED 3 94904dd6e76SRay Chi #define DWC3_REQUEST_STATUS_STALLED 4 95004dd6e76SRay Chi #define DWC3_REQUEST_STATUS_COMPLETED 5 951a3af5e3aSFelipe Balbi #define DWC3_REQUEST_STATUS_UNKNOWN -1 952a3af5e3aSFelipe Balbi 953e0ce0b0aSSebastian Andrzej Siewior u8 epnum; 954f6bafc6aSFelipe Balbi struct dwc3_trb *trb; 955e0ce0b0aSSebastian Andrzej Siewior dma_addr_t trb_dma; 956e0ce0b0aSSebastian Andrzej Siewior 95787b923a2SFelipe Balbi unsigned int num_trbs; 95809fe1f8dSFelipe Balbi 95987b923a2SFelipe Balbi unsigned int needs_extra_trb:1; 96087b923a2SFelipe Balbi unsigned int direction:1; 96187b923a2SFelipe Balbi unsigned int mapped:1; 962e0ce0b0aSSebastian Andrzej Siewior }; 963e0ce0b0aSSebastian Andrzej Siewior 9642c61a8efSPaul Zimmerman /* 9652c61a8efSPaul Zimmerman * struct dwc3_scratchpad_array - hibernation scratchpad array 9662c61a8efSPaul Zimmerman * (format defined by hw) 9672c61a8efSPaul Zimmerman */ 9682c61a8efSPaul Zimmerman struct dwc3_scratchpad_array { 9692c61a8efSPaul Zimmerman __le64 dma_adr[DWC3_MAX_HIBER_SCRATCHBUFS]; 9702c61a8efSPaul Zimmerman }; 9712c61a8efSPaul Zimmerman 972a3299499SFelipe Balbi /** 97372246da4SFelipe Balbi * struct dwc3 - representation of our controller 974bfad65eeSFelipe Balbi * @drd_work: workqueue used for role swapping 97591db07dcSFelipe Balbi * @ep0_trb: trb which is used for the ctrl_req 976bfad65eeSFelipe Balbi * @bounce: address of bounce buffer 97791db07dcSFelipe Balbi * @setup_buf: used while precessing STD USB requests 978bfad65eeSFelipe Balbi * @ep0_trb_addr: dma address of @ep0_trb 979bfad65eeSFelipe Balbi * @bounce_addr: dma address of @bounce 98091db07dcSFelipe Balbi * @ep0_usb_req: dummy req used while handling STD USB requests 981bb014736SBaolin Wang * @ep0_in_setup: one control transfer is completed and enter setup phase 98272246da4SFelipe Balbi * @lock: for synchronizing 983f88359e1SYu Chen * @mutex: for mode switching 98472246da4SFelipe Balbi * @dev: pointer to our struct device 985bfad65eeSFelipe Balbi * @sysdev: pointer to the DMA-capable device 986d07e8819SFelipe Balbi * @xhci: pointer to our xHCI child 987bfad65eeSFelipe Balbi * @xhci_resources: struct resources for our @xhci child 988bfad65eeSFelipe Balbi * @ev_buf: struct dwc3_event_buffer pointer 989bfad65eeSFelipe Balbi * @eps: endpoint array 99072246da4SFelipe Balbi * @gadget: device side representation of the peripheral controller 99172246da4SFelipe Balbi * @gadget_driver: pointer to the gadget driver 99233fb697eSSean Anderson * @bus_clk: clock for accessing the registers 99333fb697eSSean Anderson * @ref_clk: reference clock 99433fb697eSSean Anderson * @susp_clk: clock used when the SS phy is in low power (S3) state 995fe8abf33SMasahiro Yamada * @reset: reset control 99672246da4SFelipe Balbi * @regs: base address for our registers 99772246da4SFelipe Balbi * @regs_size: address space size 998bcdb3272SFelipe Balbi * @fladj: frame length adjustment 9997bee3188SBalaji Prakash J * @ref_clk_per: reference clock period configuration 10003f308d17SFelipe Balbi * @irq_gadget: peripheral controller's IRQ number 1001f09cc79bSRoger Quadros * @otg_irq: IRQ number for OTG IRQs 1002f09cc79bSRoger Quadros * @current_otg_role: current role of operation while using the OTG block 1003f09cc79bSRoger Quadros * @desired_otg_role: desired role of operation while using the OTG block 1004f09cc79bSRoger Quadros * @otg_restart_host: flag that OTG controller needs to restart host 1005fae2b904SFelipe Balbi * @u1u2: only used on revisions <1.83a for workaround 10066c167fc9SFelipe Balbi * @maximum_speed: maximum speed requested (mainly for testing purposes) 100767848146SThinh Nguyen * @max_ssp_rate: SuperSpeed Plus maximum signaling rate and lane count 10085dc71f1eSMauro Carvalho Chehab * @gadget_max_speed: maximum gadget speed requested 1009072cab8aSThinh Nguyen * @gadget_ssp_rate: Gadget driver's maximum supported SuperSpeed Plus signaling 1010072cab8aSThinh Nguyen * rate and lane count. 10119af21dd6SThinh Nguyen * @ip: controller's ID 10129af21dd6SThinh Nguyen * @revision: controller's version of an IP 1013475d8e01SThinh Nguyen * @version_type: VERSIONTYPE register contents, a sub release of a revision 1014a45c82b8SRuchika Kharwar * @dr_mode: requested mode of operation 10156b3261a2SRoger Quadros * @current_dr_role: current role of operation when in dual-role mode 101641ce1456SRoger Quadros * @desired_dr_role: desired role of operation when in dual-role mode 10179840354fSRoger Quadros * @edev: extcon handle 10189840354fSRoger Quadros * @edev_nb: extcon notifier 101932f2ed86SWilliam Wu * @hsphy_mode: UTMI phy mode, one of following: 102032f2ed86SWilliam Wu * - USBPHY_INTERFACE_MODE_UTMI 102132f2ed86SWilliam Wu * - USBPHY_INTERFACE_MODE_UTMIW 10228a0a1379SYu Chen * @role_sw: usb_role_switch handle 102398ed256aSJohn Stultz * @role_switch_default_mode: default operation mode of controller while 102498ed256aSJohn Stultz * usb role is USB_ROLE_NONE. 10250f3edf99SRay Chi * @usb_psy: pointer to power supply interface. 102651e1e7bcSFelipe Balbi * @usb2_phy: pointer to USB2 PHY 102751e1e7bcSFelipe Balbi * @usb3_phy: pointer to USB3 PHY 102857303488SKishon Vijay Abraham I * @usb2_generic_phy: pointer to USB2 PHY 102957303488SKishon Vijay Abraham I * @usb3_generic_phy: pointer to USB3 PHY 103098112041SRoger Quadros * @phys_ready: flag to indicate that PHYs are ready 103188bc9d19SHeikki Krogerus * @ulpi: pointer to ulpi interface 103298112041SRoger Quadros * @ulpi_ready: flag to indicate that ULPI is initialized 1033865e09e7SFelipe Balbi * @u2sel: parameter from Set SEL request. 1034865e09e7SFelipe Balbi * @u2pel: parameter from Set SEL request. 1035865e09e7SFelipe Balbi * @u1sel: parameter from Set SEL request. 1036865e09e7SFelipe Balbi * @u1pel: parameter from Set SEL request. 103747d3946eSBryan O'Donoghue * @num_eps: number of endpoints 1038b53c772dSFelipe Balbi * @ep0_next_event: hold the next expected event 103972246da4SFelipe Balbi * @ep0state: state of endpoint zero 104072246da4SFelipe Balbi * @link_state: link state 104172246da4SFelipe Balbi * @speed: device speed (super, high, full, low) 1042a3299499SFelipe Balbi * @hwparams: copy of hwparams registers 1043f2b685d5SFelipe Balbi * @regset: debugfs pointer to regdump file 104462ba09d6SThinh Nguyen * @dbg_lsp_select: current debug lsp mux register selection 1045f2b685d5SFelipe Balbi * @test_mode: true when we're entering a USB test mode 1046f2b685d5SFelipe Balbi * @test_mode_nr: test feature selector 104780caf7d2SHuang Rui * @lpm_nyet_threshold: LPM NYET response threshold 1048460d098cSHuang Rui * @hird_threshold: HIRD threshold 1049938a5ad1SThinh Nguyen * @rx_thr_num_pkt_prd: periodic ESS receive packet count 1050938a5ad1SThinh Nguyen * @rx_max_burst_prd: max periodic ESS receive burst size 1051938a5ad1SThinh Nguyen * @tx_thr_num_pkt_prd: periodic ESS transmit packet count 1052938a5ad1SThinh Nguyen * @tx_max_burst_prd: max periodic ESS transmit burst size 10539f607a30SWesley Cheng * @tx_fifo_resize_max_num: max number of fifos allocated during txfifo resize 10542840d6dfSWesley Cheng * @clear_stall_protocol: endpoint number that requires a delayed status phase 10553e10a2ceSHeikki Krogerus * @hsphy_interface: "utmi" or "ulpi" 1056fc8bb91bSFelipe Balbi * @connected: true when we're connected to a host, false otherwise 10578217f07aSWesley Cheng * @softconnect: true when gadget connect is called, false when disconnect runs 1058f2b685d5SFelipe Balbi * @delayed_status: true when gadget driver asks for delayed status 1059f2b685d5SFelipe Balbi * @ep0_bounced: true when we used bounce buffer 1060f2b685d5SFelipe Balbi * @ep0_expect_in: true when we expect a DATA IN transfer 1061d64ff406SArnd Bergmann * @sysdev_is_parent: true when dwc3 device has a parent driver 106280caf7d2SHuang Rui * @has_lpm_erratum: true when core was configured with LPM Erratum. Note that 106380caf7d2SHuang Rui * there's now way for software to detect this in runtime. 1064460d098cSHuang Rui * @is_utmi_l1_suspend: the core asserts output signal 1065460d098cSHuang Rui * 0 - utmi_sleep_n 1066460d098cSHuang Rui * 1 - utmi_l1_suspend_n 1067946bd579SHuang Rui * @is_fpga: true when we are using the FPGA board 1068fc8bb91bSFelipe Balbi * @pending_events: true when we have pending IRQs to be handled 10699f607a30SWesley Cheng * @do_fifo_resize: true when txfifo resizing is enabled for dwc3 endpoints 1070f2b685d5SFelipe Balbi * @pullups_connected: true when Run/Stop bit is set 1071f2b685d5SFelipe Balbi * @setup_packet_pending: true when there's a Setup Packet in FIFO. Workaround 1072f2b685d5SFelipe Balbi * @three_stage_setup: set if we perform a three phase setup 1073d92021f6SThinh Nguyen * @dis_start_transfer_quirk: set if start_transfer failure SW workaround is 1074d92021f6SThinh Nguyen * not needed for DWC_usb31 version 1.70a-ea06 and below 1075eac68e8fSRobert Baldyga * @usb3_lpm_capable: set if hadrware supports Link Power Management 1076475e8be5SThinh Nguyen * @usb2_lpm_disable: set to disable usb2 lpm for host 1077475e8be5SThinh Nguyen * @usb2_gadget_lpm_disable: set to disable usb2 lpm for gadget 10783b81221aSHuang Rui * @disable_scramble_quirk: set if we enable the disable scramble quirk 10799a5b2f31SHuang Rui * @u2exit_lfps_quirk: set if we enable u2exit lfps quirk 1080b5a65c40SHuang Rui * @u2ss_inp3_quirk: set if we enable P3 OK for U2/SS Inactive quirk 1081df31f5b3SHuang Rui * @req_p1p2p3_quirk: set if we enable request p1p2p3 quirk 1082a2a1d0f5SHuang Rui * @del_p1p2p3_quirk: set if we enable delay p1p2p3 quirk 108341c06ffdSHuang Rui * @del_phy_power_chg_quirk: set if we enable delay phy power change quirk 1084fb67afcaSHuang Rui * @lfps_filter_quirk: set if we enable LFPS filter quirk 108514f4ac53SHuang Rui * @rx_detect_poll_quirk: set if we enable rx_detect to polling lfps quirk 108659acfa20SHuang Rui * @dis_u3_susphy_quirk: set if we disable usb3 suspend phy 10870effe0a3SHuang Rui * @dis_u2_susphy_quirk: set if we disable usb2 suspend phy 1088ec791d14SJohn Youn * @dis_enblslpm_quirk: set if we clear enblslpm in GUSB2PHYCFG, 1089ec791d14SJohn Youn * disabling the suspend signal to the PHY. 1090729dcffdSAnurag Kumar Vulisha * @dis_u1_entry_quirk: set if link entering into U1 state needs to be disabled. 1091729dcffdSAnurag Kumar Vulisha * @dis_u2_entry_quirk: set if link entering into U2 state needs to be disabled. 1092bfad65eeSFelipe Balbi * @dis_rxdet_inp3_quirk: set if we disable Rx.Detect in P3 1093ad44cf40SMauro Carvalho Chehab * @async_callbacks: if set, indicate that async callbacks will be used. 1094ad44cf40SMauro Carvalho Chehab * 109516199f33SWilliam Wu * @dis_u2_freeclk_exists_quirk : set if we clear u2_freeclk_exists 109616199f33SWilliam Wu * in GUSB2PHYCFG, specify that USB2 PHY doesn't 109716199f33SWilliam Wu * provide a free-running PHY clock. 109800fe081dSWilliam Wu * @dis_del_phy_power_chg_quirk: set if we disable delay phy power 109900fe081dSWilliam Wu * change quirk. 110065db7a0cSWilliam Wu * @dis_tx_ipgap_linecheck_quirk: set if we disable u2mac linestate 110165db7a0cSWilliam Wu * check during HS transmit. 110202c18203SVincenzo Palazzo * @resume_hs_terminations: Set if we enable quirk for fixing improper crc 110363d7f981SPiyush Mehta * generation after resume from suspend. 1104b84ba26cSPiyush Mehta * @ulpi_ext_vbus_drv: Set to confiure the upli chip to drives CPEN pin 1105b84ba26cSPiyush Mehta * VBUS with an external supply. 11067ba6b09fSNeil Armstrong * @parkmode_disable_ss_quirk: set if we need to disable all SuperSpeed 11077ba6b09fSNeil Armstrong * instances in park mode. 1108d21a797aSStanley Chang * @parkmode_disable_hs_quirk: set if we need to disable all HishSpeed 1109d21a797aSStanley Chang * instances in park mode. 11106b6a0c9aSHuang Rui * @tx_de_emphasis_quirk: set if we enable Tx de-emphasis quirk 11116b6a0c9aSHuang Rui * @tx_de_emphasis: Tx de-emphasis value 11126b6a0c9aSHuang Rui * 0 - -6dB de-emphasis 11136b6a0c9aSHuang Rui * 1 - -3.5dB de-emphasis 11146b6a0c9aSHuang Rui * 2 - No de-emphasis 11156b6a0c9aSHuang Rui * 3 - Reserved 111642bf02ecSRoger Quadros * @dis_metastability_quirk: set to disable metastability quirk. 1117f580170fSYu Chen * @dis_split_quirk: set to disable split boundary. 111804716168SElson Roy Serrao * @wakeup_configured: set if the device is configured for remote wakeup. 1119*4e8ef34eSLinyu Yuan * @suspended: set to track suspend event due to U3/L2. 1120cf40b86bSJohn Youn * @imod_interval: set the interrupt moderation interval in 250ns 1121cf40b86bSJohn Youn * increments or 0 to disable. 11229f607a30SWesley Cheng * @max_cfg_eps: current max number of IN eps used across all USB configs. 11239f607a30SWesley Cheng * @last_fifo_depth: last fifo depth used to determine next fifo ram start 11249f607a30SWesley Cheng * address. 11259f607a30SWesley Cheng * @num_ep_resized: carries the current number endpoints which have had its tx 11269f607a30SWesley Cheng * fifo resized. 1127be308d68SGreg Kroah-Hartman * @debug_root: root debugfs directory for this device to put its files in. 112872246da4SFelipe Balbi */ 112972246da4SFelipe Balbi struct dwc3 { 113041ce1456SRoger Quadros struct work_struct drd_work; 1131f6bafc6aSFelipe Balbi struct dwc3_trb *ep0_trb; 1132905dc04eSFelipe Balbi void *bounce; 113372246da4SFelipe Balbi u8 *setup_buf; 113472246da4SFelipe Balbi dma_addr_t ep0_trb_addr; 1135905dc04eSFelipe Balbi dma_addr_t bounce_addr; 1136e0ce0b0aSSebastian Andrzej Siewior struct dwc3_request ep0_usb_req; 1137bb014736SBaolin Wang struct completion ep0_in_setup; 1138789451f6SFelipe Balbi 113972246da4SFelipe Balbi /* device lock */ 114072246da4SFelipe Balbi spinlock_t lock; 1141789451f6SFelipe Balbi 1142f88359e1SYu Chen /* mode switching lock */ 1143f88359e1SYu Chen struct mutex mutex; 1144f88359e1SYu Chen 114572246da4SFelipe Balbi struct device *dev; 1146d64ff406SArnd Bergmann struct device *sysdev; 114772246da4SFelipe Balbi 1148d07e8819SFelipe Balbi struct platform_device *xhci; 114951249dcaSIdo Shayevitz struct resource xhci_resources[DWC3_XHCI_RESOURCES_NUM]; 1150d07e8819SFelipe Balbi 1151696c8b12SFelipe Balbi struct dwc3_event_buffer *ev_buf; 115272246da4SFelipe Balbi struct dwc3_ep *eps[DWC3_ENDPOINTS_NUM]; 115372246da4SFelipe Balbi 1154e81a7018SPeter Chen struct usb_gadget *gadget; 115572246da4SFelipe Balbi struct usb_gadget_driver *gadget_driver; 115672246da4SFelipe Balbi 115733fb697eSSean Anderson struct clk *bus_clk; 115833fb697eSSean Anderson struct clk *ref_clk; 115933fb697eSSean Anderson struct clk *susp_clk; 1160fe8abf33SMasahiro Yamada 1161fe8abf33SMasahiro Yamada struct reset_control *reset; 1162fe8abf33SMasahiro Yamada 116351e1e7bcSFelipe Balbi struct usb_phy *usb2_phy; 116451e1e7bcSFelipe Balbi struct usb_phy *usb3_phy; 116551e1e7bcSFelipe Balbi 116657303488SKishon Vijay Abraham I struct phy *usb2_generic_phy; 116757303488SKishon Vijay Abraham I struct phy *usb3_generic_phy; 116857303488SKishon Vijay Abraham I 116998112041SRoger Quadros bool phys_ready; 117098112041SRoger Quadros 117188bc9d19SHeikki Krogerus struct ulpi *ulpi; 117298112041SRoger Quadros bool ulpi_ready; 117388bc9d19SHeikki Krogerus 117472246da4SFelipe Balbi void __iomem *regs; 117572246da4SFelipe Balbi size_t regs_size; 117672246da4SFelipe Balbi 1177a45c82b8SRuchika Kharwar enum usb_dr_mode dr_mode; 11786b3261a2SRoger Quadros u32 current_dr_role; 117941ce1456SRoger Quadros u32 desired_dr_role; 11809840354fSRoger Quadros struct extcon_dev *edev; 11819840354fSRoger Quadros struct notifier_block edev_nb; 118232f2ed86SWilliam Wu enum usb_phy_interface hsphy_mode; 11838a0a1379SYu Chen struct usb_role_switch *role_sw; 118498ed256aSJohn Stultz enum usb_dr_mode role_switch_default_mode; 1185a45c82b8SRuchika Kharwar 11866f0764b5SRay Chi struct power_supply *usb_psy; 11876f0764b5SRay Chi 1188bcdb3272SFelipe Balbi u32 fladj; 11897bee3188SBalaji Prakash J u32 ref_clk_per; 11903f308d17SFelipe Balbi u32 irq_gadget; 1191f09cc79bSRoger Quadros u32 otg_irq; 1192f09cc79bSRoger Quadros u32 current_otg_role; 1193f09cc79bSRoger Quadros u32 desired_otg_role; 1194f09cc79bSRoger Quadros bool otg_restart_host; 1195fae2b904SFelipe Balbi u32 u1u2; 11966c167fc9SFelipe Balbi u32 maximum_speed; 11977c9a2598SWesley Cheng u32 gadget_max_speed; 119867848146SThinh Nguyen enum usb_ssp_rate max_ssp_rate; 1199072cab8aSThinh Nguyen enum usb_ssp_rate gadget_ssp_rate; 1200690fb371SJohn Youn 12019af21dd6SThinh Nguyen u32 ip; 12029af21dd6SThinh Nguyen 12039af21dd6SThinh Nguyen #define DWC3_IP 0x5533 12049af21dd6SThinh Nguyen #define DWC31_IP 0x3331 12059af21dd6SThinh Nguyen #define DWC32_IP 0x3332 12069af21dd6SThinh Nguyen 120772246da4SFelipe Balbi u32 revision; 120872246da4SFelipe Balbi 12099af21dd6SThinh Nguyen #define DWC3_REVISION_ANY 0x0 121072246da4SFelipe Balbi #define DWC3_REVISION_173A 0x5533173a 121172246da4SFelipe Balbi #define DWC3_REVISION_175A 0x5533175a 121272246da4SFelipe Balbi #define DWC3_REVISION_180A 0x5533180a 121372246da4SFelipe Balbi #define DWC3_REVISION_183A 0x5533183a 121472246da4SFelipe Balbi #define DWC3_REVISION_185A 0x5533185a 12152c61a8efSPaul Zimmerman #define DWC3_REVISION_187A 0x5533187a 121672246da4SFelipe Balbi #define DWC3_REVISION_188A 0x5533188a 121772246da4SFelipe Balbi #define DWC3_REVISION_190A 0x5533190a 12182c61a8efSPaul Zimmerman #define DWC3_REVISION_194A 0x5533194a 12191522d703SFelipe Balbi #define DWC3_REVISION_200A 0x5533200a 12201522d703SFelipe Balbi #define DWC3_REVISION_202A 0x5533202a 12211522d703SFelipe Balbi #define DWC3_REVISION_210A 0x5533210a 12221522d703SFelipe Balbi #define DWC3_REVISION_220A 0x5533220a 12237ac6a593SFelipe Balbi #define DWC3_REVISION_230A 0x5533230a 12247ac6a593SFelipe Balbi #define DWC3_REVISION_240A 0x5533240a 12257ac6a593SFelipe Balbi #define DWC3_REVISION_250A 0x5533250a 1226dbf5aaf7SFelipe Balbi #define DWC3_REVISION_260A 0x5533260a 1227dbf5aaf7SFelipe Balbi #define DWC3_REVISION_270A 0x5533270a 1228dbf5aaf7SFelipe Balbi #define DWC3_REVISION_280A 0x5533280a 12290bb39ca1SJohn Youn #define DWC3_REVISION_290A 0x5533290a 1230512e4757SJohn Youn #define DWC3_REVISION_300A 0x5533300a 1231512e4757SJohn Youn #define DWC3_REVISION_310A 0x5533310a 123289a9cc47SThinh Nguyen #define DWC3_REVISION_330A 0x5533330a 123372246da4SFelipe Balbi 12349af21dd6SThinh Nguyen #define DWC31_REVISION_ANY 0x0 12359af21dd6SThinh Nguyen #define DWC31_REVISION_110A 0x3131302a 12369af21dd6SThinh Nguyen #define DWC31_REVISION_120A 0x3132302a 12379af21dd6SThinh Nguyen #define DWC31_REVISION_160A 0x3136302a 12389af21dd6SThinh Nguyen #define DWC31_REVISION_170A 0x3137302a 12399af21dd6SThinh Nguyen #define DWC31_REVISION_180A 0x3138302a 12409af21dd6SThinh Nguyen #define DWC31_REVISION_190A 0x3139302a 1241690fb371SJohn Youn 1242b10e1c25SThinh Nguyen #define DWC32_REVISION_ANY 0x0 1243b10e1c25SThinh Nguyen #define DWC32_REVISION_100A 0x3130302a 1244b10e1c25SThinh Nguyen 1245475d8e01SThinh Nguyen u32 version_type; 1246475d8e01SThinh Nguyen 12479af21dd6SThinh Nguyen #define DWC31_VERSIONTYPE_ANY 0x0 1248475d8e01SThinh Nguyen #define DWC31_VERSIONTYPE_EA01 0x65613031 1249475d8e01SThinh Nguyen #define DWC31_VERSIONTYPE_EA02 0x65613032 1250475d8e01SThinh Nguyen #define DWC31_VERSIONTYPE_EA03 0x65613033 1251475d8e01SThinh Nguyen #define DWC31_VERSIONTYPE_EA04 0x65613034 1252475d8e01SThinh Nguyen #define DWC31_VERSIONTYPE_EA05 0x65613035 1253475d8e01SThinh Nguyen #define DWC31_VERSIONTYPE_EA06 0x65613036 1254475d8e01SThinh Nguyen 1255b53c772dSFelipe Balbi enum dwc3_ep0_next ep0_next_event; 125672246da4SFelipe Balbi enum dwc3_ep0_state ep0state; 125772246da4SFelipe Balbi enum dwc3_link_state link_state; 125872246da4SFelipe Balbi 1259865e09e7SFelipe Balbi u16 u2sel; 1260865e09e7SFelipe Balbi u16 u2pel; 1261865e09e7SFelipe Balbi u8 u1sel; 1262865e09e7SFelipe Balbi u8 u1pel; 1263865e09e7SFelipe Balbi 126472246da4SFelipe Balbi u8 speed; 1265865e09e7SFelipe Balbi 126647d3946eSBryan O'Donoghue u8 num_eps; 1267789451f6SFelipe Balbi 1268a3299499SFelipe Balbi struct dwc3_hwparams hwparams; 1269d7668024SFelipe Balbi struct debugfs_regset32 *regset; 12703b637367SGerard Cauvy 127162ba09d6SThinh Nguyen u32 dbg_lsp_select; 127262ba09d6SThinh Nguyen 12733b637367SGerard Cauvy u8 test_mode; 12743b637367SGerard Cauvy u8 test_mode_nr; 127580caf7d2SHuang Rui u8 lpm_nyet_threshold; 1276460d098cSHuang Rui u8 hird_threshold; 1277938a5ad1SThinh Nguyen u8 rx_thr_num_pkt_prd; 1278938a5ad1SThinh Nguyen u8 rx_max_burst_prd; 1279938a5ad1SThinh Nguyen u8 tx_thr_num_pkt_prd; 1280938a5ad1SThinh Nguyen u8 tx_max_burst_prd; 12819f607a30SWesley Cheng u8 tx_fifo_resize_max_num; 12822840d6dfSWesley Cheng u8 clear_stall_protocol; 1283f2b685d5SFelipe Balbi 12843e10a2ceSHeikki Krogerus const char *hsphy_interface; 12853e10a2ceSHeikki Krogerus 1286fc8bb91bSFelipe Balbi unsigned connected:1; 12878217f07aSWesley Cheng unsigned softconnect:1; 1288f2b685d5SFelipe Balbi unsigned delayed_status:1; 1289f2b685d5SFelipe Balbi unsigned ep0_bounced:1; 1290f2b685d5SFelipe Balbi unsigned ep0_expect_in:1; 1291d64ff406SArnd Bergmann unsigned sysdev_is_parent:1; 129280caf7d2SHuang Rui unsigned has_lpm_erratum:1; 1293460d098cSHuang Rui unsigned is_utmi_l1_suspend:1; 1294946bd579SHuang Rui unsigned is_fpga:1; 1295fc8bb91bSFelipe Balbi unsigned pending_events:1; 12969f607a30SWesley Cheng unsigned do_fifo_resize:1; 1297f2b685d5SFelipe Balbi unsigned pullups_connected:1; 1298f2b685d5SFelipe Balbi unsigned setup_packet_pending:1; 1299f2b685d5SFelipe Balbi unsigned three_stage_setup:1; 1300d92021f6SThinh Nguyen unsigned dis_start_transfer_quirk:1; 1301eac68e8fSRobert Baldyga unsigned usb3_lpm_capable:1; 1302022a0208SThinh Nguyen unsigned usb2_lpm_disable:1; 1303475e8be5SThinh Nguyen unsigned usb2_gadget_lpm_disable:1; 13043b81221aSHuang Rui 13053b81221aSHuang Rui unsigned disable_scramble_quirk:1; 13069a5b2f31SHuang Rui unsigned u2exit_lfps_quirk:1; 1307b5a65c40SHuang Rui unsigned u2ss_inp3_quirk:1; 1308df31f5b3SHuang Rui unsigned req_p1p2p3_quirk:1; 1309a2a1d0f5SHuang Rui unsigned del_p1p2p3_quirk:1; 131041c06ffdSHuang Rui unsigned del_phy_power_chg_quirk:1; 1311fb67afcaSHuang Rui unsigned lfps_filter_quirk:1; 131214f4ac53SHuang Rui unsigned rx_detect_poll_quirk:1; 131359acfa20SHuang Rui unsigned dis_u3_susphy_quirk:1; 13140effe0a3SHuang Rui unsigned dis_u2_susphy_quirk:1; 1315ec791d14SJohn Youn unsigned dis_enblslpm_quirk:1; 1316729dcffdSAnurag Kumar Vulisha unsigned dis_u1_entry_quirk:1; 1317729dcffdSAnurag Kumar Vulisha unsigned dis_u2_entry_quirk:1; 1318e58dd357SRajesh Bhagat unsigned dis_rxdet_inp3_quirk:1; 131916199f33SWilliam Wu unsigned dis_u2_freeclk_exists_quirk:1; 132000fe081dSWilliam Wu unsigned dis_del_phy_power_chg_quirk:1; 132165db7a0cSWilliam Wu unsigned dis_tx_ipgap_linecheck_quirk:1; 132263d7f981SPiyush Mehta unsigned resume_hs_terminations:1; 1323b84ba26cSPiyush Mehta unsigned ulpi_ext_vbus_drv:1; 13247ba6b09fSNeil Armstrong unsigned parkmode_disable_ss_quirk:1; 1325d21a797aSStanley Chang unsigned parkmode_disable_hs_quirk:1; 1326a6fc2f1bSAlexander Stein unsigned gfladj_refclk_lpm_sel:1; 13276b6a0c9aSHuang Rui 13286b6a0c9aSHuang Rui unsigned tx_de_emphasis_quirk:1; 13296b6a0c9aSHuang Rui unsigned tx_de_emphasis:2; 1330cf40b86bSJohn Youn 133142bf02ecSRoger Quadros unsigned dis_metastability_quirk:1; 133242bf02ecSRoger Quadros 1333f580170fSYu Chen unsigned dis_split_quirk:1; 133440edb522SLinyu Yuan unsigned async_callbacks:1; 133504716168SElson Roy Serrao unsigned wakeup_configured:1; 1336*4e8ef34eSLinyu Yuan unsigned suspended:1; 1337f580170fSYu Chen 1338cf40b86bSJohn Youn u16 imod_interval; 13399f607a30SWesley Cheng 13409f607a30SWesley Cheng int max_cfg_eps; 13419f607a30SWesley Cheng int last_fifo_depth; 13429f607a30SWesley Cheng int num_ep_resized; 1343be308d68SGreg Kroah-Hartman struct dentry *debug_root; 134472246da4SFelipe Balbi }; 134572246da4SFelipe Balbi 1346d9612c2fSPengbo Mu #define INCRX_BURST_MODE 0 1347d9612c2fSPengbo Mu #define INCRX_UNDEF_LENGTH_BURST_MODE 1 1348d9612c2fSPengbo Mu 134941ce1456SRoger Quadros #define work_to_dwc(w) (container_of((w), struct dwc3, drd_work)) 135072246da4SFelipe Balbi 135172246da4SFelipe Balbi /* -------------------------------------------------------------------------- */ 135272246da4SFelipe Balbi 135372246da4SFelipe Balbi struct dwc3_event_type { 135472246da4SFelipe Balbi u32 is_devspec:1; 13551974d494SHuang Rui u32 type:7; 13561974d494SHuang Rui u32 reserved8_31:24; 135772246da4SFelipe Balbi } __packed; 135872246da4SFelipe Balbi 135972246da4SFelipe Balbi #define DWC3_DEPEVT_XFERCOMPLETE 0x01 136072246da4SFelipe Balbi #define DWC3_DEPEVT_XFERINPROGRESS 0x02 136172246da4SFelipe Balbi #define DWC3_DEPEVT_XFERNOTREADY 0x03 136272246da4SFelipe Balbi #define DWC3_DEPEVT_RXTXFIFOEVT 0x04 136372246da4SFelipe Balbi #define DWC3_DEPEVT_STREAMEVT 0x06 136472246da4SFelipe Balbi #define DWC3_DEPEVT_EPCMDCMPLT 0x07 136572246da4SFelipe Balbi 136672246da4SFelipe Balbi /** 1367cbdc0f54SMauro Carvalho Chehab * struct dwc3_event_depevt - Device Endpoint Events 136872246da4SFelipe Balbi * @one_bit: indicates this is an endpoint event (not used) 136972246da4SFelipe Balbi * @endpoint_number: number of the endpoint 137072246da4SFelipe Balbi * @endpoint_event: The event we have: 137172246da4SFelipe Balbi * 0x00 - Reserved 137272246da4SFelipe Balbi * 0x01 - XferComplete 137372246da4SFelipe Balbi * 0x02 - XferInProgress 137472246da4SFelipe Balbi * 0x03 - XferNotReady 137572246da4SFelipe Balbi * 0x04 - RxTxFifoEvt (IN->Underrun, OUT->Overrun) 137672246da4SFelipe Balbi * 0x05 - Reserved 137772246da4SFelipe Balbi * 0x06 - StreamEvt 137872246da4SFelipe Balbi * 0x07 - EPCmdCmplt 137972246da4SFelipe Balbi * @reserved11_10: Reserved, don't use. 138072246da4SFelipe Balbi * @status: Indicates the status of the event. Refer to databook for 138172246da4SFelipe Balbi * more information. 138272246da4SFelipe Balbi * @parameters: Parameters of the current event. Refer to databook for 138372246da4SFelipe Balbi * more information. 138472246da4SFelipe Balbi */ 138572246da4SFelipe Balbi struct dwc3_event_depevt { 138672246da4SFelipe Balbi u32 one_bit:1; 138772246da4SFelipe Balbi u32 endpoint_number:5; 138872246da4SFelipe Balbi u32 endpoint_event:4; 138972246da4SFelipe Balbi u32 reserved11_10:2; 139072246da4SFelipe Balbi u32 status:4; 139140aa41fbSFelipe Balbi 139240aa41fbSFelipe Balbi /* Within XferNotReady */ 1393ff3f0789SRoger Quadros #define DEPEVT_STATUS_TRANSFER_ACTIVE BIT(3) 139440aa41fbSFelipe Balbi 13956d8a0196SFelipe Balbi /* Within XferComplete or XferInProgress */ 1396ff3f0789SRoger Quadros #define DEPEVT_STATUS_BUSERR BIT(0) 1397ff3f0789SRoger Quadros #define DEPEVT_STATUS_SHORT BIT(1) 1398ff3f0789SRoger Quadros #define DEPEVT_STATUS_IOC BIT(2) 13996d8a0196SFelipe Balbi #define DEPEVT_STATUS_LST BIT(3) /* XferComplete */ 14006d8a0196SFelipe Balbi #define DEPEVT_STATUS_MISSED_ISOC BIT(3) /* XferInProgress */ 1401dc137f01SFelipe Balbi 1402879631aaSFelipe Balbi /* Stream event only */ 1403879631aaSFelipe Balbi #define DEPEVT_STREAMEVT_FOUND 1 1404879631aaSFelipe Balbi #define DEPEVT_STREAMEVT_NOTFOUND 2 1405879631aaSFelipe Balbi 1406140ca4cfSThinh Nguyen /* Stream event parameter */ 1407140ca4cfSThinh Nguyen #define DEPEVT_STREAM_PRIME 0xfffe 1408140ca4cfSThinh Nguyen #define DEPEVT_STREAM_NOSTREAM 0x0 1409140ca4cfSThinh Nguyen 1410dc137f01SFelipe Balbi /* Control-only Status */ 1411dc137f01SFelipe Balbi #define DEPEVT_STATUS_CONTROL_DATA 1 1412dc137f01SFelipe Balbi #define DEPEVT_STATUS_CONTROL_STATUS 2 141345a2af2fSFelipe Balbi #define DEPEVT_STATUS_CONTROL_PHASE(n) ((n) & 3) 1414dc137f01SFelipe Balbi 14157b9cc7a2SKonrad Leszczynski /* In response to Start Transfer */ 14167b9cc7a2SKonrad Leszczynski #define DEPEVT_TRANSFER_NO_RESOURCE 1 14177b9cc7a2SKonrad Leszczynski #define DEPEVT_TRANSFER_BUS_EXPIRY 2 14187b9cc7a2SKonrad Leszczynski 141972246da4SFelipe Balbi u32 parameters:16; 142076a638f8SBaolin Wang 142176a638f8SBaolin Wang /* For Command Complete Events */ 142276a638f8SBaolin Wang #define DEPEVT_PARAMETER_CMD(n) (((n) & (0xf << 8)) >> 8) 142372246da4SFelipe Balbi } __packed; 142472246da4SFelipe Balbi 142572246da4SFelipe Balbi /** 142672246da4SFelipe Balbi * struct dwc3_event_devt - Device Events 142772246da4SFelipe Balbi * @one_bit: indicates this is a non-endpoint event (not used) 142872246da4SFelipe Balbi * @device_event: indicates it's a device event. Should read as 0x00 142972246da4SFelipe Balbi * @type: indicates the type of device event. 143072246da4SFelipe Balbi * 0 - DisconnEvt 143172246da4SFelipe Balbi * 1 - USBRst 143272246da4SFelipe Balbi * 2 - ConnectDone 143372246da4SFelipe Balbi * 3 - ULStChng 143472246da4SFelipe Balbi * 4 - WkUpEvt 143572246da4SFelipe Balbi * 5 - Reserved 14366f26ebb7SJack Pham * 6 - Suspend (EOPF on revisions 2.10a and prior) 143772246da4SFelipe Balbi * 7 - SOF 143872246da4SFelipe Balbi * 8 - Reserved 143972246da4SFelipe Balbi * 9 - ErrticErr 144072246da4SFelipe Balbi * 10 - CmdCmplt 144172246da4SFelipe Balbi * 11 - EvntOverflow 144272246da4SFelipe Balbi * 12 - VndrDevTstRcved 144372246da4SFelipe Balbi * @reserved15_12: Reserved, not used 144472246da4SFelipe Balbi * @event_info: Information about this event 144506f9b6e5SHuang Rui * @reserved31_25: Reserved, not used 144672246da4SFelipe Balbi */ 144772246da4SFelipe Balbi struct dwc3_event_devt { 144872246da4SFelipe Balbi u32 one_bit:1; 144972246da4SFelipe Balbi u32 device_event:7; 145072246da4SFelipe Balbi u32 type:4; 145172246da4SFelipe Balbi u32 reserved15_12:4; 145206f9b6e5SHuang Rui u32 event_info:9; 145306f9b6e5SHuang Rui u32 reserved31_25:7; 145472246da4SFelipe Balbi } __packed; 145572246da4SFelipe Balbi 145672246da4SFelipe Balbi /** 145772246da4SFelipe Balbi * struct dwc3_event_gevt - Other Core Events 145872246da4SFelipe Balbi * @one_bit: indicates this is a non-endpoint event (not used) 145972246da4SFelipe Balbi * @device_event: indicates it's (0x03) Carkit or (0x04) I2C event. 146072246da4SFelipe Balbi * @phy_port_number: self-explanatory 146172246da4SFelipe Balbi * @reserved31_12: Reserved, not used. 146272246da4SFelipe Balbi */ 146372246da4SFelipe Balbi struct dwc3_event_gevt { 146472246da4SFelipe Balbi u32 one_bit:1; 146572246da4SFelipe Balbi u32 device_event:7; 146672246da4SFelipe Balbi u32 phy_port_number:4; 146772246da4SFelipe Balbi u32 reserved31_12:20; 146872246da4SFelipe Balbi } __packed; 146972246da4SFelipe Balbi 147072246da4SFelipe Balbi /** 147172246da4SFelipe Balbi * union dwc3_event - representation of Event Buffer contents 147272246da4SFelipe Balbi * @raw: raw 32-bit event 147372246da4SFelipe Balbi * @type: the type of the event 147472246da4SFelipe Balbi * @depevt: Device Endpoint Event 147572246da4SFelipe Balbi * @devt: Device Event 147672246da4SFelipe Balbi * @gevt: Global Event 147772246da4SFelipe Balbi */ 147872246da4SFelipe Balbi union dwc3_event { 147972246da4SFelipe Balbi u32 raw; 148072246da4SFelipe Balbi struct dwc3_event_type type; 148172246da4SFelipe Balbi struct dwc3_event_depevt depevt; 148272246da4SFelipe Balbi struct dwc3_event_devt devt; 148372246da4SFelipe Balbi struct dwc3_event_gevt gevt; 148472246da4SFelipe Balbi }; 148572246da4SFelipe Balbi 148661018305SFelipe Balbi /** 148761018305SFelipe Balbi * struct dwc3_gadget_ep_cmd_params - representation of endpoint command 148861018305SFelipe Balbi * parameters 148961018305SFelipe Balbi * @param2: third parameter 149061018305SFelipe Balbi * @param1: second parameter 149161018305SFelipe Balbi * @param0: first parameter 149261018305SFelipe Balbi */ 149361018305SFelipe Balbi struct dwc3_gadget_ep_cmd_params { 149461018305SFelipe Balbi u32 param2; 149561018305SFelipe Balbi u32 param1; 149661018305SFelipe Balbi u32 param0; 149761018305SFelipe Balbi }; 149861018305SFelipe Balbi 149972246da4SFelipe Balbi /* 150072246da4SFelipe Balbi * DWC3 Features to be used as Driver Data 150172246da4SFelipe Balbi */ 150272246da4SFelipe Balbi 150372246da4SFelipe Balbi #define DWC3_HAS_PERIPHERAL BIT(0) 150472246da4SFelipe Balbi #define DWC3_HAS_XHCI BIT(1) 150572246da4SFelipe Balbi #define DWC3_HAS_OTG BIT(3) 150672246da4SFelipe Balbi 1507d07e8819SFelipe Balbi /* prototypes */ 1508f09cc79bSRoger Quadros void dwc3_set_prtcap(struct dwc3 *dwc, u32 mode); 15093140e8cbSSebastian Andrzej Siewior void dwc3_set_mode(struct dwc3 *dwc, u32 mode); 1510cf6d867dSFelipe Balbi u32 dwc3_core_fifo_space(struct dwc3_ep *dep, u8 type); 15113140e8cbSSebastian Andrzej Siewior 15129af21dd6SThinh Nguyen #define DWC3_IP_IS(_ip) \ 15139af21dd6SThinh Nguyen (dwc->ip == _ip##_IP) 1514a987a906SJohn Youn 15159af21dd6SThinh Nguyen #define DWC3_VER_IS(_ip, _ver) \ 15169af21dd6SThinh Nguyen (DWC3_IP_IS(_ip) && dwc->revision == _ip##_REVISION_##_ver) 15179af21dd6SThinh Nguyen 15189af21dd6SThinh Nguyen #define DWC3_VER_IS_PRIOR(_ip, _ver) \ 15199af21dd6SThinh Nguyen (DWC3_IP_IS(_ip) && dwc->revision < _ip##_REVISION_##_ver) 15209af21dd6SThinh Nguyen 15219af21dd6SThinh Nguyen #define DWC3_VER_IS_WITHIN(_ip, _from, _to) \ 15229af21dd6SThinh Nguyen (DWC3_IP_IS(_ip) && \ 15239af21dd6SThinh Nguyen dwc->revision >= _ip##_REVISION_##_from && \ 15249af21dd6SThinh Nguyen (!(_ip##_REVISION_##_to) || \ 15259af21dd6SThinh Nguyen dwc->revision <= _ip##_REVISION_##_to)) 15269af21dd6SThinh Nguyen 15279af21dd6SThinh Nguyen #define DWC3_VER_TYPE_IS_WITHIN(_ip, _ver, _from, _to) \ 15289af21dd6SThinh Nguyen (DWC3_VER_IS(_ip, _ver) && \ 15299af21dd6SThinh Nguyen dwc->version_type >= _ip##_VERSIONTYPE_##_from && \ 15309af21dd6SThinh Nguyen (!(_ip##_VERSIONTYPE_##_to) || \ 15319af21dd6SThinh Nguyen dwc->version_type <= _ip##_VERSIONTYPE_##_to)) 1532c4137a9cSJohn Youn 1533d00be779SThinh Nguyen /** 1534d00be779SThinh Nguyen * dwc3_mdwidth - get MDWIDTH value in bits 1535d00be779SThinh Nguyen * @dwc: pointer to our context structure 1536d00be779SThinh Nguyen * 1537d00be779SThinh Nguyen * Return MDWIDTH configuration value in bits. 1538d00be779SThinh Nguyen */ 1539d00be779SThinh Nguyen static inline u32 dwc3_mdwidth(struct dwc3 *dwc) 1540d00be779SThinh Nguyen { 1541d00be779SThinh Nguyen u32 mdwidth; 1542d00be779SThinh Nguyen 1543d00be779SThinh Nguyen mdwidth = DWC3_GHWPARAMS0_MDWIDTH(dwc->hwparams.hwparams0); 1544d00be779SThinh Nguyen if (DWC3_IP_IS(DWC32)) 1545d00be779SThinh Nguyen mdwidth += DWC3_GHWPARAMS6_MDWIDTH(dwc->hwparams.hwparams6); 1546d00be779SThinh Nguyen 1547d00be779SThinh Nguyen return mdwidth; 1548d00be779SThinh Nguyen } 1549d00be779SThinh Nguyen 1550cf40b86bSJohn Youn bool dwc3_has_imod(struct dwc3 *dwc); 1551cf40b86bSJohn Youn 1552f09cc79bSRoger Quadros int dwc3_event_buffers_setup(struct dwc3 *dwc); 1553f09cc79bSRoger Quadros void dwc3_event_buffers_cleanup(struct dwc3 *dwc); 1554f09cc79bSRoger Quadros 15550066472dSWesley Cheng int dwc3_core_soft_reset(struct dwc3 *dwc); 15560066472dSWesley Cheng 1557388e5c51SVivek Gautam #if IS_ENABLED(CONFIG_USB_DWC3_HOST) || IS_ENABLED(CONFIG_USB_DWC3_DUAL_ROLE) 1558d07e8819SFelipe Balbi int dwc3_host_init(struct dwc3 *dwc); 1559d07e8819SFelipe Balbi void dwc3_host_exit(struct dwc3 *dwc); 1560388e5c51SVivek Gautam #else 1561388e5c51SVivek Gautam static inline int dwc3_host_init(struct dwc3 *dwc) 1562388e5c51SVivek Gautam { return 0; } 1563388e5c51SVivek Gautam static inline void dwc3_host_exit(struct dwc3 *dwc) 1564388e5c51SVivek Gautam { } 1565388e5c51SVivek Gautam #endif 1566d07e8819SFelipe Balbi 1567388e5c51SVivek Gautam #if IS_ENABLED(CONFIG_USB_DWC3_GADGET) || IS_ENABLED(CONFIG_USB_DWC3_DUAL_ROLE) 1568f80b45e7SFelipe Balbi int dwc3_gadget_init(struct dwc3 *dwc); 1569f80b45e7SFelipe Balbi void dwc3_gadget_exit(struct dwc3 *dwc); 157061018305SFelipe Balbi int dwc3_gadget_set_test_mode(struct dwc3 *dwc, int mode); 157161018305SFelipe Balbi int dwc3_gadget_get_link_state(struct dwc3 *dwc); 157261018305SFelipe Balbi int dwc3_gadget_set_link_state(struct dwc3 *dwc, enum dwc3_link_state state); 157387b923a2SFelipe Balbi int dwc3_send_gadget_ep_cmd(struct dwc3_ep *dep, unsigned int cmd, 15742cd4718dSFelipe Balbi struct dwc3_gadget_ep_cmd_params *params); 157587b923a2SFelipe Balbi int dwc3_send_gadget_generic_command(struct dwc3 *dwc, unsigned int cmd, 157687b923a2SFelipe Balbi u32 param); 15779f607a30SWesley Cheng void dwc3_gadget_clear_tx_fifos(struct dwc3 *dwc); 15782b2da657SWesley Cheng void dwc3_remove_requests(struct dwc3 *dwc, struct dwc3_ep *dep, int status); 1579388e5c51SVivek Gautam #else 1580388e5c51SVivek Gautam static inline int dwc3_gadget_init(struct dwc3 *dwc) 1581388e5c51SVivek Gautam { return 0; } 1582388e5c51SVivek Gautam static inline void dwc3_gadget_exit(struct dwc3 *dwc) 1583388e5c51SVivek Gautam { } 158461018305SFelipe Balbi static inline int dwc3_gadget_set_test_mode(struct dwc3 *dwc, int mode) 158561018305SFelipe Balbi { return 0; } 158661018305SFelipe Balbi static inline int dwc3_gadget_get_link_state(struct dwc3 *dwc) 158761018305SFelipe Balbi { return 0; } 158861018305SFelipe Balbi static inline int dwc3_gadget_set_link_state(struct dwc3 *dwc, 158961018305SFelipe Balbi enum dwc3_link_state state) 159061018305SFelipe Balbi { return 0; } 159161018305SFelipe Balbi 159287b923a2SFelipe Balbi static inline int dwc3_send_gadget_ep_cmd(struct dwc3_ep *dep, unsigned int cmd, 15932cd4718dSFelipe Balbi struct dwc3_gadget_ep_cmd_params *params) 159461018305SFelipe Balbi { return 0; } 159561018305SFelipe Balbi static inline int dwc3_send_gadget_generic_command(struct dwc3 *dwc, 159661018305SFelipe Balbi int cmd, u32 param) 159761018305SFelipe Balbi { return 0; } 15989f607a30SWesley Cheng static inline void dwc3_gadget_clear_tx_fifos(struct dwc3 *dwc) 15999f607a30SWesley Cheng { } 1600388e5c51SVivek Gautam #endif 1601f80b45e7SFelipe Balbi 16029840354fSRoger Quadros #if IS_ENABLED(CONFIG_USB_DWC3_DUAL_ROLE) 16039840354fSRoger Quadros int dwc3_drd_init(struct dwc3 *dwc); 16049840354fSRoger Quadros void dwc3_drd_exit(struct dwc3 *dwc); 1605f09cc79bSRoger Quadros void dwc3_otg_init(struct dwc3 *dwc); 1606f09cc79bSRoger Quadros void dwc3_otg_exit(struct dwc3 *dwc); 1607f09cc79bSRoger Quadros void dwc3_otg_update(struct dwc3 *dwc, bool ignore_idstatus); 1608f09cc79bSRoger Quadros void dwc3_otg_host_init(struct dwc3 *dwc); 16099840354fSRoger Quadros #else 16109840354fSRoger Quadros static inline int dwc3_drd_init(struct dwc3 *dwc) 16119840354fSRoger Quadros { return 0; } 16129840354fSRoger Quadros static inline void dwc3_drd_exit(struct dwc3 *dwc) 16139840354fSRoger Quadros { } 1614f09cc79bSRoger Quadros static inline void dwc3_otg_init(struct dwc3 *dwc) 1615f09cc79bSRoger Quadros { } 1616f09cc79bSRoger Quadros static inline void dwc3_otg_exit(struct dwc3 *dwc) 1617f09cc79bSRoger Quadros { } 1618f09cc79bSRoger Quadros static inline void dwc3_otg_update(struct dwc3 *dwc, bool ignore_idstatus) 1619f09cc79bSRoger Quadros { } 1620f09cc79bSRoger Quadros static inline void dwc3_otg_host_init(struct dwc3 *dwc) 1621f09cc79bSRoger Quadros { } 16229840354fSRoger Quadros #endif 16239840354fSRoger Quadros 16247415f17cSFelipe Balbi /* power management interface */ 16257415f17cSFelipe Balbi #if !IS_ENABLED(CONFIG_USB_DWC3_HOST) 16267415f17cSFelipe Balbi int dwc3_gadget_suspend(struct dwc3 *dwc); 16277415f17cSFelipe Balbi int dwc3_gadget_resume(struct dwc3 *dwc); 1628fc8bb91bSFelipe Balbi void dwc3_gadget_process_pending_events(struct dwc3 *dwc); 16297415f17cSFelipe Balbi #else 16307415f17cSFelipe Balbi static inline int dwc3_gadget_suspend(struct dwc3 *dwc) 16317415f17cSFelipe Balbi { 16327415f17cSFelipe Balbi return 0; 16337415f17cSFelipe Balbi } 16347415f17cSFelipe Balbi 16357415f17cSFelipe Balbi static inline int dwc3_gadget_resume(struct dwc3 *dwc) 16367415f17cSFelipe Balbi { 16377415f17cSFelipe Balbi return 0; 16387415f17cSFelipe Balbi } 1639fc8bb91bSFelipe Balbi 1640fc8bb91bSFelipe Balbi static inline void dwc3_gadget_process_pending_events(struct dwc3 *dwc) 1641fc8bb91bSFelipe Balbi { 1642fc8bb91bSFelipe Balbi } 16437415f17cSFelipe Balbi #endif /* !IS_ENABLED(CONFIG_USB_DWC3_HOST) */ 16447415f17cSFelipe Balbi 164588bc9d19SHeikki Krogerus #if IS_ENABLED(CONFIG_USB_DWC3_ULPI) 164688bc9d19SHeikki Krogerus int dwc3_ulpi_init(struct dwc3 *dwc); 164788bc9d19SHeikki Krogerus void dwc3_ulpi_exit(struct dwc3 *dwc); 164888bc9d19SHeikki Krogerus #else 164988bc9d19SHeikki Krogerus static inline int dwc3_ulpi_init(struct dwc3 *dwc) 165088bc9d19SHeikki Krogerus { return 0; } 165188bc9d19SHeikki Krogerus static inline void dwc3_ulpi_exit(struct dwc3 *dwc) 165288bc9d19SHeikki Krogerus { } 165388bc9d19SHeikki Krogerus #endif 165488bc9d19SHeikki Krogerus 165572246da4SFelipe Balbi #endif /* __DRIVERS_USB_DWC3_CORE_H */ 1656