172246da4SFelipe Balbi /** 272246da4SFelipe Balbi * core.h - DesignWare USB3 DRD Core Header 372246da4SFelipe Balbi * 472246da4SFelipe Balbi * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com 572246da4SFelipe Balbi * 672246da4SFelipe Balbi * Authors: Felipe Balbi <balbi@ti.com>, 772246da4SFelipe Balbi * Sebastian Andrzej Siewior <bigeasy@linutronix.de> 872246da4SFelipe Balbi * 95945f789SFelipe Balbi * This program is free software: you can redistribute it and/or modify 105945f789SFelipe Balbi * it under the terms of the GNU General Public License version 2 of 115945f789SFelipe Balbi * the License as published by the Free Software Foundation. 1272246da4SFelipe Balbi * 135945f789SFelipe Balbi * This program is distributed in the hope that it will be useful, 145945f789SFelipe Balbi * but WITHOUT ANY WARRANTY; without even the implied warranty of 155945f789SFelipe Balbi * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 165945f789SFelipe Balbi * GNU General Public License for more details. 1772246da4SFelipe Balbi */ 1872246da4SFelipe Balbi 1972246da4SFelipe Balbi #ifndef __DRIVERS_USB_DWC3_CORE_H 2072246da4SFelipe Balbi #define __DRIVERS_USB_DWC3_CORE_H 2172246da4SFelipe Balbi 2272246da4SFelipe Balbi #include <linux/device.h> 2372246da4SFelipe Balbi #include <linux/spinlock.h> 24d07e8819SFelipe Balbi #include <linux/ioport.h> 2572246da4SFelipe Balbi #include <linux/list.h> 2672246da4SFelipe Balbi #include <linux/dma-mapping.h> 2772246da4SFelipe Balbi #include <linux/mm.h> 2872246da4SFelipe Balbi #include <linux/debugfs.h> 2976a638f8SBaolin Wang #include <linux/wait.h> 3072246da4SFelipe Balbi 3172246da4SFelipe Balbi #include <linux/usb/ch9.h> 3272246da4SFelipe Balbi #include <linux/usb/gadget.h> 33a45c82b8SRuchika Kharwar #include <linux/usb/otg.h> 3488bc9d19SHeikki Krogerus #include <linux/ulpi/interface.h> 3572246da4SFelipe Balbi 3657303488SKishon Vijay Abraham I #include <linux/phy/phy.h> 3757303488SKishon Vijay Abraham I 382c4cbe6eSFelipe Balbi #define DWC3_MSG_MAX 500 392c4cbe6eSFelipe Balbi 4072246da4SFelipe Balbi /* Global constants */ 41bb014736SBaolin Wang #define DWC3_PULL_UP_TIMEOUT 500 /* ms */ 4204c03d10SFelipe Balbi #define DWC3_ZLP_BUF_SIZE 1024 /* size of a superspeed bulk */ 43905dc04eSFelipe Balbi #define DWC3_BOUNCE_SIZE 1024 /* size of a superspeed bulk */ 443ef35fafSFelipe Balbi #define DWC3_EP0_BOUNCE_SIZE 512 4572246da4SFelipe Balbi #define DWC3_ENDPOINTS_NUM 32 4651249dcaSIdo Shayevitz #define DWC3_XHCI_RESOURCES_NUM 2 4772246da4SFelipe Balbi 480ffcaf37SFelipe Balbi #define DWC3_SCRATCHBUF_SIZE 4096 /* each buffer is assumed to be 4KiB */ 49e71d363dSFelipe Balbi #define DWC3_EVENT_BUFFERS_SIZE 4096 5072246da4SFelipe Balbi #define DWC3_EVENT_TYPE_MASK 0xfe 5172246da4SFelipe Balbi 5272246da4SFelipe Balbi #define DWC3_EVENT_TYPE_DEV 0 5372246da4SFelipe Balbi #define DWC3_EVENT_TYPE_CARKIT 3 5472246da4SFelipe Balbi #define DWC3_EVENT_TYPE_I2C 4 5572246da4SFelipe Balbi 5672246da4SFelipe Balbi #define DWC3_DEVICE_EVENT_DISCONNECT 0 5772246da4SFelipe Balbi #define DWC3_DEVICE_EVENT_RESET 1 5872246da4SFelipe Balbi #define DWC3_DEVICE_EVENT_CONNECT_DONE 2 5972246da4SFelipe Balbi #define DWC3_DEVICE_EVENT_LINK_STATUS_CHANGE 3 6072246da4SFelipe Balbi #define DWC3_DEVICE_EVENT_WAKEUP 4 612c61a8efSPaul Zimmerman #define DWC3_DEVICE_EVENT_HIBER_REQ 5 6272246da4SFelipe Balbi #define DWC3_DEVICE_EVENT_EOPF 6 6372246da4SFelipe Balbi #define DWC3_DEVICE_EVENT_SOF 7 6472246da4SFelipe Balbi #define DWC3_DEVICE_EVENT_ERRATIC_ERROR 9 6572246da4SFelipe Balbi #define DWC3_DEVICE_EVENT_CMD_CMPL 10 6672246da4SFelipe Balbi #define DWC3_DEVICE_EVENT_OVERFLOW 11 6772246da4SFelipe Balbi 6872246da4SFelipe Balbi #define DWC3_GEVNTCOUNT_MASK 0xfffc 69cf40b86bSJohn Youn #define DWC3_GEVNTCOUNT_EHB (1 << 31) 7072246da4SFelipe Balbi #define DWC3_GSNPSID_MASK 0xffff0000 7172246da4SFelipe Balbi #define DWC3_GSNPSREV_MASK 0xffff 7272246da4SFelipe Balbi 7351249dcaSIdo Shayevitz /* DWC3 registers memory space boundries */ 7451249dcaSIdo Shayevitz #define DWC3_XHCI_REGS_START 0x0 7551249dcaSIdo Shayevitz #define DWC3_XHCI_REGS_END 0x7fff 7651249dcaSIdo Shayevitz #define DWC3_GLOBALS_REGS_START 0xc100 7751249dcaSIdo Shayevitz #define DWC3_GLOBALS_REGS_END 0xc6ff 7851249dcaSIdo Shayevitz #define DWC3_DEVICE_REGS_START 0xc700 7951249dcaSIdo Shayevitz #define DWC3_DEVICE_REGS_END 0xcbff 8051249dcaSIdo Shayevitz #define DWC3_OTG_REGS_START 0xcc00 8151249dcaSIdo Shayevitz #define DWC3_OTG_REGS_END 0xccff 8251249dcaSIdo Shayevitz 8372246da4SFelipe Balbi /* Global Registers */ 8472246da4SFelipe Balbi #define DWC3_GSBUSCFG0 0xc100 8572246da4SFelipe Balbi #define DWC3_GSBUSCFG1 0xc104 8672246da4SFelipe Balbi #define DWC3_GTXTHRCFG 0xc108 8772246da4SFelipe Balbi #define DWC3_GRXTHRCFG 0xc10c 8872246da4SFelipe Balbi #define DWC3_GCTL 0xc110 8972246da4SFelipe Balbi #define DWC3_GEVTEN 0xc114 9072246da4SFelipe Balbi #define DWC3_GSTS 0xc118 91475c8bebSWilliam Wu #define DWC3_GUCTL1 0xc11c 9272246da4SFelipe Balbi #define DWC3_GSNPSID 0xc120 9372246da4SFelipe Balbi #define DWC3_GGPIO 0xc124 9472246da4SFelipe Balbi #define DWC3_GUID 0xc128 9572246da4SFelipe Balbi #define DWC3_GUCTL 0xc12c 9672246da4SFelipe Balbi #define DWC3_GBUSERRADDR0 0xc130 9772246da4SFelipe Balbi #define DWC3_GBUSERRADDR1 0xc134 9872246da4SFelipe Balbi #define DWC3_GPRTBIMAP0 0xc138 9972246da4SFelipe Balbi #define DWC3_GPRTBIMAP1 0xc13c 10072246da4SFelipe Balbi #define DWC3_GHWPARAMS0 0xc140 10172246da4SFelipe Balbi #define DWC3_GHWPARAMS1 0xc144 10272246da4SFelipe Balbi #define DWC3_GHWPARAMS2 0xc148 10372246da4SFelipe Balbi #define DWC3_GHWPARAMS3 0xc14c 10472246da4SFelipe Balbi #define DWC3_GHWPARAMS4 0xc150 10572246da4SFelipe Balbi #define DWC3_GHWPARAMS5 0xc154 10672246da4SFelipe Balbi #define DWC3_GHWPARAMS6 0xc158 10772246da4SFelipe Balbi #define DWC3_GHWPARAMS7 0xc15c 10872246da4SFelipe Balbi #define DWC3_GDBGFIFOSPACE 0xc160 10972246da4SFelipe Balbi #define DWC3_GDBGLTSSM 0xc164 11072246da4SFelipe Balbi #define DWC3_GPRTBIMAP_HS0 0xc180 11172246da4SFelipe Balbi #define DWC3_GPRTBIMAP_HS1 0xc184 11272246da4SFelipe Balbi #define DWC3_GPRTBIMAP_FS0 0xc188 11372246da4SFelipe Balbi #define DWC3_GPRTBIMAP_FS1 0xc18c 11406281d46SJohn Youn #define DWC3_GUCTL2 0xc19c 11572246da4SFelipe Balbi 116690fb371SJohn Youn #define DWC3_VER_NUMBER 0xc1a0 117690fb371SJohn Youn #define DWC3_VER_TYPE 0xc1a4 118690fb371SJohn Youn 1198261bd4eSRoger Quadros #define DWC3_GUSB2PHYCFG(n) (0xc200 + ((n) * 0x04)) 1208261bd4eSRoger Quadros #define DWC3_GUSB2I2CCTL(n) (0xc240 + ((n) * 0x04)) 12172246da4SFelipe Balbi 1228261bd4eSRoger Quadros #define DWC3_GUSB2PHYACC(n) (0xc280 + ((n) * 0x04)) 12372246da4SFelipe Balbi 1248261bd4eSRoger Quadros #define DWC3_GUSB3PIPECTL(n) (0xc2c0 + ((n) * 0x04)) 12572246da4SFelipe Balbi 1268261bd4eSRoger Quadros #define DWC3_GTXFIFOSIZ(n) (0xc300 + ((n) * 0x04)) 1278261bd4eSRoger Quadros #define DWC3_GRXFIFOSIZ(n) (0xc380 + ((n) * 0x04)) 12872246da4SFelipe Balbi 1298261bd4eSRoger Quadros #define DWC3_GEVNTADRLO(n) (0xc400 + ((n) * 0x10)) 1308261bd4eSRoger Quadros #define DWC3_GEVNTADRHI(n) (0xc404 + ((n) * 0x10)) 1318261bd4eSRoger Quadros #define DWC3_GEVNTSIZ(n) (0xc408 + ((n) * 0x10)) 1328261bd4eSRoger Quadros #define DWC3_GEVNTCOUNT(n) (0xc40c + ((n) * 0x10)) 13372246da4SFelipe Balbi 13472246da4SFelipe Balbi #define DWC3_GHWPARAMS8 0xc600 135db2be4e9SNikhil Badola #define DWC3_GFLADJ 0xc630 13672246da4SFelipe Balbi 13772246da4SFelipe Balbi /* Device Registers */ 13872246da4SFelipe Balbi #define DWC3_DCFG 0xc700 13972246da4SFelipe Balbi #define DWC3_DCTL 0xc704 14072246da4SFelipe Balbi #define DWC3_DEVTEN 0xc708 14172246da4SFelipe Balbi #define DWC3_DSTS 0xc70c 14272246da4SFelipe Balbi #define DWC3_DGCMDPAR 0xc710 14372246da4SFelipe Balbi #define DWC3_DGCMD 0xc714 14472246da4SFelipe Balbi #define DWC3_DALEPENA 0xc720 1452eb88016SFelipe Balbi 1468261bd4eSRoger Quadros #define DWC3_DEP_BASE(n) (0xc800 + ((n) * 0x10)) 1472eb88016SFelipe Balbi #define DWC3_DEPCMDPAR2 0x00 1482eb88016SFelipe Balbi #define DWC3_DEPCMDPAR1 0x04 1492eb88016SFelipe Balbi #define DWC3_DEPCMDPAR0 0x08 1502eb88016SFelipe Balbi #define DWC3_DEPCMD 0x0c 15172246da4SFelipe Balbi 1528261bd4eSRoger Quadros #define DWC3_DEV_IMOD(n) (0xca00 + ((n) * 0x4)) 153cf40b86bSJohn Youn 15472246da4SFelipe Balbi /* OTG Registers */ 15572246da4SFelipe Balbi #define DWC3_OCFG 0xcc00 15672246da4SFelipe Balbi #define DWC3_OCTL 0xcc04 157d4436c3aSGeorge Cherian #define DWC3_OEVT 0xcc08 158d4436c3aSGeorge Cherian #define DWC3_OEVTEN 0xcc0C 159d4436c3aSGeorge Cherian #define DWC3_OSTS 0xcc10 16072246da4SFelipe Balbi 16172246da4SFelipe Balbi /* Bit fields */ 16272246da4SFelipe Balbi 163cf6d867dSFelipe Balbi /* Global Debug Queue/FIFO Space Available Register */ 164cf6d867dSFelipe Balbi #define DWC3_GDBGFIFOSPACE_NUM(n) ((n) & 0x1f) 165cf6d867dSFelipe Balbi #define DWC3_GDBGFIFOSPACE_TYPE(n) (((n) << 5) & 0x1e0) 166cf6d867dSFelipe Balbi #define DWC3_GDBGFIFOSPACE_SPACE_AVAILABLE(n) (((n) >> 16) & 0xffff) 167cf6d867dSFelipe Balbi 168cf6d867dSFelipe Balbi #define DWC3_TXFIFOQ 1 169cf6d867dSFelipe Balbi #define DWC3_RXFIFOQ 3 170cf6d867dSFelipe Balbi #define DWC3_TXREQQ 5 171cf6d867dSFelipe Balbi #define DWC3_RXREQQ 7 172cf6d867dSFelipe Balbi #define DWC3_RXINFOQ 9 173cf6d867dSFelipe Balbi #define DWC3_DESCFETCHQ 13 174cf6d867dSFelipe Balbi #define DWC3_EVENTQ 15 175cf6d867dSFelipe Balbi 1762a58f9c1SFelipe Balbi /* Global RX Threshold Configuration Register */ 1772a58f9c1SFelipe Balbi #define DWC3_GRXTHRCFG_MAXRXBURSTSIZE(n) (((n) & 0x1f) << 19) 1782a58f9c1SFelipe Balbi #define DWC3_GRXTHRCFG_RXPKTCNT(n) (((n) & 0xf) << 24) 1792a58f9c1SFelipe Balbi #define DWC3_GRXTHRCFG_PKTCNTSEL (1 << 29) 1802a58f9c1SFelipe Balbi 18172246da4SFelipe Balbi /* Global Configuration Register */ 1821d046793SPaul Zimmerman #define DWC3_GCTL_PWRDNSCALE(n) ((n) << 19) 183f4aadbe4SFelipe Balbi #define DWC3_GCTL_U2RSTECN (1 << 16) 1841d046793SPaul Zimmerman #define DWC3_GCTL_RAMCLKSEL(x) (((x) & DWC3_GCTL_CLK_MASK) << 6) 18572246da4SFelipe Balbi #define DWC3_GCTL_CLK_BUS (0) 18672246da4SFelipe Balbi #define DWC3_GCTL_CLK_PIPE (1) 18772246da4SFelipe Balbi #define DWC3_GCTL_CLK_PIPEHALF (2) 18872246da4SFelipe Balbi #define DWC3_GCTL_CLK_MASK (3) 18972246da4SFelipe Balbi 1900b9fe32dSFelipe Balbi #define DWC3_GCTL_PRTCAP(n) (((n) & (3 << 12)) >> 12) 1911d046793SPaul Zimmerman #define DWC3_GCTL_PRTCAPDIR(n) ((n) << 12) 19272246da4SFelipe Balbi #define DWC3_GCTL_PRTCAP_HOST 1 19372246da4SFelipe Balbi #define DWC3_GCTL_PRTCAP_DEVICE 2 19472246da4SFelipe Balbi #define DWC3_GCTL_PRTCAP_OTG 3 19572246da4SFelipe Balbi 19672246da4SFelipe Balbi #define DWC3_GCTL_CORESOFTRESET (1 << 11) 197183ca111SFelipe Balbi #define DWC3_GCTL_SOFITPSYNC (1 << 10) 1981d046793SPaul Zimmerman #define DWC3_GCTL_SCALEDOWN(n) ((n) << 4) 1993e87c42aSPaul Zimmerman #define DWC3_GCTL_SCALEDOWN_MASK DWC3_GCTL_SCALEDOWN(3) 20072246da4SFelipe Balbi #define DWC3_GCTL_DISSCRAMBLE (1 << 3) 2019a5b2f31SHuang Rui #define DWC3_GCTL_U2EXIT_LFPS (1 << 2) 2022c61a8efSPaul Zimmerman #define DWC3_GCTL_GBLHIBERNATIONEN (1 << 1) 203aabb7075SFelipe Balbi #define DWC3_GCTL_DSBLCLKGTNG (1 << 0) 20472246da4SFelipe Balbi 2050bb39ca1SJohn Youn /* Global User Control 1 Register */ 2060bb39ca1SJohn Youn #define DWC3_GUCTL1_DEV_L1_EXIT_BY_HW (1 << 24) 2070bb39ca1SJohn Youn 20872246da4SFelipe Balbi /* Global USB2 PHY Configuration Register */ 20972246da4SFelipe Balbi #define DWC3_GUSB2PHYCFG_PHYSOFTRST (1 << 31) 21016199f33SWilliam Wu #define DWC3_GUSB2PHYCFG_U2_FREECLK_EXISTS (1 << 30) 21172246da4SFelipe Balbi #define DWC3_GUSB2PHYCFG_SUSPHY (1 << 6) 212f699b947SHeikki Krogerus #define DWC3_GUSB2PHYCFG_ULPI_UTMI (1 << 4) 213ec791d14SJohn Youn #define DWC3_GUSB2PHYCFG_ENBLSLPM (1 << 8) 21432f2ed86SWilliam Wu #define DWC3_GUSB2PHYCFG_PHYIF(n) (n << 3) 21532f2ed86SWilliam Wu #define DWC3_GUSB2PHYCFG_PHYIF_MASK DWC3_GUSB2PHYCFG_PHYIF(1) 21632f2ed86SWilliam Wu #define DWC3_GUSB2PHYCFG_USBTRDTIM(n) (n << 10) 21732f2ed86SWilliam Wu #define DWC3_GUSB2PHYCFG_USBTRDTIM_MASK DWC3_GUSB2PHYCFG_USBTRDTIM(0xf) 21832f2ed86SWilliam Wu #define USBTRDTIM_UTMI_8_BIT 9 21932f2ed86SWilliam Wu #define USBTRDTIM_UTMI_16_BIT 5 22032f2ed86SWilliam Wu #define UTMI_PHYIF_16_BIT 1 22132f2ed86SWilliam Wu #define UTMI_PHYIF_8_BIT 0 22272246da4SFelipe Balbi 223b5699eeeSHeikki Krogerus /* Global USB2 PHY Vendor Control Register */ 224b5699eeeSHeikki Krogerus #define DWC3_GUSB2PHYACC_NEWREGREQ (1 << 25) 225b5699eeeSHeikki Krogerus #define DWC3_GUSB2PHYACC_BUSY (1 << 23) 226b5699eeeSHeikki Krogerus #define DWC3_GUSB2PHYACC_WRITE (1 << 22) 227b5699eeeSHeikki Krogerus #define DWC3_GUSB2PHYACC_ADDR(n) (n << 16) 228b5699eeeSHeikki Krogerus #define DWC3_GUSB2PHYACC_EXTEND_ADDR(n) (n << 8) 229b5699eeeSHeikki Krogerus #define DWC3_GUSB2PHYACC_DATA(n) (n & 0xff) 230b5699eeeSHeikki Krogerus 23172246da4SFelipe Balbi /* Global USB3 PIPE Control Register */ 23272246da4SFelipe Balbi #define DWC3_GUSB3PIPECTL_PHYSOFTRST (1 << 31) 233b5a65c40SHuang Rui #define DWC3_GUSB3PIPECTL_U2SSINP3OK (1 << 29) 234e58dd357SRajesh Bhagat #define DWC3_GUSB3PIPECTL_DISRXDETINP3 (1 << 28) 2351966b865SFelipe Balbi #define DWC3_GUSB3PIPECTL_UX_EXIT_PX (1 << 27) 236df31f5b3SHuang Rui #define DWC3_GUSB3PIPECTL_REQP1P2P3 (1 << 24) 237a2a1d0f5SHuang Rui #define DWC3_GUSB3PIPECTL_DEP1P2P3(n) ((n) << 19) 238a2a1d0f5SHuang Rui #define DWC3_GUSB3PIPECTL_DEP1P2P3_MASK DWC3_GUSB3PIPECTL_DEP1P2P3(7) 239a2a1d0f5SHuang Rui #define DWC3_GUSB3PIPECTL_DEP1P2P3_EN DWC3_GUSB3PIPECTL_DEP1P2P3(1) 24041c06ffdSHuang Rui #define DWC3_GUSB3PIPECTL_DEPOCHANGE (1 << 18) 24172246da4SFelipe Balbi #define DWC3_GUSB3PIPECTL_SUSPHY (1 << 17) 242fb67afcaSHuang Rui #define DWC3_GUSB3PIPECTL_LFPSFILT (1 << 9) 24314f4ac53SHuang Rui #define DWC3_GUSB3PIPECTL_RX_DETOPOLL (1 << 8) 2446b6a0c9aSHuang Rui #define DWC3_GUSB3PIPECTL_TX_DEEPH_MASK DWC3_GUSB3PIPECTL_TX_DEEPH(3) 2456b6a0c9aSHuang Rui #define DWC3_GUSB3PIPECTL_TX_DEEPH(n) ((n) << 1) 24672246da4SFelipe Balbi 247457e84b6SFelipe Balbi /* Global TX Fifo Size Register */ 248457e84b6SFelipe Balbi #define DWC3_GTXFIFOSIZ_TXFDEF(n) ((n) & 0xffff) 249457e84b6SFelipe Balbi #define DWC3_GTXFIFOSIZ_TXFSTADDR(n) ((n) & 0xffff0000) 250457e84b6SFelipe Balbi 25168d6a01bSFelipe Balbi /* Global Event Size Registers */ 25268d6a01bSFelipe Balbi #define DWC3_GEVNTSIZ_INTMASK (1 << 31) 25368d6a01bSFelipe Balbi #define DWC3_GEVNTSIZ_SIZE(n) ((n) & 0xffff) 25468d6a01bSFelipe Balbi 2554e99472bSFelipe Balbi /* Global HWPARAMS0 Register */ 2569d6173e1SThinh Nguyen #define DWC3_GHWPARAMS0_MODE(n) ((n) & 0x3) 2579d6173e1SThinh Nguyen #define DWC3_GHWPARAMS0_MODE_GADGET 0 2589d6173e1SThinh Nguyen #define DWC3_GHWPARAMS0_MODE_HOST 1 2599d6173e1SThinh Nguyen #define DWC3_GHWPARAMS0_MODE_DRD 2 2604e99472bSFelipe Balbi #define DWC3_GHWPARAMS0_MBUS_TYPE(n) (((n) >> 3) & 0x7) 2614e99472bSFelipe Balbi #define DWC3_GHWPARAMS0_SBUS_TYPE(n) (((n) >> 6) & 0x3) 2624e99472bSFelipe Balbi #define DWC3_GHWPARAMS0_MDWIDTH(n) (((n) >> 8) & 0xff) 2634e99472bSFelipe Balbi #define DWC3_GHWPARAMS0_SDWIDTH(n) (((n) >> 16) & 0xff) 2644e99472bSFelipe Balbi #define DWC3_GHWPARAMS0_AWIDTH(n) (((n) >> 24) & 0xff) 2654e99472bSFelipe Balbi 266aabb7075SFelipe Balbi /* Global HWPARAMS1 Register */ 2671d046793SPaul Zimmerman #define DWC3_GHWPARAMS1_EN_PWROPT(n) (((n) & (3 << 24)) >> 24) 268aabb7075SFelipe Balbi #define DWC3_GHWPARAMS1_EN_PWROPT_NO 0 269aabb7075SFelipe Balbi #define DWC3_GHWPARAMS1_EN_PWROPT_CLK 1 2702c61a8efSPaul Zimmerman #define DWC3_GHWPARAMS1_EN_PWROPT_HIB 2 2712c61a8efSPaul Zimmerman #define DWC3_GHWPARAMS1_PWROPT(n) ((n) << 24) 2722c61a8efSPaul Zimmerman #define DWC3_GHWPARAMS1_PWROPT_MASK DWC3_GHWPARAMS1_PWROPT(3) 2732c61a8efSPaul Zimmerman 2740e1e5c47SPaul Zimmerman /* Global HWPARAMS3 Register */ 2750e1e5c47SPaul Zimmerman #define DWC3_GHWPARAMS3_SSPHY_IFC(n) ((n) & 3) 2760e1e5c47SPaul Zimmerman #define DWC3_GHWPARAMS3_SSPHY_IFC_DIS 0 2771f38f88aSJohn Youn #define DWC3_GHWPARAMS3_SSPHY_IFC_GEN1 1 2781f38f88aSJohn Youn #define DWC3_GHWPARAMS3_SSPHY_IFC_GEN2 2 /* DWC_usb31 only */ 2790e1e5c47SPaul Zimmerman #define DWC3_GHWPARAMS3_HSPHY_IFC(n) (((n) & (3 << 2)) >> 2) 2800e1e5c47SPaul Zimmerman #define DWC3_GHWPARAMS3_HSPHY_IFC_DIS 0 2810e1e5c47SPaul Zimmerman #define DWC3_GHWPARAMS3_HSPHY_IFC_UTMI 1 2820e1e5c47SPaul Zimmerman #define DWC3_GHWPARAMS3_HSPHY_IFC_ULPI 2 2830e1e5c47SPaul Zimmerman #define DWC3_GHWPARAMS3_HSPHY_IFC_UTMI_ULPI 3 2840e1e5c47SPaul Zimmerman #define DWC3_GHWPARAMS3_FSPHY_IFC(n) (((n) & (3 << 4)) >> 4) 2850e1e5c47SPaul Zimmerman #define DWC3_GHWPARAMS3_FSPHY_IFC_DIS 0 2860e1e5c47SPaul Zimmerman #define DWC3_GHWPARAMS3_FSPHY_IFC_ENA 1 2870e1e5c47SPaul Zimmerman 2882c61a8efSPaul Zimmerman /* Global HWPARAMS4 Register */ 2892c61a8efSPaul Zimmerman #define DWC3_GHWPARAMS4_HIBER_SCRATCHBUFS(n) (((n) & (0x0f << 13)) >> 13) 2902c61a8efSPaul Zimmerman #define DWC3_MAX_HIBER_SCRATCHBUFS 15 291aabb7075SFelipe Balbi 292946bd579SHuang Rui /* Global HWPARAMS6 Register */ 293946bd579SHuang Rui #define DWC3_GHWPARAMS6_EN_FPGA (1 << 7) 294946bd579SHuang Rui 2954e99472bSFelipe Balbi /* Global HWPARAMS7 Register */ 2964e99472bSFelipe Balbi #define DWC3_GHWPARAMS7_RAM1_DEPTH(n) ((n) & 0xffff) 2974e99472bSFelipe Balbi #define DWC3_GHWPARAMS7_RAM2_DEPTH(n) (((n) >> 16) & 0xffff) 2984e99472bSFelipe Balbi 299db2be4e9SNikhil Badola /* Global Frame Length Adjustment Register */ 300db2be4e9SNikhil Badola #define DWC3_GFLADJ_30MHZ_SDBND_SEL (1 << 7) 301db2be4e9SNikhil Badola #define DWC3_GFLADJ_30MHZ_MASK 0x3f 302db2be4e9SNikhil Badola 30306281d46SJohn Youn /* Global User Control Register 2 */ 30406281d46SJohn Youn #define DWC3_GUCTL2_RST_ACTBITLATER (1 << 14) 30506281d46SJohn Youn 30672246da4SFelipe Balbi /* Device Configuration Register */ 30772246da4SFelipe Balbi #define DWC3_DCFG_DEVADDR(addr) ((addr) << 3) 30872246da4SFelipe Balbi #define DWC3_DCFG_DEVADDR_MASK DWC3_DCFG_DEVADDR(0x7f) 30972246da4SFelipe Balbi 31072246da4SFelipe Balbi #define DWC3_DCFG_SPEED_MASK (7 << 0) 3111f38f88aSJohn Youn #define DWC3_DCFG_SUPERSPEED_PLUS (5 << 0) /* DWC_usb31 only */ 31272246da4SFelipe Balbi #define DWC3_DCFG_SUPERSPEED (4 << 0) 31372246da4SFelipe Balbi #define DWC3_DCFG_HIGHSPEED (0 << 0) 3149418ee15SRoger Quadros #define DWC3_DCFG_FULLSPEED (1 << 0) 31572246da4SFelipe Balbi #define DWC3_DCFG_LOWSPEED (2 << 0) 31672246da4SFelipe Balbi 317676e3497SFelipe Balbi #define DWC3_DCFG_NUMP_SHIFT 17 31897398612SDan Carpenter #define DWC3_DCFG_NUMP(n) (((n) >> DWC3_DCFG_NUMP_SHIFT) & 0x1f) 319676e3497SFelipe Balbi #define DWC3_DCFG_NUMP_MASK (0x1f << DWC3_DCFG_NUMP_SHIFT) 3202c61a8efSPaul Zimmerman #define DWC3_DCFG_LPM_CAP (1 << 22) 3212c61a8efSPaul Zimmerman 32272246da4SFelipe Balbi /* Device Control Register */ 32372246da4SFelipe Balbi #define DWC3_DCTL_RUN_STOP (1 << 31) 32472246da4SFelipe Balbi #define DWC3_DCTL_CSFTRST (1 << 30) 32572246da4SFelipe Balbi #define DWC3_DCTL_LSFTRST (1 << 29) 32672246da4SFelipe Balbi 32772246da4SFelipe Balbi #define DWC3_DCTL_HIRD_THRES_MASK (0x1f << 24) 3287e39b817SPratyush Anand #define DWC3_DCTL_HIRD_THRES(n) ((n) << 24) 32972246da4SFelipe Balbi 33072246da4SFelipe Balbi #define DWC3_DCTL_APPL1RES (1 << 23) 33172246da4SFelipe Balbi 3322c61a8efSPaul Zimmerman /* These apply for core versions 1.87a and earlier */ 3338db7ed15SFelipe Balbi #define DWC3_DCTL_TRGTULST_MASK (0x0f << 17) 3348db7ed15SFelipe Balbi #define DWC3_DCTL_TRGTULST(n) ((n) << 17) 3358db7ed15SFelipe Balbi #define DWC3_DCTL_TRGTULST_U2 (DWC3_DCTL_TRGTULST(2)) 3368db7ed15SFelipe Balbi #define DWC3_DCTL_TRGTULST_U3 (DWC3_DCTL_TRGTULST(3)) 3378db7ed15SFelipe Balbi #define DWC3_DCTL_TRGTULST_SS_DIS (DWC3_DCTL_TRGTULST(4)) 3388db7ed15SFelipe Balbi #define DWC3_DCTL_TRGTULST_RX_DET (DWC3_DCTL_TRGTULST(5)) 3398db7ed15SFelipe Balbi #define DWC3_DCTL_TRGTULST_SS_INACT (DWC3_DCTL_TRGTULST(6)) 3408db7ed15SFelipe Balbi 3412c61a8efSPaul Zimmerman /* These apply for core versions 1.94a and later */ 34280caf7d2SHuang Rui #define DWC3_DCTL_LPM_ERRATA_MASK DWC3_DCTL_LPM_ERRATA(0xf) 34380caf7d2SHuang Rui #define DWC3_DCTL_LPM_ERRATA(n) ((n) << 20) 34480caf7d2SHuang Rui 3452c61a8efSPaul Zimmerman #define DWC3_DCTL_KEEP_CONNECT (1 << 19) 3462c61a8efSPaul Zimmerman #define DWC3_DCTL_L1_HIBER_EN (1 << 18) 3472c61a8efSPaul Zimmerman #define DWC3_DCTL_CRS (1 << 17) 3482c61a8efSPaul Zimmerman #define DWC3_DCTL_CSS (1 << 16) 3492c61a8efSPaul Zimmerman 35072246da4SFelipe Balbi #define DWC3_DCTL_INITU2ENA (1 << 12) 35172246da4SFelipe Balbi #define DWC3_DCTL_ACCEPTU2ENA (1 << 11) 35272246da4SFelipe Balbi #define DWC3_DCTL_INITU1ENA (1 << 10) 35372246da4SFelipe Balbi #define DWC3_DCTL_ACCEPTU1ENA (1 << 9) 35472246da4SFelipe Balbi #define DWC3_DCTL_TSTCTRL_MASK (0xf << 1) 35572246da4SFelipe Balbi 35672246da4SFelipe Balbi #define DWC3_DCTL_ULSTCHNGREQ_MASK (0x0f << 5) 35772246da4SFelipe Balbi #define DWC3_DCTL_ULSTCHNGREQ(n) (((n) << 5) & DWC3_DCTL_ULSTCHNGREQ_MASK) 35872246da4SFelipe Balbi 35972246da4SFelipe Balbi #define DWC3_DCTL_ULSTCHNG_NO_ACTION (DWC3_DCTL_ULSTCHNGREQ(0)) 36072246da4SFelipe Balbi #define DWC3_DCTL_ULSTCHNG_SS_DISABLED (DWC3_DCTL_ULSTCHNGREQ(4)) 36172246da4SFelipe Balbi #define DWC3_DCTL_ULSTCHNG_RX_DETECT (DWC3_DCTL_ULSTCHNGREQ(5)) 36272246da4SFelipe Balbi #define DWC3_DCTL_ULSTCHNG_SS_INACTIVE (DWC3_DCTL_ULSTCHNGREQ(6)) 36372246da4SFelipe Balbi #define DWC3_DCTL_ULSTCHNG_RECOVERY (DWC3_DCTL_ULSTCHNGREQ(8)) 36472246da4SFelipe Balbi #define DWC3_DCTL_ULSTCHNG_COMPLIANCE (DWC3_DCTL_ULSTCHNGREQ(10)) 36572246da4SFelipe Balbi #define DWC3_DCTL_ULSTCHNG_LOOPBACK (DWC3_DCTL_ULSTCHNGREQ(11)) 36672246da4SFelipe Balbi 36772246da4SFelipe Balbi /* Device Event Enable Register */ 36872246da4SFelipe Balbi #define DWC3_DEVTEN_VNDRDEVTSTRCVEDEN (1 << 12) 36972246da4SFelipe Balbi #define DWC3_DEVTEN_EVNTOVERFLOWEN (1 << 11) 37072246da4SFelipe Balbi #define DWC3_DEVTEN_CMDCMPLTEN (1 << 10) 37172246da4SFelipe Balbi #define DWC3_DEVTEN_ERRTICERREN (1 << 9) 37272246da4SFelipe Balbi #define DWC3_DEVTEN_SOFEN (1 << 7) 37372246da4SFelipe Balbi #define DWC3_DEVTEN_EOPFEN (1 << 6) 3742c61a8efSPaul Zimmerman #define DWC3_DEVTEN_HIBERNATIONREQEVTEN (1 << 5) 37572246da4SFelipe Balbi #define DWC3_DEVTEN_WKUPEVTEN (1 << 4) 37672246da4SFelipe Balbi #define DWC3_DEVTEN_ULSTCNGEN (1 << 3) 37772246da4SFelipe Balbi #define DWC3_DEVTEN_CONNECTDONEEN (1 << 2) 37872246da4SFelipe Balbi #define DWC3_DEVTEN_USBRSTEN (1 << 1) 37972246da4SFelipe Balbi #define DWC3_DEVTEN_DISCONNEVTEN (1 << 0) 38072246da4SFelipe Balbi 38172246da4SFelipe Balbi /* Device Status Register */ 3822c61a8efSPaul Zimmerman #define DWC3_DSTS_DCNRD (1 << 29) 3832c61a8efSPaul Zimmerman 3842c61a8efSPaul Zimmerman /* This applies for core versions 1.87a and earlier */ 38572246da4SFelipe Balbi #define DWC3_DSTS_PWRUPREQ (1 << 24) 3862c61a8efSPaul Zimmerman 3872c61a8efSPaul Zimmerman /* These apply for core versions 1.94a and later */ 3882c61a8efSPaul Zimmerman #define DWC3_DSTS_RSS (1 << 25) 3892c61a8efSPaul Zimmerman #define DWC3_DSTS_SSS (1 << 24) 3902c61a8efSPaul Zimmerman 39172246da4SFelipe Balbi #define DWC3_DSTS_COREIDLE (1 << 23) 39272246da4SFelipe Balbi #define DWC3_DSTS_DEVCTRLHLT (1 << 22) 39372246da4SFelipe Balbi 39472246da4SFelipe Balbi #define DWC3_DSTS_USBLNKST_MASK (0x0f << 18) 39572246da4SFelipe Balbi #define DWC3_DSTS_USBLNKST(n) (((n) & DWC3_DSTS_USBLNKST_MASK) >> 18) 39672246da4SFelipe Balbi 39772246da4SFelipe Balbi #define DWC3_DSTS_RXFIFOEMPTY (1 << 17) 39872246da4SFelipe Balbi 399d05b8182SPratyush Anand #define DWC3_DSTS_SOFFN_MASK (0x3fff << 3) 40072246da4SFelipe Balbi #define DWC3_DSTS_SOFFN(n) (((n) & DWC3_DSTS_SOFFN_MASK) >> 3) 40172246da4SFelipe Balbi 40272246da4SFelipe Balbi #define DWC3_DSTS_CONNECTSPD (7 << 0) 40372246da4SFelipe Balbi 4041f38f88aSJohn Youn #define DWC3_DSTS_SUPERSPEED_PLUS (5 << 0) /* DWC_usb31 only */ 40572246da4SFelipe Balbi #define DWC3_DSTS_SUPERSPEED (4 << 0) 40672246da4SFelipe Balbi #define DWC3_DSTS_HIGHSPEED (0 << 0) 4079418ee15SRoger Quadros #define DWC3_DSTS_FULLSPEED (1 << 0) 40872246da4SFelipe Balbi #define DWC3_DSTS_LOWSPEED (2 << 0) 40972246da4SFelipe Balbi 41072246da4SFelipe Balbi /* Device Generic Command Register */ 41172246da4SFelipe Balbi #define DWC3_DGCMD_SET_LMP 0x01 41272246da4SFelipe Balbi #define DWC3_DGCMD_SET_PERIODIC_PAR 0x02 41372246da4SFelipe Balbi #define DWC3_DGCMD_XMIT_FUNCTION 0x03 4142c61a8efSPaul Zimmerman 4152c61a8efSPaul Zimmerman /* These apply for core versions 1.94a and later */ 4162c61a8efSPaul Zimmerman #define DWC3_DGCMD_SET_SCRATCHPAD_ADDR_LO 0x04 4172c61a8efSPaul Zimmerman #define DWC3_DGCMD_SET_SCRATCHPAD_ADDR_HI 0x05 4182c61a8efSPaul Zimmerman 41972246da4SFelipe Balbi #define DWC3_DGCMD_SELECTED_FIFO_FLUSH 0x09 42072246da4SFelipe Balbi #define DWC3_DGCMD_ALL_FIFO_FLUSH 0x0a 42172246da4SFelipe Balbi #define DWC3_DGCMD_SET_ENDPOINT_NRDY 0x0c 42272246da4SFelipe Balbi #define DWC3_DGCMD_RUN_SOC_BUS_LOOPBACK 0x10 42372246da4SFelipe Balbi 424459e210cSSubbaraya Sundeep Bhatta #define DWC3_DGCMD_STATUS(n) (((n) >> 12) & 0x0F) 425b09bb642SFelipe Balbi #define DWC3_DGCMD_CMDACT (1 << 10) 4262c61a8efSPaul Zimmerman #define DWC3_DGCMD_CMDIOC (1 << 8) 4272c61a8efSPaul Zimmerman 4282c61a8efSPaul Zimmerman /* Device Generic Command Parameter Register */ 4292c61a8efSPaul Zimmerman #define DWC3_DGCMDPAR_FORCE_LINKPM_ACCEPT (1 << 0) 4302c61a8efSPaul Zimmerman #define DWC3_DGCMDPAR_FIFO_NUM(n) ((n) << 0) 4312c61a8efSPaul Zimmerman #define DWC3_DGCMDPAR_RX_FIFO (0 << 5) 4322c61a8efSPaul Zimmerman #define DWC3_DGCMDPAR_TX_FIFO (1 << 5) 4332c61a8efSPaul Zimmerman #define DWC3_DGCMDPAR_LOOPBACK_DIS (0 << 0) 4342c61a8efSPaul Zimmerman #define DWC3_DGCMDPAR_LOOPBACK_ENA (1 << 0) 435b09bb642SFelipe Balbi 43672246da4SFelipe Balbi /* Device Endpoint Command Register */ 43772246da4SFelipe Balbi #define DWC3_DEPCMD_PARAM_SHIFT 16 4381d046793SPaul Zimmerman #define DWC3_DEPCMD_PARAM(x) ((x) << DWC3_DEPCMD_PARAM_SHIFT) 4391d046793SPaul Zimmerman #define DWC3_DEPCMD_GET_RSC_IDX(x) (((x) >> DWC3_DEPCMD_PARAM_SHIFT) & 0x7f) 440459e210cSSubbaraya Sundeep Bhatta #define DWC3_DEPCMD_STATUS(x) (((x) >> 12) & 0x0F) 44172246da4SFelipe Balbi #define DWC3_DEPCMD_HIPRI_FORCERM (1 << 11) 44250c763f8SJohn Youn #define DWC3_DEPCMD_CLEARPENDIN (1 << 11) 44372246da4SFelipe Balbi #define DWC3_DEPCMD_CMDACT (1 << 10) 44472246da4SFelipe Balbi #define DWC3_DEPCMD_CMDIOC (1 << 8) 44572246da4SFelipe Balbi 44672246da4SFelipe Balbi #define DWC3_DEPCMD_DEPSTARTCFG (0x09 << 0) 44772246da4SFelipe Balbi #define DWC3_DEPCMD_ENDTRANSFER (0x08 << 0) 44872246da4SFelipe Balbi #define DWC3_DEPCMD_UPDATETRANSFER (0x07 << 0) 44972246da4SFelipe Balbi #define DWC3_DEPCMD_STARTTRANSFER (0x06 << 0) 45072246da4SFelipe Balbi #define DWC3_DEPCMD_CLEARSTALL (0x05 << 0) 45172246da4SFelipe Balbi #define DWC3_DEPCMD_SETSTALL (0x04 << 0) 4522c61a8efSPaul Zimmerman /* This applies for core versions 1.90a and earlier */ 45372246da4SFelipe Balbi #define DWC3_DEPCMD_GETSEQNUMBER (0x03 << 0) 4542c61a8efSPaul Zimmerman /* This applies for core versions 1.94a and later */ 4552c61a8efSPaul Zimmerman #define DWC3_DEPCMD_GETEPSTATE (0x03 << 0) 45672246da4SFelipe Balbi #define DWC3_DEPCMD_SETTRANSFRESOURCE (0x02 << 0) 45772246da4SFelipe Balbi #define DWC3_DEPCMD_SETEPCONFIG (0x01 << 0) 45872246da4SFelipe Balbi 4595999914fSFelipe Balbi #define DWC3_DEPCMD_CMD(x) ((x) & 0xf) 4605999914fSFelipe Balbi 46172246da4SFelipe Balbi /* The EP number goes 0..31 so ep0 is always out and ep1 is always in */ 4628261bd4eSRoger Quadros #define DWC3_DALEPENA_EP(n) (1 << (n)) 46372246da4SFelipe Balbi 46472246da4SFelipe Balbi #define DWC3_DEPCMD_TYPE_CONTROL 0 46572246da4SFelipe Balbi #define DWC3_DEPCMD_TYPE_ISOC 1 46672246da4SFelipe Balbi #define DWC3_DEPCMD_TYPE_BULK 2 46772246da4SFelipe Balbi #define DWC3_DEPCMD_TYPE_INTR 3 46872246da4SFelipe Balbi 469cf40b86bSJohn Youn #define DWC3_DEV_IMOD_COUNT_SHIFT 16 470cf40b86bSJohn Youn #define DWC3_DEV_IMOD_COUNT_MASK (0xffff << 16) 471cf40b86bSJohn Youn #define DWC3_DEV_IMOD_INTERVAL_SHIFT 0 472cf40b86bSJohn Youn #define DWC3_DEV_IMOD_INTERVAL_MASK (0xffff << 0) 473cf40b86bSJohn Youn 47472246da4SFelipe Balbi /* Structures */ 47572246da4SFelipe Balbi 476f6bafc6aSFelipe Balbi struct dwc3_trb; 47772246da4SFelipe Balbi 47872246da4SFelipe Balbi /** 47972246da4SFelipe Balbi * struct dwc3_event_buffer - Software event buffer representation 48072246da4SFelipe Balbi * @buf: _THE_ buffer 481d9fa4c63SJohn Youn * @cache: The buffer cache used in the threaded interrupt 48272246da4SFelipe Balbi * @length: size of this buffer 483abed4118SFelipe Balbi * @lpos: event offset 48460d04bbeSFelipe Balbi * @count: cache of last read event count register 485abed4118SFelipe Balbi * @flags: flags related to this event buffer 48672246da4SFelipe Balbi * @dma: dma_addr_t 48772246da4SFelipe Balbi * @dwc: pointer to DWC controller 48872246da4SFelipe Balbi */ 48972246da4SFelipe Balbi struct dwc3_event_buffer { 49072246da4SFelipe Balbi void *buf; 491d9fa4c63SJohn Youn void *cache; 49272246da4SFelipe Balbi unsigned length; 49372246da4SFelipe Balbi unsigned int lpos; 49460d04bbeSFelipe Balbi unsigned int count; 495abed4118SFelipe Balbi unsigned int flags; 496abed4118SFelipe Balbi 497abed4118SFelipe Balbi #define DWC3_EVENT_PENDING BIT(0) 49872246da4SFelipe Balbi 49972246da4SFelipe Balbi dma_addr_t dma; 50072246da4SFelipe Balbi 50172246da4SFelipe Balbi struct dwc3 *dwc; 50272246da4SFelipe Balbi }; 50372246da4SFelipe Balbi 50472246da4SFelipe Balbi #define DWC3_EP_FLAG_STALLED (1 << 0) 50572246da4SFelipe Balbi #define DWC3_EP_FLAG_WEDGED (1 << 1) 50672246da4SFelipe Balbi 50772246da4SFelipe Balbi #define DWC3_EP_DIRECTION_TX true 50872246da4SFelipe Balbi #define DWC3_EP_DIRECTION_RX false 50972246da4SFelipe Balbi 5108495036eSFelipe Balbi #define DWC3_TRB_NUM 256 51172246da4SFelipe Balbi 51272246da4SFelipe Balbi /** 51372246da4SFelipe Balbi * struct dwc3_ep - device side endpoint representation 51472246da4SFelipe Balbi * @endpoint: usb endpoint 515aa3342c8SFelipe Balbi * @pending_list: list of pending requests for this endpoint 516aa3342c8SFelipe Balbi * @started_list: list of started requests on this endpoint 51776a638f8SBaolin Wang * @wait_end_transfer: wait_queue_head_t for waiting on End Transfer complete 51874674cbfSFelipe Balbi * @lock: spinlock for endpoint request queue traversal 5192eb88016SFelipe Balbi * @regs: pointer to first endpoint register 52072246da4SFelipe Balbi * @trb_pool: array of transaction buffers 52172246da4SFelipe Balbi * @trb_pool_dma: dma address of @trb_pool 52253fd8818SFelipe Balbi * @trb_enqueue: enqueue 'pointer' into TRB array 52353fd8818SFelipe Balbi * @trb_dequeue: dequeue 'pointer' into TRB array 52472246da4SFelipe Balbi * @desc: usb_endpoint_descriptor pointer 52572246da4SFelipe Balbi * @dwc: pointer to DWC controller 5264cfcf876SPaul Zimmerman * @saved_state: ep state saved during hibernation 52772246da4SFelipe Balbi * @flags: endpoint flags (wedged, stalled, ...) 52872246da4SFelipe Balbi * @number: endpoint number (1 - 15) 52972246da4SFelipe Balbi * @type: set to bmAttributes & USB_ENDPOINT_XFERTYPE_MASK 530b4996a86SFelipe Balbi * @resource_index: Resource transfer index 531c75f52fbSHuang Rui * @interval: the interval on which the ISOC transfer is started 53268d34c8aSFelipe Balbi * @allocated_requests: number of requests allocated 53368d34c8aSFelipe Balbi * @queued_requests: number of requests queued for transfer 53472246da4SFelipe Balbi * @name: a human readable name e.g. ep1out-bulk 53572246da4SFelipe Balbi * @direction: true for TX, false for RX 536879631aaSFelipe Balbi * @stream_capable: true when streams are enabled 53772246da4SFelipe Balbi */ 53872246da4SFelipe Balbi struct dwc3_ep { 53972246da4SFelipe Balbi struct usb_ep endpoint; 540aa3342c8SFelipe Balbi struct list_head pending_list; 541aa3342c8SFelipe Balbi struct list_head started_list; 54272246da4SFelipe Balbi 54376a638f8SBaolin Wang wait_queue_head_t wait_end_transfer; 54476a638f8SBaolin Wang 54574674cbfSFelipe Balbi spinlock_t lock; 5462eb88016SFelipe Balbi void __iomem *regs; 5472eb88016SFelipe Balbi 548f6bafc6aSFelipe Balbi struct dwc3_trb *trb_pool; 54972246da4SFelipe Balbi dma_addr_t trb_pool_dma; 55072246da4SFelipe Balbi struct dwc3 *dwc; 55172246da4SFelipe Balbi 5524cfcf876SPaul Zimmerman u32 saved_state; 55372246da4SFelipe Balbi unsigned flags; 55472246da4SFelipe Balbi #define DWC3_EP_ENABLED (1 << 0) 55572246da4SFelipe Balbi #define DWC3_EP_STALL (1 << 1) 55672246da4SFelipe Balbi #define DWC3_EP_WEDGE (1 << 2) 55772246da4SFelipe Balbi #define DWC3_EP_BUSY (1 << 4) 55872246da4SFelipe Balbi #define DWC3_EP_PENDING_REQUEST (1 << 5) 559d6d6ec7bSPratyush Anand #define DWC3_EP_MISSED_ISOC (1 << 6) 56076a638f8SBaolin Wang #define DWC3_EP_END_TRANSFER_PENDING (1 << 7) 5616cb2e4e3SFelipe Balbi #define DWC3_EP_TRANSFER_STARTED (1 << 8) 56272246da4SFelipe Balbi 563984f66a6SFelipe Balbi /* This last one is specific to EP0 */ 564984f66a6SFelipe Balbi #define DWC3_EP0_DIR_IN (1 << 31) 565984f66a6SFelipe Balbi 566c28f8259SFelipe Balbi /* 567c28f8259SFelipe Balbi * IMPORTANT: we *know* we have 256 TRBs in our @trb_pool, so we will 568c28f8259SFelipe Balbi * use a u8 type here. If anybody decides to increase number of TRBs to 569c28f8259SFelipe Balbi * anything larger than 256 - I can't see why people would want to do 570c28f8259SFelipe Balbi * this though - then this type needs to be changed. 571c28f8259SFelipe Balbi * 572c28f8259SFelipe Balbi * By using u8 types we ensure that our % operator when incrementing 573c28f8259SFelipe Balbi * enqueue and dequeue get optimized away by the compiler. 574c28f8259SFelipe Balbi */ 575c28f8259SFelipe Balbi u8 trb_enqueue; 576c28f8259SFelipe Balbi u8 trb_dequeue; 577c28f8259SFelipe Balbi 57872246da4SFelipe Balbi u8 number; 57972246da4SFelipe Balbi u8 type; 580b4996a86SFelipe Balbi u8 resource_index; 58168d34c8aSFelipe Balbi u32 allocated_requests; 58268d34c8aSFelipe Balbi u32 queued_requests; 58372246da4SFelipe Balbi u32 interval; 58472246da4SFelipe Balbi 58572246da4SFelipe Balbi char name[20]; 58672246da4SFelipe Balbi 58772246da4SFelipe Balbi unsigned direction:1; 588879631aaSFelipe Balbi unsigned stream_capable:1; 58972246da4SFelipe Balbi }; 59072246da4SFelipe Balbi 59172246da4SFelipe Balbi enum dwc3_phy { 59272246da4SFelipe Balbi DWC3_PHY_UNKNOWN = 0, 59372246da4SFelipe Balbi DWC3_PHY_USB3, 59472246da4SFelipe Balbi DWC3_PHY_USB2, 59572246da4SFelipe Balbi }; 59672246da4SFelipe Balbi 597b53c772dSFelipe Balbi enum dwc3_ep0_next { 598b53c772dSFelipe Balbi DWC3_EP0_UNKNOWN = 0, 599b53c772dSFelipe Balbi DWC3_EP0_COMPLETE, 600b53c772dSFelipe Balbi DWC3_EP0_NRDY_DATA, 601b53c772dSFelipe Balbi DWC3_EP0_NRDY_STATUS, 602b53c772dSFelipe Balbi }; 603b53c772dSFelipe Balbi 60472246da4SFelipe Balbi enum dwc3_ep0_state { 60572246da4SFelipe Balbi EP0_UNCONNECTED = 0, 606c7fcdeb2SFelipe Balbi EP0_SETUP_PHASE, 607c7fcdeb2SFelipe Balbi EP0_DATA_PHASE, 608c7fcdeb2SFelipe Balbi EP0_STATUS_PHASE, 60972246da4SFelipe Balbi }; 61072246da4SFelipe Balbi 61172246da4SFelipe Balbi enum dwc3_link_state { 61272246da4SFelipe Balbi /* In SuperSpeed */ 61372246da4SFelipe Balbi DWC3_LINK_STATE_U0 = 0x00, /* in HS, means ON */ 61472246da4SFelipe Balbi DWC3_LINK_STATE_U1 = 0x01, 61572246da4SFelipe Balbi DWC3_LINK_STATE_U2 = 0x02, /* in HS, means SLEEP */ 61672246da4SFelipe Balbi DWC3_LINK_STATE_U3 = 0x03, /* in HS, means SUSPEND */ 61772246da4SFelipe Balbi DWC3_LINK_STATE_SS_DIS = 0x04, 61872246da4SFelipe Balbi DWC3_LINK_STATE_RX_DET = 0x05, /* in HS, means Early Suspend */ 61972246da4SFelipe Balbi DWC3_LINK_STATE_SS_INACT = 0x06, 62072246da4SFelipe Balbi DWC3_LINK_STATE_POLL = 0x07, 62172246da4SFelipe Balbi DWC3_LINK_STATE_RECOV = 0x08, 62272246da4SFelipe Balbi DWC3_LINK_STATE_HRESET = 0x09, 62372246da4SFelipe Balbi DWC3_LINK_STATE_CMPLY = 0x0a, 62472246da4SFelipe Balbi DWC3_LINK_STATE_LPBK = 0x0b, 6252c61a8efSPaul Zimmerman DWC3_LINK_STATE_RESET = 0x0e, 6262c61a8efSPaul Zimmerman DWC3_LINK_STATE_RESUME = 0x0f, 62772246da4SFelipe Balbi DWC3_LINK_STATE_MASK = 0x0f, 62872246da4SFelipe Balbi }; 62972246da4SFelipe Balbi 630f6bafc6aSFelipe Balbi /* TRB Length, PCM and Status */ 631f6bafc6aSFelipe Balbi #define DWC3_TRB_SIZE_MASK (0x00ffffff) 632f6bafc6aSFelipe Balbi #define DWC3_TRB_SIZE_LENGTH(n) ((n) & DWC3_TRB_SIZE_MASK) 633f6bafc6aSFelipe Balbi #define DWC3_TRB_SIZE_PCM1(n) (((n) & 0x03) << 24) 634389f2828SPratyush Anand #define DWC3_TRB_SIZE_TRBSTS(n) (((n) & (0x0f << 28)) >> 28) 63572246da4SFelipe Balbi 636f6bafc6aSFelipe Balbi #define DWC3_TRBSTS_OK 0 637f6bafc6aSFelipe Balbi #define DWC3_TRBSTS_MISSED_ISOC 1 638f6bafc6aSFelipe Balbi #define DWC3_TRBSTS_SETUP_PENDING 2 6392c61a8efSPaul Zimmerman #define DWC3_TRB_STS_XFER_IN_PROG 4 64072246da4SFelipe Balbi 641f6bafc6aSFelipe Balbi /* TRB Control */ 642f6bafc6aSFelipe Balbi #define DWC3_TRB_CTRL_HWO (1 << 0) 643f6bafc6aSFelipe Balbi #define DWC3_TRB_CTRL_LST (1 << 1) 644f6bafc6aSFelipe Balbi #define DWC3_TRB_CTRL_CHN (1 << 2) 645f6bafc6aSFelipe Balbi #define DWC3_TRB_CTRL_CSP (1 << 3) 646f6bafc6aSFelipe Balbi #define DWC3_TRB_CTRL_TRBCTL(n) (((n) & 0x3f) << 4) 647f6bafc6aSFelipe Balbi #define DWC3_TRB_CTRL_ISP_IMI (1 << 10) 648f6bafc6aSFelipe Balbi #define DWC3_TRB_CTRL_IOC (1 << 11) 649f6bafc6aSFelipe Balbi #define DWC3_TRB_CTRL_SID_SOFN(n) (((n) & 0xffff) << 14) 650f6bafc6aSFelipe Balbi 651b058f3e8SFelipe Balbi #define DWC3_TRBCTL_TYPE(n) ((n) & (0x3f << 4)) 652f6bafc6aSFelipe Balbi #define DWC3_TRBCTL_NORMAL DWC3_TRB_CTRL_TRBCTL(1) 653f6bafc6aSFelipe Balbi #define DWC3_TRBCTL_CONTROL_SETUP DWC3_TRB_CTRL_TRBCTL(2) 654f6bafc6aSFelipe Balbi #define DWC3_TRBCTL_CONTROL_STATUS2 DWC3_TRB_CTRL_TRBCTL(3) 655f6bafc6aSFelipe Balbi #define DWC3_TRBCTL_CONTROL_STATUS3 DWC3_TRB_CTRL_TRBCTL(4) 656f6bafc6aSFelipe Balbi #define DWC3_TRBCTL_CONTROL_DATA DWC3_TRB_CTRL_TRBCTL(5) 657f6bafc6aSFelipe Balbi #define DWC3_TRBCTL_ISOCHRONOUS_FIRST DWC3_TRB_CTRL_TRBCTL(6) 658f6bafc6aSFelipe Balbi #define DWC3_TRBCTL_ISOCHRONOUS DWC3_TRB_CTRL_TRBCTL(7) 659f6bafc6aSFelipe Balbi #define DWC3_TRBCTL_LINK_TRB DWC3_TRB_CTRL_TRBCTL(8) 66072246da4SFelipe Balbi 66172246da4SFelipe Balbi /** 662f6bafc6aSFelipe Balbi * struct dwc3_trb - transfer request block (hw format) 66372246da4SFelipe Balbi * @bpl: DW0-3 66472246da4SFelipe Balbi * @bph: DW4-7 66572246da4SFelipe Balbi * @size: DW8-B 66672246da4SFelipe Balbi * @trl: DWC-F 66772246da4SFelipe Balbi */ 668f6bafc6aSFelipe Balbi struct dwc3_trb { 669f6bafc6aSFelipe Balbi u32 bpl; 670f6bafc6aSFelipe Balbi u32 bph; 671f6bafc6aSFelipe Balbi u32 size; 672f6bafc6aSFelipe Balbi u32 ctrl; 67372246da4SFelipe Balbi } __packed; 67472246da4SFelipe Balbi 67572246da4SFelipe Balbi /** 676a3299499SFelipe Balbi * dwc3_hwparams - copy of HWPARAMS registers 677a3299499SFelipe Balbi * @hwparams0 - GHWPARAMS0 678a3299499SFelipe Balbi * @hwparams1 - GHWPARAMS1 679a3299499SFelipe Balbi * @hwparams2 - GHWPARAMS2 680a3299499SFelipe Balbi * @hwparams3 - GHWPARAMS3 681a3299499SFelipe Balbi * @hwparams4 - GHWPARAMS4 682a3299499SFelipe Balbi * @hwparams5 - GHWPARAMS5 683a3299499SFelipe Balbi * @hwparams6 - GHWPARAMS6 684a3299499SFelipe Balbi * @hwparams7 - GHWPARAMS7 685a3299499SFelipe Balbi * @hwparams8 - GHWPARAMS8 686a3299499SFelipe Balbi */ 687a3299499SFelipe Balbi struct dwc3_hwparams { 688a3299499SFelipe Balbi u32 hwparams0; 689a3299499SFelipe Balbi u32 hwparams1; 690a3299499SFelipe Balbi u32 hwparams2; 691a3299499SFelipe Balbi u32 hwparams3; 692a3299499SFelipe Balbi u32 hwparams4; 693a3299499SFelipe Balbi u32 hwparams5; 694a3299499SFelipe Balbi u32 hwparams6; 695a3299499SFelipe Balbi u32 hwparams7; 696a3299499SFelipe Balbi u32 hwparams8; 697a3299499SFelipe Balbi }; 698a3299499SFelipe Balbi 6990949e99bSFelipe Balbi /* HWPARAMS0 */ 7000949e99bSFelipe Balbi #define DWC3_MODE(n) ((n) & 0x7) 7010949e99bSFelipe Balbi 702457e84b6SFelipe Balbi #define DWC3_MDWIDTH(n) (((n) & 0xff00) >> 8) 703457e84b6SFelipe Balbi 7040949e99bSFelipe Balbi /* HWPARAMS1 */ 7059f622b2aSFelipe Balbi #define DWC3_NUM_INT(n) (((n) & (0x3f << 15)) >> 15) 7069f622b2aSFelipe Balbi 707789451f6SFelipe Balbi /* HWPARAMS3 */ 708789451f6SFelipe Balbi #define DWC3_NUM_IN_EPS_MASK (0x1f << 18) 709789451f6SFelipe Balbi #define DWC3_NUM_EPS_MASK (0x3f << 12) 710789451f6SFelipe Balbi #define DWC3_NUM_EPS(p) (((p)->hwparams3 & \ 711789451f6SFelipe Balbi (DWC3_NUM_EPS_MASK)) >> 12) 712789451f6SFelipe Balbi #define DWC3_NUM_IN_EPS(p) (((p)->hwparams3 & \ 713789451f6SFelipe Balbi (DWC3_NUM_IN_EPS_MASK)) >> 18) 714789451f6SFelipe Balbi 715457e84b6SFelipe Balbi /* HWPARAMS7 */ 716457e84b6SFelipe Balbi #define DWC3_RAM1_DEPTH(n) ((n) & 0xffff) 717457e84b6SFelipe Balbi 7185ef68c56SFelipe Balbi /** 7195ef68c56SFelipe Balbi * struct dwc3_request - representation of a transfer request 7205ef68c56SFelipe Balbi * @request: struct usb_request to be transferred 7215ef68c56SFelipe Balbi * @list: a list_head used for request queueing 7225ef68c56SFelipe Balbi * @dep: struct dwc3_ep owning this request 7230b3e4af3SFelipe Balbi * @sg: pointer to first incomplete sg 7240b3e4af3SFelipe Balbi * @num_pending_sgs: counter to pending sgs 725e62c5bc5SFelipe Balbi * @remaining: amount of data remaining 7265ef68c56SFelipe Balbi * @epnum: endpoint number to which this request refers 7275ef68c56SFelipe Balbi * @trb: pointer to struct dwc3_trb 7285ef68c56SFelipe Balbi * @trb_dma: DMA address of @trb 729c6267a51SFelipe Balbi * @unaligned: true for OUT endpoints with length not divisible by maxp 7305ef68c56SFelipe Balbi * @direction: IN or OUT direction flag 7315ef68c56SFelipe Balbi * @mapped: true when request has been dma-mapped 7325ef68c56SFelipe Balbi * @queued: true when request has been queued to HW 7335ef68c56SFelipe Balbi */ 734e0ce0b0aSSebastian Andrzej Siewior struct dwc3_request { 735e0ce0b0aSSebastian Andrzej Siewior struct usb_request request; 736e0ce0b0aSSebastian Andrzej Siewior struct list_head list; 737e0ce0b0aSSebastian Andrzej Siewior struct dwc3_ep *dep; 7380b3e4af3SFelipe Balbi struct scatterlist *sg; 739e0ce0b0aSSebastian Andrzej Siewior 7400b3e4af3SFelipe Balbi unsigned num_pending_sgs; 741e62c5bc5SFelipe Balbi unsigned remaining; 742e0ce0b0aSSebastian Andrzej Siewior u8 epnum; 743f6bafc6aSFelipe Balbi struct dwc3_trb *trb; 744e0ce0b0aSSebastian Andrzej Siewior dma_addr_t trb_dma; 745e0ce0b0aSSebastian Andrzej Siewior 746c6267a51SFelipe Balbi unsigned unaligned:1; 747e0ce0b0aSSebastian Andrzej Siewior unsigned direction:1; 748e0ce0b0aSSebastian Andrzej Siewior unsigned mapped:1; 749aa3342c8SFelipe Balbi unsigned started:1; 750e0ce0b0aSSebastian Andrzej Siewior }; 751e0ce0b0aSSebastian Andrzej Siewior 7522c61a8efSPaul Zimmerman /* 7532c61a8efSPaul Zimmerman * struct dwc3_scratchpad_array - hibernation scratchpad array 7542c61a8efSPaul Zimmerman * (format defined by hw) 7552c61a8efSPaul Zimmerman */ 7562c61a8efSPaul Zimmerman struct dwc3_scratchpad_array { 7572c61a8efSPaul Zimmerman __le64 dma_adr[DWC3_MAX_HIBER_SCRATCHBUFS]; 7582c61a8efSPaul Zimmerman }; 7592c61a8efSPaul Zimmerman 760a3299499SFelipe Balbi /** 76172246da4SFelipe Balbi * struct dwc3 - representation of our controller 76291db07dcSFelipe Balbi * @ctrl_req: usb control request which is used for ep0 76391db07dcSFelipe Balbi * @ep0_trb: trb which is used for the ctrl_req 7645812b1c2SFelipe Balbi * @ep0_bounce: bounce buffer for ep0 76504c03d10SFelipe Balbi * @zlp_buf: used when request->zero is set 76691db07dcSFelipe Balbi * @setup_buf: used while precessing STD USB requests 76791db07dcSFelipe Balbi * @ctrl_req_addr: dma address of ctrl_req 76891db07dcSFelipe Balbi * @ep0_trb: dma address of ep0_trb 76991db07dcSFelipe Balbi * @ep0_usb_req: dummy req used while handling STD USB requests 7705812b1c2SFelipe Balbi * @ep0_bounce_addr: dma address of ep0_bounce 7710ffcaf37SFelipe Balbi * @scratch_addr: dma address of scratchbuf 772bb014736SBaolin Wang * @ep0_in_setup: one control transfer is completed and enter setup phase 77372246da4SFelipe Balbi * @lock: for synchronizing 77472246da4SFelipe Balbi * @dev: pointer to our struct device 775d07e8819SFelipe Balbi * @xhci: pointer to our xHCI child 77672246da4SFelipe Balbi * @event_buffer_list: a list of event buffers 77772246da4SFelipe Balbi * @gadget: device side representation of the peripheral controller 77872246da4SFelipe Balbi * @gadget_driver: pointer to the gadget driver 77972246da4SFelipe Balbi * @regs: base address for our registers 78072246da4SFelipe Balbi * @regs_size: address space size 781bcdb3272SFelipe Balbi * @fladj: frame length adjustment 7823f308d17SFelipe Balbi * @irq_gadget: peripheral controller's IRQ number 7830ffcaf37SFelipe Balbi * @nr_scratch: number of scratch buffers 784fae2b904SFelipe Balbi * @u1u2: only used on revisions <1.83a for workaround 7856c167fc9SFelipe Balbi * @maximum_speed: maximum speed requested (mainly for testing purposes) 78672246da4SFelipe Balbi * @revision: revision register contents 787a45c82b8SRuchika Kharwar * @dr_mode: requested mode of operation 78832f2ed86SWilliam Wu * @hsphy_mode: UTMI phy mode, one of following: 78932f2ed86SWilliam Wu * - USBPHY_INTERFACE_MODE_UTMI 79032f2ed86SWilliam Wu * - USBPHY_INTERFACE_MODE_UTMIW 79151e1e7bcSFelipe Balbi * @usb2_phy: pointer to USB2 PHY 79251e1e7bcSFelipe Balbi * @usb3_phy: pointer to USB3 PHY 79357303488SKishon Vijay Abraham I * @usb2_generic_phy: pointer to USB2 PHY 79457303488SKishon Vijay Abraham I * @usb3_generic_phy: pointer to USB3 PHY 79588bc9d19SHeikki Krogerus * @ulpi: pointer to ulpi interface 7967415f17cSFelipe Balbi * @dcfg: saved contents of DCFG register 7977415f17cSFelipe Balbi * @gctl: saved contents of GCTL register 798c12a0d86SFelipe Balbi * @isoch_delay: wValue from Set Isochronous Delay request; 799865e09e7SFelipe Balbi * @u2sel: parameter from Set SEL request. 800865e09e7SFelipe Balbi * @u2pel: parameter from Set SEL request. 801865e09e7SFelipe Balbi * @u1sel: parameter from Set SEL request. 802865e09e7SFelipe Balbi * @u1pel: parameter from Set SEL request. 80347d3946eSBryan O'Donoghue * @num_eps: number of endpoints 804b53c772dSFelipe Balbi * @ep0_next_event: hold the next expected event 80572246da4SFelipe Balbi * @ep0state: state of endpoint zero 80672246da4SFelipe Balbi * @link_state: link state 80772246da4SFelipe Balbi * @speed: device speed (super, high, full, low) 808a3299499SFelipe Balbi * @hwparams: copy of hwparams registers 80972246da4SFelipe Balbi * @root: debugfs root folder pointer 810f2b685d5SFelipe Balbi * @regset: debugfs pointer to regdump file 811f2b685d5SFelipe Balbi * @test_mode: true when we're entering a USB test mode 812f2b685d5SFelipe Balbi * @test_mode_nr: test feature selector 81380caf7d2SHuang Rui * @lpm_nyet_threshold: LPM NYET response threshold 814460d098cSHuang Rui * @hird_threshold: HIRD threshold 8153e10a2ceSHeikki Krogerus * @hsphy_interface: "utmi" or "ulpi" 816fc8bb91bSFelipe Balbi * @connected: true when we're connected to a host, false otherwise 817f2b685d5SFelipe Balbi * @delayed_status: true when gadget driver asks for delayed status 818f2b685d5SFelipe Balbi * @ep0_bounced: true when we used bounce buffer 819f2b685d5SFelipe Balbi * @ep0_expect_in: true when we expect a DATA IN transfer 82081bc5599SFelipe Balbi * @has_hibernation: true when dwc3 was configured with Hibernation 821d64ff406SArnd Bergmann * @sysdev_is_parent: true when dwc3 device has a parent driver 82280caf7d2SHuang Rui * @has_lpm_erratum: true when core was configured with LPM Erratum. Note that 82380caf7d2SHuang Rui * there's now way for software to detect this in runtime. 824460d098cSHuang Rui * @is_utmi_l1_suspend: the core asserts output signal 825460d098cSHuang Rui * 0 - utmi_sleep_n 826460d098cSHuang Rui * 1 - utmi_l1_suspend_n 827946bd579SHuang Rui * @is_fpga: true when we are using the FPGA board 828fc8bb91bSFelipe Balbi * @pending_events: true when we have pending IRQs to be handled 829f2b685d5SFelipe Balbi * @pullups_connected: true when Run/Stop bit is set 830f2b685d5SFelipe Balbi * @setup_packet_pending: true when there's a Setup Packet in FIFO. Workaround 831f2b685d5SFelipe Balbi * @start_config_issued: true when StartConfig command has been issued 832f2b685d5SFelipe Balbi * @three_stage_setup: set if we perform a three phase setup 833eac68e8fSRobert Baldyga * @usb3_lpm_capable: set if hadrware supports Link Power Management 8343b81221aSHuang Rui * @disable_scramble_quirk: set if we enable the disable scramble quirk 8359a5b2f31SHuang Rui * @u2exit_lfps_quirk: set if we enable u2exit lfps quirk 836b5a65c40SHuang Rui * @u2ss_inp3_quirk: set if we enable P3 OK for U2/SS Inactive quirk 837df31f5b3SHuang Rui * @req_p1p2p3_quirk: set if we enable request p1p2p3 quirk 838a2a1d0f5SHuang Rui * @del_p1p2p3_quirk: set if we enable delay p1p2p3 quirk 83941c06ffdSHuang Rui * @del_phy_power_chg_quirk: set if we enable delay phy power change quirk 840fb67afcaSHuang Rui * @lfps_filter_quirk: set if we enable LFPS filter quirk 84114f4ac53SHuang Rui * @rx_detect_poll_quirk: set if we enable rx_detect to polling lfps quirk 84259acfa20SHuang Rui * @dis_u3_susphy_quirk: set if we disable usb3 suspend phy 8430effe0a3SHuang Rui * @dis_u2_susphy_quirk: set if we disable usb2 suspend phy 844ec791d14SJohn Youn * @dis_enblslpm_quirk: set if we clear enblslpm in GUSB2PHYCFG, 845ec791d14SJohn Youn * disabling the suspend signal to the PHY. 84616199f33SWilliam Wu * @dis_u2_freeclk_exists_quirk : set if we clear u2_freeclk_exists 84716199f33SWilliam Wu * in GUSB2PHYCFG, specify that USB2 PHY doesn't 84816199f33SWilliam Wu * provide a free-running PHY clock. 84900fe081dSWilliam Wu * @dis_del_phy_power_chg_quirk: set if we disable delay phy power 85000fe081dSWilliam Wu * change quirk. 8516b6a0c9aSHuang Rui * @tx_de_emphasis_quirk: set if we enable Tx de-emphasis quirk 8526b6a0c9aSHuang Rui * @tx_de_emphasis: Tx de-emphasis value 8536b6a0c9aSHuang Rui * 0 - -6dB de-emphasis 8546b6a0c9aSHuang Rui * 1 - -3.5dB de-emphasis 8556b6a0c9aSHuang Rui * 2 - No de-emphasis 8566b6a0c9aSHuang Rui * 3 - Reserved 857cf40b86bSJohn Youn * @imod_interval: set the interrupt moderation interval in 250ns 858cf40b86bSJohn Youn * increments or 0 to disable. 85972246da4SFelipe Balbi */ 86072246da4SFelipe Balbi struct dwc3 { 86172246da4SFelipe Balbi struct usb_ctrlrequest *ctrl_req; 862f6bafc6aSFelipe Balbi struct dwc3_trb *ep0_trb; 863905dc04eSFelipe Balbi void *bounce; 8645812b1c2SFelipe Balbi void *ep0_bounce; 86504c03d10SFelipe Balbi void *zlp_buf; 8660ffcaf37SFelipe Balbi void *scratchbuf; 86772246da4SFelipe Balbi u8 *setup_buf; 86872246da4SFelipe Balbi dma_addr_t ctrl_req_addr; 86972246da4SFelipe Balbi dma_addr_t ep0_trb_addr; 870905dc04eSFelipe Balbi dma_addr_t bounce_addr; 8715812b1c2SFelipe Balbi dma_addr_t ep0_bounce_addr; 8720ffcaf37SFelipe Balbi dma_addr_t scratch_addr; 873e0ce0b0aSSebastian Andrzej Siewior struct dwc3_request ep0_usb_req; 874bb014736SBaolin Wang struct completion ep0_in_setup; 875789451f6SFelipe Balbi 87672246da4SFelipe Balbi /* device lock */ 87772246da4SFelipe Balbi spinlock_t lock; 878789451f6SFelipe Balbi 87972246da4SFelipe Balbi struct device *dev; 880d64ff406SArnd Bergmann struct device *sysdev; 88172246da4SFelipe Balbi 882d07e8819SFelipe Balbi struct platform_device *xhci; 88351249dcaSIdo Shayevitz struct resource xhci_resources[DWC3_XHCI_RESOURCES_NUM]; 884d07e8819SFelipe Balbi 885696c8b12SFelipe Balbi struct dwc3_event_buffer *ev_buf; 88672246da4SFelipe Balbi struct dwc3_ep *eps[DWC3_ENDPOINTS_NUM]; 88772246da4SFelipe Balbi 88872246da4SFelipe Balbi struct usb_gadget gadget; 88972246da4SFelipe Balbi struct usb_gadget_driver *gadget_driver; 89072246da4SFelipe Balbi 89151e1e7bcSFelipe Balbi struct usb_phy *usb2_phy; 89251e1e7bcSFelipe Balbi struct usb_phy *usb3_phy; 89351e1e7bcSFelipe Balbi 89457303488SKishon Vijay Abraham I struct phy *usb2_generic_phy; 89557303488SKishon Vijay Abraham I struct phy *usb3_generic_phy; 89657303488SKishon Vijay Abraham I 89788bc9d19SHeikki Krogerus struct ulpi *ulpi; 89888bc9d19SHeikki Krogerus 89972246da4SFelipe Balbi void __iomem *regs; 90072246da4SFelipe Balbi size_t regs_size; 90172246da4SFelipe Balbi 902a45c82b8SRuchika Kharwar enum usb_dr_mode dr_mode; 90332f2ed86SWilliam Wu enum usb_phy_interface hsphy_mode; 904a45c82b8SRuchika Kharwar 905bcdb3272SFelipe Balbi u32 fladj; 9063f308d17SFelipe Balbi u32 irq_gadget; 9070ffcaf37SFelipe Balbi u32 nr_scratch; 908fae2b904SFelipe Balbi u32 u1u2; 9096c167fc9SFelipe Balbi u32 maximum_speed; 910690fb371SJohn Youn 911690fb371SJohn Youn /* 912690fb371SJohn Youn * All 3.1 IP version constants are greater than the 3.0 IP 913690fb371SJohn Youn * version constants. This works for most version checks in 914690fb371SJohn Youn * dwc3. However, in the future, this may not apply as 915690fb371SJohn Youn * features may be developed on newer versions of the 3.0 IP 916690fb371SJohn Youn * that are not in the 3.1 IP. 917690fb371SJohn Youn */ 91872246da4SFelipe Balbi u32 revision; 91972246da4SFelipe Balbi 92072246da4SFelipe Balbi #define DWC3_REVISION_173A 0x5533173a 92172246da4SFelipe Balbi #define DWC3_REVISION_175A 0x5533175a 92272246da4SFelipe Balbi #define DWC3_REVISION_180A 0x5533180a 92372246da4SFelipe Balbi #define DWC3_REVISION_183A 0x5533183a 92472246da4SFelipe Balbi #define DWC3_REVISION_185A 0x5533185a 9252c61a8efSPaul Zimmerman #define DWC3_REVISION_187A 0x5533187a 92672246da4SFelipe Balbi #define DWC3_REVISION_188A 0x5533188a 92772246da4SFelipe Balbi #define DWC3_REVISION_190A 0x5533190a 9282c61a8efSPaul Zimmerman #define DWC3_REVISION_194A 0x5533194a 9291522d703SFelipe Balbi #define DWC3_REVISION_200A 0x5533200a 9301522d703SFelipe Balbi #define DWC3_REVISION_202A 0x5533202a 9311522d703SFelipe Balbi #define DWC3_REVISION_210A 0x5533210a 9321522d703SFelipe Balbi #define DWC3_REVISION_220A 0x5533220a 9337ac6a593SFelipe Balbi #define DWC3_REVISION_230A 0x5533230a 9347ac6a593SFelipe Balbi #define DWC3_REVISION_240A 0x5533240a 9357ac6a593SFelipe Balbi #define DWC3_REVISION_250A 0x5533250a 936dbf5aaf7SFelipe Balbi #define DWC3_REVISION_260A 0x5533260a 937dbf5aaf7SFelipe Balbi #define DWC3_REVISION_270A 0x5533270a 938dbf5aaf7SFelipe Balbi #define DWC3_REVISION_280A 0x5533280a 9390bb39ca1SJohn Youn #define DWC3_REVISION_290A 0x5533290a 940512e4757SJohn Youn #define DWC3_REVISION_300A 0x5533300a 941512e4757SJohn Youn #define DWC3_REVISION_310A 0x5533310a 94272246da4SFelipe Balbi 943690fb371SJohn Youn /* 944690fb371SJohn Youn * NOTICE: we're using bit 31 as a "is usb 3.1" flag. This is really 945690fb371SJohn Youn * just so dwc31 revisions are always larger than dwc3. 946690fb371SJohn Youn */ 947690fb371SJohn Youn #define DWC3_REVISION_IS_DWC31 0x80000000 948e77c5614SJohn Youn #define DWC3_USB31_REVISION_110A (0x3131302a | DWC3_REVISION_IS_DWC31) 949cf40b86bSJohn Youn #define DWC3_USB31_REVISION_120A (0x3132302a | DWC3_REVISION_IS_DWC31) 950690fb371SJohn Youn 951b53c772dSFelipe Balbi enum dwc3_ep0_next ep0_next_event; 95272246da4SFelipe Balbi enum dwc3_ep0_state ep0state; 95372246da4SFelipe Balbi enum dwc3_link_state link_state; 95472246da4SFelipe Balbi 955c12a0d86SFelipe Balbi u16 isoch_delay; 956865e09e7SFelipe Balbi u16 u2sel; 957865e09e7SFelipe Balbi u16 u2pel; 958865e09e7SFelipe Balbi u8 u1sel; 959865e09e7SFelipe Balbi u8 u1pel; 960865e09e7SFelipe Balbi 96172246da4SFelipe Balbi u8 speed; 962865e09e7SFelipe Balbi 96347d3946eSBryan O'Donoghue u8 num_eps; 964789451f6SFelipe Balbi 965a3299499SFelipe Balbi struct dwc3_hwparams hwparams; 96672246da4SFelipe Balbi struct dentry *root; 967d7668024SFelipe Balbi struct debugfs_regset32 *regset; 9683b637367SGerard Cauvy 9693b637367SGerard Cauvy u8 test_mode; 9703b637367SGerard Cauvy u8 test_mode_nr; 97180caf7d2SHuang Rui u8 lpm_nyet_threshold; 972460d098cSHuang Rui u8 hird_threshold; 973f2b685d5SFelipe Balbi 9743e10a2ceSHeikki Krogerus const char *hsphy_interface; 9753e10a2ceSHeikki Krogerus 976fc8bb91bSFelipe Balbi unsigned connected:1; 977f2b685d5SFelipe Balbi unsigned delayed_status:1; 978f2b685d5SFelipe Balbi unsigned ep0_bounced:1; 979f2b685d5SFelipe Balbi unsigned ep0_expect_in:1; 98081bc5599SFelipe Balbi unsigned has_hibernation:1; 981d64ff406SArnd Bergmann unsigned sysdev_is_parent:1; 98280caf7d2SHuang Rui unsigned has_lpm_erratum:1; 983460d098cSHuang Rui unsigned is_utmi_l1_suspend:1; 984946bd579SHuang Rui unsigned is_fpga:1; 985fc8bb91bSFelipe Balbi unsigned pending_events:1; 986f2b685d5SFelipe Balbi unsigned pullups_connected:1; 987f2b685d5SFelipe Balbi unsigned setup_packet_pending:1; 988f2b685d5SFelipe Balbi unsigned three_stage_setup:1; 989eac68e8fSRobert Baldyga unsigned usb3_lpm_capable:1; 9903b81221aSHuang Rui 9913b81221aSHuang Rui unsigned disable_scramble_quirk:1; 9929a5b2f31SHuang Rui unsigned u2exit_lfps_quirk:1; 993b5a65c40SHuang Rui unsigned u2ss_inp3_quirk:1; 994df31f5b3SHuang Rui unsigned req_p1p2p3_quirk:1; 995a2a1d0f5SHuang Rui unsigned del_p1p2p3_quirk:1; 99641c06ffdSHuang Rui unsigned del_phy_power_chg_quirk:1; 997fb67afcaSHuang Rui unsigned lfps_filter_quirk:1; 99814f4ac53SHuang Rui unsigned rx_detect_poll_quirk:1; 99959acfa20SHuang Rui unsigned dis_u3_susphy_quirk:1; 10000effe0a3SHuang Rui unsigned dis_u2_susphy_quirk:1; 1001ec791d14SJohn Youn unsigned dis_enblslpm_quirk:1; 1002e58dd357SRajesh Bhagat unsigned dis_rxdet_inp3_quirk:1; 100316199f33SWilliam Wu unsigned dis_u2_freeclk_exists_quirk:1; 100400fe081dSWilliam Wu unsigned dis_del_phy_power_chg_quirk:1; 10056b6a0c9aSHuang Rui 10066b6a0c9aSHuang Rui unsigned tx_de_emphasis_quirk:1; 10076b6a0c9aSHuang Rui unsigned tx_de_emphasis:2; 1008cf40b86bSJohn Youn 1009cf40b86bSJohn Youn u16 imod_interval; 101072246da4SFelipe Balbi }; 101172246da4SFelipe Balbi 101272246da4SFelipe Balbi /* -------------------------------------------------------------------------- */ 101372246da4SFelipe Balbi 101472246da4SFelipe Balbi /* -------------------------------------------------------------------------- */ 101572246da4SFelipe Balbi 101672246da4SFelipe Balbi struct dwc3_event_type { 101772246da4SFelipe Balbi u32 is_devspec:1; 10181974d494SHuang Rui u32 type:7; 10191974d494SHuang Rui u32 reserved8_31:24; 102072246da4SFelipe Balbi } __packed; 102172246da4SFelipe Balbi 102272246da4SFelipe Balbi #define DWC3_DEPEVT_XFERCOMPLETE 0x01 102372246da4SFelipe Balbi #define DWC3_DEPEVT_XFERINPROGRESS 0x02 102472246da4SFelipe Balbi #define DWC3_DEPEVT_XFERNOTREADY 0x03 102572246da4SFelipe Balbi #define DWC3_DEPEVT_RXTXFIFOEVT 0x04 102672246da4SFelipe Balbi #define DWC3_DEPEVT_STREAMEVT 0x06 102772246da4SFelipe Balbi #define DWC3_DEPEVT_EPCMDCMPLT 0x07 102872246da4SFelipe Balbi 102972246da4SFelipe Balbi /** 103072246da4SFelipe Balbi * struct dwc3_event_depvt - Device Endpoint Events 103172246da4SFelipe Balbi * @one_bit: indicates this is an endpoint event (not used) 103272246da4SFelipe Balbi * @endpoint_number: number of the endpoint 103372246da4SFelipe Balbi * @endpoint_event: The event we have: 103472246da4SFelipe Balbi * 0x00 - Reserved 103572246da4SFelipe Balbi * 0x01 - XferComplete 103672246da4SFelipe Balbi * 0x02 - XferInProgress 103772246da4SFelipe Balbi * 0x03 - XferNotReady 103872246da4SFelipe Balbi * 0x04 - RxTxFifoEvt (IN->Underrun, OUT->Overrun) 103972246da4SFelipe Balbi * 0x05 - Reserved 104072246da4SFelipe Balbi * 0x06 - StreamEvt 104172246da4SFelipe Balbi * 0x07 - EPCmdCmplt 104272246da4SFelipe Balbi * @reserved11_10: Reserved, don't use. 104372246da4SFelipe Balbi * @status: Indicates the status of the event. Refer to databook for 104472246da4SFelipe Balbi * more information. 104572246da4SFelipe Balbi * @parameters: Parameters of the current event. Refer to databook for 104672246da4SFelipe Balbi * more information. 104772246da4SFelipe Balbi */ 104872246da4SFelipe Balbi struct dwc3_event_depevt { 104972246da4SFelipe Balbi u32 one_bit:1; 105072246da4SFelipe Balbi u32 endpoint_number:5; 105172246da4SFelipe Balbi u32 endpoint_event:4; 105272246da4SFelipe Balbi u32 reserved11_10:2; 105372246da4SFelipe Balbi u32 status:4; 105440aa41fbSFelipe Balbi 105540aa41fbSFelipe Balbi /* Within XferNotReady */ 105640aa41fbSFelipe Balbi #define DEPEVT_STATUS_TRANSFER_ACTIVE (1 << 3) 105740aa41fbSFelipe Balbi 105840aa41fbSFelipe Balbi /* Within XferComplete */ 105972246da4SFelipe Balbi #define DEPEVT_STATUS_BUSERR (1 << 0) 106072246da4SFelipe Balbi #define DEPEVT_STATUS_SHORT (1 << 1) 106172246da4SFelipe Balbi #define DEPEVT_STATUS_IOC (1 << 2) 106272246da4SFelipe Balbi #define DEPEVT_STATUS_LST (1 << 3) 1063dc137f01SFelipe Balbi 1064879631aaSFelipe Balbi /* Stream event only */ 1065879631aaSFelipe Balbi #define DEPEVT_STREAMEVT_FOUND 1 1066879631aaSFelipe Balbi #define DEPEVT_STREAMEVT_NOTFOUND 2 1067879631aaSFelipe Balbi 1068dc137f01SFelipe Balbi /* Control-only Status */ 1069dc137f01SFelipe Balbi #define DEPEVT_STATUS_CONTROL_DATA 1 1070dc137f01SFelipe Balbi #define DEPEVT_STATUS_CONTROL_STATUS 2 107145a2af2fSFelipe Balbi #define DEPEVT_STATUS_CONTROL_PHASE(n) ((n) & 3) 1072dc137f01SFelipe Balbi 10737b9cc7a2SKonrad Leszczynski /* In response to Start Transfer */ 10747b9cc7a2SKonrad Leszczynski #define DEPEVT_TRANSFER_NO_RESOURCE 1 10757b9cc7a2SKonrad Leszczynski #define DEPEVT_TRANSFER_BUS_EXPIRY 2 10767b9cc7a2SKonrad Leszczynski 107772246da4SFelipe Balbi u32 parameters:16; 107876a638f8SBaolin Wang 107976a638f8SBaolin Wang /* For Command Complete Events */ 108076a638f8SBaolin Wang #define DEPEVT_PARAMETER_CMD(n) (((n) & (0xf << 8)) >> 8) 108172246da4SFelipe Balbi } __packed; 108272246da4SFelipe Balbi 108372246da4SFelipe Balbi /** 108472246da4SFelipe Balbi * struct dwc3_event_devt - Device Events 108572246da4SFelipe Balbi * @one_bit: indicates this is a non-endpoint event (not used) 108672246da4SFelipe Balbi * @device_event: indicates it's a device event. Should read as 0x00 108772246da4SFelipe Balbi * @type: indicates the type of device event. 108872246da4SFelipe Balbi * 0 - DisconnEvt 108972246da4SFelipe Balbi * 1 - USBRst 109072246da4SFelipe Balbi * 2 - ConnectDone 109172246da4SFelipe Balbi * 3 - ULStChng 109272246da4SFelipe Balbi * 4 - WkUpEvt 109372246da4SFelipe Balbi * 5 - Reserved 109472246da4SFelipe Balbi * 6 - EOPF 109572246da4SFelipe Balbi * 7 - SOF 109672246da4SFelipe Balbi * 8 - Reserved 109772246da4SFelipe Balbi * 9 - ErrticErr 109872246da4SFelipe Balbi * 10 - CmdCmplt 109972246da4SFelipe Balbi * 11 - EvntOverflow 110072246da4SFelipe Balbi * 12 - VndrDevTstRcved 110172246da4SFelipe Balbi * @reserved15_12: Reserved, not used 110272246da4SFelipe Balbi * @event_info: Information about this event 110306f9b6e5SHuang Rui * @reserved31_25: Reserved, not used 110472246da4SFelipe Balbi */ 110572246da4SFelipe Balbi struct dwc3_event_devt { 110672246da4SFelipe Balbi u32 one_bit:1; 110772246da4SFelipe Balbi u32 device_event:7; 110872246da4SFelipe Balbi u32 type:4; 110972246da4SFelipe Balbi u32 reserved15_12:4; 111006f9b6e5SHuang Rui u32 event_info:9; 111106f9b6e5SHuang Rui u32 reserved31_25:7; 111272246da4SFelipe Balbi } __packed; 111372246da4SFelipe Balbi 111472246da4SFelipe Balbi /** 111572246da4SFelipe Balbi * struct dwc3_event_gevt - Other Core Events 111672246da4SFelipe Balbi * @one_bit: indicates this is a non-endpoint event (not used) 111772246da4SFelipe Balbi * @device_event: indicates it's (0x03) Carkit or (0x04) I2C event. 111872246da4SFelipe Balbi * @phy_port_number: self-explanatory 111972246da4SFelipe Balbi * @reserved31_12: Reserved, not used. 112072246da4SFelipe Balbi */ 112172246da4SFelipe Balbi struct dwc3_event_gevt { 112272246da4SFelipe Balbi u32 one_bit:1; 112372246da4SFelipe Balbi u32 device_event:7; 112472246da4SFelipe Balbi u32 phy_port_number:4; 112572246da4SFelipe Balbi u32 reserved31_12:20; 112672246da4SFelipe Balbi } __packed; 112772246da4SFelipe Balbi 112872246da4SFelipe Balbi /** 112972246da4SFelipe Balbi * union dwc3_event - representation of Event Buffer contents 113072246da4SFelipe Balbi * @raw: raw 32-bit event 113172246da4SFelipe Balbi * @type: the type of the event 113272246da4SFelipe Balbi * @depevt: Device Endpoint Event 113372246da4SFelipe Balbi * @devt: Device Event 113472246da4SFelipe Balbi * @gevt: Global Event 113572246da4SFelipe Balbi */ 113672246da4SFelipe Balbi union dwc3_event { 113772246da4SFelipe Balbi u32 raw; 113872246da4SFelipe Balbi struct dwc3_event_type type; 113972246da4SFelipe Balbi struct dwc3_event_depevt depevt; 114072246da4SFelipe Balbi struct dwc3_event_devt devt; 114172246da4SFelipe Balbi struct dwc3_event_gevt gevt; 114272246da4SFelipe Balbi }; 114372246da4SFelipe Balbi 114461018305SFelipe Balbi /** 114561018305SFelipe Balbi * struct dwc3_gadget_ep_cmd_params - representation of endpoint command 114661018305SFelipe Balbi * parameters 114761018305SFelipe Balbi * @param2: third parameter 114861018305SFelipe Balbi * @param1: second parameter 114961018305SFelipe Balbi * @param0: first parameter 115061018305SFelipe Balbi */ 115161018305SFelipe Balbi struct dwc3_gadget_ep_cmd_params { 115261018305SFelipe Balbi u32 param2; 115361018305SFelipe Balbi u32 param1; 115461018305SFelipe Balbi u32 param0; 115561018305SFelipe Balbi }; 115661018305SFelipe Balbi 115772246da4SFelipe Balbi /* 115872246da4SFelipe Balbi * DWC3 Features to be used as Driver Data 115972246da4SFelipe Balbi */ 116072246da4SFelipe Balbi 116172246da4SFelipe Balbi #define DWC3_HAS_PERIPHERAL BIT(0) 116272246da4SFelipe Balbi #define DWC3_HAS_XHCI BIT(1) 116372246da4SFelipe Balbi #define DWC3_HAS_OTG BIT(3) 116472246da4SFelipe Balbi 1165d07e8819SFelipe Balbi /* prototypes */ 11663140e8cbSSebastian Andrzej Siewior void dwc3_set_mode(struct dwc3 *dwc, u32 mode); 1167cf6d867dSFelipe Balbi u32 dwc3_core_fifo_space(struct dwc3_ep *dep, u8 type); 11683140e8cbSSebastian Andrzej Siewior 1169a987a906SJohn Youn /* check whether we are on the DWC_usb3 core */ 1170a987a906SJohn Youn static inline bool dwc3_is_usb3(struct dwc3 *dwc) 1171a987a906SJohn Youn { 1172a987a906SJohn Youn return !(dwc->revision & DWC3_REVISION_IS_DWC31); 1173a987a906SJohn Youn } 1174a987a906SJohn Youn 1175c4137a9cSJohn Youn /* check whether we are on the DWC_usb31 core */ 1176c4137a9cSJohn Youn static inline bool dwc3_is_usb31(struct dwc3 *dwc) 1177c4137a9cSJohn Youn { 1178c4137a9cSJohn Youn return !!(dwc->revision & DWC3_REVISION_IS_DWC31); 1179c4137a9cSJohn Youn } 1180c4137a9cSJohn Youn 1181cf40b86bSJohn Youn bool dwc3_has_imod(struct dwc3 *dwc); 1182cf40b86bSJohn Youn 1183388e5c51SVivek Gautam #if IS_ENABLED(CONFIG_USB_DWC3_HOST) || IS_ENABLED(CONFIG_USB_DWC3_DUAL_ROLE) 1184d07e8819SFelipe Balbi int dwc3_host_init(struct dwc3 *dwc); 1185d07e8819SFelipe Balbi void dwc3_host_exit(struct dwc3 *dwc); 1186388e5c51SVivek Gautam #else 1187388e5c51SVivek Gautam static inline int dwc3_host_init(struct dwc3 *dwc) 1188388e5c51SVivek Gautam { return 0; } 1189388e5c51SVivek Gautam static inline void dwc3_host_exit(struct dwc3 *dwc) 1190388e5c51SVivek Gautam { } 1191388e5c51SVivek Gautam #endif 1192d07e8819SFelipe Balbi 1193388e5c51SVivek Gautam #if IS_ENABLED(CONFIG_USB_DWC3_GADGET) || IS_ENABLED(CONFIG_USB_DWC3_DUAL_ROLE) 1194f80b45e7SFelipe Balbi int dwc3_gadget_init(struct dwc3 *dwc); 1195f80b45e7SFelipe Balbi void dwc3_gadget_exit(struct dwc3 *dwc); 119661018305SFelipe Balbi int dwc3_gadget_set_test_mode(struct dwc3 *dwc, int mode); 119761018305SFelipe Balbi int dwc3_gadget_get_link_state(struct dwc3 *dwc); 119861018305SFelipe Balbi int dwc3_gadget_set_link_state(struct dwc3 *dwc, enum dwc3_link_state state); 11992cd4718dSFelipe Balbi int dwc3_send_gadget_ep_cmd(struct dwc3_ep *dep, unsigned cmd, 12002cd4718dSFelipe Balbi struct dwc3_gadget_ep_cmd_params *params); 12013ece0ec4SFelipe Balbi int dwc3_send_gadget_generic_command(struct dwc3 *dwc, unsigned cmd, u32 param); 1202388e5c51SVivek Gautam #else 1203388e5c51SVivek Gautam static inline int dwc3_gadget_init(struct dwc3 *dwc) 1204388e5c51SVivek Gautam { return 0; } 1205388e5c51SVivek Gautam static inline void dwc3_gadget_exit(struct dwc3 *dwc) 1206388e5c51SVivek Gautam { } 120761018305SFelipe Balbi static inline int dwc3_gadget_set_test_mode(struct dwc3 *dwc, int mode) 120861018305SFelipe Balbi { return 0; } 120961018305SFelipe Balbi static inline int dwc3_gadget_get_link_state(struct dwc3 *dwc) 121061018305SFelipe Balbi { return 0; } 121161018305SFelipe Balbi static inline int dwc3_gadget_set_link_state(struct dwc3 *dwc, 121261018305SFelipe Balbi enum dwc3_link_state state) 121361018305SFelipe Balbi { return 0; } 121461018305SFelipe Balbi 12152cd4718dSFelipe Balbi static inline int dwc3_send_gadget_ep_cmd(struct dwc3_ep *dep, unsigned cmd, 12162cd4718dSFelipe Balbi struct dwc3_gadget_ep_cmd_params *params) 121761018305SFelipe Balbi { return 0; } 121861018305SFelipe Balbi static inline int dwc3_send_gadget_generic_command(struct dwc3 *dwc, 121961018305SFelipe Balbi int cmd, u32 param) 122061018305SFelipe Balbi { return 0; } 1221388e5c51SVivek Gautam #endif 1222f80b45e7SFelipe Balbi 12237415f17cSFelipe Balbi /* power management interface */ 12247415f17cSFelipe Balbi #if !IS_ENABLED(CONFIG_USB_DWC3_HOST) 12257415f17cSFelipe Balbi int dwc3_gadget_suspend(struct dwc3 *dwc); 12267415f17cSFelipe Balbi int dwc3_gadget_resume(struct dwc3 *dwc); 1227fc8bb91bSFelipe Balbi void dwc3_gadget_process_pending_events(struct dwc3 *dwc); 12287415f17cSFelipe Balbi #else 12297415f17cSFelipe Balbi static inline int dwc3_gadget_suspend(struct dwc3 *dwc) 12307415f17cSFelipe Balbi { 12317415f17cSFelipe Balbi return 0; 12327415f17cSFelipe Balbi } 12337415f17cSFelipe Balbi 12347415f17cSFelipe Balbi static inline int dwc3_gadget_resume(struct dwc3 *dwc) 12357415f17cSFelipe Balbi { 12367415f17cSFelipe Balbi return 0; 12377415f17cSFelipe Balbi } 1238fc8bb91bSFelipe Balbi 1239fc8bb91bSFelipe Balbi static inline void dwc3_gadget_process_pending_events(struct dwc3 *dwc) 1240fc8bb91bSFelipe Balbi { 1241fc8bb91bSFelipe Balbi } 12427415f17cSFelipe Balbi #endif /* !IS_ENABLED(CONFIG_USB_DWC3_HOST) */ 12437415f17cSFelipe Balbi 124488bc9d19SHeikki Krogerus #if IS_ENABLED(CONFIG_USB_DWC3_ULPI) 124588bc9d19SHeikki Krogerus int dwc3_ulpi_init(struct dwc3 *dwc); 124688bc9d19SHeikki Krogerus void dwc3_ulpi_exit(struct dwc3 *dwc); 124788bc9d19SHeikki Krogerus #else 124888bc9d19SHeikki Krogerus static inline int dwc3_ulpi_init(struct dwc3 *dwc) 124988bc9d19SHeikki Krogerus { return 0; } 125088bc9d19SHeikki Krogerus static inline void dwc3_ulpi_exit(struct dwc3 *dwc) 125188bc9d19SHeikki Krogerus { } 125288bc9d19SHeikki Krogerus #endif 125388bc9d19SHeikki Krogerus 125472246da4SFelipe Balbi #endif /* __DRIVERS_USB_DWC3_CORE_H */ 1255