172246da4SFelipe Balbi /** 272246da4SFelipe Balbi * core.h - DesignWare USB3 DRD Core Header 372246da4SFelipe Balbi * 472246da4SFelipe Balbi * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com 572246da4SFelipe Balbi * 672246da4SFelipe Balbi * Authors: Felipe Balbi <balbi@ti.com>, 772246da4SFelipe Balbi * Sebastian Andrzej Siewior <bigeasy@linutronix.de> 872246da4SFelipe Balbi * 95945f789SFelipe Balbi * This program is free software: you can redistribute it and/or modify 105945f789SFelipe Balbi * it under the terms of the GNU General Public License version 2 of 115945f789SFelipe Balbi * the License as published by the Free Software Foundation. 1272246da4SFelipe Balbi * 135945f789SFelipe Balbi * This program is distributed in the hope that it will be useful, 145945f789SFelipe Balbi * but WITHOUT ANY WARRANTY; without even the implied warranty of 155945f789SFelipe Balbi * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 165945f789SFelipe Balbi * GNU General Public License for more details. 1772246da4SFelipe Balbi */ 1872246da4SFelipe Balbi 1972246da4SFelipe Balbi #ifndef __DRIVERS_USB_DWC3_CORE_H 2072246da4SFelipe Balbi #define __DRIVERS_USB_DWC3_CORE_H 2172246da4SFelipe Balbi 2272246da4SFelipe Balbi #include <linux/device.h> 2372246da4SFelipe Balbi #include <linux/spinlock.h> 24d07e8819SFelipe Balbi #include <linux/ioport.h> 2572246da4SFelipe Balbi #include <linux/list.h> 2672246da4SFelipe Balbi #include <linux/dma-mapping.h> 2772246da4SFelipe Balbi #include <linux/mm.h> 2872246da4SFelipe Balbi #include <linux/debugfs.h> 2972246da4SFelipe Balbi 3072246da4SFelipe Balbi #include <linux/usb/ch9.h> 3172246da4SFelipe Balbi #include <linux/usb/gadget.h> 32a45c82b8SRuchika Kharwar #include <linux/usb/otg.h> 3372246da4SFelipe Balbi 3457303488SKishon Vijay Abraham I #include <linux/phy/phy.h> 3557303488SKishon Vijay Abraham I 362c4cbe6eSFelipe Balbi #define DWC3_MSG_MAX 500 372c4cbe6eSFelipe Balbi 3872246da4SFelipe Balbi /* Global constants */ 393ef35fafSFelipe Balbi #define DWC3_EP0_BOUNCE_SIZE 512 4072246da4SFelipe Balbi #define DWC3_ENDPOINTS_NUM 32 4151249dcaSIdo Shayevitz #define DWC3_XHCI_RESOURCES_NUM 2 4272246da4SFelipe Balbi 430ffcaf37SFelipe Balbi #define DWC3_SCRATCHBUF_SIZE 4096 /* each buffer is assumed to be 4KiB */ 445da93478SFelipe Balbi #define DWC3_EVENT_SIZE 4 /* bytes */ 455da93478SFelipe Balbi #define DWC3_EVENT_MAX_NUM 64 /* 2 events/endpoint */ 465da93478SFelipe Balbi #define DWC3_EVENT_BUFFERS_SIZE (DWC3_EVENT_SIZE * DWC3_EVENT_MAX_NUM) 4772246da4SFelipe Balbi #define DWC3_EVENT_TYPE_MASK 0xfe 4872246da4SFelipe Balbi 4972246da4SFelipe Balbi #define DWC3_EVENT_TYPE_DEV 0 5072246da4SFelipe Balbi #define DWC3_EVENT_TYPE_CARKIT 3 5172246da4SFelipe Balbi #define DWC3_EVENT_TYPE_I2C 4 5272246da4SFelipe Balbi 5372246da4SFelipe Balbi #define DWC3_DEVICE_EVENT_DISCONNECT 0 5472246da4SFelipe Balbi #define DWC3_DEVICE_EVENT_RESET 1 5572246da4SFelipe Balbi #define DWC3_DEVICE_EVENT_CONNECT_DONE 2 5672246da4SFelipe Balbi #define DWC3_DEVICE_EVENT_LINK_STATUS_CHANGE 3 5772246da4SFelipe Balbi #define DWC3_DEVICE_EVENT_WAKEUP 4 582c61a8efSPaul Zimmerman #define DWC3_DEVICE_EVENT_HIBER_REQ 5 5972246da4SFelipe Balbi #define DWC3_DEVICE_EVENT_EOPF 6 6072246da4SFelipe Balbi #define DWC3_DEVICE_EVENT_SOF 7 6172246da4SFelipe Balbi #define DWC3_DEVICE_EVENT_ERRATIC_ERROR 9 6272246da4SFelipe Balbi #define DWC3_DEVICE_EVENT_CMD_CMPL 10 6372246da4SFelipe Balbi #define DWC3_DEVICE_EVENT_OVERFLOW 11 6472246da4SFelipe Balbi 6572246da4SFelipe Balbi #define DWC3_GEVNTCOUNT_MASK 0xfffc 6672246da4SFelipe Balbi #define DWC3_GSNPSID_MASK 0xffff0000 6772246da4SFelipe Balbi #define DWC3_GSNPSREV_MASK 0xffff 6872246da4SFelipe Balbi 6951249dcaSIdo Shayevitz /* DWC3 registers memory space boundries */ 7051249dcaSIdo Shayevitz #define DWC3_XHCI_REGS_START 0x0 7151249dcaSIdo Shayevitz #define DWC3_XHCI_REGS_END 0x7fff 7251249dcaSIdo Shayevitz #define DWC3_GLOBALS_REGS_START 0xc100 7351249dcaSIdo Shayevitz #define DWC3_GLOBALS_REGS_END 0xc6ff 7451249dcaSIdo Shayevitz #define DWC3_DEVICE_REGS_START 0xc700 7551249dcaSIdo Shayevitz #define DWC3_DEVICE_REGS_END 0xcbff 7651249dcaSIdo Shayevitz #define DWC3_OTG_REGS_START 0xcc00 7751249dcaSIdo Shayevitz #define DWC3_OTG_REGS_END 0xccff 7851249dcaSIdo Shayevitz 7972246da4SFelipe Balbi /* Global Registers */ 8072246da4SFelipe Balbi #define DWC3_GSBUSCFG0 0xc100 8172246da4SFelipe Balbi #define DWC3_GSBUSCFG1 0xc104 8272246da4SFelipe Balbi #define DWC3_GTXTHRCFG 0xc108 8372246da4SFelipe Balbi #define DWC3_GRXTHRCFG 0xc10c 8472246da4SFelipe Balbi #define DWC3_GCTL 0xc110 8572246da4SFelipe Balbi #define DWC3_GEVTEN 0xc114 8672246da4SFelipe Balbi #define DWC3_GSTS 0xc118 8772246da4SFelipe Balbi #define DWC3_GSNPSID 0xc120 8872246da4SFelipe Balbi #define DWC3_GGPIO 0xc124 8972246da4SFelipe Balbi #define DWC3_GUID 0xc128 9072246da4SFelipe Balbi #define DWC3_GUCTL 0xc12c 9172246da4SFelipe Balbi #define DWC3_GBUSERRADDR0 0xc130 9272246da4SFelipe Balbi #define DWC3_GBUSERRADDR1 0xc134 9372246da4SFelipe Balbi #define DWC3_GPRTBIMAP0 0xc138 9472246da4SFelipe Balbi #define DWC3_GPRTBIMAP1 0xc13c 9572246da4SFelipe Balbi #define DWC3_GHWPARAMS0 0xc140 9672246da4SFelipe Balbi #define DWC3_GHWPARAMS1 0xc144 9772246da4SFelipe Balbi #define DWC3_GHWPARAMS2 0xc148 9872246da4SFelipe Balbi #define DWC3_GHWPARAMS3 0xc14c 9972246da4SFelipe Balbi #define DWC3_GHWPARAMS4 0xc150 10072246da4SFelipe Balbi #define DWC3_GHWPARAMS5 0xc154 10172246da4SFelipe Balbi #define DWC3_GHWPARAMS6 0xc158 10272246da4SFelipe Balbi #define DWC3_GHWPARAMS7 0xc15c 10372246da4SFelipe Balbi #define DWC3_GDBGFIFOSPACE 0xc160 10472246da4SFelipe Balbi #define DWC3_GDBGLTSSM 0xc164 10572246da4SFelipe Balbi #define DWC3_GPRTBIMAP_HS0 0xc180 10672246da4SFelipe Balbi #define DWC3_GPRTBIMAP_HS1 0xc184 10772246da4SFelipe Balbi #define DWC3_GPRTBIMAP_FS0 0xc188 10872246da4SFelipe Balbi #define DWC3_GPRTBIMAP_FS1 0xc18c 10972246da4SFelipe Balbi 11072246da4SFelipe Balbi #define DWC3_GUSB2PHYCFG(n) (0xc200 + (n * 0x04)) 11172246da4SFelipe Balbi #define DWC3_GUSB2I2CCTL(n) (0xc240 + (n * 0x04)) 11272246da4SFelipe Balbi 11372246da4SFelipe Balbi #define DWC3_GUSB2PHYACC(n) (0xc280 + (n * 0x04)) 11472246da4SFelipe Balbi 11572246da4SFelipe Balbi #define DWC3_GUSB3PIPECTL(n) (0xc2c0 + (n * 0x04)) 11672246da4SFelipe Balbi 11772246da4SFelipe Balbi #define DWC3_GTXFIFOSIZ(n) (0xc300 + (n * 0x04)) 11872246da4SFelipe Balbi #define DWC3_GRXFIFOSIZ(n) (0xc380 + (n * 0x04)) 11972246da4SFelipe Balbi 12072246da4SFelipe Balbi #define DWC3_GEVNTADRLO(n) (0xc400 + (n * 0x10)) 12172246da4SFelipe Balbi #define DWC3_GEVNTADRHI(n) (0xc404 + (n * 0x10)) 12272246da4SFelipe Balbi #define DWC3_GEVNTSIZ(n) (0xc408 + (n * 0x10)) 12372246da4SFelipe Balbi #define DWC3_GEVNTCOUNT(n) (0xc40c + (n * 0x10)) 12472246da4SFelipe Balbi 12572246da4SFelipe Balbi #define DWC3_GHWPARAMS8 0xc600 12672246da4SFelipe Balbi 12772246da4SFelipe Balbi /* Device Registers */ 12872246da4SFelipe Balbi #define DWC3_DCFG 0xc700 12972246da4SFelipe Balbi #define DWC3_DCTL 0xc704 13072246da4SFelipe Balbi #define DWC3_DEVTEN 0xc708 13172246da4SFelipe Balbi #define DWC3_DSTS 0xc70c 13272246da4SFelipe Balbi #define DWC3_DGCMDPAR 0xc710 13372246da4SFelipe Balbi #define DWC3_DGCMD 0xc714 13472246da4SFelipe Balbi #define DWC3_DALEPENA 0xc720 13572246da4SFelipe Balbi #define DWC3_DEPCMDPAR2(n) (0xc800 + (n * 0x10)) 13672246da4SFelipe Balbi #define DWC3_DEPCMDPAR1(n) (0xc804 + (n * 0x10)) 13772246da4SFelipe Balbi #define DWC3_DEPCMDPAR0(n) (0xc808 + (n * 0x10)) 13872246da4SFelipe Balbi #define DWC3_DEPCMD(n) (0xc80c + (n * 0x10)) 13972246da4SFelipe Balbi 14072246da4SFelipe Balbi /* OTG Registers */ 14172246da4SFelipe Balbi #define DWC3_OCFG 0xcc00 14272246da4SFelipe Balbi #define DWC3_OCTL 0xcc04 143d4436c3aSGeorge Cherian #define DWC3_OEVT 0xcc08 144d4436c3aSGeorge Cherian #define DWC3_OEVTEN 0xcc0C 145d4436c3aSGeorge Cherian #define DWC3_OSTS 0xcc10 14672246da4SFelipe Balbi 14772246da4SFelipe Balbi /* Bit fields */ 14872246da4SFelipe Balbi 14972246da4SFelipe Balbi /* Global Configuration Register */ 1501d046793SPaul Zimmerman #define DWC3_GCTL_PWRDNSCALE(n) ((n) << 19) 151f4aadbe4SFelipe Balbi #define DWC3_GCTL_U2RSTECN (1 << 16) 1521d046793SPaul Zimmerman #define DWC3_GCTL_RAMCLKSEL(x) (((x) & DWC3_GCTL_CLK_MASK) << 6) 15372246da4SFelipe Balbi #define DWC3_GCTL_CLK_BUS (0) 15472246da4SFelipe Balbi #define DWC3_GCTL_CLK_PIPE (1) 15572246da4SFelipe Balbi #define DWC3_GCTL_CLK_PIPEHALF (2) 15672246da4SFelipe Balbi #define DWC3_GCTL_CLK_MASK (3) 15772246da4SFelipe Balbi 1580b9fe32dSFelipe Balbi #define DWC3_GCTL_PRTCAP(n) (((n) & (3 << 12)) >> 12) 1591d046793SPaul Zimmerman #define DWC3_GCTL_PRTCAPDIR(n) ((n) << 12) 16072246da4SFelipe Balbi #define DWC3_GCTL_PRTCAP_HOST 1 16172246da4SFelipe Balbi #define DWC3_GCTL_PRTCAP_DEVICE 2 16272246da4SFelipe Balbi #define DWC3_GCTL_PRTCAP_OTG 3 16372246da4SFelipe Balbi 16472246da4SFelipe Balbi #define DWC3_GCTL_CORESOFTRESET (1 << 11) 165183ca111SFelipe Balbi #define DWC3_GCTL_SOFITPSYNC (1 << 10) 1661d046793SPaul Zimmerman #define DWC3_GCTL_SCALEDOWN(n) ((n) << 4) 1673e87c42aSPaul Zimmerman #define DWC3_GCTL_SCALEDOWN_MASK DWC3_GCTL_SCALEDOWN(3) 16872246da4SFelipe Balbi #define DWC3_GCTL_DISSCRAMBLE (1 << 3) 1699a5b2f31SHuang Rui #define DWC3_GCTL_U2EXIT_LFPS (1 << 2) 1702c61a8efSPaul Zimmerman #define DWC3_GCTL_GBLHIBERNATIONEN (1 << 1) 171aabb7075SFelipe Balbi #define DWC3_GCTL_DSBLCLKGTNG (1 << 0) 17272246da4SFelipe Balbi 17372246da4SFelipe Balbi /* Global USB2 PHY Configuration Register */ 17472246da4SFelipe Balbi #define DWC3_GUSB2PHYCFG_PHYSOFTRST (1 << 31) 17572246da4SFelipe Balbi #define DWC3_GUSB2PHYCFG_SUSPHY (1 << 6) 17672246da4SFelipe Balbi 17772246da4SFelipe Balbi /* Global USB3 PIPE Control Register */ 17872246da4SFelipe Balbi #define DWC3_GUSB3PIPECTL_PHYSOFTRST (1 << 31) 179b5a65c40SHuang Rui #define DWC3_GUSB3PIPECTL_U2SSINP3OK (1 << 29) 180df31f5b3SHuang Rui #define DWC3_GUSB3PIPECTL_REQP1P2P3 (1 << 24) 181a2a1d0f5SHuang Rui #define DWC3_GUSB3PIPECTL_DEP1P2P3(n) ((n) << 19) 182a2a1d0f5SHuang Rui #define DWC3_GUSB3PIPECTL_DEP1P2P3_MASK DWC3_GUSB3PIPECTL_DEP1P2P3(7) 183a2a1d0f5SHuang Rui #define DWC3_GUSB3PIPECTL_DEP1P2P3_EN DWC3_GUSB3PIPECTL_DEP1P2P3(1) 18441c06ffdSHuang Rui #define DWC3_GUSB3PIPECTL_DEPOCHANGE (1 << 18) 18572246da4SFelipe Balbi #define DWC3_GUSB3PIPECTL_SUSPHY (1 << 17) 186fb67afcaSHuang Rui #define DWC3_GUSB3PIPECTL_LFPSFILT (1 << 9) 18714f4ac53SHuang Rui #define DWC3_GUSB3PIPECTL_RX_DETOPOLL (1 << 8) 1886b6a0c9aSHuang Rui #define DWC3_GUSB3PIPECTL_TX_DEEPH_MASK DWC3_GUSB3PIPECTL_TX_DEEPH(3) 1896b6a0c9aSHuang Rui #define DWC3_GUSB3PIPECTL_TX_DEEPH(n) ((n) << 1) 19072246da4SFelipe Balbi 191457e84b6SFelipe Balbi /* Global TX Fifo Size Register */ 192457e84b6SFelipe Balbi #define DWC3_GTXFIFOSIZ_TXFDEF(n) ((n) & 0xffff) 193457e84b6SFelipe Balbi #define DWC3_GTXFIFOSIZ_TXFSTADDR(n) ((n) & 0xffff0000) 194457e84b6SFelipe Balbi 19568d6a01bSFelipe Balbi /* Global Event Size Registers */ 19668d6a01bSFelipe Balbi #define DWC3_GEVNTSIZ_INTMASK (1 << 31) 19768d6a01bSFelipe Balbi #define DWC3_GEVNTSIZ_SIZE(n) ((n) & 0xffff) 19868d6a01bSFelipe Balbi 199aabb7075SFelipe Balbi /* Global HWPARAMS1 Register */ 2001d046793SPaul Zimmerman #define DWC3_GHWPARAMS1_EN_PWROPT(n) (((n) & (3 << 24)) >> 24) 201aabb7075SFelipe Balbi #define DWC3_GHWPARAMS1_EN_PWROPT_NO 0 202aabb7075SFelipe Balbi #define DWC3_GHWPARAMS1_EN_PWROPT_CLK 1 2032c61a8efSPaul Zimmerman #define DWC3_GHWPARAMS1_EN_PWROPT_HIB 2 2042c61a8efSPaul Zimmerman #define DWC3_GHWPARAMS1_PWROPT(n) ((n) << 24) 2052c61a8efSPaul Zimmerman #define DWC3_GHWPARAMS1_PWROPT_MASK DWC3_GHWPARAMS1_PWROPT(3) 2062c61a8efSPaul Zimmerman 2070e1e5c47SPaul Zimmerman /* Global HWPARAMS3 Register */ 2080e1e5c47SPaul Zimmerman #define DWC3_GHWPARAMS3_SSPHY_IFC(n) ((n) & 3) 2090e1e5c47SPaul Zimmerman #define DWC3_GHWPARAMS3_SSPHY_IFC_DIS 0 2100e1e5c47SPaul Zimmerman #define DWC3_GHWPARAMS3_SSPHY_IFC_ENA 1 2110e1e5c47SPaul Zimmerman #define DWC3_GHWPARAMS3_HSPHY_IFC(n) (((n) & (3 << 2)) >> 2) 2120e1e5c47SPaul Zimmerman #define DWC3_GHWPARAMS3_HSPHY_IFC_DIS 0 2130e1e5c47SPaul Zimmerman #define DWC3_GHWPARAMS3_HSPHY_IFC_UTMI 1 2140e1e5c47SPaul Zimmerman #define DWC3_GHWPARAMS3_HSPHY_IFC_ULPI 2 2150e1e5c47SPaul Zimmerman #define DWC3_GHWPARAMS3_HSPHY_IFC_UTMI_ULPI 3 2160e1e5c47SPaul Zimmerman #define DWC3_GHWPARAMS3_FSPHY_IFC(n) (((n) & (3 << 4)) >> 4) 2170e1e5c47SPaul Zimmerman #define DWC3_GHWPARAMS3_FSPHY_IFC_DIS 0 2180e1e5c47SPaul Zimmerman #define DWC3_GHWPARAMS3_FSPHY_IFC_ENA 1 2190e1e5c47SPaul Zimmerman 2202c61a8efSPaul Zimmerman /* Global HWPARAMS4 Register */ 2212c61a8efSPaul Zimmerman #define DWC3_GHWPARAMS4_HIBER_SCRATCHBUFS(n) (((n) & (0x0f << 13)) >> 13) 2222c61a8efSPaul Zimmerman #define DWC3_MAX_HIBER_SCRATCHBUFS 15 223aabb7075SFelipe Balbi 224946bd579SHuang Rui /* Global HWPARAMS6 Register */ 225946bd579SHuang Rui #define DWC3_GHWPARAMS6_EN_FPGA (1 << 7) 226946bd579SHuang Rui 22772246da4SFelipe Balbi /* Device Configuration Register */ 22872246da4SFelipe Balbi #define DWC3_DCFG_DEVADDR(addr) ((addr) << 3) 22972246da4SFelipe Balbi #define DWC3_DCFG_DEVADDR_MASK DWC3_DCFG_DEVADDR(0x7f) 23072246da4SFelipe Balbi 23172246da4SFelipe Balbi #define DWC3_DCFG_SPEED_MASK (7 << 0) 23272246da4SFelipe Balbi #define DWC3_DCFG_SUPERSPEED (4 << 0) 23372246da4SFelipe Balbi #define DWC3_DCFG_HIGHSPEED (0 << 0) 23472246da4SFelipe Balbi #define DWC3_DCFG_FULLSPEED2 (1 << 0) 23572246da4SFelipe Balbi #define DWC3_DCFG_LOWSPEED (2 << 0) 23672246da4SFelipe Balbi #define DWC3_DCFG_FULLSPEED1 (3 << 0) 23772246da4SFelipe Balbi 2382c61a8efSPaul Zimmerman #define DWC3_DCFG_LPM_CAP (1 << 22) 2392c61a8efSPaul Zimmerman 24072246da4SFelipe Balbi /* Device Control Register */ 24172246da4SFelipe Balbi #define DWC3_DCTL_RUN_STOP (1 << 31) 24272246da4SFelipe Balbi #define DWC3_DCTL_CSFTRST (1 << 30) 24372246da4SFelipe Balbi #define DWC3_DCTL_LSFTRST (1 << 29) 24472246da4SFelipe Balbi 24572246da4SFelipe Balbi #define DWC3_DCTL_HIRD_THRES_MASK (0x1f << 24) 2467e39b817SPratyush Anand #define DWC3_DCTL_HIRD_THRES(n) ((n) << 24) 24772246da4SFelipe Balbi 24872246da4SFelipe Balbi #define DWC3_DCTL_APPL1RES (1 << 23) 24972246da4SFelipe Balbi 2502c61a8efSPaul Zimmerman /* These apply for core versions 1.87a and earlier */ 2518db7ed15SFelipe Balbi #define DWC3_DCTL_TRGTULST_MASK (0x0f << 17) 2528db7ed15SFelipe Balbi #define DWC3_DCTL_TRGTULST(n) ((n) << 17) 2538db7ed15SFelipe Balbi #define DWC3_DCTL_TRGTULST_U2 (DWC3_DCTL_TRGTULST(2)) 2548db7ed15SFelipe Balbi #define DWC3_DCTL_TRGTULST_U3 (DWC3_DCTL_TRGTULST(3)) 2558db7ed15SFelipe Balbi #define DWC3_DCTL_TRGTULST_SS_DIS (DWC3_DCTL_TRGTULST(4)) 2568db7ed15SFelipe Balbi #define DWC3_DCTL_TRGTULST_RX_DET (DWC3_DCTL_TRGTULST(5)) 2578db7ed15SFelipe Balbi #define DWC3_DCTL_TRGTULST_SS_INACT (DWC3_DCTL_TRGTULST(6)) 2588db7ed15SFelipe Balbi 2592c61a8efSPaul Zimmerman /* These apply for core versions 1.94a and later */ 26080caf7d2SHuang Rui #define DWC3_DCTL_LPM_ERRATA_MASK DWC3_DCTL_LPM_ERRATA(0xf) 26180caf7d2SHuang Rui #define DWC3_DCTL_LPM_ERRATA(n) ((n) << 20) 26280caf7d2SHuang Rui 2632c61a8efSPaul Zimmerman #define DWC3_DCTL_KEEP_CONNECT (1 << 19) 2642c61a8efSPaul Zimmerman #define DWC3_DCTL_L1_HIBER_EN (1 << 18) 2652c61a8efSPaul Zimmerman #define DWC3_DCTL_CRS (1 << 17) 2662c61a8efSPaul Zimmerman #define DWC3_DCTL_CSS (1 << 16) 2672c61a8efSPaul Zimmerman 26872246da4SFelipe Balbi #define DWC3_DCTL_INITU2ENA (1 << 12) 26972246da4SFelipe Balbi #define DWC3_DCTL_ACCEPTU2ENA (1 << 11) 27072246da4SFelipe Balbi #define DWC3_DCTL_INITU1ENA (1 << 10) 27172246da4SFelipe Balbi #define DWC3_DCTL_ACCEPTU1ENA (1 << 9) 27272246da4SFelipe Balbi #define DWC3_DCTL_TSTCTRL_MASK (0xf << 1) 27372246da4SFelipe Balbi 27472246da4SFelipe Balbi #define DWC3_DCTL_ULSTCHNGREQ_MASK (0x0f << 5) 27572246da4SFelipe Balbi #define DWC3_DCTL_ULSTCHNGREQ(n) (((n) << 5) & DWC3_DCTL_ULSTCHNGREQ_MASK) 27672246da4SFelipe Balbi 27772246da4SFelipe Balbi #define DWC3_DCTL_ULSTCHNG_NO_ACTION (DWC3_DCTL_ULSTCHNGREQ(0)) 27872246da4SFelipe Balbi #define DWC3_DCTL_ULSTCHNG_SS_DISABLED (DWC3_DCTL_ULSTCHNGREQ(4)) 27972246da4SFelipe Balbi #define DWC3_DCTL_ULSTCHNG_RX_DETECT (DWC3_DCTL_ULSTCHNGREQ(5)) 28072246da4SFelipe Balbi #define DWC3_DCTL_ULSTCHNG_SS_INACTIVE (DWC3_DCTL_ULSTCHNGREQ(6)) 28172246da4SFelipe Balbi #define DWC3_DCTL_ULSTCHNG_RECOVERY (DWC3_DCTL_ULSTCHNGREQ(8)) 28272246da4SFelipe Balbi #define DWC3_DCTL_ULSTCHNG_COMPLIANCE (DWC3_DCTL_ULSTCHNGREQ(10)) 28372246da4SFelipe Balbi #define DWC3_DCTL_ULSTCHNG_LOOPBACK (DWC3_DCTL_ULSTCHNGREQ(11)) 28472246da4SFelipe Balbi 28572246da4SFelipe Balbi /* Device Event Enable Register */ 28672246da4SFelipe Balbi #define DWC3_DEVTEN_VNDRDEVTSTRCVEDEN (1 << 12) 28772246da4SFelipe Balbi #define DWC3_DEVTEN_EVNTOVERFLOWEN (1 << 11) 28872246da4SFelipe Balbi #define DWC3_DEVTEN_CMDCMPLTEN (1 << 10) 28972246da4SFelipe Balbi #define DWC3_DEVTEN_ERRTICERREN (1 << 9) 29072246da4SFelipe Balbi #define DWC3_DEVTEN_SOFEN (1 << 7) 29172246da4SFelipe Balbi #define DWC3_DEVTEN_EOPFEN (1 << 6) 2922c61a8efSPaul Zimmerman #define DWC3_DEVTEN_HIBERNATIONREQEVTEN (1 << 5) 29372246da4SFelipe Balbi #define DWC3_DEVTEN_WKUPEVTEN (1 << 4) 29472246da4SFelipe Balbi #define DWC3_DEVTEN_ULSTCNGEN (1 << 3) 29572246da4SFelipe Balbi #define DWC3_DEVTEN_CONNECTDONEEN (1 << 2) 29672246da4SFelipe Balbi #define DWC3_DEVTEN_USBRSTEN (1 << 1) 29772246da4SFelipe Balbi #define DWC3_DEVTEN_DISCONNEVTEN (1 << 0) 29872246da4SFelipe Balbi 29972246da4SFelipe Balbi /* Device Status Register */ 3002c61a8efSPaul Zimmerman #define DWC3_DSTS_DCNRD (1 << 29) 3012c61a8efSPaul Zimmerman 3022c61a8efSPaul Zimmerman /* This applies for core versions 1.87a and earlier */ 30372246da4SFelipe Balbi #define DWC3_DSTS_PWRUPREQ (1 << 24) 3042c61a8efSPaul Zimmerman 3052c61a8efSPaul Zimmerman /* These apply for core versions 1.94a and later */ 3062c61a8efSPaul Zimmerman #define DWC3_DSTS_RSS (1 << 25) 3072c61a8efSPaul Zimmerman #define DWC3_DSTS_SSS (1 << 24) 3082c61a8efSPaul Zimmerman 30972246da4SFelipe Balbi #define DWC3_DSTS_COREIDLE (1 << 23) 31072246da4SFelipe Balbi #define DWC3_DSTS_DEVCTRLHLT (1 << 22) 31172246da4SFelipe Balbi 31272246da4SFelipe Balbi #define DWC3_DSTS_USBLNKST_MASK (0x0f << 18) 31372246da4SFelipe Balbi #define DWC3_DSTS_USBLNKST(n) (((n) & DWC3_DSTS_USBLNKST_MASK) >> 18) 31472246da4SFelipe Balbi 31572246da4SFelipe Balbi #define DWC3_DSTS_RXFIFOEMPTY (1 << 17) 31672246da4SFelipe Balbi 317d05b8182SPratyush Anand #define DWC3_DSTS_SOFFN_MASK (0x3fff << 3) 31872246da4SFelipe Balbi #define DWC3_DSTS_SOFFN(n) (((n) & DWC3_DSTS_SOFFN_MASK) >> 3) 31972246da4SFelipe Balbi 32072246da4SFelipe Balbi #define DWC3_DSTS_CONNECTSPD (7 << 0) 32172246da4SFelipe Balbi 32272246da4SFelipe Balbi #define DWC3_DSTS_SUPERSPEED (4 << 0) 32372246da4SFelipe Balbi #define DWC3_DSTS_HIGHSPEED (0 << 0) 32472246da4SFelipe Balbi #define DWC3_DSTS_FULLSPEED2 (1 << 0) 32572246da4SFelipe Balbi #define DWC3_DSTS_LOWSPEED (2 << 0) 32672246da4SFelipe Balbi #define DWC3_DSTS_FULLSPEED1 (3 << 0) 32772246da4SFelipe Balbi 32872246da4SFelipe Balbi /* Device Generic Command Register */ 32972246da4SFelipe Balbi #define DWC3_DGCMD_SET_LMP 0x01 33072246da4SFelipe Balbi #define DWC3_DGCMD_SET_PERIODIC_PAR 0x02 33172246da4SFelipe Balbi #define DWC3_DGCMD_XMIT_FUNCTION 0x03 3322c61a8efSPaul Zimmerman 3332c61a8efSPaul Zimmerman /* These apply for core versions 1.94a and later */ 3342c61a8efSPaul Zimmerman #define DWC3_DGCMD_SET_SCRATCHPAD_ADDR_LO 0x04 3352c61a8efSPaul Zimmerman #define DWC3_DGCMD_SET_SCRATCHPAD_ADDR_HI 0x05 3362c61a8efSPaul Zimmerman 33772246da4SFelipe Balbi #define DWC3_DGCMD_SELECTED_FIFO_FLUSH 0x09 33872246da4SFelipe Balbi #define DWC3_DGCMD_ALL_FIFO_FLUSH 0x0a 33972246da4SFelipe Balbi #define DWC3_DGCMD_SET_ENDPOINT_NRDY 0x0c 34072246da4SFelipe Balbi #define DWC3_DGCMD_RUN_SOC_BUS_LOOPBACK 0x10 34172246da4SFelipe Balbi 342b09bb642SFelipe Balbi #define DWC3_DGCMD_STATUS(n) (((n) >> 15) & 1) 343b09bb642SFelipe Balbi #define DWC3_DGCMD_CMDACT (1 << 10) 3442c61a8efSPaul Zimmerman #define DWC3_DGCMD_CMDIOC (1 << 8) 3452c61a8efSPaul Zimmerman 3462c61a8efSPaul Zimmerman /* Device Generic Command Parameter Register */ 3472c61a8efSPaul Zimmerman #define DWC3_DGCMDPAR_FORCE_LINKPM_ACCEPT (1 << 0) 3482c61a8efSPaul Zimmerman #define DWC3_DGCMDPAR_FIFO_NUM(n) ((n) << 0) 3492c61a8efSPaul Zimmerman #define DWC3_DGCMDPAR_RX_FIFO (0 << 5) 3502c61a8efSPaul Zimmerman #define DWC3_DGCMDPAR_TX_FIFO (1 << 5) 3512c61a8efSPaul Zimmerman #define DWC3_DGCMDPAR_LOOPBACK_DIS (0 << 0) 3522c61a8efSPaul Zimmerman #define DWC3_DGCMDPAR_LOOPBACK_ENA (1 << 0) 353b09bb642SFelipe Balbi 35472246da4SFelipe Balbi /* Device Endpoint Command Register */ 35572246da4SFelipe Balbi #define DWC3_DEPCMD_PARAM_SHIFT 16 3561d046793SPaul Zimmerman #define DWC3_DEPCMD_PARAM(x) ((x) << DWC3_DEPCMD_PARAM_SHIFT) 3571d046793SPaul Zimmerman #define DWC3_DEPCMD_GET_RSC_IDX(x) (((x) >> DWC3_DEPCMD_PARAM_SHIFT) & 0x7f) 358b09bb642SFelipe Balbi #define DWC3_DEPCMD_STATUS(x) (((x) >> 15) & 1) 35972246da4SFelipe Balbi #define DWC3_DEPCMD_HIPRI_FORCERM (1 << 11) 36072246da4SFelipe Balbi #define DWC3_DEPCMD_CMDACT (1 << 10) 36172246da4SFelipe Balbi #define DWC3_DEPCMD_CMDIOC (1 << 8) 36272246da4SFelipe Balbi 36372246da4SFelipe Balbi #define DWC3_DEPCMD_DEPSTARTCFG (0x09 << 0) 36472246da4SFelipe Balbi #define DWC3_DEPCMD_ENDTRANSFER (0x08 << 0) 36572246da4SFelipe Balbi #define DWC3_DEPCMD_UPDATETRANSFER (0x07 << 0) 36672246da4SFelipe Balbi #define DWC3_DEPCMD_STARTTRANSFER (0x06 << 0) 36772246da4SFelipe Balbi #define DWC3_DEPCMD_CLEARSTALL (0x05 << 0) 36872246da4SFelipe Balbi #define DWC3_DEPCMD_SETSTALL (0x04 << 0) 3692c61a8efSPaul Zimmerman /* This applies for core versions 1.90a and earlier */ 37072246da4SFelipe Balbi #define DWC3_DEPCMD_GETSEQNUMBER (0x03 << 0) 3712c61a8efSPaul Zimmerman /* This applies for core versions 1.94a and later */ 3722c61a8efSPaul Zimmerman #define DWC3_DEPCMD_GETEPSTATE (0x03 << 0) 37372246da4SFelipe Balbi #define DWC3_DEPCMD_SETTRANSFRESOURCE (0x02 << 0) 37472246da4SFelipe Balbi #define DWC3_DEPCMD_SETEPCONFIG (0x01 << 0) 37572246da4SFelipe Balbi 37672246da4SFelipe Balbi /* The EP number goes 0..31 so ep0 is always out and ep1 is always in */ 37772246da4SFelipe Balbi #define DWC3_DALEPENA_EP(n) (1 << n) 37872246da4SFelipe Balbi 37972246da4SFelipe Balbi #define DWC3_DEPCMD_TYPE_CONTROL 0 38072246da4SFelipe Balbi #define DWC3_DEPCMD_TYPE_ISOC 1 38172246da4SFelipe Balbi #define DWC3_DEPCMD_TYPE_BULK 2 38272246da4SFelipe Balbi #define DWC3_DEPCMD_TYPE_INTR 3 38372246da4SFelipe Balbi 38472246da4SFelipe Balbi /* Structures */ 38572246da4SFelipe Balbi 386f6bafc6aSFelipe Balbi struct dwc3_trb; 38772246da4SFelipe Balbi 38872246da4SFelipe Balbi /** 38972246da4SFelipe Balbi * struct dwc3_event_buffer - Software event buffer representation 39072246da4SFelipe Balbi * @buf: _THE_ buffer 39172246da4SFelipe Balbi * @length: size of this buffer 392abed4118SFelipe Balbi * @lpos: event offset 39360d04bbeSFelipe Balbi * @count: cache of last read event count register 394abed4118SFelipe Balbi * @flags: flags related to this event buffer 39572246da4SFelipe Balbi * @dma: dma_addr_t 39672246da4SFelipe Balbi * @dwc: pointer to DWC controller 39772246da4SFelipe Balbi */ 39872246da4SFelipe Balbi struct dwc3_event_buffer { 39972246da4SFelipe Balbi void *buf; 40072246da4SFelipe Balbi unsigned length; 40172246da4SFelipe Balbi unsigned int lpos; 40260d04bbeSFelipe Balbi unsigned int count; 403abed4118SFelipe Balbi unsigned int flags; 404abed4118SFelipe Balbi 405abed4118SFelipe Balbi #define DWC3_EVENT_PENDING BIT(0) 40672246da4SFelipe Balbi 40772246da4SFelipe Balbi dma_addr_t dma; 40872246da4SFelipe Balbi 40972246da4SFelipe Balbi struct dwc3 *dwc; 41072246da4SFelipe Balbi }; 41172246da4SFelipe Balbi 41272246da4SFelipe Balbi #define DWC3_EP_FLAG_STALLED (1 << 0) 41372246da4SFelipe Balbi #define DWC3_EP_FLAG_WEDGED (1 << 1) 41472246da4SFelipe Balbi 41572246da4SFelipe Balbi #define DWC3_EP_DIRECTION_TX true 41672246da4SFelipe Balbi #define DWC3_EP_DIRECTION_RX false 41772246da4SFelipe Balbi 41872246da4SFelipe Balbi #define DWC3_TRB_NUM 32 41972246da4SFelipe Balbi #define DWC3_TRB_MASK (DWC3_TRB_NUM - 1) 42072246da4SFelipe Balbi 42172246da4SFelipe Balbi /** 42272246da4SFelipe Balbi * struct dwc3_ep - device side endpoint representation 42372246da4SFelipe Balbi * @endpoint: usb endpoint 42472246da4SFelipe Balbi * @request_list: list of requests for this endpoint 42572246da4SFelipe Balbi * @req_queued: list of requests on this ep which have TRBs setup 42672246da4SFelipe Balbi * @trb_pool: array of transaction buffers 42772246da4SFelipe Balbi * @trb_pool_dma: dma address of @trb_pool 42872246da4SFelipe Balbi * @free_slot: next slot which is going to be used 42972246da4SFelipe Balbi * @busy_slot: first slot which is owned by HW 43072246da4SFelipe Balbi * @desc: usb_endpoint_descriptor pointer 43172246da4SFelipe Balbi * @dwc: pointer to DWC controller 4324cfcf876SPaul Zimmerman * @saved_state: ep state saved during hibernation 43372246da4SFelipe Balbi * @flags: endpoint flags (wedged, stalled, ...) 43472246da4SFelipe Balbi * @current_trb: index of current used trb 43572246da4SFelipe Balbi * @number: endpoint number (1 - 15) 43672246da4SFelipe Balbi * @type: set to bmAttributes & USB_ENDPOINT_XFERTYPE_MASK 437b4996a86SFelipe Balbi * @resource_index: Resource transfer index 438c75f52fbSHuang Rui * @interval: the interval on which the ISOC transfer is started 43972246da4SFelipe Balbi * @name: a human readable name e.g. ep1out-bulk 44072246da4SFelipe Balbi * @direction: true for TX, false for RX 441879631aaSFelipe Balbi * @stream_capable: true when streams are enabled 44272246da4SFelipe Balbi */ 44372246da4SFelipe Balbi struct dwc3_ep { 44472246da4SFelipe Balbi struct usb_ep endpoint; 44572246da4SFelipe Balbi struct list_head request_list; 44672246da4SFelipe Balbi struct list_head req_queued; 44772246da4SFelipe Balbi 448f6bafc6aSFelipe Balbi struct dwc3_trb *trb_pool; 44972246da4SFelipe Balbi dma_addr_t trb_pool_dma; 45072246da4SFelipe Balbi u32 free_slot; 45172246da4SFelipe Balbi u32 busy_slot; 452c90bfaecSFelipe Balbi const struct usb_ss_ep_comp_descriptor *comp_desc; 45372246da4SFelipe Balbi struct dwc3 *dwc; 45472246da4SFelipe Balbi 4554cfcf876SPaul Zimmerman u32 saved_state; 45672246da4SFelipe Balbi unsigned flags; 45772246da4SFelipe Balbi #define DWC3_EP_ENABLED (1 << 0) 45872246da4SFelipe Balbi #define DWC3_EP_STALL (1 << 1) 45972246da4SFelipe Balbi #define DWC3_EP_WEDGE (1 << 2) 46072246da4SFelipe Balbi #define DWC3_EP_BUSY (1 << 4) 46172246da4SFelipe Balbi #define DWC3_EP_PENDING_REQUEST (1 << 5) 462d6d6ec7bSPratyush Anand #define DWC3_EP_MISSED_ISOC (1 << 6) 46372246da4SFelipe Balbi 464984f66a6SFelipe Balbi /* This last one is specific to EP0 */ 465984f66a6SFelipe Balbi #define DWC3_EP0_DIR_IN (1 << 31) 466984f66a6SFelipe Balbi 46772246da4SFelipe Balbi unsigned current_trb; 46872246da4SFelipe Balbi 46972246da4SFelipe Balbi u8 number; 47072246da4SFelipe Balbi u8 type; 471b4996a86SFelipe Balbi u8 resource_index; 47272246da4SFelipe Balbi u32 interval; 47372246da4SFelipe Balbi 47472246da4SFelipe Balbi char name[20]; 47572246da4SFelipe Balbi 47672246da4SFelipe Balbi unsigned direction:1; 477879631aaSFelipe Balbi unsigned stream_capable:1; 47872246da4SFelipe Balbi }; 47972246da4SFelipe Balbi 48072246da4SFelipe Balbi enum dwc3_phy { 48172246da4SFelipe Balbi DWC3_PHY_UNKNOWN = 0, 48272246da4SFelipe Balbi DWC3_PHY_USB3, 48372246da4SFelipe Balbi DWC3_PHY_USB2, 48472246da4SFelipe Balbi }; 48572246da4SFelipe Balbi 486b53c772dSFelipe Balbi enum dwc3_ep0_next { 487b53c772dSFelipe Balbi DWC3_EP0_UNKNOWN = 0, 488b53c772dSFelipe Balbi DWC3_EP0_COMPLETE, 489b53c772dSFelipe Balbi DWC3_EP0_NRDY_DATA, 490b53c772dSFelipe Balbi DWC3_EP0_NRDY_STATUS, 491b53c772dSFelipe Balbi }; 492b53c772dSFelipe Balbi 49372246da4SFelipe Balbi enum dwc3_ep0_state { 49472246da4SFelipe Balbi EP0_UNCONNECTED = 0, 495c7fcdeb2SFelipe Balbi EP0_SETUP_PHASE, 496c7fcdeb2SFelipe Balbi EP0_DATA_PHASE, 497c7fcdeb2SFelipe Balbi EP0_STATUS_PHASE, 49872246da4SFelipe Balbi }; 49972246da4SFelipe Balbi 50072246da4SFelipe Balbi enum dwc3_link_state { 50172246da4SFelipe Balbi /* In SuperSpeed */ 50272246da4SFelipe Balbi DWC3_LINK_STATE_U0 = 0x00, /* in HS, means ON */ 50372246da4SFelipe Balbi DWC3_LINK_STATE_U1 = 0x01, 50472246da4SFelipe Balbi DWC3_LINK_STATE_U2 = 0x02, /* in HS, means SLEEP */ 50572246da4SFelipe Balbi DWC3_LINK_STATE_U3 = 0x03, /* in HS, means SUSPEND */ 50672246da4SFelipe Balbi DWC3_LINK_STATE_SS_DIS = 0x04, 50772246da4SFelipe Balbi DWC3_LINK_STATE_RX_DET = 0x05, /* in HS, means Early Suspend */ 50872246da4SFelipe Balbi DWC3_LINK_STATE_SS_INACT = 0x06, 50972246da4SFelipe Balbi DWC3_LINK_STATE_POLL = 0x07, 51072246da4SFelipe Balbi DWC3_LINK_STATE_RECOV = 0x08, 51172246da4SFelipe Balbi DWC3_LINK_STATE_HRESET = 0x09, 51272246da4SFelipe Balbi DWC3_LINK_STATE_CMPLY = 0x0a, 51372246da4SFelipe Balbi DWC3_LINK_STATE_LPBK = 0x0b, 5142c61a8efSPaul Zimmerman DWC3_LINK_STATE_RESET = 0x0e, 5152c61a8efSPaul Zimmerman DWC3_LINK_STATE_RESUME = 0x0f, 51672246da4SFelipe Balbi DWC3_LINK_STATE_MASK = 0x0f, 51772246da4SFelipe Balbi }; 51872246da4SFelipe Balbi 519f6bafc6aSFelipe Balbi /* TRB Length, PCM and Status */ 520f6bafc6aSFelipe Balbi #define DWC3_TRB_SIZE_MASK (0x00ffffff) 521f6bafc6aSFelipe Balbi #define DWC3_TRB_SIZE_LENGTH(n) ((n) & DWC3_TRB_SIZE_MASK) 522f6bafc6aSFelipe Balbi #define DWC3_TRB_SIZE_PCM1(n) (((n) & 0x03) << 24) 523389f2828SPratyush Anand #define DWC3_TRB_SIZE_TRBSTS(n) (((n) & (0x0f << 28)) >> 28) 52472246da4SFelipe Balbi 525f6bafc6aSFelipe Balbi #define DWC3_TRBSTS_OK 0 526f6bafc6aSFelipe Balbi #define DWC3_TRBSTS_MISSED_ISOC 1 527f6bafc6aSFelipe Balbi #define DWC3_TRBSTS_SETUP_PENDING 2 5282c61a8efSPaul Zimmerman #define DWC3_TRB_STS_XFER_IN_PROG 4 52972246da4SFelipe Balbi 530f6bafc6aSFelipe Balbi /* TRB Control */ 531f6bafc6aSFelipe Balbi #define DWC3_TRB_CTRL_HWO (1 << 0) 532f6bafc6aSFelipe Balbi #define DWC3_TRB_CTRL_LST (1 << 1) 533f6bafc6aSFelipe Balbi #define DWC3_TRB_CTRL_CHN (1 << 2) 534f6bafc6aSFelipe Balbi #define DWC3_TRB_CTRL_CSP (1 << 3) 535f6bafc6aSFelipe Balbi #define DWC3_TRB_CTRL_TRBCTL(n) (((n) & 0x3f) << 4) 536f6bafc6aSFelipe Balbi #define DWC3_TRB_CTRL_ISP_IMI (1 << 10) 537f6bafc6aSFelipe Balbi #define DWC3_TRB_CTRL_IOC (1 << 11) 538f6bafc6aSFelipe Balbi #define DWC3_TRB_CTRL_SID_SOFN(n) (((n) & 0xffff) << 14) 539f6bafc6aSFelipe Balbi 540f6bafc6aSFelipe Balbi #define DWC3_TRBCTL_NORMAL DWC3_TRB_CTRL_TRBCTL(1) 541f6bafc6aSFelipe Balbi #define DWC3_TRBCTL_CONTROL_SETUP DWC3_TRB_CTRL_TRBCTL(2) 542f6bafc6aSFelipe Balbi #define DWC3_TRBCTL_CONTROL_STATUS2 DWC3_TRB_CTRL_TRBCTL(3) 543f6bafc6aSFelipe Balbi #define DWC3_TRBCTL_CONTROL_STATUS3 DWC3_TRB_CTRL_TRBCTL(4) 544f6bafc6aSFelipe Balbi #define DWC3_TRBCTL_CONTROL_DATA DWC3_TRB_CTRL_TRBCTL(5) 545f6bafc6aSFelipe Balbi #define DWC3_TRBCTL_ISOCHRONOUS_FIRST DWC3_TRB_CTRL_TRBCTL(6) 546f6bafc6aSFelipe Balbi #define DWC3_TRBCTL_ISOCHRONOUS DWC3_TRB_CTRL_TRBCTL(7) 547f6bafc6aSFelipe Balbi #define DWC3_TRBCTL_LINK_TRB DWC3_TRB_CTRL_TRBCTL(8) 54872246da4SFelipe Balbi 54972246da4SFelipe Balbi /** 550f6bafc6aSFelipe Balbi * struct dwc3_trb - transfer request block (hw format) 55172246da4SFelipe Balbi * @bpl: DW0-3 55272246da4SFelipe Balbi * @bph: DW4-7 55372246da4SFelipe Balbi * @size: DW8-B 55472246da4SFelipe Balbi * @trl: DWC-F 55572246da4SFelipe Balbi */ 556f6bafc6aSFelipe Balbi struct dwc3_trb { 557f6bafc6aSFelipe Balbi u32 bpl; 558f6bafc6aSFelipe Balbi u32 bph; 559f6bafc6aSFelipe Balbi u32 size; 560f6bafc6aSFelipe Balbi u32 ctrl; 56172246da4SFelipe Balbi } __packed; 56272246da4SFelipe Balbi 56372246da4SFelipe Balbi /** 564a3299499SFelipe Balbi * dwc3_hwparams - copy of HWPARAMS registers 565a3299499SFelipe Balbi * @hwparams0 - GHWPARAMS0 566a3299499SFelipe Balbi * @hwparams1 - GHWPARAMS1 567a3299499SFelipe Balbi * @hwparams2 - GHWPARAMS2 568a3299499SFelipe Balbi * @hwparams3 - GHWPARAMS3 569a3299499SFelipe Balbi * @hwparams4 - GHWPARAMS4 570a3299499SFelipe Balbi * @hwparams5 - GHWPARAMS5 571a3299499SFelipe Balbi * @hwparams6 - GHWPARAMS6 572a3299499SFelipe Balbi * @hwparams7 - GHWPARAMS7 573a3299499SFelipe Balbi * @hwparams8 - GHWPARAMS8 574a3299499SFelipe Balbi */ 575a3299499SFelipe Balbi struct dwc3_hwparams { 576a3299499SFelipe Balbi u32 hwparams0; 577a3299499SFelipe Balbi u32 hwparams1; 578a3299499SFelipe Balbi u32 hwparams2; 579a3299499SFelipe Balbi u32 hwparams3; 580a3299499SFelipe Balbi u32 hwparams4; 581a3299499SFelipe Balbi u32 hwparams5; 582a3299499SFelipe Balbi u32 hwparams6; 583a3299499SFelipe Balbi u32 hwparams7; 584a3299499SFelipe Balbi u32 hwparams8; 585a3299499SFelipe Balbi }; 586a3299499SFelipe Balbi 5870949e99bSFelipe Balbi /* HWPARAMS0 */ 5880949e99bSFelipe Balbi #define DWC3_MODE(n) ((n) & 0x7) 5890949e99bSFelipe Balbi 590457e84b6SFelipe Balbi #define DWC3_MDWIDTH(n) (((n) & 0xff00) >> 8) 591457e84b6SFelipe Balbi 5920949e99bSFelipe Balbi /* HWPARAMS1 */ 5939f622b2aSFelipe Balbi #define DWC3_NUM_INT(n) (((n) & (0x3f << 15)) >> 15) 5949f622b2aSFelipe Balbi 595789451f6SFelipe Balbi /* HWPARAMS3 */ 596789451f6SFelipe Balbi #define DWC3_NUM_IN_EPS_MASK (0x1f << 18) 597789451f6SFelipe Balbi #define DWC3_NUM_EPS_MASK (0x3f << 12) 598789451f6SFelipe Balbi #define DWC3_NUM_EPS(p) (((p)->hwparams3 & \ 599789451f6SFelipe Balbi (DWC3_NUM_EPS_MASK)) >> 12) 600789451f6SFelipe Balbi #define DWC3_NUM_IN_EPS(p) (((p)->hwparams3 & \ 601789451f6SFelipe Balbi (DWC3_NUM_IN_EPS_MASK)) >> 18) 602789451f6SFelipe Balbi 603457e84b6SFelipe Balbi /* HWPARAMS7 */ 604457e84b6SFelipe Balbi #define DWC3_RAM1_DEPTH(n) ((n) & 0xffff) 605457e84b6SFelipe Balbi 606e0ce0b0aSSebastian Andrzej Siewior struct dwc3_request { 607e0ce0b0aSSebastian Andrzej Siewior struct usb_request request; 608e0ce0b0aSSebastian Andrzej Siewior struct list_head list; 609e0ce0b0aSSebastian Andrzej Siewior struct dwc3_ep *dep; 610e5ba5ec8SPratyush Anand u32 start_slot; 611e0ce0b0aSSebastian Andrzej Siewior 612e0ce0b0aSSebastian Andrzej Siewior u8 epnum; 613f6bafc6aSFelipe Balbi struct dwc3_trb *trb; 614e0ce0b0aSSebastian Andrzej Siewior dma_addr_t trb_dma; 615e0ce0b0aSSebastian Andrzej Siewior 616e0ce0b0aSSebastian Andrzej Siewior unsigned direction:1; 617e0ce0b0aSSebastian Andrzej Siewior unsigned mapped:1; 618e0ce0b0aSSebastian Andrzej Siewior unsigned queued:1; 619e0ce0b0aSSebastian Andrzej Siewior }; 620e0ce0b0aSSebastian Andrzej Siewior 6212c61a8efSPaul Zimmerman /* 6222c61a8efSPaul Zimmerman * struct dwc3_scratchpad_array - hibernation scratchpad array 6232c61a8efSPaul Zimmerman * (format defined by hw) 6242c61a8efSPaul Zimmerman */ 6252c61a8efSPaul Zimmerman struct dwc3_scratchpad_array { 6262c61a8efSPaul Zimmerman __le64 dma_adr[DWC3_MAX_HIBER_SCRATCHBUFS]; 6272c61a8efSPaul Zimmerman }; 6282c61a8efSPaul Zimmerman 629a3299499SFelipe Balbi /** 63072246da4SFelipe Balbi * struct dwc3 - representation of our controller 63191db07dcSFelipe Balbi * @ctrl_req: usb control request which is used for ep0 63291db07dcSFelipe Balbi * @ep0_trb: trb which is used for the ctrl_req 6335812b1c2SFelipe Balbi * @ep0_bounce: bounce buffer for ep0 63491db07dcSFelipe Balbi * @setup_buf: used while precessing STD USB requests 63591db07dcSFelipe Balbi * @ctrl_req_addr: dma address of ctrl_req 63691db07dcSFelipe Balbi * @ep0_trb: dma address of ep0_trb 63791db07dcSFelipe Balbi * @ep0_usb_req: dummy req used while handling STD USB requests 6385812b1c2SFelipe Balbi * @ep0_bounce_addr: dma address of ep0_bounce 6390ffcaf37SFelipe Balbi * @scratch_addr: dma address of scratchbuf 64072246da4SFelipe Balbi * @lock: for synchronizing 64172246da4SFelipe Balbi * @dev: pointer to our struct device 642d07e8819SFelipe Balbi * @xhci: pointer to our xHCI child 64372246da4SFelipe Balbi * @event_buffer_list: a list of event buffers 64472246da4SFelipe Balbi * @gadget: device side representation of the peripheral controller 64572246da4SFelipe Balbi * @gadget_driver: pointer to the gadget driver 64672246da4SFelipe Balbi * @regs: base address for our registers 64772246da4SFelipe Balbi * @regs_size: address space size 6480ffcaf37SFelipe Balbi * @nr_scratch: number of scratch buffers 6499f622b2aSFelipe Balbi * @num_event_buffers: calculated number of event buffers 650fae2b904SFelipe Balbi * @u1u2: only used on revisions <1.83a for workaround 6516c167fc9SFelipe Balbi * @maximum_speed: maximum speed requested (mainly for testing purposes) 65272246da4SFelipe Balbi * @revision: revision register contents 653a45c82b8SRuchika Kharwar * @dr_mode: requested mode of operation 65451e1e7bcSFelipe Balbi * @usb2_phy: pointer to USB2 PHY 65551e1e7bcSFelipe Balbi * @usb3_phy: pointer to USB3 PHY 65657303488SKishon Vijay Abraham I * @usb2_generic_phy: pointer to USB2 PHY 65757303488SKishon Vijay Abraham I * @usb3_generic_phy: pointer to USB3 PHY 6587415f17cSFelipe Balbi * @dcfg: saved contents of DCFG register 6597415f17cSFelipe Balbi * @gctl: saved contents of GCTL register 660c12a0d86SFelipe Balbi * @isoch_delay: wValue from Set Isochronous Delay request; 661865e09e7SFelipe Balbi * @u2sel: parameter from Set SEL request. 662865e09e7SFelipe Balbi * @u2pel: parameter from Set SEL request. 663865e09e7SFelipe Balbi * @u1sel: parameter from Set SEL request. 664865e09e7SFelipe Balbi * @u1pel: parameter from Set SEL request. 665789451f6SFelipe Balbi * @num_out_eps: number of out endpoints 666789451f6SFelipe Balbi * @num_in_eps: number of in endpoints 667b53c772dSFelipe Balbi * @ep0_next_event: hold the next expected event 66872246da4SFelipe Balbi * @ep0state: state of endpoint zero 66972246da4SFelipe Balbi * @link_state: link state 67072246da4SFelipe Balbi * @speed: device speed (super, high, full, low) 67172246da4SFelipe Balbi * @mem: points to start of memory which is used for this struct. 672a3299499SFelipe Balbi * @hwparams: copy of hwparams registers 67372246da4SFelipe Balbi * @root: debugfs root folder pointer 674f2b685d5SFelipe Balbi * @regset: debugfs pointer to regdump file 675f2b685d5SFelipe Balbi * @test_mode: true when we're entering a USB test mode 676f2b685d5SFelipe Balbi * @test_mode_nr: test feature selector 67780caf7d2SHuang Rui * @lpm_nyet_threshold: LPM NYET response threshold 678460d098cSHuang Rui * @hird_threshold: HIRD threshold 679f2b685d5SFelipe Balbi * @delayed_status: true when gadget driver asks for delayed status 680f2b685d5SFelipe Balbi * @ep0_bounced: true when we used bounce buffer 681f2b685d5SFelipe Balbi * @ep0_expect_in: true when we expect a DATA IN transfer 68281bc5599SFelipe Balbi * @has_hibernation: true when dwc3 was configured with Hibernation 68380caf7d2SHuang Rui * @has_lpm_erratum: true when core was configured with LPM Erratum. Note that 68480caf7d2SHuang Rui * there's now way for software to detect this in runtime. 685460d098cSHuang Rui * @is_utmi_l1_suspend: the core asserts output signal 686460d098cSHuang Rui * 0 - utmi_sleep_n 687460d098cSHuang Rui * 1 - utmi_l1_suspend_n 688f2b685d5SFelipe Balbi * @is_selfpowered: true when we are selfpowered 689946bd579SHuang Rui * @is_fpga: true when we are using the FPGA board 690f2b685d5SFelipe Balbi * @needs_fifo_resize: not all users might want fifo resizing, flag it 691f2b685d5SFelipe Balbi * @pullups_connected: true when Run/Stop bit is set 692f2b685d5SFelipe Balbi * @resize_fifos: tells us it's ok to reconfigure our TxFIFO sizes. 693f2b685d5SFelipe Balbi * @setup_packet_pending: true when there's a Setup Packet in FIFO. Workaround 694f2b685d5SFelipe Balbi * @start_config_issued: true when StartConfig command has been issued 695f2b685d5SFelipe Balbi * @three_stage_setup: set if we perform a three phase setup 6963b81221aSHuang Rui * @disable_scramble_quirk: set if we enable the disable scramble quirk 6979a5b2f31SHuang Rui * @u2exit_lfps_quirk: set if we enable u2exit lfps quirk 698b5a65c40SHuang Rui * @u2ss_inp3_quirk: set if we enable P3 OK for U2/SS Inactive quirk 699df31f5b3SHuang Rui * @req_p1p2p3_quirk: set if we enable request p1p2p3 quirk 700a2a1d0f5SHuang Rui * @del_p1p2p3_quirk: set if we enable delay p1p2p3 quirk 70141c06ffdSHuang Rui * @del_phy_power_chg_quirk: set if we enable delay phy power change quirk 702fb67afcaSHuang Rui * @lfps_filter_quirk: set if we enable LFPS filter quirk 70314f4ac53SHuang Rui * @rx_detect_poll_quirk: set if we enable rx_detect to polling lfps quirk 70459acfa20SHuang Rui * @dis_u3_susphy_quirk: set if we disable usb3 suspend phy 7050effe0a3SHuang Rui * @dis_u2_susphy_quirk: set if we disable usb2 suspend phy 7066b6a0c9aSHuang Rui * @tx_de_emphasis_quirk: set if we enable Tx de-emphasis quirk 7076b6a0c9aSHuang Rui * @tx_de_emphasis: Tx de-emphasis value 7086b6a0c9aSHuang Rui * 0 - -6dB de-emphasis 7096b6a0c9aSHuang Rui * 1 - -3.5dB de-emphasis 7106b6a0c9aSHuang Rui * 2 - No de-emphasis 7116b6a0c9aSHuang Rui * 3 - Reserved 71272246da4SFelipe Balbi */ 71372246da4SFelipe Balbi struct dwc3 { 71472246da4SFelipe Balbi struct usb_ctrlrequest *ctrl_req; 715f6bafc6aSFelipe Balbi struct dwc3_trb *ep0_trb; 7165812b1c2SFelipe Balbi void *ep0_bounce; 7170ffcaf37SFelipe Balbi void *scratchbuf; 71872246da4SFelipe Balbi u8 *setup_buf; 71972246da4SFelipe Balbi dma_addr_t ctrl_req_addr; 72072246da4SFelipe Balbi dma_addr_t ep0_trb_addr; 7215812b1c2SFelipe Balbi dma_addr_t ep0_bounce_addr; 7220ffcaf37SFelipe Balbi dma_addr_t scratch_addr; 723e0ce0b0aSSebastian Andrzej Siewior struct dwc3_request ep0_usb_req; 724789451f6SFelipe Balbi 72572246da4SFelipe Balbi /* device lock */ 72672246da4SFelipe Balbi spinlock_t lock; 727789451f6SFelipe Balbi 72872246da4SFelipe Balbi struct device *dev; 72972246da4SFelipe Balbi 730d07e8819SFelipe Balbi struct platform_device *xhci; 73151249dcaSIdo Shayevitz struct resource xhci_resources[DWC3_XHCI_RESOURCES_NUM]; 732d07e8819SFelipe Balbi 733457d3f21SFelipe Balbi struct dwc3_event_buffer **ev_buffs; 73472246da4SFelipe Balbi struct dwc3_ep *eps[DWC3_ENDPOINTS_NUM]; 73572246da4SFelipe Balbi 73672246da4SFelipe Balbi struct usb_gadget gadget; 73772246da4SFelipe Balbi struct usb_gadget_driver *gadget_driver; 73872246da4SFelipe Balbi 73951e1e7bcSFelipe Balbi struct usb_phy *usb2_phy; 74051e1e7bcSFelipe Balbi struct usb_phy *usb3_phy; 74151e1e7bcSFelipe Balbi 74257303488SKishon Vijay Abraham I struct phy *usb2_generic_phy; 74357303488SKishon Vijay Abraham I struct phy *usb3_generic_phy; 74457303488SKishon Vijay Abraham I 74572246da4SFelipe Balbi void __iomem *regs; 74672246da4SFelipe Balbi size_t regs_size; 74772246da4SFelipe Balbi 748a45c82b8SRuchika Kharwar enum usb_dr_mode dr_mode; 749a45c82b8SRuchika Kharwar 7507415f17cSFelipe Balbi /* used for suspend/resume */ 7517415f17cSFelipe Balbi u32 dcfg; 7527415f17cSFelipe Balbi u32 gctl; 7537415f17cSFelipe Balbi 7540ffcaf37SFelipe Balbi u32 nr_scratch; 7559f622b2aSFelipe Balbi u32 num_event_buffers; 756fae2b904SFelipe Balbi u32 u1u2; 7576c167fc9SFelipe Balbi u32 maximum_speed; 75872246da4SFelipe Balbi u32 revision; 75972246da4SFelipe Balbi 76072246da4SFelipe Balbi #define DWC3_REVISION_173A 0x5533173a 76172246da4SFelipe Balbi #define DWC3_REVISION_175A 0x5533175a 76272246da4SFelipe Balbi #define DWC3_REVISION_180A 0x5533180a 76372246da4SFelipe Balbi #define DWC3_REVISION_183A 0x5533183a 76472246da4SFelipe Balbi #define DWC3_REVISION_185A 0x5533185a 7652c61a8efSPaul Zimmerman #define DWC3_REVISION_187A 0x5533187a 76672246da4SFelipe Balbi #define DWC3_REVISION_188A 0x5533188a 76772246da4SFelipe Balbi #define DWC3_REVISION_190A 0x5533190a 7682c61a8efSPaul Zimmerman #define DWC3_REVISION_194A 0x5533194a 7691522d703SFelipe Balbi #define DWC3_REVISION_200A 0x5533200a 7701522d703SFelipe Balbi #define DWC3_REVISION_202A 0x5533202a 7711522d703SFelipe Balbi #define DWC3_REVISION_210A 0x5533210a 7721522d703SFelipe Balbi #define DWC3_REVISION_220A 0x5533220a 7737ac6a593SFelipe Balbi #define DWC3_REVISION_230A 0x5533230a 7747ac6a593SFelipe Balbi #define DWC3_REVISION_240A 0x5533240a 7757ac6a593SFelipe Balbi #define DWC3_REVISION_250A 0x5533250a 776dbf5aaf7SFelipe Balbi #define DWC3_REVISION_260A 0x5533260a 777dbf5aaf7SFelipe Balbi #define DWC3_REVISION_270A 0x5533270a 778dbf5aaf7SFelipe Balbi #define DWC3_REVISION_280A 0x5533280a 77972246da4SFelipe Balbi 780b53c772dSFelipe Balbi enum dwc3_ep0_next ep0_next_event; 78172246da4SFelipe Balbi enum dwc3_ep0_state ep0state; 78272246da4SFelipe Balbi enum dwc3_link_state link_state; 78372246da4SFelipe Balbi 784c12a0d86SFelipe Balbi u16 isoch_delay; 785865e09e7SFelipe Balbi u16 u2sel; 786865e09e7SFelipe Balbi u16 u2pel; 787865e09e7SFelipe Balbi u8 u1sel; 788865e09e7SFelipe Balbi u8 u1pel; 789865e09e7SFelipe Balbi 79072246da4SFelipe Balbi u8 speed; 791865e09e7SFelipe Balbi 792789451f6SFelipe Balbi u8 num_out_eps; 793789451f6SFelipe Balbi u8 num_in_eps; 794789451f6SFelipe Balbi 79572246da4SFelipe Balbi void *mem; 79672246da4SFelipe Balbi 797a3299499SFelipe Balbi struct dwc3_hwparams hwparams; 79872246da4SFelipe Balbi struct dentry *root; 799d7668024SFelipe Balbi struct debugfs_regset32 *regset; 8003b637367SGerard Cauvy 8013b637367SGerard Cauvy u8 test_mode; 8023b637367SGerard Cauvy u8 test_mode_nr; 80380caf7d2SHuang Rui u8 lpm_nyet_threshold; 804460d098cSHuang Rui u8 hird_threshold; 805f2b685d5SFelipe Balbi 806f2b685d5SFelipe Balbi unsigned delayed_status:1; 807f2b685d5SFelipe Balbi unsigned ep0_bounced:1; 808f2b685d5SFelipe Balbi unsigned ep0_expect_in:1; 80981bc5599SFelipe Balbi unsigned has_hibernation:1; 81080caf7d2SHuang Rui unsigned has_lpm_erratum:1; 811460d098cSHuang Rui unsigned is_utmi_l1_suspend:1; 812f2b685d5SFelipe Balbi unsigned is_selfpowered:1; 813946bd579SHuang Rui unsigned is_fpga:1; 814f2b685d5SFelipe Balbi unsigned needs_fifo_resize:1; 815f2b685d5SFelipe Balbi unsigned pullups_connected:1; 816f2b685d5SFelipe Balbi unsigned resize_fifos:1; 817f2b685d5SFelipe Balbi unsigned setup_packet_pending:1; 818f2b685d5SFelipe Balbi unsigned start_config_issued:1; 819f2b685d5SFelipe Balbi unsigned three_stage_setup:1; 8203b81221aSHuang Rui 8213b81221aSHuang Rui unsigned disable_scramble_quirk:1; 8229a5b2f31SHuang Rui unsigned u2exit_lfps_quirk:1; 823b5a65c40SHuang Rui unsigned u2ss_inp3_quirk:1; 824df31f5b3SHuang Rui unsigned req_p1p2p3_quirk:1; 825a2a1d0f5SHuang Rui unsigned del_p1p2p3_quirk:1; 82641c06ffdSHuang Rui unsigned del_phy_power_chg_quirk:1; 827fb67afcaSHuang Rui unsigned lfps_filter_quirk:1; 82814f4ac53SHuang Rui unsigned rx_detect_poll_quirk:1; 82959acfa20SHuang Rui unsigned dis_u3_susphy_quirk:1; 8300effe0a3SHuang Rui unsigned dis_u2_susphy_quirk:1; 8316b6a0c9aSHuang Rui 8326b6a0c9aSHuang Rui unsigned tx_de_emphasis_quirk:1; 8336b6a0c9aSHuang Rui unsigned tx_de_emphasis:2; 83472246da4SFelipe Balbi }; 83572246da4SFelipe Balbi 83672246da4SFelipe Balbi /* -------------------------------------------------------------------------- */ 83772246da4SFelipe Balbi 83872246da4SFelipe Balbi /* -------------------------------------------------------------------------- */ 83972246da4SFelipe Balbi 84072246da4SFelipe Balbi struct dwc3_event_type { 84172246da4SFelipe Balbi u32 is_devspec:1; 8421974d494SHuang Rui u32 type:7; 8431974d494SHuang Rui u32 reserved8_31:24; 84472246da4SFelipe Balbi } __packed; 84572246da4SFelipe Balbi 84672246da4SFelipe Balbi #define DWC3_DEPEVT_XFERCOMPLETE 0x01 84772246da4SFelipe Balbi #define DWC3_DEPEVT_XFERINPROGRESS 0x02 84872246da4SFelipe Balbi #define DWC3_DEPEVT_XFERNOTREADY 0x03 84972246da4SFelipe Balbi #define DWC3_DEPEVT_RXTXFIFOEVT 0x04 85072246da4SFelipe Balbi #define DWC3_DEPEVT_STREAMEVT 0x06 85172246da4SFelipe Balbi #define DWC3_DEPEVT_EPCMDCMPLT 0x07 85272246da4SFelipe Balbi 85372246da4SFelipe Balbi /** 85472246da4SFelipe Balbi * struct dwc3_event_depvt - Device Endpoint Events 85572246da4SFelipe Balbi * @one_bit: indicates this is an endpoint event (not used) 85672246da4SFelipe Balbi * @endpoint_number: number of the endpoint 85772246da4SFelipe Balbi * @endpoint_event: The event we have: 85872246da4SFelipe Balbi * 0x00 - Reserved 85972246da4SFelipe Balbi * 0x01 - XferComplete 86072246da4SFelipe Balbi * 0x02 - XferInProgress 86172246da4SFelipe Balbi * 0x03 - XferNotReady 86272246da4SFelipe Balbi * 0x04 - RxTxFifoEvt (IN->Underrun, OUT->Overrun) 86372246da4SFelipe Balbi * 0x05 - Reserved 86472246da4SFelipe Balbi * 0x06 - StreamEvt 86572246da4SFelipe Balbi * 0x07 - EPCmdCmplt 86672246da4SFelipe Balbi * @reserved11_10: Reserved, don't use. 86772246da4SFelipe Balbi * @status: Indicates the status of the event. Refer to databook for 86872246da4SFelipe Balbi * more information. 86972246da4SFelipe Balbi * @parameters: Parameters of the current event. Refer to databook for 87072246da4SFelipe Balbi * more information. 87172246da4SFelipe Balbi */ 87272246da4SFelipe Balbi struct dwc3_event_depevt { 87372246da4SFelipe Balbi u32 one_bit:1; 87472246da4SFelipe Balbi u32 endpoint_number:5; 87572246da4SFelipe Balbi u32 endpoint_event:4; 87672246da4SFelipe Balbi u32 reserved11_10:2; 87772246da4SFelipe Balbi u32 status:4; 87840aa41fbSFelipe Balbi 87940aa41fbSFelipe Balbi /* Within XferNotReady */ 88040aa41fbSFelipe Balbi #define DEPEVT_STATUS_TRANSFER_ACTIVE (1 << 3) 88140aa41fbSFelipe Balbi 88240aa41fbSFelipe Balbi /* Within XferComplete */ 88372246da4SFelipe Balbi #define DEPEVT_STATUS_BUSERR (1 << 0) 88472246da4SFelipe Balbi #define DEPEVT_STATUS_SHORT (1 << 1) 88572246da4SFelipe Balbi #define DEPEVT_STATUS_IOC (1 << 2) 88672246da4SFelipe Balbi #define DEPEVT_STATUS_LST (1 << 3) 887dc137f01SFelipe Balbi 888879631aaSFelipe Balbi /* Stream event only */ 889879631aaSFelipe Balbi #define DEPEVT_STREAMEVT_FOUND 1 890879631aaSFelipe Balbi #define DEPEVT_STREAMEVT_NOTFOUND 2 891879631aaSFelipe Balbi 892dc137f01SFelipe Balbi /* Control-only Status */ 893dc137f01SFelipe Balbi #define DEPEVT_STATUS_CONTROL_DATA 1 894dc137f01SFelipe Balbi #define DEPEVT_STATUS_CONTROL_STATUS 2 895dc137f01SFelipe Balbi 89672246da4SFelipe Balbi u32 parameters:16; 89772246da4SFelipe Balbi } __packed; 89872246da4SFelipe Balbi 89972246da4SFelipe Balbi /** 90072246da4SFelipe Balbi * struct dwc3_event_devt - Device Events 90172246da4SFelipe Balbi * @one_bit: indicates this is a non-endpoint event (not used) 90272246da4SFelipe Balbi * @device_event: indicates it's a device event. Should read as 0x00 90372246da4SFelipe Balbi * @type: indicates the type of device event. 90472246da4SFelipe Balbi * 0 - DisconnEvt 90572246da4SFelipe Balbi * 1 - USBRst 90672246da4SFelipe Balbi * 2 - ConnectDone 90772246da4SFelipe Balbi * 3 - ULStChng 90872246da4SFelipe Balbi * 4 - WkUpEvt 90972246da4SFelipe Balbi * 5 - Reserved 91072246da4SFelipe Balbi * 6 - EOPF 91172246da4SFelipe Balbi * 7 - SOF 91272246da4SFelipe Balbi * 8 - Reserved 91372246da4SFelipe Balbi * 9 - ErrticErr 91472246da4SFelipe Balbi * 10 - CmdCmplt 91572246da4SFelipe Balbi * 11 - EvntOverflow 91672246da4SFelipe Balbi * 12 - VndrDevTstRcved 91772246da4SFelipe Balbi * @reserved15_12: Reserved, not used 91872246da4SFelipe Balbi * @event_info: Information about this event 91906f9b6e5SHuang Rui * @reserved31_25: Reserved, not used 92072246da4SFelipe Balbi */ 92172246da4SFelipe Balbi struct dwc3_event_devt { 92272246da4SFelipe Balbi u32 one_bit:1; 92372246da4SFelipe Balbi u32 device_event:7; 92472246da4SFelipe Balbi u32 type:4; 92572246da4SFelipe Balbi u32 reserved15_12:4; 92606f9b6e5SHuang Rui u32 event_info:9; 92706f9b6e5SHuang Rui u32 reserved31_25:7; 92872246da4SFelipe Balbi } __packed; 92972246da4SFelipe Balbi 93072246da4SFelipe Balbi /** 93172246da4SFelipe Balbi * struct dwc3_event_gevt - Other Core Events 93272246da4SFelipe Balbi * @one_bit: indicates this is a non-endpoint event (not used) 93372246da4SFelipe Balbi * @device_event: indicates it's (0x03) Carkit or (0x04) I2C event. 93472246da4SFelipe Balbi * @phy_port_number: self-explanatory 93572246da4SFelipe Balbi * @reserved31_12: Reserved, not used. 93672246da4SFelipe Balbi */ 93772246da4SFelipe Balbi struct dwc3_event_gevt { 93872246da4SFelipe Balbi u32 one_bit:1; 93972246da4SFelipe Balbi u32 device_event:7; 94072246da4SFelipe Balbi u32 phy_port_number:4; 94172246da4SFelipe Balbi u32 reserved31_12:20; 94272246da4SFelipe Balbi } __packed; 94372246da4SFelipe Balbi 94472246da4SFelipe Balbi /** 94572246da4SFelipe Balbi * union dwc3_event - representation of Event Buffer contents 94672246da4SFelipe Balbi * @raw: raw 32-bit event 94772246da4SFelipe Balbi * @type: the type of the event 94872246da4SFelipe Balbi * @depevt: Device Endpoint Event 94972246da4SFelipe Balbi * @devt: Device Event 95072246da4SFelipe Balbi * @gevt: Global Event 95172246da4SFelipe Balbi */ 95272246da4SFelipe Balbi union dwc3_event { 95372246da4SFelipe Balbi u32 raw; 95472246da4SFelipe Balbi struct dwc3_event_type type; 95572246da4SFelipe Balbi struct dwc3_event_depevt depevt; 95672246da4SFelipe Balbi struct dwc3_event_devt devt; 95772246da4SFelipe Balbi struct dwc3_event_gevt gevt; 95872246da4SFelipe Balbi }; 95972246da4SFelipe Balbi 96061018305SFelipe Balbi /** 96161018305SFelipe Balbi * struct dwc3_gadget_ep_cmd_params - representation of endpoint command 96261018305SFelipe Balbi * parameters 96361018305SFelipe Balbi * @param2: third parameter 96461018305SFelipe Balbi * @param1: second parameter 96561018305SFelipe Balbi * @param0: first parameter 96661018305SFelipe Balbi */ 96761018305SFelipe Balbi struct dwc3_gadget_ep_cmd_params { 96861018305SFelipe Balbi u32 param2; 96961018305SFelipe Balbi u32 param1; 97061018305SFelipe Balbi u32 param0; 97161018305SFelipe Balbi }; 97261018305SFelipe Balbi 97372246da4SFelipe Balbi /* 97472246da4SFelipe Balbi * DWC3 Features to be used as Driver Data 97572246da4SFelipe Balbi */ 97672246da4SFelipe Balbi 97772246da4SFelipe Balbi #define DWC3_HAS_PERIPHERAL BIT(0) 97872246da4SFelipe Balbi #define DWC3_HAS_XHCI BIT(1) 97972246da4SFelipe Balbi #define DWC3_HAS_OTG BIT(3) 98072246da4SFelipe Balbi 981d07e8819SFelipe Balbi /* prototypes */ 9823140e8cbSSebastian Andrzej Siewior void dwc3_set_mode(struct dwc3 *dwc, u32 mode); 983457e84b6SFelipe Balbi int dwc3_gadget_resize_tx_fifos(struct dwc3 *dwc); 9843140e8cbSSebastian Andrzej Siewior 985388e5c51SVivek Gautam #if IS_ENABLED(CONFIG_USB_DWC3_HOST) || IS_ENABLED(CONFIG_USB_DWC3_DUAL_ROLE) 986d07e8819SFelipe Balbi int dwc3_host_init(struct dwc3 *dwc); 987d07e8819SFelipe Balbi void dwc3_host_exit(struct dwc3 *dwc); 988388e5c51SVivek Gautam #else 989388e5c51SVivek Gautam static inline int dwc3_host_init(struct dwc3 *dwc) 990388e5c51SVivek Gautam { return 0; } 991388e5c51SVivek Gautam static inline void dwc3_host_exit(struct dwc3 *dwc) 992388e5c51SVivek Gautam { } 993388e5c51SVivek Gautam #endif 994d07e8819SFelipe Balbi 995388e5c51SVivek Gautam #if IS_ENABLED(CONFIG_USB_DWC3_GADGET) || IS_ENABLED(CONFIG_USB_DWC3_DUAL_ROLE) 996f80b45e7SFelipe Balbi int dwc3_gadget_init(struct dwc3 *dwc); 997f80b45e7SFelipe Balbi void dwc3_gadget_exit(struct dwc3 *dwc); 99861018305SFelipe Balbi int dwc3_gadget_set_test_mode(struct dwc3 *dwc, int mode); 99961018305SFelipe Balbi int dwc3_gadget_get_link_state(struct dwc3 *dwc); 100061018305SFelipe Balbi int dwc3_gadget_set_link_state(struct dwc3 *dwc, enum dwc3_link_state state); 100161018305SFelipe Balbi int dwc3_send_gadget_ep_cmd(struct dwc3 *dwc, unsigned ep, 100261018305SFelipe Balbi unsigned cmd, struct dwc3_gadget_ep_cmd_params *params); 10033ece0ec4SFelipe Balbi int dwc3_send_gadget_generic_command(struct dwc3 *dwc, unsigned cmd, u32 param); 1004388e5c51SVivek Gautam #else 1005388e5c51SVivek Gautam static inline int dwc3_gadget_init(struct dwc3 *dwc) 1006388e5c51SVivek Gautam { return 0; } 1007388e5c51SVivek Gautam static inline void dwc3_gadget_exit(struct dwc3 *dwc) 1008388e5c51SVivek Gautam { } 100961018305SFelipe Balbi static inline int dwc3_gadget_set_test_mode(struct dwc3 *dwc, int mode) 101061018305SFelipe Balbi { return 0; } 101161018305SFelipe Balbi static inline int dwc3_gadget_get_link_state(struct dwc3 *dwc) 101261018305SFelipe Balbi { return 0; } 101361018305SFelipe Balbi static inline int dwc3_gadget_set_link_state(struct dwc3 *dwc, 101461018305SFelipe Balbi enum dwc3_link_state state) 101561018305SFelipe Balbi { return 0; } 101661018305SFelipe Balbi 101761018305SFelipe Balbi static inline int dwc3_send_gadget_ep_cmd(struct dwc3 *dwc, unsigned ep, 101861018305SFelipe Balbi unsigned cmd, struct dwc3_gadget_ep_cmd_params *params) 101961018305SFelipe Balbi { return 0; } 102061018305SFelipe Balbi static inline int dwc3_send_gadget_generic_command(struct dwc3 *dwc, 102161018305SFelipe Balbi int cmd, u32 param) 102261018305SFelipe Balbi { return 0; } 1023388e5c51SVivek Gautam #endif 1024f80b45e7SFelipe Balbi 10257415f17cSFelipe Balbi /* power management interface */ 10267415f17cSFelipe Balbi #if !IS_ENABLED(CONFIG_USB_DWC3_HOST) 10277415f17cSFelipe Balbi int dwc3_gadget_suspend(struct dwc3 *dwc); 10287415f17cSFelipe Balbi int dwc3_gadget_resume(struct dwc3 *dwc); 10297415f17cSFelipe Balbi #else 10307415f17cSFelipe Balbi static inline int dwc3_gadget_suspend(struct dwc3 *dwc) 10317415f17cSFelipe Balbi { 10327415f17cSFelipe Balbi return 0; 10337415f17cSFelipe Balbi } 10347415f17cSFelipe Balbi 10357415f17cSFelipe Balbi static inline int dwc3_gadget_resume(struct dwc3 *dwc) 10367415f17cSFelipe Balbi { 10377415f17cSFelipe Balbi return 0; 10387415f17cSFelipe Balbi } 10397415f17cSFelipe Balbi #endif /* !IS_ENABLED(CONFIG_USB_DWC3_HOST) */ 10407415f17cSFelipe Balbi 104172246da4SFelipe Balbi #endif /* __DRIVERS_USB_DWC3_CORE_H */ 1042