172246da4SFelipe Balbi /** 272246da4SFelipe Balbi * core.h - DesignWare USB3 DRD Core Header 372246da4SFelipe Balbi * 472246da4SFelipe Balbi * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com 572246da4SFelipe Balbi * 672246da4SFelipe Balbi * Authors: Felipe Balbi <balbi@ti.com>, 772246da4SFelipe Balbi * Sebastian Andrzej Siewior <bigeasy@linutronix.de> 872246da4SFelipe Balbi * 95945f789SFelipe Balbi * This program is free software: you can redistribute it and/or modify 105945f789SFelipe Balbi * it under the terms of the GNU General Public License version 2 of 115945f789SFelipe Balbi * the License as published by the Free Software Foundation. 1272246da4SFelipe Balbi * 135945f789SFelipe Balbi * This program is distributed in the hope that it will be useful, 145945f789SFelipe Balbi * but WITHOUT ANY WARRANTY; without even the implied warranty of 155945f789SFelipe Balbi * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 165945f789SFelipe Balbi * GNU General Public License for more details. 1772246da4SFelipe Balbi */ 1872246da4SFelipe Balbi 1972246da4SFelipe Balbi #ifndef __DRIVERS_USB_DWC3_CORE_H 2072246da4SFelipe Balbi #define __DRIVERS_USB_DWC3_CORE_H 2172246da4SFelipe Balbi 2272246da4SFelipe Balbi #include <linux/device.h> 2372246da4SFelipe Balbi #include <linux/spinlock.h> 24d07e8819SFelipe Balbi #include <linux/ioport.h> 2572246da4SFelipe Balbi #include <linux/list.h> 2672246da4SFelipe Balbi #include <linux/dma-mapping.h> 2772246da4SFelipe Balbi #include <linux/mm.h> 2872246da4SFelipe Balbi #include <linux/debugfs.h> 2972246da4SFelipe Balbi 3072246da4SFelipe Balbi #include <linux/usb/ch9.h> 3172246da4SFelipe Balbi #include <linux/usb/gadget.h> 32a45c82b8SRuchika Kharwar #include <linux/usb/otg.h> 3372246da4SFelipe Balbi 3457303488SKishon Vijay Abraham I #include <linux/phy/phy.h> 3557303488SKishon Vijay Abraham I 362c4cbe6eSFelipe Balbi #define DWC3_MSG_MAX 500 372c4cbe6eSFelipe Balbi 3872246da4SFelipe Balbi /* Global constants */ 393ef35fafSFelipe Balbi #define DWC3_EP0_BOUNCE_SIZE 512 4072246da4SFelipe Balbi #define DWC3_ENDPOINTS_NUM 32 4151249dcaSIdo Shayevitz #define DWC3_XHCI_RESOURCES_NUM 2 4272246da4SFelipe Balbi 430ffcaf37SFelipe Balbi #define DWC3_SCRATCHBUF_SIZE 4096 /* each buffer is assumed to be 4KiB */ 445da93478SFelipe Balbi #define DWC3_EVENT_SIZE 4 /* bytes */ 455da93478SFelipe Balbi #define DWC3_EVENT_MAX_NUM 64 /* 2 events/endpoint */ 465da93478SFelipe Balbi #define DWC3_EVENT_BUFFERS_SIZE (DWC3_EVENT_SIZE * DWC3_EVENT_MAX_NUM) 4772246da4SFelipe Balbi #define DWC3_EVENT_TYPE_MASK 0xfe 4872246da4SFelipe Balbi 4972246da4SFelipe Balbi #define DWC3_EVENT_TYPE_DEV 0 5072246da4SFelipe Balbi #define DWC3_EVENT_TYPE_CARKIT 3 5172246da4SFelipe Balbi #define DWC3_EVENT_TYPE_I2C 4 5272246da4SFelipe Balbi 5372246da4SFelipe Balbi #define DWC3_DEVICE_EVENT_DISCONNECT 0 5472246da4SFelipe Balbi #define DWC3_DEVICE_EVENT_RESET 1 5572246da4SFelipe Balbi #define DWC3_DEVICE_EVENT_CONNECT_DONE 2 5672246da4SFelipe Balbi #define DWC3_DEVICE_EVENT_LINK_STATUS_CHANGE 3 5772246da4SFelipe Balbi #define DWC3_DEVICE_EVENT_WAKEUP 4 582c61a8efSPaul Zimmerman #define DWC3_DEVICE_EVENT_HIBER_REQ 5 5972246da4SFelipe Balbi #define DWC3_DEVICE_EVENT_EOPF 6 6072246da4SFelipe Balbi #define DWC3_DEVICE_EVENT_SOF 7 6172246da4SFelipe Balbi #define DWC3_DEVICE_EVENT_ERRATIC_ERROR 9 6272246da4SFelipe Balbi #define DWC3_DEVICE_EVENT_CMD_CMPL 10 6372246da4SFelipe Balbi #define DWC3_DEVICE_EVENT_OVERFLOW 11 6472246da4SFelipe Balbi 6572246da4SFelipe Balbi #define DWC3_GEVNTCOUNT_MASK 0xfffc 6672246da4SFelipe Balbi #define DWC3_GSNPSID_MASK 0xffff0000 6772246da4SFelipe Balbi #define DWC3_GSNPSREV_MASK 0xffff 6872246da4SFelipe Balbi 6951249dcaSIdo Shayevitz /* DWC3 registers memory space boundries */ 7051249dcaSIdo Shayevitz #define DWC3_XHCI_REGS_START 0x0 7151249dcaSIdo Shayevitz #define DWC3_XHCI_REGS_END 0x7fff 7251249dcaSIdo Shayevitz #define DWC3_GLOBALS_REGS_START 0xc100 7351249dcaSIdo Shayevitz #define DWC3_GLOBALS_REGS_END 0xc6ff 7451249dcaSIdo Shayevitz #define DWC3_DEVICE_REGS_START 0xc700 7551249dcaSIdo Shayevitz #define DWC3_DEVICE_REGS_END 0xcbff 7651249dcaSIdo Shayevitz #define DWC3_OTG_REGS_START 0xcc00 7751249dcaSIdo Shayevitz #define DWC3_OTG_REGS_END 0xccff 7851249dcaSIdo Shayevitz 7972246da4SFelipe Balbi /* Global Registers */ 8072246da4SFelipe Balbi #define DWC3_GSBUSCFG0 0xc100 8172246da4SFelipe Balbi #define DWC3_GSBUSCFG1 0xc104 8272246da4SFelipe Balbi #define DWC3_GTXTHRCFG 0xc108 8372246da4SFelipe Balbi #define DWC3_GRXTHRCFG 0xc10c 8472246da4SFelipe Balbi #define DWC3_GCTL 0xc110 8572246da4SFelipe Balbi #define DWC3_GEVTEN 0xc114 8672246da4SFelipe Balbi #define DWC3_GSTS 0xc118 8772246da4SFelipe Balbi #define DWC3_GSNPSID 0xc120 8872246da4SFelipe Balbi #define DWC3_GGPIO 0xc124 8972246da4SFelipe Balbi #define DWC3_GUID 0xc128 9072246da4SFelipe Balbi #define DWC3_GUCTL 0xc12c 9172246da4SFelipe Balbi #define DWC3_GBUSERRADDR0 0xc130 9272246da4SFelipe Balbi #define DWC3_GBUSERRADDR1 0xc134 9372246da4SFelipe Balbi #define DWC3_GPRTBIMAP0 0xc138 9472246da4SFelipe Balbi #define DWC3_GPRTBIMAP1 0xc13c 9572246da4SFelipe Balbi #define DWC3_GHWPARAMS0 0xc140 9672246da4SFelipe Balbi #define DWC3_GHWPARAMS1 0xc144 9772246da4SFelipe Balbi #define DWC3_GHWPARAMS2 0xc148 9872246da4SFelipe Balbi #define DWC3_GHWPARAMS3 0xc14c 9972246da4SFelipe Balbi #define DWC3_GHWPARAMS4 0xc150 10072246da4SFelipe Balbi #define DWC3_GHWPARAMS5 0xc154 10172246da4SFelipe Balbi #define DWC3_GHWPARAMS6 0xc158 10272246da4SFelipe Balbi #define DWC3_GHWPARAMS7 0xc15c 10372246da4SFelipe Balbi #define DWC3_GDBGFIFOSPACE 0xc160 10472246da4SFelipe Balbi #define DWC3_GDBGLTSSM 0xc164 10572246da4SFelipe Balbi #define DWC3_GPRTBIMAP_HS0 0xc180 10672246da4SFelipe Balbi #define DWC3_GPRTBIMAP_HS1 0xc184 10772246da4SFelipe Balbi #define DWC3_GPRTBIMAP_FS0 0xc188 10872246da4SFelipe Balbi #define DWC3_GPRTBIMAP_FS1 0xc18c 10972246da4SFelipe Balbi 11072246da4SFelipe Balbi #define DWC3_GUSB2PHYCFG(n) (0xc200 + (n * 0x04)) 11172246da4SFelipe Balbi #define DWC3_GUSB2I2CCTL(n) (0xc240 + (n * 0x04)) 11272246da4SFelipe Balbi 11372246da4SFelipe Balbi #define DWC3_GUSB2PHYACC(n) (0xc280 + (n * 0x04)) 11472246da4SFelipe Balbi 11572246da4SFelipe Balbi #define DWC3_GUSB3PIPECTL(n) (0xc2c0 + (n * 0x04)) 11672246da4SFelipe Balbi 11772246da4SFelipe Balbi #define DWC3_GTXFIFOSIZ(n) (0xc300 + (n * 0x04)) 11872246da4SFelipe Balbi #define DWC3_GRXFIFOSIZ(n) (0xc380 + (n * 0x04)) 11972246da4SFelipe Balbi 12072246da4SFelipe Balbi #define DWC3_GEVNTADRLO(n) (0xc400 + (n * 0x10)) 12172246da4SFelipe Balbi #define DWC3_GEVNTADRHI(n) (0xc404 + (n * 0x10)) 12272246da4SFelipe Balbi #define DWC3_GEVNTSIZ(n) (0xc408 + (n * 0x10)) 12372246da4SFelipe Balbi #define DWC3_GEVNTCOUNT(n) (0xc40c + (n * 0x10)) 12472246da4SFelipe Balbi 12572246da4SFelipe Balbi #define DWC3_GHWPARAMS8 0xc600 12672246da4SFelipe Balbi 12772246da4SFelipe Balbi /* Device Registers */ 12872246da4SFelipe Balbi #define DWC3_DCFG 0xc700 12972246da4SFelipe Balbi #define DWC3_DCTL 0xc704 13072246da4SFelipe Balbi #define DWC3_DEVTEN 0xc708 13172246da4SFelipe Balbi #define DWC3_DSTS 0xc70c 13272246da4SFelipe Balbi #define DWC3_DGCMDPAR 0xc710 13372246da4SFelipe Balbi #define DWC3_DGCMD 0xc714 13472246da4SFelipe Balbi #define DWC3_DALEPENA 0xc720 13572246da4SFelipe Balbi #define DWC3_DEPCMDPAR2(n) (0xc800 + (n * 0x10)) 13672246da4SFelipe Balbi #define DWC3_DEPCMDPAR1(n) (0xc804 + (n * 0x10)) 13772246da4SFelipe Balbi #define DWC3_DEPCMDPAR0(n) (0xc808 + (n * 0x10)) 13872246da4SFelipe Balbi #define DWC3_DEPCMD(n) (0xc80c + (n * 0x10)) 13972246da4SFelipe Balbi 14072246da4SFelipe Balbi /* OTG Registers */ 14172246da4SFelipe Balbi #define DWC3_OCFG 0xcc00 14272246da4SFelipe Balbi #define DWC3_OCTL 0xcc04 143d4436c3aSGeorge Cherian #define DWC3_OEVT 0xcc08 144d4436c3aSGeorge Cherian #define DWC3_OEVTEN 0xcc0C 145d4436c3aSGeorge Cherian #define DWC3_OSTS 0xcc10 14672246da4SFelipe Balbi 14772246da4SFelipe Balbi /* Bit fields */ 14872246da4SFelipe Balbi 14972246da4SFelipe Balbi /* Global Configuration Register */ 1501d046793SPaul Zimmerman #define DWC3_GCTL_PWRDNSCALE(n) ((n) << 19) 151f4aadbe4SFelipe Balbi #define DWC3_GCTL_U2RSTECN (1 << 16) 1521d046793SPaul Zimmerman #define DWC3_GCTL_RAMCLKSEL(x) (((x) & DWC3_GCTL_CLK_MASK) << 6) 15372246da4SFelipe Balbi #define DWC3_GCTL_CLK_BUS (0) 15472246da4SFelipe Balbi #define DWC3_GCTL_CLK_PIPE (1) 15572246da4SFelipe Balbi #define DWC3_GCTL_CLK_PIPEHALF (2) 15672246da4SFelipe Balbi #define DWC3_GCTL_CLK_MASK (3) 15772246da4SFelipe Balbi 1580b9fe32dSFelipe Balbi #define DWC3_GCTL_PRTCAP(n) (((n) & (3 << 12)) >> 12) 1591d046793SPaul Zimmerman #define DWC3_GCTL_PRTCAPDIR(n) ((n) << 12) 16072246da4SFelipe Balbi #define DWC3_GCTL_PRTCAP_HOST 1 16172246da4SFelipe Balbi #define DWC3_GCTL_PRTCAP_DEVICE 2 16272246da4SFelipe Balbi #define DWC3_GCTL_PRTCAP_OTG 3 16372246da4SFelipe Balbi 16472246da4SFelipe Balbi #define DWC3_GCTL_CORESOFTRESET (1 << 11) 165183ca111SFelipe Balbi #define DWC3_GCTL_SOFITPSYNC (1 << 10) 1661d046793SPaul Zimmerman #define DWC3_GCTL_SCALEDOWN(n) ((n) << 4) 1673e87c42aSPaul Zimmerman #define DWC3_GCTL_SCALEDOWN_MASK DWC3_GCTL_SCALEDOWN(3) 16872246da4SFelipe Balbi #define DWC3_GCTL_DISSCRAMBLE (1 << 3) 1699a5b2f31SHuang Rui #define DWC3_GCTL_U2EXIT_LFPS (1 << 2) 1702c61a8efSPaul Zimmerman #define DWC3_GCTL_GBLHIBERNATIONEN (1 << 1) 171aabb7075SFelipe Balbi #define DWC3_GCTL_DSBLCLKGTNG (1 << 0) 17272246da4SFelipe Balbi 17372246da4SFelipe Balbi /* Global USB2 PHY Configuration Register */ 17472246da4SFelipe Balbi #define DWC3_GUSB2PHYCFG_PHYSOFTRST (1 << 31) 17572246da4SFelipe Balbi #define DWC3_GUSB2PHYCFG_SUSPHY (1 << 6) 17672246da4SFelipe Balbi 17772246da4SFelipe Balbi /* Global USB3 PIPE Control Register */ 17872246da4SFelipe Balbi #define DWC3_GUSB3PIPECTL_PHYSOFTRST (1 << 31) 179b5a65c40SHuang Rui #define DWC3_GUSB3PIPECTL_U2SSINP3OK (1 << 29) 180df31f5b3SHuang Rui #define DWC3_GUSB3PIPECTL_REQP1P2P3 (1 << 24) 181a2a1d0f5SHuang Rui #define DWC3_GUSB3PIPECTL_DEP1P2P3(n) ((n) << 19) 182a2a1d0f5SHuang Rui #define DWC3_GUSB3PIPECTL_DEP1P2P3_MASK DWC3_GUSB3PIPECTL_DEP1P2P3(7) 183a2a1d0f5SHuang Rui #define DWC3_GUSB3PIPECTL_DEP1P2P3_EN DWC3_GUSB3PIPECTL_DEP1P2P3(1) 18441c06ffdSHuang Rui #define DWC3_GUSB3PIPECTL_DEPOCHANGE (1 << 18) 18572246da4SFelipe Balbi #define DWC3_GUSB3PIPECTL_SUSPHY (1 << 17) 18672246da4SFelipe Balbi 187457e84b6SFelipe Balbi /* Global TX Fifo Size Register */ 188457e84b6SFelipe Balbi #define DWC3_GTXFIFOSIZ_TXFDEF(n) ((n) & 0xffff) 189457e84b6SFelipe Balbi #define DWC3_GTXFIFOSIZ_TXFSTADDR(n) ((n) & 0xffff0000) 190457e84b6SFelipe Balbi 19168d6a01bSFelipe Balbi /* Global Event Size Registers */ 19268d6a01bSFelipe Balbi #define DWC3_GEVNTSIZ_INTMASK (1 << 31) 19368d6a01bSFelipe Balbi #define DWC3_GEVNTSIZ_SIZE(n) ((n) & 0xffff) 19468d6a01bSFelipe Balbi 195aabb7075SFelipe Balbi /* Global HWPARAMS1 Register */ 1961d046793SPaul Zimmerman #define DWC3_GHWPARAMS1_EN_PWROPT(n) (((n) & (3 << 24)) >> 24) 197aabb7075SFelipe Balbi #define DWC3_GHWPARAMS1_EN_PWROPT_NO 0 198aabb7075SFelipe Balbi #define DWC3_GHWPARAMS1_EN_PWROPT_CLK 1 1992c61a8efSPaul Zimmerman #define DWC3_GHWPARAMS1_EN_PWROPT_HIB 2 2002c61a8efSPaul Zimmerman #define DWC3_GHWPARAMS1_PWROPT(n) ((n) << 24) 2012c61a8efSPaul Zimmerman #define DWC3_GHWPARAMS1_PWROPT_MASK DWC3_GHWPARAMS1_PWROPT(3) 2022c61a8efSPaul Zimmerman 2030e1e5c47SPaul Zimmerman /* Global HWPARAMS3 Register */ 2040e1e5c47SPaul Zimmerman #define DWC3_GHWPARAMS3_SSPHY_IFC(n) ((n) & 3) 2050e1e5c47SPaul Zimmerman #define DWC3_GHWPARAMS3_SSPHY_IFC_DIS 0 2060e1e5c47SPaul Zimmerman #define DWC3_GHWPARAMS3_SSPHY_IFC_ENA 1 2070e1e5c47SPaul Zimmerman #define DWC3_GHWPARAMS3_HSPHY_IFC(n) (((n) & (3 << 2)) >> 2) 2080e1e5c47SPaul Zimmerman #define DWC3_GHWPARAMS3_HSPHY_IFC_DIS 0 2090e1e5c47SPaul Zimmerman #define DWC3_GHWPARAMS3_HSPHY_IFC_UTMI 1 2100e1e5c47SPaul Zimmerman #define DWC3_GHWPARAMS3_HSPHY_IFC_ULPI 2 2110e1e5c47SPaul Zimmerman #define DWC3_GHWPARAMS3_HSPHY_IFC_UTMI_ULPI 3 2120e1e5c47SPaul Zimmerman #define DWC3_GHWPARAMS3_FSPHY_IFC(n) (((n) & (3 << 4)) >> 4) 2130e1e5c47SPaul Zimmerman #define DWC3_GHWPARAMS3_FSPHY_IFC_DIS 0 2140e1e5c47SPaul Zimmerman #define DWC3_GHWPARAMS3_FSPHY_IFC_ENA 1 2150e1e5c47SPaul Zimmerman 2162c61a8efSPaul Zimmerman /* Global HWPARAMS4 Register */ 2172c61a8efSPaul Zimmerman #define DWC3_GHWPARAMS4_HIBER_SCRATCHBUFS(n) (((n) & (0x0f << 13)) >> 13) 2182c61a8efSPaul Zimmerman #define DWC3_MAX_HIBER_SCRATCHBUFS 15 219aabb7075SFelipe Balbi 220946bd579SHuang Rui /* Global HWPARAMS6 Register */ 221946bd579SHuang Rui #define DWC3_GHWPARAMS6_EN_FPGA (1 << 7) 222946bd579SHuang Rui 22372246da4SFelipe Balbi /* Device Configuration Register */ 22472246da4SFelipe Balbi #define DWC3_DCFG_DEVADDR(addr) ((addr) << 3) 22572246da4SFelipe Balbi #define DWC3_DCFG_DEVADDR_MASK DWC3_DCFG_DEVADDR(0x7f) 22672246da4SFelipe Balbi 22772246da4SFelipe Balbi #define DWC3_DCFG_SPEED_MASK (7 << 0) 22872246da4SFelipe Balbi #define DWC3_DCFG_SUPERSPEED (4 << 0) 22972246da4SFelipe Balbi #define DWC3_DCFG_HIGHSPEED (0 << 0) 23072246da4SFelipe Balbi #define DWC3_DCFG_FULLSPEED2 (1 << 0) 23172246da4SFelipe Balbi #define DWC3_DCFG_LOWSPEED (2 << 0) 23272246da4SFelipe Balbi #define DWC3_DCFG_FULLSPEED1 (3 << 0) 23372246da4SFelipe Balbi 2342c61a8efSPaul Zimmerman #define DWC3_DCFG_LPM_CAP (1 << 22) 2352c61a8efSPaul Zimmerman 23672246da4SFelipe Balbi /* Device Control Register */ 23772246da4SFelipe Balbi #define DWC3_DCTL_RUN_STOP (1 << 31) 23872246da4SFelipe Balbi #define DWC3_DCTL_CSFTRST (1 << 30) 23972246da4SFelipe Balbi #define DWC3_DCTL_LSFTRST (1 << 29) 24072246da4SFelipe Balbi 24172246da4SFelipe Balbi #define DWC3_DCTL_HIRD_THRES_MASK (0x1f << 24) 2427e39b817SPratyush Anand #define DWC3_DCTL_HIRD_THRES(n) ((n) << 24) 24372246da4SFelipe Balbi 24472246da4SFelipe Balbi #define DWC3_DCTL_APPL1RES (1 << 23) 24572246da4SFelipe Balbi 2462c61a8efSPaul Zimmerman /* These apply for core versions 1.87a and earlier */ 2478db7ed15SFelipe Balbi #define DWC3_DCTL_TRGTULST_MASK (0x0f << 17) 2488db7ed15SFelipe Balbi #define DWC3_DCTL_TRGTULST(n) ((n) << 17) 2498db7ed15SFelipe Balbi #define DWC3_DCTL_TRGTULST_U2 (DWC3_DCTL_TRGTULST(2)) 2508db7ed15SFelipe Balbi #define DWC3_DCTL_TRGTULST_U3 (DWC3_DCTL_TRGTULST(3)) 2518db7ed15SFelipe Balbi #define DWC3_DCTL_TRGTULST_SS_DIS (DWC3_DCTL_TRGTULST(4)) 2528db7ed15SFelipe Balbi #define DWC3_DCTL_TRGTULST_RX_DET (DWC3_DCTL_TRGTULST(5)) 2538db7ed15SFelipe Balbi #define DWC3_DCTL_TRGTULST_SS_INACT (DWC3_DCTL_TRGTULST(6)) 2548db7ed15SFelipe Balbi 2552c61a8efSPaul Zimmerman /* These apply for core versions 1.94a and later */ 25680caf7d2SHuang Rui #define DWC3_DCTL_LPM_ERRATA_MASK DWC3_DCTL_LPM_ERRATA(0xf) 25780caf7d2SHuang Rui #define DWC3_DCTL_LPM_ERRATA(n) ((n) << 20) 25880caf7d2SHuang Rui 2592c61a8efSPaul Zimmerman #define DWC3_DCTL_KEEP_CONNECT (1 << 19) 2602c61a8efSPaul Zimmerman #define DWC3_DCTL_L1_HIBER_EN (1 << 18) 2612c61a8efSPaul Zimmerman #define DWC3_DCTL_CRS (1 << 17) 2622c61a8efSPaul Zimmerman #define DWC3_DCTL_CSS (1 << 16) 2632c61a8efSPaul Zimmerman 26472246da4SFelipe Balbi #define DWC3_DCTL_INITU2ENA (1 << 12) 26572246da4SFelipe Balbi #define DWC3_DCTL_ACCEPTU2ENA (1 << 11) 26672246da4SFelipe Balbi #define DWC3_DCTL_INITU1ENA (1 << 10) 26772246da4SFelipe Balbi #define DWC3_DCTL_ACCEPTU1ENA (1 << 9) 26872246da4SFelipe Balbi #define DWC3_DCTL_TSTCTRL_MASK (0xf << 1) 26972246da4SFelipe Balbi 27072246da4SFelipe Balbi #define DWC3_DCTL_ULSTCHNGREQ_MASK (0x0f << 5) 27172246da4SFelipe Balbi #define DWC3_DCTL_ULSTCHNGREQ(n) (((n) << 5) & DWC3_DCTL_ULSTCHNGREQ_MASK) 27272246da4SFelipe Balbi 27372246da4SFelipe Balbi #define DWC3_DCTL_ULSTCHNG_NO_ACTION (DWC3_DCTL_ULSTCHNGREQ(0)) 27472246da4SFelipe Balbi #define DWC3_DCTL_ULSTCHNG_SS_DISABLED (DWC3_DCTL_ULSTCHNGREQ(4)) 27572246da4SFelipe Balbi #define DWC3_DCTL_ULSTCHNG_RX_DETECT (DWC3_DCTL_ULSTCHNGREQ(5)) 27672246da4SFelipe Balbi #define DWC3_DCTL_ULSTCHNG_SS_INACTIVE (DWC3_DCTL_ULSTCHNGREQ(6)) 27772246da4SFelipe Balbi #define DWC3_DCTL_ULSTCHNG_RECOVERY (DWC3_DCTL_ULSTCHNGREQ(8)) 27872246da4SFelipe Balbi #define DWC3_DCTL_ULSTCHNG_COMPLIANCE (DWC3_DCTL_ULSTCHNGREQ(10)) 27972246da4SFelipe Balbi #define DWC3_DCTL_ULSTCHNG_LOOPBACK (DWC3_DCTL_ULSTCHNGREQ(11)) 28072246da4SFelipe Balbi 28172246da4SFelipe Balbi /* Device Event Enable Register */ 28272246da4SFelipe Balbi #define DWC3_DEVTEN_VNDRDEVTSTRCVEDEN (1 << 12) 28372246da4SFelipe Balbi #define DWC3_DEVTEN_EVNTOVERFLOWEN (1 << 11) 28472246da4SFelipe Balbi #define DWC3_DEVTEN_CMDCMPLTEN (1 << 10) 28572246da4SFelipe Balbi #define DWC3_DEVTEN_ERRTICERREN (1 << 9) 28672246da4SFelipe Balbi #define DWC3_DEVTEN_SOFEN (1 << 7) 28772246da4SFelipe Balbi #define DWC3_DEVTEN_EOPFEN (1 << 6) 2882c61a8efSPaul Zimmerman #define DWC3_DEVTEN_HIBERNATIONREQEVTEN (1 << 5) 28972246da4SFelipe Balbi #define DWC3_DEVTEN_WKUPEVTEN (1 << 4) 29072246da4SFelipe Balbi #define DWC3_DEVTEN_ULSTCNGEN (1 << 3) 29172246da4SFelipe Balbi #define DWC3_DEVTEN_CONNECTDONEEN (1 << 2) 29272246da4SFelipe Balbi #define DWC3_DEVTEN_USBRSTEN (1 << 1) 29372246da4SFelipe Balbi #define DWC3_DEVTEN_DISCONNEVTEN (1 << 0) 29472246da4SFelipe Balbi 29572246da4SFelipe Balbi /* Device Status Register */ 2962c61a8efSPaul Zimmerman #define DWC3_DSTS_DCNRD (1 << 29) 2972c61a8efSPaul Zimmerman 2982c61a8efSPaul Zimmerman /* This applies for core versions 1.87a and earlier */ 29972246da4SFelipe Balbi #define DWC3_DSTS_PWRUPREQ (1 << 24) 3002c61a8efSPaul Zimmerman 3012c61a8efSPaul Zimmerman /* These apply for core versions 1.94a and later */ 3022c61a8efSPaul Zimmerman #define DWC3_DSTS_RSS (1 << 25) 3032c61a8efSPaul Zimmerman #define DWC3_DSTS_SSS (1 << 24) 3042c61a8efSPaul Zimmerman 30572246da4SFelipe Balbi #define DWC3_DSTS_COREIDLE (1 << 23) 30672246da4SFelipe Balbi #define DWC3_DSTS_DEVCTRLHLT (1 << 22) 30772246da4SFelipe Balbi 30872246da4SFelipe Balbi #define DWC3_DSTS_USBLNKST_MASK (0x0f << 18) 30972246da4SFelipe Balbi #define DWC3_DSTS_USBLNKST(n) (((n) & DWC3_DSTS_USBLNKST_MASK) >> 18) 31072246da4SFelipe Balbi 31172246da4SFelipe Balbi #define DWC3_DSTS_RXFIFOEMPTY (1 << 17) 31272246da4SFelipe Balbi 313d05b8182SPratyush Anand #define DWC3_DSTS_SOFFN_MASK (0x3fff << 3) 31472246da4SFelipe Balbi #define DWC3_DSTS_SOFFN(n) (((n) & DWC3_DSTS_SOFFN_MASK) >> 3) 31572246da4SFelipe Balbi 31672246da4SFelipe Balbi #define DWC3_DSTS_CONNECTSPD (7 << 0) 31772246da4SFelipe Balbi 31872246da4SFelipe Balbi #define DWC3_DSTS_SUPERSPEED (4 << 0) 31972246da4SFelipe Balbi #define DWC3_DSTS_HIGHSPEED (0 << 0) 32072246da4SFelipe Balbi #define DWC3_DSTS_FULLSPEED2 (1 << 0) 32172246da4SFelipe Balbi #define DWC3_DSTS_LOWSPEED (2 << 0) 32272246da4SFelipe Balbi #define DWC3_DSTS_FULLSPEED1 (3 << 0) 32372246da4SFelipe Balbi 32472246da4SFelipe Balbi /* Device Generic Command Register */ 32572246da4SFelipe Balbi #define DWC3_DGCMD_SET_LMP 0x01 32672246da4SFelipe Balbi #define DWC3_DGCMD_SET_PERIODIC_PAR 0x02 32772246da4SFelipe Balbi #define DWC3_DGCMD_XMIT_FUNCTION 0x03 3282c61a8efSPaul Zimmerman 3292c61a8efSPaul Zimmerman /* These apply for core versions 1.94a and later */ 3302c61a8efSPaul Zimmerman #define DWC3_DGCMD_SET_SCRATCHPAD_ADDR_LO 0x04 3312c61a8efSPaul Zimmerman #define DWC3_DGCMD_SET_SCRATCHPAD_ADDR_HI 0x05 3322c61a8efSPaul Zimmerman 33372246da4SFelipe Balbi #define DWC3_DGCMD_SELECTED_FIFO_FLUSH 0x09 33472246da4SFelipe Balbi #define DWC3_DGCMD_ALL_FIFO_FLUSH 0x0a 33572246da4SFelipe Balbi #define DWC3_DGCMD_SET_ENDPOINT_NRDY 0x0c 33672246da4SFelipe Balbi #define DWC3_DGCMD_RUN_SOC_BUS_LOOPBACK 0x10 33772246da4SFelipe Balbi 338b09bb642SFelipe Balbi #define DWC3_DGCMD_STATUS(n) (((n) >> 15) & 1) 339b09bb642SFelipe Balbi #define DWC3_DGCMD_CMDACT (1 << 10) 3402c61a8efSPaul Zimmerman #define DWC3_DGCMD_CMDIOC (1 << 8) 3412c61a8efSPaul Zimmerman 3422c61a8efSPaul Zimmerman /* Device Generic Command Parameter Register */ 3432c61a8efSPaul Zimmerman #define DWC3_DGCMDPAR_FORCE_LINKPM_ACCEPT (1 << 0) 3442c61a8efSPaul Zimmerman #define DWC3_DGCMDPAR_FIFO_NUM(n) ((n) << 0) 3452c61a8efSPaul Zimmerman #define DWC3_DGCMDPAR_RX_FIFO (0 << 5) 3462c61a8efSPaul Zimmerman #define DWC3_DGCMDPAR_TX_FIFO (1 << 5) 3472c61a8efSPaul Zimmerman #define DWC3_DGCMDPAR_LOOPBACK_DIS (0 << 0) 3482c61a8efSPaul Zimmerman #define DWC3_DGCMDPAR_LOOPBACK_ENA (1 << 0) 349b09bb642SFelipe Balbi 35072246da4SFelipe Balbi /* Device Endpoint Command Register */ 35172246da4SFelipe Balbi #define DWC3_DEPCMD_PARAM_SHIFT 16 3521d046793SPaul Zimmerman #define DWC3_DEPCMD_PARAM(x) ((x) << DWC3_DEPCMD_PARAM_SHIFT) 3531d046793SPaul Zimmerman #define DWC3_DEPCMD_GET_RSC_IDX(x) (((x) >> DWC3_DEPCMD_PARAM_SHIFT) & 0x7f) 354b09bb642SFelipe Balbi #define DWC3_DEPCMD_STATUS(x) (((x) >> 15) & 1) 35572246da4SFelipe Balbi #define DWC3_DEPCMD_HIPRI_FORCERM (1 << 11) 35672246da4SFelipe Balbi #define DWC3_DEPCMD_CMDACT (1 << 10) 35772246da4SFelipe Balbi #define DWC3_DEPCMD_CMDIOC (1 << 8) 35872246da4SFelipe Balbi 35972246da4SFelipe Balbi #define DWC3_DEPCMD_DEPSTARTCFG (0x09 << 0) 36072246da4SFelipe Balbi #define DWC3_DEPCMD_ENDTRANSFER (0x08 << 0) 36172246da4SFelipe Balbi #define DWC3_DEPCMD_UPDATETRANSFER (0x07 << 0) 36272246da4SFelipe Balbi #define DWC3_DEPCMD_STARTTRANSFER (0x06 << 0) 36372246da4SFelipe Balbi #define DWC3_DEPCMD_CLEARSTALL (0x05 << 0) 36472246da4SFelipe Balbi #define DWC3_DEPCMD_SETSTALL (0x04 << 0) 3652c61a8efSPaul Zimmerman /* This applies for core versions 1.90a and earlier */ 36672246da4SFelipe Balbi #define DWC3_DEPCMD_GETSEQNUMBER (0x03 << 0) 3672c61a8efSPaul Zimmerman /* This applies for core versions 1.94a and later */ 3682c61a8efSPaul Zimmerman #define DWC3_DEPCMD_GETEPSTATE (0x03 << 0) 36972246da4SFelipe Balbi #define DWC3_DEPCMD_SETTRANSFRESOURCE (0x02 << 0) 37072246da4SFelipe Balbi #define DWC3_DEPCMD_SETEPCONFIG (0x01 << 0) 37172246da4SFelipe Balbi 37272246da4SFelipe Balbi /* The EP number goes 0..31 so ep0 is always out and ep1 is always in */ 37372246da4SFelipe Balbi #define DWC3_DALEPENA_EP(n) (1 << n) 37472246da4SFelipe Balbi 37572246da4SFelipe Balbi #define DWC3_DEPCMD_TYPE_CONTROL 0 37672246da4SFelipe Balbi #define DWC3_DEPCMD_TYPE_ISOC 1 37772246da4SFelipe Balbi #define DWC3_DEPCMD_TYPE_BULK 2 37872246da4SFelipe Balbi #define DWC3_DEPCMD_TYPE_INTR 3 37972246da4SFelipe Balbi 38072246da4SFelipe Balbi /* Structures */ 38172246da4SFelipe Balbi 382f6bafc6aSFelipe Balbi struct dwc3_trb; 38372246da4SFelipe Balbi 38472246da4SFelipe Balbi /** 38572246da4SFelipe Balbi * struct dwc3_event_buffer - Software event buffer representation 38672246da4SFelipe Balbi * @buf: _THE_ buffer 38772246da4SFelipe Balbi * @length: size of this buffer 388abed4118SFelipe Balbi * @lpos: event offset 38960d04bbeSFelipe Balbi * @count: cache of last read event count register 390abed4118SFelipe Balbi * @flags: flags related to this event buffer 39172246da4SFelipe Balbi * @dma: dma_addr_t 39272246da4SFelipe Balbi * @dwc: pointer to DWC controller 39372246da4SFelipe Balbi */ 39472246da4SFelipe Balbi struct dwc3_event_buffer { 39572246da4SFelipe Balbi void *buf; 39672246da4SFelipe Balbi unsigned length; 39772246da4SFelipe Balbi unsigned int lpos; 39860d04bbeSFelipe Balbi unsigned int count; 399abed4118SFelipe Balbi unsigned int flags; 400abed4118SFelipe Balbi 401abed4118SFelipe Balbi #define DWC3_EVENT_PENDING BIT(0) 40272246da4SFelipe Balbi 40372246da4SFelipe Balbi dma_addr_t dma; 40472246da4SFelipe Balbi 40572246da4SFelipe Balbi struct dwc3 *dwc; 40672246da4SFelipe Balbi }; 40772246da4SFelipe Balbi 40872246da4SFelipe Balbi #define DWC3_EP_FLAG_STALLED (1 << 0) 40972246da4SFelipe Balbi #define DWC3_EP_FLAG_WEDGED (1 << 1) 41072246da4SFelipe Balbi 41172246da4SFelipe Balbi #define DWC3_EP_DIRECTION_TX true 41272246da4SFelipe Balbi #define DWC3_EP_DIRECTION_RX false 41372246da4SFelipe Balbi 41472246da4SFelipe Balbi #define DWC3_TRB_NUM 32 41572246da4SFelipe Balbi #define DWC3_TRB_MASK (DWC3_TRB_NUM - 1) 41672246da4SFelipe Balbi 41772246da4SFelipe Balbi /** 41872246da4SFelipe Balbi * struct dwc3_ep - device side endpoint representation 41972246da4SFelipe Balbi * @endpoint: usb endpoint 42072246da4SFelipe Balbi * @request_list: list of requests for this endpoint 42172246da4SFelipe Balbi * @req_queued: list of requests on this ep which have TRBs setup 42272246da4SFelipe Balbi * @trb_pool: array of transaction buffers 42372246da4SFelipe Balbi * @trb_pool_dma: dma address of @trb_pool 42472246da4SFelipe Balbi * @free_slot: next slot which is going to be used 42572246da4SFelipe Balbi * @busy_slot: first slot which is owned by HW 42672246da4SFelipe Balbi * @desc: usb_endpoint_descriptor pointer 42772246da4SFelipe Balbi * @dwc: pointer to DWC controller 4284cfcf876SPaul Zimmerman * @saved_state: ep state saved during hibernation 42972246da4SFelipe Balbi * @flags: endpoint flags (wedged, stalled, ...) 43072246da4SFelipe Balbi * @current_trb: index of current used trb 43172246da4SFelipe Balbi * @number: endpoint number (1 - 15) 43272246da4SFelipe Balbi * @type: set to bmAttributes & USB_ENDPOINT_XFERTYPE_MASK 433b4996a86SFelipe Balbi * @resource_index: Resource transfer index 434c75f52fbSHuang Rui * @interval: the interval on which the ISOC transfer is started 43572246da4SFelipe Balbi * @name: a human readable name e.g. ep1out-bulk 43672246da4SFelipe Balbi * @direction: true for TX, false for RX 437879631aaSFelipe Balbi * @stream_capable: true when streams are enabled 43872246da4SFelipe Balbi */ 43972246da4SFelipe Balbi struct dwc3_ep { 44072246da4SFelipe Balbi struct usb_ep endpoint; 44172246da4SFelipe Balbi struct list_head request_list; 44272246da4SFelipe Balbi struct list_head req_queued; 44372246da4SFelipe Balbi 444f6bafc6aSFelipe Balbi struct dwc3_trb *trb_pool; 44572246da4SFelipe Balbi dma_addr_t trb_pool_dma; 44672246da4SFelipe Balbi u32 free_slot; 44772246da4SFelipe Balbi u32 busy_slot; 448c90bfaecSFelipe Balbi const struct usb_ss_ep_comp_descriptor *comp_desc; 44972246da4SFelipe Balbi struct dwc3 *dwc; 45072246da4SFelipe Balbi 4514cfcf876SPaul Zimmerman u32 saved_state; 45272246da4SFelipe Balbi unsigned flags; 45372246da4SFelipe Balbi #define DWC3_EP_ENABLED (1 << 0) 45472246da4SFelipe Balbi #define DWC3_EP_STALL (1 << 1) 45572246da4SFelipe Balbi #define DWC3_EP_WEDGE (1 << 2) 45672246da4SFelipe Balbi #define DWC3_EP_BUSY (1 << 4) 45772246da4SFelipe Balbi #define DWC3_EP_PENDING_REQUEST (1 << 5) 458d6d6ec7bSPratyush Anand #define DWC3_EP_MISSED_ISOC (1 << 6) 45972246da4SFelipe Balbi 460984f66a6SFelipe Balbi /* This last one is specific to EP0 */ 461984f66a6SFelipe Balbi #define DWC3_EP0_DIR_IN (1 << 31) 462984f66a6SFelipe Balbi 46372246da4SFelipe Balbi unsigned current_trb; 46472246da4SFelipe Balbi 46572246da4SFelipe Balbi u8 number; 46672246da4SFelipe Balbi u8 type; 467b4996a86SFelipe Balbi u8 resource_index; 46872246da4SFelipe Balbi u32 interval; 46972246da4SFelipe Balbi 47072246da4SFelipe Balbi char name[20]; 47172246da4SFelipe Balbi 47272246da4SFelipe Balbi unsigned direction:1; 473879631aaSFelipe Balbi unsigned stream_capable:1; 47472246da4SFelipe Balbi }; 47572246da4SFelipe Balbi 47672246da4SFelipe Balbi enum dwc3_phy { 47772246da4SFelipe Balbi DWC3_PHY_UNKNOWN = 0, 47872246da4SFelipe Balbi DWC3_PHY_USB3, 47972246da4SFelipe Balbi DWC3_PHY_USB2, 48072246da4SFelipe Balbi }; 48172246da4SFelipe Balbi 482b53c772dSFelipe Balbi enum dwc3_ep0_next { 483b53c772dSFelipe Balbi DWC3_EP0_UNKNOWN = 0, 484b53c772dSFelipe Balbi DWC3_EP0_COMPLETE, 485b53c772dSFelipe Balbi DWC3_EP0_NRDY_DATA, 486b53c772dSFelipe Balbi DWC3_EP0_NRDY_STATUS, 487b53c772dSFelipe Balbi }; 488b53c772dSFelipe Balbi 48972246da4SFelipe Balbi enum dwc3_ep0_state { 49072246da4SFelipe Balbi EP0_UNCONNECTED = 0, 491c7fcdeb2SFelipe Balbi EP0_SETUP_PHASE, 492c7fcdeb2SFelipe Balbi EP0_DATA_PHASE, 493c7fcdeb2SFelipe Balbi EP0_STATUS_PHASE, 49472246da4SFelipe Balbi }; 49572246da4SFelipe Balbi 49672246da4SFelipe Balbi enum dwc3_link_state { 49772246da4SFelipe Balbi /* In SuperSpeed */ 49872246da4SFelipe Balbi DWC3_LINK_STATE_U0 = 0x00, /* in HS, means ON */ 49972246da4SFelipe Balbi DWC3_LINK_STATE_U1 = 0x01, 50072246da4SFelipe Balbi DWC3_LINK_STATE_U2 = 0x02, /* in HS, means SLEEP */ 50172246da4SFelipe Balbi DWC3_LINK_STATE_U3 = 0x03, /* in HS, means SUSPEND */ 50272246da4SFelipe Balbi DWC3_LINK_STATE_SS_DIS = 0x04, 50372246da4SFelipe Balbi DWC3_LINK_STATE_RX_DET = 0x05, /* in HS, means Early Suspend */ 50472246da4SFelipe Balbi DWC3_LINK_STATE_SS_INACT = 0x06, 50572246da4SFelipe Balbi DWC3_LINK_STATE_POLL = 0x07, 50672246da4SFelipe Balbi DWC3_LINK_STATE_RECOV = 0x08, 50772246da4SFelipe Balbi DWC3_LINK_STATE_HRESET = 0x09, 50872246da4SFelipe Balbi DWC3_LINK_STATE_CMPLY = 0x0a, 50972246da4SFelipe Balbi DWC3_LINK_STATE_LPBK = 0x0b, 5102c61a8efSPaul Zimmerman DWC3_LINK_STATE_RESET = 0x0e, 5112c61a8efSPaul Zimmerman DWC3_LINK_STATE_RESUME = 0x0f, 51272246da4SFelipe Balbi DWC3_LINK_STATE_MASK = 0x0f, 51372246da4SFelipe Balbi }; 51472246da4SFelipe Balbi 515f6bafc6aSFelipe Balbi /* TRB Length, PCM and Status */ 516f6bafc6aSFelipe Balbi #define DWC3_TRB_SIZE_MASK (0x00ffffff) 517f6bafc6aSFelipe Balbi #define DWC3_TRB_SIZE_LENGTH(n) ((n) & DWC3_TRB_SIZE_MASK) 518f6bafc6aSFelipe Balbi #define DWC3_TRB_SIZE_PCM1(n) (((n) & 0x03) << 24) 519389f2828SPratyush Anand #define DWC3_TRB_SIZE_TRBSTS(n) (((n) & (0x0f << 28)) >> 28) 52072246da4SFelipe Balbi 521f6bafc6aSFelipe Balbi #define DWC3_TRBSTS_OK 0 522f6bafc6aSFelipe Balbi #define DWC3_TRBSTS_MISSED_ISOC 1 523f6bafc6aSFelipe Balbi #define DWC3_TRBSTS_SETUP_PENDING 2 5242c61a8efSPaul Zimmerman #define DWC3_TRB_STS_XFER_IN_PROG 4 52572246da4SFelipe Balbi 526f6bafc6aSFelipe Balbi /* TRB Control */ 527f6bafc6aSFelipe Balbi #define DWC3_TRB_CTRL_HWO (1 << 0) 528f6bafc6aSFelipe Balbi #define DWC3_TRB_CTRL_LST (1 << 1) 529f6bafc6aSFelipe Balbi #define DWC3_TRB_CTRL_CHN (1 << 2) 530f6bafc6aSFelipe Balbi #define DWC3_TRB_CTRL_CSP (1 << 3) 531f6bafc6aSFelipe Balbi #define DWC3_TRB_CTRL_TRBCTL(n) (((n) & 0x3f) << 4) 532f6bafc6aSFelipe Balbi #define DWC3_TRB_CTRL_ISP_IMI (1 << 10) 533f6bafc6aSFelipe Balbi #define DWC3_TRB_CTRL_IOC (1 << 11) 534f6bafc6aSFelipe Balbi #define DWC3_TRB_CTRL_SID_SOFN(n) (((n) & 0xffff) << 14) 535f6bafc6aSFelipe Balbi 536f6bafc6aSFelipe Balbi #define DWC3_TRBCTL_NORMAL DWC3_TRB_CTRL_TRBCTL(1) 537f6bafc6aSFelipe Balbi #define DWC3_TRBCTL_CONTROL_SETUP DWC3_TRB_CTRL_TRBCTL(2) 538f6bafc6aSFelipe Balbi #define DWC3_TRBCTL_CONTROL_STATUS2 DWC3_TRB_CTRL_TRBCTL(3) 539f6bafc6aSFelipe Balbi #define DWC3_TRBCTL_CONTROL_STATUS3 DWC3_TRB_CTRL_TRBCTL(4) 540f6bafc6aSFelipe Balbi #define DWC3_TRBCTL_CONTROL_DATA DWC3_TRB_CTRL_TRBCTL(5) 541f6bafc6aSFelipe Balbi #define DWC3_TRBCTL_ISOCHRONOUS_FIRST DWC3_TRB_CTRL_TRBCTL(6) 542f6bafc6aSFelipe Balbi #define DWC3_TRBCTL_ISOCHRONOUS DWC3_TRB_CTRL_TRBCTL(7) 543f6bafc6aSFelipe Balbi #define DWC3_TRBCTL_LINK_TRB DWC3_TRB_CTRL_TRBCTL(8) 54472246da4SFelipe Balbi 54572246da4SFelipe Balbi /** 546f6bafc6aSFelipe Balbi * struct dwc3_trb - transfer request block (hw format) 54772246da4SFelipe Balbi * @bpl: DW0-3 54872246da4SFelipe Balbi * @bph: DW4-7 54972246da4SFelipe Balbi * @size: DW8-B 55072246da4SFelipe Balbi * @trl: DWC-F 55172246da4SFelipe Balbi */ 552f6bafc6aSFelipe Balbi struct dwc3_trb { 553f6bafc6aSFelipe Balbi u32 bpl; 554f6bafc6aSFelipe Balbi u32 bph; 555f6bafc6aSFelipe Balbi u32 size; 556f6bafc6aSFelipe Balbi u32 ctrl; 55772246da4SFelipe Balbi } __packed; 55872246da4SFelipe Balbi 55972246da4SFelipe Balbi /** 560a3299499SFelipe Balbi * dwc3_hwparams - copy of HWPARAMS registers 561a3299499SFelipe Balbi * @hwparams0 - GHWPARAMS0 562a3299499SFelipe Balbi * @hwparams1 - GHWPARAMS1 563a3299499SFelipe Balbi * @hwparams2 - GHWPARAMS2 564a3299499SFelipe Balbi * @hwparams3 - GHWPARAMS3 565a3299499SFelipe Balbi * @hwparams4 - GHWPARAMS4 566a3299499SFelipe Balbi * @hwparams5 - GHWPARAMS5 567a3299499SFelipe Balbi * @hwparams6 - GHWPARAMS6 568a3299499SFelipe Balbi * @hwparams7 - GHWPARAMS7 569a3299499SFelipe Balbi * @hwparams8 - GHWPARAMS8 570a3299499SFelipe Balbi */ 571a3299499SFelipe Balbi struct dwc3_hwparams { 572a3299499SFelipe Balbi u32 hwparams0; 573a3299499SFelipe Balbi u32 hwparams1; 574a3299499SFelipe Balbi u32 hwparams2; 575a3299499SFelipe Balbi u32 hwparams3; 576a3299499SFelipe Balbi u32 hwparams4; 577a3299499SFelipe Balbi u32 hwparams5; 578a3299499SFelipe Balbi u32 hwparams6; 579a3299499SFelipe Balbi u32 hwparams7; 580a3299499SFelipe Balbi u32 hwparams8; 581a3299499SFelipe Balbi }; 582a3299499SFelipe Balbi 5830949e99bSFelipe Balbi /* HWPARAMS0 */ 5840949e99bSFelipe Balbi #define DWC3_MODE(n) ((n) & 0x7) 5850949e99bSFelipe Balbi 586457e84b6SFelipe Balbi #define DWC3_MDWIDTH(n) (((n) & 0xff00) >> 8) 587457e84b6SFelipe Balbi 5880949e99bSFelipe Balbi /* HWPARAMS1 */ 5899f622b2aSFelipe Balbi #define DWC3_NUM_INT(n) (((n) & (0x3f << 15)) >> 15) 5909f622b2aSFelipe Balbi 591789451f6SFelipe Balbi /* HWPARAMS3 */ 592789451f6SFelipe Balbi #define DWC3_NUM_IN_EPS_MASK (0x1f << 18) 593789451f6SFelipe Balbi #define DWC3_NUM_EPS_MASK (0x3f << 12) 594789451f6SFelipe Balbi #define DWC3_NUM_EPS(p) (((p)->hwparams3 & \ 595789451f6SFelipe Balbi (DWC3_NUM_EPS_MASK)) >> 12) 596789451f6SFelipe Balbi #define DWC3_NUM_IN_EPS(p) (((p)->hwparams3 & \ 597789451f6SFelipe Balbi (DWC3_NUM_IN_EPS_MASK)) >> 18) 598789451f6SFelipe Balbi 599457e84b6SFelipe Balbi /* HWPARAMS7 */ 600457e84b6SFelipe Balbi #define DWC3_RAM1_DEPTH(n) ((n) & 0xffff) 601457e84b6SFelipe Balbi 602e0ce0b0aSSebastian Andrzej Siewior struct dwc3_request { 603e0ce0b0aSSebastian Andrzej Siewior struct usb_request request; 604e0ce0b0aSSebastian Andrzej Siewior struct list_head list; 605e0ce0b0aSSebastian Andrzej Siewior struct dwc3_ep *dep; 606e5ba5ec8SPratyush Anand u32 start_slot; 607e0ce0b0aSSebastian Andrzej Siewior 608e0ce0b0aSSebastian Andrzej Siewior u8 epnum; 609f6bafc6aSFelipe Balbi struct dwc3_trb *trb; 610e0ce0b0aSSebastian Andrzej Siewior dma_addr_t trb_dma; 611e0ce0b0aSSebastian Andrzej Siewior 612e0ce0b0aSSebastian Andrzej Siewior unsigned direction:1; 613e0ce0b0aSSebastian Andrzej Siewior unsigned mapped:1; 614e0ce0b0aSSebastian Andrzej Siewior unsigned queued:1; 615e0ce0b0aSSebastian Andrzej Siewior }; 616e0ce0b0aSSebastian Andrzej Siewior 6172c61a8efSPaul Zimmerman /* 6182c61a8efSPaul Zimmerman * struct dwc3_scratchpad_array - hibernation scratchpad array 6192c61a8efSPaul Zimmerman * (format defined by hw) 6202c61a8efSPaul Zimmerman */ 6212c61a8efSPaul Zimmerman struct dwc3_scratchpad_array { 6222c61a8efSPaul Zimmerman __le64 dma_adr[DWC3_MAX_HIBER_SCRATCHBUFS]; 6232c61a8efSPaul Zimmerman }; 6242c61a8efSPaul Zimmerman 625a3299499SFelipe Balbi /** 62672246da4SFelipe Balbi * struct dwc3 - representation of our controller 62791db07dcSFelipe Balbi * @ctrl_req: usb control request which is used for ep0 62891db07dcSFelipe Balbi * @ep0_trb: trb which is used for the ctrl_req 6295812b1c2SFelipe Balbi * @ep0_bounce: bounce buffer for ep0 63091db07dcSFelipe Balbi * @setup_buf: used while precessing STD USB requests 63191db07dcSFelipe Balbi * @ctrl_req_addr: dma address of ctrl_req 63291db07dcSFelipe Balbi * @ep0_trb: dma address of ep0_trb 63391db07dcSFelipe Balbi * @ep0_usb_req: dummy req used while handling STD USB requests 6345812b1c2SFelipe Balbi * @ep0_bounce_addr: dma address of ep0_bounce 6350ffcaf37SFelipe Balbi * @scratch_addr: dma address of scratchbuf 63672246da4SFelipe Balbi * @lock: for synchronizing 63772246da4SFelipe Balbi * @dev: pointer to our struct device 638d07e8819SFelipe Balbi * @xhci: pointer to our xHCI child 63972246da4SFelipe Balbi * @event_buffer_list: a list of event buffers 64072246da4SFelipe Balbi * @gadget: device side representation of the peripheral controller 64172246da4SFelipe Balbi * @gadget_driver: pointer to the gadget driver 64272246da4SFelipe Balbi * @regs: base address for our registers 64372246da4SFelipe Balbi * @regs_size: address space size 6440ffcaf37SFelipe Balbi * @nr_scratch: number of scratch buffers 6459f622b2aSFelipe Balbi * @num_event_buffers: calculated number of event buffers 646fae2b904SFelipe Balbi * @u1u2: only used on revisions <1.83a for workaround 6476c167fc9SFelipe Balbi * @maximum_speed: maximum speed requested (mainly for testing purposes) 64872246da4SFelipe Balbi * @revision: revision register contents 649a45c82b8SRuchika Kharwar * @dr_mode: requested mode of operation 65051e1e7bcSFelipe Balbi * @usb2_phy: pointer to USB2 PHY 65151e1e7bcSFelipe Balbi * @usb3_phy: pointer to USB3 PHY 65257303488SKishon Vijay Abraham I * @usb2_generic_phy: pointer to USB2 PHY 65357303488SKishon Vijay Abraham I * @usb3_generic_phy: pointer to USB3 PHY 6547415f17cSFelipe Balbi * @dcfg: saved contents of DCFG register 6557415f17cSFelipe Balbi * @gctl: saved contents of GCTL register 656c12a0d86SFelipe Balbi * @isoch_delay: wValue from Set Isochronous Delay request; 657865e09e7SFelipe Balbi * @u2sel: parameter from Set SEL request. 658865e09e7SFelipe Balbi * @u2pel: parameter from Set SEL request. 659865e09e7SFelipe Balbi * @u1sel: parameter from Set SEL request. 660865e09e7SFelipe Balbi * @u1pel: parameter from Set SEL request. 661789451f6SFelipe Balbi * @num_out_eps: number of out endpoints 662789451f6SFelipe Balbi * @num_in_eps: number of in endpoints 663b53c772dSFelipe Balbi * @ep0_next_event: hold the next expected event 66472246da4SFelipe Balbi * @ep0state: state of endpoint zero 66572246da4SFelipe Balbi * @link_state: link state 66672246da4SFelipe Balbi * @speed: device speed (super, high, full, low) 66772246da4SFelipe Balbi * @mem: points to start of memory which is used for this struct. 668a3299499SFelipe Balbi * @hwparams: copy of hwparams registers 66972246da4SFelipe Balbi * @root: debugfs root folder pointer 670f2b685d5SFelipe Balbi * @regset: debugfs pointer to regdump file 671f2b685d5SFelipe Balbi * @test_mode: true when we're entering a USB test mode 672f2b685d5SFelipe Balbi * @test_mode_nr: test feature selector 67380caf7d2SHuang Rui * @lpm_nyet_threshold: LPM NYET response threshold 674f2b685d5SFelipe Balbi * @delayed_status: true when gadget driver asks for delayed status 675f2b685d5SFelipe Balbi * @ep0_bounced: true when we used bounce buffer 676f2b685d5SFelipe Balbi * @ep0_expect_in: true when we expect a DATA IN transfer 67781bc5599SFelipe Balbi * @has_hibernation: true when dwc3 was configured with Hibernation 67880caf7d2SHuang Rui * @has_lpm_erratum: true when core was configured with LPM Erratum. Note that 67980caf7d2SHuang Rui * there's now way for software to detect this in runtime. 680f2b685d5SFelipe Balbi * @is_selfpowered: true when we are selfpowered 681946bd579SHuang Rui * @is_fpga: true when we are using the FPGA board 682f2b685d5SFelipe Balbi * @needs_fifo_resize: not all users might want fifo resizing, flag it 683f2b685d5SFelipe Balbi * @pullups_connected: true when Run/Stop bit is set 684f2b685d5SFelipe Balbi * @resize_fifos: tells us it's ok to reconfigure our TxFIFO sizes. 685f2b685d5SFelipe Balbi * @setup_packet_pending: true when there's a Setup Packet in FIFO. Workaround 686f2b685d5SFelipe Balbi * @start_config_issued: true when StartConfig command has been issued 687f2b685d5SFelipe Balbi * @three_stage_setup: set if we perform a three phase setup 6883b81221aSHuang Rui * @disable_scramble_quirk: set if we enable the disable scramble quirk 6899a5b2f31SHuang Rui * @u2exit_lfps_quirk: set if we enable u2exit lfps quirk 690b5a65c40SHuang Rui * @u2ss_inp3_quirk: set if we enable P3 OK for U2/SS Inactive quirk 691df31f5b3SHuang Rui * @req_p1p2p3_quirk: set if we enable request p1p2p3 quirk 692a2a1d0f5SHuang Rui * @del_p1p2p3_quirk: set if we enable delay p1p2p3 quirk 69341c06ffdSHuang Rui * @del_phy_power_chg_quirk: set if we enable delay phy power change quirk 69472246da4SFelipe Balbi */ 69572246da4SFelipe Balbi struct dwc3 { 69672246da4SFelipe Balbi struct usb_ctrlrequest *ctrl_req; 697f6bafc6aSFelipe Balbi struct dwc3_trb *ep0_trb; 6985812b1c2SFelipe Balbi void *ep0_bounce; 6990ffcaf37SFelipe Balbi void *scratchbuf; 70072246da4SFelipe Balbi u8 *setup_buf; 70172246da4SFelipe Balbi dma_addr_t ctrl_req_addr; 70272246da4SFelipe Balbi dma_addr_t ep0_trb_addr; 7035812b1c2SFelipe Balbi dma_addr_t ep0_bounce_addr; 7040ffcaf37SFelipe Balbi dma_addr_t scratch_addr; 705e0ce0b0aSSebastian Andrzej Siewior struct dwc3_request ep0_usb_req; 706789451f6SFelipe Balbi 70772246da4SFelipe Balbi /* device lock */ 70872246da4SFelipe Balbi spinlock_t lock; 709789451f6SFelipe Balbi 71072246da4SFelipe Balbi struct device *dev; 71172246da4SFelipe Balbi 712d07e8819SFelipe Balbi struct platform_device *xhci; 71351249dcaSIdo Shayevitz struct resource xhci_resources[DWC3_XHCI_RESOURCES_NUM]; 714d07e8819SFelipe Balbi 715457d3f21SFelipe Balbi struct dwc3_event_buffer **ev_buffs; 71672246da4SFelipe Balbi struct dwc3_ep *eps[DWC3_ENDPOINTS_NUM]; 71772246da4SFelipe Balbi 71872246da4SFelipe Balbi struct usb_gadget gadget; 71972246da4SFelipe Balbi struct usb_gadget_driver *gadget_driver; 72072246da4SFelipe Balbi 72151e1e7bcSFelipe Balbi struct usb_phy *usb2_phy; 72251e1e7bcSFelipe Balbi struct usb_phy *usb3_phy; 72351e1e7bcSFelipe Balbi 72457303488SKishon Vijay Abraham I struct phy *usb2_generic_phy; 72557303488SKishon Vijay Abraham I struct phy *usb3_generic_phy; 72657303488SKishon Vijay Abraham I 72772246da4SFelipe Balbi void __iomem *regs; 72872246da4SFelipe Balbi size_t regs_size; 72972246da4SFelipe Balbi 730a45c82b8SRuchika Kharwar enum usb_dr_mode dr_mode; 731a45c82b8SRuchika Kharwar 7327415f17cSFelipe Balbi /* used for suspend/resume */ 7337415f17cSFelipe Balbi u32 dcfg; 7347415f17cSFelipe Balbi u32 gctl; 7357415f17cSFelipe Balbi 7360ffcaf37SFelipe Balbi u32 nr_scratch; 7379f622b2aSFelipe Balbi u32 num_event_buffers; 738fae2b904SFelipe Balbi u32 u1u2; 7396c167fc9SFelipe Balbi u32 maximum_speed; 74072246da4SFelipe Balbi u32 revision; 74172246da4SFelipe Balbi 74272246da4SFelipe Balbi #define DWC3_REVISION_173A 0x5533173a 74372246da4SFelipe Balbi #define DWC3_REVISION_175A 0x5533175a 74472246da4SFelipe Balbi #define DWC3_REVISION_180A 0x5533180a 74572246da4SFelipe Balbi #define DWC3_REVISION_183A 0x5533183a 74672246da4SFelipe Balbi #define DWC3_REVISION_185A 0x5533185a 7472c61a8efSPaul Zimmerman #define DWC3_REVISION_187A 0x5533187a 74872246da4SFelipe Balbi #define DWC3_REVISION_188A 0x5533188a 74972246da4SFelipe Balbi #define DWC3_REVISION_190A 0x5533190a 7502c61a8efSPaul Zimmerman #define DWC3_REVISION_194A 0x5533194a 7511522d703SFelipe Balbi #define DWC3_REVISION_200A 0x5533200a 7521522d703SFelipe Balbi #define DWC3_REVISION_202A 0x5533202a 7531522d703SFelipe Balbi #define DWC3_REVISION_210A 0x5533210a 7541522d703SFelipe Balbi #define DWC3_REVISION_220A 0x5533220a 7557ac6a593SFelipe Balbi #define DWC3_REVISION_230A 0x5533230a 7567ac6a593SFelipe Balbi #define DWC3_REVISION_240A 0x5533240a 7577ac6a593SFelipe Balbi #define DWC3_REVISION_250A 0x5533250a 758dbf5aaf7SFelipe Balbi #define DWC3_REVISION_260A 0x5533260a 759dbf5aaf7SFelipe Balbi #define DWC3_REVISION_270A 0x5533270a 760dbf5aaf7SFelipe Balbi #define DWC3_REVISION_280A 0x5533280a 76172246da4SFelipe Balbi 762b53c772dSFelipe Balbi enum dwc3_ep0_next ep0_next_event; 76372246da4SFelipe Balbi enum dwc3_ep0_state ep0state; 76472246da4SFelipe Balbi enum dwc3_link_state link_state; 76572246da4SFelipe Balbi 766c12a0d86SFelipe Balbi u16 isoch_delay; 767865e09e7SFelipe Balbi u16 u2sel; 768865e09e7SFelipe Balbi u16 u2pel; 769865e09e7SFelipe Balbi u8 u1sel; 770865e09e7SFelipe Balbi u8 u1pel; 771865e09e7SFelipe Balbi 77272246da4SFelipe Balbi u8 speed; 773865e09e7SFelipe Balbi 774789451f6SFelipe Balbi u8 num_out_eps; 775789451f6SFelipe Balbi u8 num_in_eps; 776789451f6SFelipe Balbi 77772246da4SFelipe Balbi void *mem; 77872246da4SFelipe Balbi 779a3299499SFelipe Balbi struct dwc3_hwparams hwparams; 78072246da4SFelipe Balbi struct dentry *root; 781d7668024SFelipe Balbi struct debugfs_regset32 *regset; 7823b637367SGerard Cauvy 7833b637367SGerard Cauvy u8 test_mode; 7843b637367SGerard Cauvy u8 test_mode_nr; 78580caf7d2SHuang Rui u8 lpm_nyet_threshold; 786f2b685d5SFelipe Balbi 787f2b685d5SFelipe Balbi unsigned delayed_status:1; 788f2b685d5SFelipe Balbi unsigned ep0_bounced:1; 789f2b685d5SFelipe Balbi unsigned ep0_expect_in:1; 79081bc5599SFelipe Balbi unsigned has_hibernation:1; 79180caf7d2SHuang Rui unsigned has_lpm_erratum:1; 792f2b685d5SFelipe Balbi unsigned is_selfpowered:1; 793946bd579SHuang Rui unsigned is_fpga:1; 794f2b685d5SFelipe Balbi unsigned needs_fifo_resize:1; 795f2b685d5SFelipe Balbi unsigned pullups_connected:1; 796f2b685d5SFelipe Balbi unsigned resize_fifos:1; 797f2b685d5SFelipe Balbi unsigned setup_packet_pending:1; 798f2b685d5SFelipe Balbi unsigned start_config_issued:1; 799f2b685d5SFelipe Balbi unsigned three_stage_setup:1; 8003b81221aSHuang Rui 8013b81221aSHuang Rui unsigned disable_scramble_quirk:1; 8029a5b2f31SHuang Rui unsigned u2exit_lfps_quirk:1; 803b5a65c40SHuang Rui unsigned u2ss_inp3_quirk:1; 804df31f5b3SHuang Rui unsigned req_p1p2p3_quirk:1; 805a2a1d0f5SHuang Rui unsigned del_p1p2p3_quirk:1; 80641c06ffdSHuang Rui unsigned del_phy_power_chg_quirk:1; 80772246da4SFelipe Balbi }; 80872246da4SFelipe Balbi 80972246da4SFelipe Balbi /* -------------------------------------------------------------------------- */ 81072246da4SFelipe Balbi 81172246da4SFelipe Balbi /* -------------------------------------------------------------------------- */ 81272246da4SFelipe Balbi 81372246da4SFelipe Balbi struct dwc3_event_type { 81472246da4SFelipe Balbi u32 is_devspec:1; 8151974d494SHuang Rui u32 type:7; 8161974d494SHuang Rui u32 reserved8_31:24; 81772246da4SFelipe Balbi } __packed; 81872246da4SFelipe Balbi 81972246da4SFelipe Balbi #define DWC3_DEPEVT_XFERCOMPLETE 0x01 82072246da4SFelipe Balbi #define DWC3_DEPEVT_XFERINPROGRESS 0x02 82172246da4SFelipe Balbi #define DWC3_DEPEVT_XFERNOTREADY 0x03 82272246da4SFelipe Balbi #define DWC3_DEPEVT_RXTXFIFOEVT 0x04 82372246da4SFelipe Balbi #define DWC3_DEPEVT_STREAMEVT 0x06 82472246da4SFelipe Balbi #define DWC3_DEPEVT_EPCMDCMPLT 0x07 82572246da4SFelipe Balbi 82672246da4SFelipe Balbi /** 82772246da4SFelipe Balbi * struct dwc3_event_depvt - Device Endpoint Events 82872246da4SFelipe Balbi * @one_bit: indicates this is an endpoint event (not used) 82972246da4SFelipe Balbi * @endpoint_number: number of the endpoint 83072246da4SFelipe Balbi * @endpoint_event: The event we have: 83172246da4SFelipe Balbi * 0x00 - Reserved 83272246da4SFelipe Balbi * 0x01 - XferComplete 83372246da4SFelipe Balbi * 0x02 - XferInProgress 83472246da4SFelipe Balbi * 0x03 - XferNotReady 83572246da4SFelipe Balbi * 0x04 - RxTxFifoEvt (IN->Underrun, OUT->Overrun) 83672246da4SFelipe Balbi * 0x05 - Reserved 83772246da4SFelipe Balbi * 0x06 - StreamEvt 83872246da4SFelipe Balbi * 0x07 - EPCmdCmplt 83972246da4SFelipe Balbi * @reserved11_10: Reserved, don't use. 84072246da4SFelipe Balbi * @status: Indicates the status of the event. Refer to databook for 84172246da4SFelipe Balbi * more information. 84272246da4SFelipe Balbi * @parameters: Parameters of the current event. Refer to databook for 84372246da4SFelipe Balbi * more information. 84472246da4SFelipe Balbi */ 84572246da4SFelipe Balbi struct dwc3_event_depevt { 84672246da4SFelipe Balbi u32 one_bit:1; 84772246da4SFelipe Balbi u32 endpoint_number:5; 84872246da4SFelipe Balbi u32 endpoint_event:4; 84972246da4SFelipe Balbi u32 reserved11_10:2; 85072246da4SFelipe Balbi u32 status:4; 85140aa41fbSFelipe Balbi 85240aa41fbSFelipe Balbi /* Within XferNotReady */ 85340aa41fbSFelipe Balbi #define DEPEVT_STATUS_TRANSFER_ACTIVE (1 << 3) 85440aa41fbSFelipe Balbi 85540aa41fbSFelipe Balbi /* Within XferComplete */ 85672246da4SFelipe Balbi #define DEPEVT_STATUS_BUSERR (1 << 0) 85772246da4SFelipe Balbi #define DEPEVT_STATUS_SHORT (1 << 1) 85872246da4SFelipe Balbi #define DEPEVT_STATUS_IOC (1 << 2) 85972246da4SFelipe Balbi #define DEPEVT_STATUS_LST (1 << 3) 860dc137f01SFelipe Balbi 861879631aaSFelipe Balbi /* Stream event only */ 862879631aaSFelipe Balbi #define DEPEVT_STREAMEVT_FOUND 1 863879631aaSFelipe Balbi #define DEPEVT_STREAMEVT_NOTFOUND 2 864879631aaSFelipe Balbi 865dc137f01SFelipe Balbi /* Control-only Status */ 866dc137f01SFelipe Balbi #define DEPEVT_STATUS_CONTROL_DATA 1 867dc137f01SFelipe Balbi #define DEPEVT_STATUS_CONTROL_STATUS 2 868dc137f01SFelipe Balbi 86972246da4SFelipe Balbi u32 parameters:16; 87072246da4SFelipe Balbi } __packed; 87172246da4SFelipe Balbi 87272246da4SFelipe Balbi /** 87372246da4SFelipe Balbi * struct dwc3_event_devt - Device Events 87472246da4SFelipe Balbi * @one_bit: indicates this is a non-endpoint event (not used) 87572246da4SFelipe Balbi * @device_event: indicates it's a device event. Should read as 0x00 87672246da4SFelipe Balbi * @type: indicates the type of device event. 87772246da4SFelipe Balbi * 0 - DisconnEvt 87872246da4SFelipe Balbi * 1 - USBRst 87972246da4SFelipe Balbi * 2 - ConnectDone 88072246da4SFelipe Balbi * 3 - ULStChng 88172246da4SFelipe Balbi * 4 - WkUpEvt 88272246da4SFelipe Balbi * 5 - Reserved 88372246da4SFelipe Balbi * 6 - EOPF 88472246da4SFelipe Balbi * 7 - SOF 88572246da4SFelipe Balbi * 8 - Reserved 88672246da4SFelipe Balbi * 9 - ErrticErr 88772246da4SFelipe Balbi * 10 - CmdCmplt 88872246da4SFelipe Balbi * 11 - EvntOverflow 88972246da4SFelipe Balbi * 12 - VndrDevTstRcved 89072246da4SFelipe Balbi * @reserved15_12: Reserved, not used 89172246da4SFelipe Balbi * @event_info: Information about this event 89206f9b6e5SHuang Rui * @reserved31_25: Reserved, not used 89372246da4SFelipe Balbi */ 89472246da4SFelipe Balbi struct dwc3_event_devt { 89572246da4SFelipe Balbi u32 one_bit:1; 89672246da4SFelipe Balbi u32 device_event:7; 89772246da4SFelipe Balbi u32 type:4; 89872246da4SFelipe Balbi u32 reserved15_12:4; 89906f9b6e5SHuang Rui u32 event_info:9; 90006f9b6e5SHuang Rui u32 reserved31_25:7; 90172246da4SFelipe Balbi } __packed; 90272246da4SFelipe Balbi 90372246da4SFelipe Balbi /** 90472246da4SFelipe Balbi * struct dwc3_event_gevt - Other Core Events 90572246da4SFelipe Balbi * @one_bit: indicates this is a non-endpoint event (not used) 90672246da4SFelipe Balbi * @device_event: indicates it's (0x03) Carkit or (0x04) I2C event. 90772246da4SFelipe Balbi * @phy_port_number: self-explanatory 90872246da4SFelipe Balbi * @reserved31_12: Reserved, not used. 90972246da4SFelipe Balbi */ 91072246da4SFelipe Balbi struct dwc3_event_gevt { 91172246da4SFelipe Balbi u32 one_bit:1; 91272246da4SFelipe Balbi u32 device_event:7; 91372246da4SFelipe Balbi u32 phy_port_number:4; 91472246da4SFelipe Balbi u32 reserved31_12:20; 91572246da4SFelipe Balbi } __packed; 91672246da4SFelipe Balbi 91772246da4SFelipe Balbi /** 91872246da4SFelipe Balbi * union dwc3_event - representation of Event Buffer contents 91972246da4SFelipe Balbi * @raw: raw 32-bit event 92072246da4SFelipe Balbi * @type: the type of the event 92172246da4SFelipe Balbi * @depevt: Device Endpoint Event 92272246da4SFelipe Balbi * @devt: Device Event 92372246da4SFelipe Balbi * @gevt: Global Event 92472246da4SFelipe Balbi */ 92572246da4SFelipe Balbi union dwc3_event { 92672246da4SFelipe Balbi u32 raw; 92772246da4SFelipe Balbi struct dwc3_event_type type; 92872246da4SFelipe Balbi struct dwc3_event_depevt depevt; 92972246da4SFelipe Balbi struct dwc3_event_devt devt; 93072246da4SFelipe Balbi struct dwc3_event_gevt gevt; 93172246da4SFelipe Balbi }; 93272246da4SFelipe Balbi 93361018305SFelipe Balbi /** 93461018305SFelipe Balbi * struct dwc3_gadget_ep_cmd_params - representation of endpoint command 93561018305SFelipe Balbi * parameters 93661018305SFelipe Balbi * @param2: third parameter 93761018305SFelipe Balbi * @param1: second parameter 93861018305SFelipe Balbi * @param0: first parameter 93961018305SFelipe Balbi */ 94061018305SFelipe Balbi struct dwc3_gadget_ep_cmd_params { 94161018305SFelipe Balbi u32 param2; 94261018305SFelipe Balbi u32 param1; 94361018305SFelipe Balbi u32 param0; 94461018305SFelipe Balbi }; 94561018305SFelipe Balbi 94672246da4SFelipe Balbi /* 94772246da4SFelipe Balbi * DWC3 Features to be used as Driver Data 94872246da4SFelipe Balbi */ 94972246da4SFelipe Balbi 95072246da4SFelipe Balbi #define DWC3_HAS_PERIPHERAL BIT(0) 95172246da4SFelipe Balbi #define DWC3_HAS_XHCI BIT(1) 95272246da4SFelipe Balbi #define DWC3_HAS_OTG BIT(3) 95372246da4SFelipe Balbi 954d07e8819SFelipe Balbi /* prototypes */ 9553140e8cbSSebastian Andrzej Siewior void dwc3_set_mode(struct dwc3 *dwc, u32 mode); 956457e84b6SFelipe Balbi int dwc3_gadget_resize_tx_fifos(struct dwc3 *dwc); 9573140e8cbSSebastian Andrzej Siewior 958388e5c51SVivek Gautam #if IS_ENABLED(CONFIG_USB_DWC3_HOST) || IS_ENABLED(CONFIG_USB_DWC3_DUAL_ROLE) 959d07e8819SFelipe Balbi int dwc3_host_init(struct dwc3 *dwc); 960d07e8819SFelipe Balbi void dwc3_host_exit(struct dwc3 *dwc); 961388e5c51SVivek Gautam #else 962388e5c51SVivek Gautam static inline int dwc3_host_init(struct dwc3 *dwc) 963388e5c51SVivek Gautam { return 0; } 964388e5c51SVivek Gautam static inline void dwc3_host_exit(struct dwc3 *dwc) 965388e5c51SVivek Gautam { } 966388e5c51SVivek Gautam #endif 967d07e8819SFelipe Balbi 968388e5c51SVivek Gautam #if IS_ENABLED(CONFIG_USB_DWC3_GADGET) || IS_ENABLED(CONFIG_USB_DWC3_DUAL_ROLE) 969f80b45e7SFelipe Balbi int dwc3_gadget_init(struct dwc3 *dwc); 970f80b45e7SFelipe Balbi void dwc3_gadget_exit(struct dwc3 *dwc); 97161018305SFelipe Balbi int dwc3_gadget_set_test_mode(struct dwc3 *dwc, int mode); 97261018305SFelipe Balbi int dwc3_gadget_get_link_state(struct dwc3 *dwc); 97361018305SFelipe Balbi int dwc3_gadget_set_link_state(struct dwc3 *dwc, enum dwc3_link_state state); 97461018305SFelipe Balbi int dwc3_send_gadget_ep_cmd(struct dwc3 *dwc, unsigned ep, 97561018305SFelipe Balbi unsigned cmd, struct dwc3_gadget_ep_cmd_params *params); 9763ece0ec4SFelipe Balbi int dwc3_send_gadget_generic_command(struct dwc3 *dwc, unsigned cmd, u32 param); 977388e5c51SVivek Gautam #else 978388e5c51SVivek Gautam static inline int dwc3_gadget_init(struct dwc3 *dwc) 979388e5c51SVivek Gautam { return 0; } 980388e5c51SVivek Gautam static inline void dwc3_gadget_exit(struct dwc3 *dwc) 981388e5c51SVivek Gautam { } 98261018305SFelipe Balbi static inline int dwc3_gadget_set_test_mode(struct dwc3 *dwc, int mode) 98361018305SFelipe Balbi { return 0; } 98461018305SFelipe Balbi static inline int dwc3_gadget_get_link_state(struct dwc3 *dwc) 98561018305SFelipe Balbi { return 0; } 98661018305SFelipe Balbi static inline int dwc3_gadget_set_link_state(struct dwc3 *dwc, 98761018305SFelipe Balbi enum dwc3_link_state state) 98861018305SFelipe Balbi { return 0; } 98961018305SFelipe Balbi 99061018305SFelipe Balbi static inline int dwc3_send_gadget_ep_cmd(struct dwc3 *dwc, unsigned ep, 99161018305SFelipe Balbi unsigned cmd, struct dwc3_gadget_ep_cmd_params *params) 99261018305SFelipe Balbi { return 0; } 99361018305SFelipe Balbi static inline int dwc3_send_gadget_generic_command(struct dwc3 *dwc, 99461018305SFelipe Balbi int cmd, u32 param) 99561018305SFelipe Balbi { return 0; } 996388e5c51SVivek Gautam #endif 997f80b45e7SFelipe Balbi 9987415f17cSFelipe Balbi /* power management interface */ 9997415f17cSFelipe Balbi #if !IS_ENABLED(CONFIG_USB_DWC3_HOST) 10007415f17cSFelipe Balbi int dwc3_gadget_suspend(struct dwc3 *dwc); 10017415f17cSFelipe Balbi int dwc3_gadget_resume(struct dwc3 *dwc); 10027415f17cSFelipe Balbi #else 10037415f17cSFelipe Balbi static inline int dwc3_gadget_suspend(struct dwc3 *dwc) 10047415f17cSFelipe Balbi { 10057415f17cSFelipe Balbi return 0; 10067415f17cSFelipe Balbi } 10077415f17cSFelipe Balbi 10087415f17cSFelipe Balbi static inline int dwc3_gadget_resume(struct dwc3 *dwc) 10097415f17cSFelipe Balbi { 10107415f17cSFelipe Balbi return 0; 10117415f17cSFelipe Balbi } 10127415f17cSFelipe Balbi #endif /* !IS_ENABLED(CONFIG_USB_DWC3_HOST) */ 10137415f17cSFelipe Balbi 101472246da4SFelipe Balbi #endif /* __DRIVERS_USB_DWC3_CORE_H */ 1015