172246da4SFelipe Balbi /** 272246da4SFelipe Balbi * core.h - DesignWare USB3 DRD Core Header 372246da4SFelipe Balbi * 472246da4SFelipe Balbi * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com 572246da4SFelipe Balbi * 672246da4SFelipe Balbi * Authors: Felipe Balbi <balbi@ti.com>, 772246da4SFelipe Balbi * Sebastian Andrzej Siewior <bigeasy@linutronix.de> 872246da4SFelipe Balbi * 95945f789SFelipe Balbi * This program is free software: you can redistribute it and/or modify 105945f789SFelipe Balbi * it under the terms of the GNU General Public License version 2 of 115945f789SFelipe Balbi * the License as published by the Free Software Foundation. 1272246da4SFelipe Balbi * 135945f789SFelipe Balbi * This program is distributed in the hope that it will be useful, 145945f789SFelipe Balbi * but WITHOUT ANY WARRANTY; without even the implied warranty of 155945f789SFelipe Balbi * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 165945f789SFelipe Balbi * GNU General Public License for more details. 1772246da4SFelipe Balbi */ 1872246da4SFelipe Balbi 1972246da4SFelipe Balbi #ifndef __DRIVERS_USB_DWC3_CORE_H 2072246da4SFelipe Balbi #define __DRIVERS_USB_DWC3_CORE_H 2172246da4SFelipe Balbi 2272246da4SFelipe Balbi #include <linux/device.h> 2372246da4SFelipe Balbi #include <linux/spinlock.h> 24d07e8819SFelipe Balbi #include <linux/ioport.h> 2572246da4SFelipe Balbi #include <linux/list.h> 2672246da4SFelipe Balbi #include <linux/dma-mapping.h> 2772246da4SFelipe Balbi #include <linux/mm.h> 2872246da4SFelipe Balbi #include <linux/debugfs.h> 2972246da4SFelipe Balbi 3072246da4SFelipe Balbi #include <linux/usb/ch9.h> 3172246da4SFelipe Balbi #include <linux/usb/gadget.h> 32a45c82b8SRuchika Kharwar #include <linux/usb/otg.h> 3372246da4SFelipe Balbi 3472246da4SFelipe Balbi /* Global constants */ 353ef35fafSFelipe Balbi #define DWC3_EP0_BOUNCE_SIZE 512 3672246da4SFelipe Balbi #define DWC3_ENDPOINTS_NUM 32 3751249dcaSIdo Shayevitz #define DWC3_XHCI_RESOURCES_NUM 2 3872246da4SFelipe Balbi 395da93478SFelipe Balbi #define DWC3_EVENT_SIZE 4 /* bytes */ 405da93478SFelipe Balbi #define DWC3_EVENT_MAX_NUM 64 /* 2 events/endpoint */ 415da93478SFelipe Balbi #define DWC3_EVENT_BUFFERS_SIZE (DWC3_EVENT_SIZE * DWC3_EVENT_MAX_NUM) 4272246da4SFelipe Balbi #define DWC3_EVENT_TYPE_MASK 0xfe 4372246da4SFelipe Balbi 4472246da4SFelipe Balbi #define DWC3_EVENT_TYPE_DEV 0 4572246da4SFelipe Balbi #define DWC3_EVENT_TYPE_CARKIT 3 4672246da4SFelipe Balbi #define DWC3_EVENT_TYPE_I2C 4 4772246da4SFelipe Balbi 4872246da4SFelipe Balbi #define DWC3_DEVICE_EVENT_DISCONNECT 0 4972246da4SFelipe Balbi #define DWC3_DEVICE_EVENT_RESET 1 5072246da4SFelipe Balbi #define DWC3_DEVICE_EVENT_CONNECT_DONE 2 5172246da4SFelipe Balbi #define DWC3_DEVICE_EVENT_LINK_STATUS_CHANGE 3 5272246da4SFelipe Balbi #define DWC3_DEVICE_EVENT_WAKEUP 4 532c61a8efSPaul Zimmerman #define DWC3_DEVICE_EVENT_HIBER_REQ 5 5472246da4SFelipe Balbi #define DWC3_DEVICE_EVENT_EOPF 6 5572246da4SFelipe Balbi #define DWC3_DEVICE_EVENT_SOF 7 5672246da4SFelipe Balbi #define DWC3_DEVICE_EVENT_ERRATIC_ERROR 9 5772246da4SFelipe Balbi #define DWC3_DEVICE_EVENT_CMD_CMPL 10 5872246da4SFelipe Balbi #define DWC3_DEVICE_EVENT_OVERFLOW 11 5972246da4SFelipe Balbi 6072246da4SFelipe Balbi #define DWC3_GEVNTCOUNT_MASK 0xfffc 6172246da4SFelipe Balbi #define DWC3_GSNPSID_MASK 0xffff0000 6272246da4SFelipe Balbi #define DWC3_GSNPSREV_MASK 0xffff 6372246da4SFelipe Balbi 6451249dcaSIdo Shayevitz /* DWC3 registers memory space boundries */ 6551249dcaSIdo Shayevitz #define DWC3_XHCI_REGS_START 0x0 6651249dcaSIdo Shayevitz #define DWC3_XHCI_REGS_END 0x7fff 6751249dcaSIdo Shayevitz #define DWC3_GLOBALS_REGS_START 0xc100 6851249dcaSIdo Shayevitz #define DWC3_GLOBALS_REGS_END 0xc6ff 6951249dcaSIdo Shayevitz #define DWC3_DEVICE_REGS_START 0xc700 7051249dcaSIdo Shayevitz #define DWC3_DEVICE_REGS_END 0xcbff 7151249dcaSIdo Shayevitz #define DWC3_OTG_REGS_START 0xcc00 7251249dcaSIdo Shayevitz #define DWC3_OTG_REGS_END 0xccff 7351249dcaSIdo Shayevitz 7472246da4SFelipe Balbi /* Global Registers */ 7572246da4SFelipe Balbi #define DWC3_GSBUSCFG0 0xc100 7672246da4SFelipe Balbi #define DWC3_GSBUSCFG1 0xc104 7772246da4SFelipe Balbi #define DWC3_GTXTHRCFG 0xc108 7872246da4SFelipe Balbi #define DWC3_GRXTHRCFG 0xc10c 7972246da4SFelipe Balbi #define DWC3_GCTL 0xc110 8072246da4SFelipe Balbi #define DWC3_GEVTEN 0xc114 8172246da4SFelipe Balbi #define DWC3_GSTS 0xc118 8272246da4SFelipe Balbi #define DWC3_GSNPSID 0xc120 8372246da4SFelipe Balbi #define DWC3_GGPIO 0xc124 8472246da4SFelipe Balbi #define DWC3_GUID 0xc128 8572246da4SFelipe Balbi #define DWC3_GUCTL 0xc12c 8672246da4SFelipe Balbi #define DWC3_GBUSERRADDR0 0xc130 8772246da4SFelipe Balbi #define DWC3_GBUSERRADDR1 0xc134 8872246da4SFelipe Balbi #define DWC3_GPRTBIMAP0 0xc138 8972246da4SFelipe Balbi #define DWC3_GPRTBIMAP1 0xc13c 9072246da4SFelipe Balbi #define DWC3_GHWPARAMS0 0xc140 9172246da4SFelipe Balbi #define DWC3_GHWPARAMS1 0xc144 9272246da4SFelipe Balbi #define DWC3_GHWPARAMS2 0xc148 9372246da4SFelipe Balbi #define DWC3_GHWPARAMS3 0xc14c 9472246da4SFelipe Balbi #define DWC3_GHWPARAMS4 0xc150 9572246da4SFelipe Balbi #define DWC3_GHWPARAMS5 0xc154 9672246da4SFelipe Balbi #define DWC3_GHWPARAMS6 0xc158 9772246da4SFelipe Balbi #define DWC3_GHWPARAMS7 0xc15c 9872246da4SFelipe Balbi #define DWC3_GDBGFIFOSPACE 0xc160 9972246da4SFelipe Balbi #define DWC3_GDBGLTSSM 0xc164 10072246da4SFelipe Balbi #define DWC3_GPRTBIMAP_HS0 0xc180 10172246da4SFelipe Balbi #define DWC3_GPRTBIMAP_HS1 0xc184 10272246da4SFelipe Balbi #define DWC3_GPRTBIMAP_FS0 0xc188 10372246da4SFelipe Balbi #define DWC3_GPRTBIMAP_FS1 0xc18c 10472246da4SFelipe Balbi 10572246da4SFelipe Balbi #define DWC3_GUSB2PHYCFG(n) (0xc200 + (n * 0x04)) 10672246da4SFelipe Balbi #define DWC3_GUSB2I2CCTL(n) (0xc240 + (n * 0x04)) 10772246da4SFelipe Balbi 10872246da4SFelipe Balbi #define DWC3_GUSB2PHYACC(n) (0xc280 + (n * 0x04)) 10972246da4SFelipe Balbi 11072246da4SFelipe Balbi #define DWC3_GUSB3PIPECTL(n) (0xc2c0 + (n * 0x04)) 11172246da4SFelipe Balbi 11272246da4SFelipe Balbi #define DWC3_GTXFIFOSIZ(n) (0xc300 + (n * 0x04)) 11372246da4SFelipe Balbi #define DWC3_GRXFIFOSIZ(n) (0xc380 + (n * 0x04)) 11472246da4SFelipe Balbi 11572246da4SFelipe Balbi #define DWC3_GEVNTADRLO(n) (0xc400 + (n * 0x10)) 11672246da4SFelipe Balbi #define DWC3_GEVNTADRHI(n) (0xc404 + (n * 0x10)) 11772246da4SFelipe Balbi #define DWC3_GEVNTSIZ(n) (0xc408 + (n * 0x10)) 11872246da4SFelipe Balbi #define DWC3_GEVNTCOUNT(n) (0xc40c + (n * 0x10)) 11972246da4SFelipe Balbi 12072246da4SFelipe Balbi #define DWC3_GHWPARAMS8 0xc600 12172246da4SFelipe Balbi 12272246da4SFelipe Balbi /* Device Registers */ 12372246da4SFelipe Balbi #define DWC3_DCFG 0xc700 12472246da4SFelipe Balbi #define DWC3_DCTL 0xc704 12572246da4SFelipe Balbi #define DWC3_DEVTEN 0xc708 12672246da4SFelipe Balbi #define DWC3_DSTS 0xc70c 12772246da4SFelipe Balbi #define DWC3_DGCMDPAR 0xc710 12872246da4SFelipe Balbi #define DWC3_DGCMD 0xc714 12972246da4SFelipe Balbi #define DWC3_DALEPENA 0xc720 13072246da4SFelipe Balbi #define DWC3_DEPCMDPAR2(n) (0xc800 + (n * 0x10)) 13172246da4SFelipe Balbi #define DWC3_DEPCMDPAR1(n) (0xc804 + (n * 0x10)) 13272246da4SFelipe Balbi #define DWC3_DEPCMDPAR0(n) (0xc808 + (n * 0x10)) 13372246da4SFelipe Balbi #define DWC3_DEPCMD(n) (0xc80c + (n * 0x10)) 13472246da4SFelipe Balbi 13572246da4SFelipe Balbi /* OTG Registers */ 13672246da4SFelipe Balbi #define DWC3_OCFG 0xcc00 13772246da4SFelipe Balbi #define DWC3_OCTL 0xcc04 138d4436c3aSGeorge Cherian #define DWC3_OEVT 0xcc08 139d4436c3aSGeorge Cherian #define DWC3_OEVTEN 0xcc0C 140d4436c3aSGeorge Cherian #define DWC3_OSTS 0xcc10 14172246da4SFelipe Balbi 14272246da4SFelipe Balbi /* Bit fields */ 14372246da4SFelipe Balbi 14472246da4SFelipe Balbi /* Global Configuration Register */ 1451d046793SPaul Zimmerman #define DWC3_GCTL_PWRDNSCALE(n) ((n) << 19) 146f4aadbe4SFelipe Balbi #define DWC3_GCTL_U2RSTECN (1 << 16) 1471d046793SPaul Zimmerman #define DWC3_GCTL_RAMCLKSEL(x) (((x) & DWC3_GCTL_CLK_MASK) << 6) 14872246da4SFelipe Balbi #define DWC3_GCTL_CLK_BUS (0) 14972246da4SFelipe Balbi #define DWC3_GCTL_CLK_PIPE (1) 15072246da4SFelipe Balbi #define DWC3_GCTL_CLK_PIPEHALF (2) 15172246da4SFelipe Balbi #define DWC3_GCTL_CLK_MASK (3) 15272246da4SFelipe Balbi 1530b9fe32dSFelipe Balbi #define DWC3_GCTL_PRTCAP(n) (((n) & (3 << 12)) >> 12) 1541d046793SPaul Zimmerman #define DWC3_GCTL_PRTCAPDIR(n) ((n) << 12) 15572246da4SFelipe Balbi #define DWC3_GCTL_PRTCAP_HOST 1 15672246da4SFelipe Balbi #define DWC3_GCTL_PRTCAP_DEVICE 2 15772246da4SFelipe Balbi #define DWC3_GCTL_PRTCAP_OTG 3 15872246da4SFelipe Balbi 15972246da4SFelipe Balbi #define DWC3_GCTL_CORESOFTRESET (1 << 11) 160*183ca111SFelipe Balbi #define DWC3_GCTL_SOFITPSYNC (1 << 10) 1611d046793SPaul Zimmerman #define DWC3_GCTL_SCALEDOWN(n) ((n) << 4) 1623e87c42aSPaul Zimmerman #define DWC3_GCTL_SCALEDOWN_MASK DWC3_GCTL_SCALEDOWN(3) 16372246da4SFelipe Balbi #define DWC3_GCTL_DISSCRAMBLE (1 << 3) 1642c61a8efSPaul Zimmerman #define DWC3_GCTL_GBLHIBERNATIONEN (1 << 1) 165aabb7075SFelipe Balbi #define DWC3_GCTL_DSBLCLKGTNG (1 << 0) 16672246da4SFelipe Balbi 16772246da4SFelipe Balbi /* Global USB2 PHY Configuration Register */ 16872246da4SFelipe Balbi #define DWC3_GUSB2PHYCFG_PHYSOFTRST (1 << 31) 16972246da4SFelipe Balbi #define DWC3_GUSB2PHYCFG_SUSPHY (1 << 6) 17072246da4SFelipe Balbi 17172246da4SFelipe Balbi /* Global USB3 PIPE Control Register */ 17272246da4SFelipe Balbi #define DWC3_GUSB3PIPECTL_PHYSOFTRST (1 << 31) 17372246da4SFelipe Balbi #define DWC3_GUSB3PIPECTL_SUSPHY (1 << 17) 17472246da4SFelipe Balbi 175457e84b6SFelipe Balbi /* Global TX Fifo Size Register */ 176457e84b6SFelipe Balbi #define DWC3_GTXFIFOSIZ_TXFDEF(n) ((n) & 0xffff) 177457e84b6SFelipe Balbi #define DWC3_GTXFIFOSIZ_TXFSTADDR(n) ((n) & 0xffff0000) 178457e84b6SFelipe Balbi 17968d6a01bSFelipe Balbi /* Global Event Size Registers */ 18068d6a01bSFelipe Balbi #define DWC3_GEVNTSIZ_INTMASK (1 << 31) 18168d6a01bSFelipe Balbi #define DWC3_GEVNTSIZ_SIZE(n) ((n) & 0xffff) 18268d6a01bSFelipe Balbi 183aabb7075SFelipe Balbi /* Global HWPARAMS1 Register */ 1841d046793SPaul Zimmerman #define DWC3_GHWPARAMS1_EN_PWROPT(n) (((n) & (3 << 24)) >> 24) 185aabb7075SFelipe Balbi #define DWC3_GHWPARAMS1_EN_PWROPT_NO 0 186aabb7075SFelipe Balbi #define DWC3_GHWPARAMS1_EN_PWROPT_CLK 1 1872c61a8efSPaul Zimmerman #define DWC3_GHWPARAMS1_EN_PWROPT_HIB 2 1882c61a8efSPaul Zimmerman #define DWC3_GHWPARAMS1_PWROPT(n) ((n) << 24) 1892c61a8efSPaul Zimmerman #define DWC3_GHWPARAMS1_PWROPT_MASK DWC3_GHWPARAMS1_PWROPT(3) 1902c61a8efSPaul Zimmerman 1912c61a8efSPaul Zimmerman /* Global HWPARAMS4 Register */ 1922c61a8efSPaul Zimmerman #define DWC3_GHWPARAMS4_HIBER_SCRATCHBUFS(n) (((n) & (0x0f << 13)) >> 13) 1932c61a8efSPaul Zimmerman #define DWC3_MAX_HIBER_SCRATCHBUFS 15 194aabb7075SFelipe Balbi 19572246da4SFelipe Balbi /* Device Configuration Register */ 19672246da4SFelipe Balbi #define DWC3_DCFG_DEVADDR(addr) ((addr) << 3) 19772246da4SFelipe Balbi #define DWC3_DCFG_DEVADDR_MASK DWC3_DCFG_DEVADDR(0x7f) 19872246da4SFelipe Balbi 19972246da4SFelipe Balbi #define DWC3_DCFG_SPEED_MASK (7 << 0) 20072246da4SFelipe Balbi #define DWC3_DCFG_SUPERSPEED (4 << 0) 20172246da4SFelipe Balbi #define DWC3_DCFG_HIGHSPEED (0 << 0) 20272246da4SFelipe Balbi #define DWC3_DCFG_FULLSPEED2 (1 << 0) 20372246da4SFelipe Balbi #define DWC3_DCFG_LOWSPEED (2 << 0) 20472246da4SFelipe Balbi #define DWC3_DCFG_FULLSPEED1 (3 << 0) 20572246da4SFelipe Balbi 2062c61a8efSPaul Zimmerman #define DWC3_DCFG_LPM_CAP (1 << 22) 2072c61a8efSPaul Zimmerman 20872246da4SFelipe Balbi /* Device Control Register */ 20972246da4SFelipe Balbi #define DWC3_DCTL_RUN_STOP (1 << 31) 21072246da4SFelipe Balbi #define DWC3_DCTL_CSFTRST (1 << 30) 21172246da4SFelipe Balbi #define DWC3_DCTL_LSFTRST (1 << 29) 21272246da4SFelipe Balbi 21372246da4SFelipe Balbi #define DWC3_DCTL_HIRD_THRES_MASK (0x1f << 24) 2147e39b817SPratyush Anand #define DWC3_DCTL_HIRD_THRES(n) ((n) << 24) 21572246da4SFelipe Balbi 21672246da4SFelipe Balbi #define DWC3_DCTL_APPL1RES (1 << 23) 21772246da4SFelipe Balbi 2182c61a8efSPaul Zimmerman /* These apply for core versions 1.87a and earlier */ 2198db7ed15SFelipe Balbi #define DWC3_DCTL_TRGTULST_MASK (0x0f << 17) 2208db7ed15SFelipe Balbi #define DWC3_DCTL_TRGTULST(n) ((n) << 17) 2218db7ed15SFelipe Balbi #define DWC3_DCTL_TRGTULST_U2 (DWC3_DCTL_TRGTULST(2)) 2228db7ed15SFelipe Balbi #define DWC3_DCTL_TRGTULST_U3 (DWC3_DCTL_TRGTULST(3)) 2238db7ed15SFelipe Balbi #define DWC3_DCTL_TRGTULST_SS_DIS (DWC3_DCTL_TRGTULST(4)) 2248db7ed15SFelipe Balbi #define DWC3_DCTL_TRGTULST_RX_DET (DWC3_DCTL_TRGTULST(5)) 2258db7ed15SFelipe Balbi #define DWC3_DCTL_TRGTULST_SS_INACT (DWC3_DCTL_TRGTULST(6)) 2268db7ed15SFelipe Balbi 2272c61a8efSPaul Zimmerman /* These apply for core versions 1.94a and later */ 2282c61a8efSPaul Zimmerman #define DWC3_DCTL_KEEP_CONNECT (1 << 19) 2292c61a8efSPaul Zimmerman #define DWC3_DCTL_L1_HIBER_EN (1 << 18) 2302c61a8efSPaul Zimmerman #define DWC3_DCTL_CRS (1 << 17) 2312c61a8efSPaul Zimmerman #define DWC3_DCTL_CSS (1 << 16) 2322c61a8efSPaul Zimmerman 23372246da4SFelipe Balbi #define DWC3_DCTL_INITU2ENA (1 << 12) 23472246da4SFelipe Balbi #define DWC3_DCTL_ACCEPTU2ENA (1 << 11) 23572246da4SFelipe Balbi #define DWC3_DCTL_INITU1ENA (1 << 10) 23672246da4SFelipe Balbi #define DWC3_DCTL_ACCEPTU1ENA (1 << 9) 23772246da4SFelipe Balbi #define DWC3_DCTL_TSTCTRL_MASK (0xf << 1) 23872246da4SFelipe Balbi 23972246da4SFelipe Balbi #define DWC3_DCTL_ULSTCHNGREQ_MASK (0x0f << 5) 24072246da4SFelipe Balbi #define DWC3_DCTL_ULSTCHNGREQ(n) (((n) << 5) & DWC3_DCTL_ULSTCHNGREQ_MASK) 24172246da4SFelipe Balbi 24272246da4SFelipe Balbi #define DWC3_DCTL_ULSTCHNG_NO_ACTION (DWC3_DCTL_ULSTCHNGREQ(0)) 24372246da4SFelipe Balbi #define DWC3_DCTL_ULSTCHNG_SS_DISABLED (DWC3_DCTL_ULSTCHNGREQ(4)) 24472246da4SFelipe Balbi #define DWC3_DCTL_ULSTCHNG_RX_DETECT (DWC3_DCTL_ULSTCHNGREQ(5)) 24572246da4SFelipe Balbi #define DWC3_DCTL_ULSTCHNG_SS_INACTIVE (DWC3_DCTL_ULSTCHNGREQ(6)) 24672246da4SFelipe Balbi #define DWC3_DCTL_ULSTCHNG_RECOVERY (DWC3_DCTL_ULSTCHNGREQ(8)) 24772246da4SFelipe Balbi #define DWC3_DCTL_ULSTCHNG_COMPLIANCE (DWC3_DCTL_ULSTCHNGREQ(10)) 24872246da4SFelipe Balbi #define DWC3_DCTL_ULSTCHNG_LOOPBACK (DWC3_DCTL_ULSTCHNGREQ(11)) 24972246da4SFelipe Balbi 25072246da4SFelipe Balbi /* Device Event Enable Register */ 25172246da4SFelipe Balbi #define DWC3_DEVTEN_VNDRDEVTSTRCVEDEN (1 << 12) 25272246da4SFelipe Balbi #define DWC3_DEVTEN_EVNTOVERFLOWEN (1 << 11) 25372246da4SFelipe Balbi #define DWC3_DEVTEN_CMDCMPLTEN (1 << 10) 25472246da4SFelipe Balbi #define DWC3_DEVTEN_ERRTICERREN (1 << 9) 25572246da4SFelipe Balbi #define DWC3_DEVTEN_SOFEN (1 << 7) 25672246da4SFelipe Balbi #define DWC3_DEVTEN_EOPFEN (1 << 6) 2572c61a8efSPaul Zimmerman #define DWC3_DEVTEN_HIBERNATIONREQEVTEN (1 << 5) 25872246da4SFelipe Balbi #define DWC3_DEVTEN_WKUPEVTEN (1 << 4) 25972246da4SFelipe Balbi #define DWC3_DEVTEN_ULSTCNGEN (1 << 3) 26072246da4SFelipe Balbi #define DWC3_DEVTEN_CONNECTDONEEN (1 << 2) 26172246da4SFelipe Balbi #define DWC3_DEVTEN_USBRSTEN (1 << 1) 26272246da4SFelipe Balbi #define DWC3_DEVTEN_DISCONNEVTEN (1 << 0) 26372246da4SFelipe Balbi 26472246da4SFelipe Balbi /* Device Status Register */ 2652c61a8efSPaul Zimmerman #define DWC3_DSTS_DCNRD (1 << 29) 2662c61a8efSPaul Zimmerman 2672c61a8efSPaul Zimmerman /* This applies for core versions 1.87a and earlier */ 26872246da4SFelipe Balbi #define DWC3_DSTS_PWRUPREQ (1 << 24) 2692c61a8efSPaul Zimmerman 2702c61a8efSPaul Zimmerman /* These apply for core versions 1.94a and later */ 2712c61a8efSPaul Zimmerman #define DWC3_DSTS_RSS (1 << 25) 2722c61a8efSPaul Zimmerman #define DWC3_DSTS_SSS (1 << 24) 2732c61a8efSPaul Zimmerman 27472246da4SFelipe Balbi #define DWC3_DSTS_COREIDLE (1 << 23) 27572246da4SFelipe Balbi #define DWC3_DSTS_DEVCTRLHLT (1 << 22) 27672246da4SFelipe Balbi 27772246da4SFelipe Balbi #define DWC3_DSTS_USBLNKST_MASK (0x0f << 18) 27872246da4SFelipe Balbi #define DWC3_DSTS_USBLNKST(n) (((n) & DWC3_DSTS_USBLNKST_MASK) >> 18) 27972246da4SFelipe Balbi 28072246da4SFelipe Balbi #define DWC3_DSTS_RXFIFOEMPTY (1 << 17) 28172246da4SFelipe Balbi 282d05b8182SPratyush Anand #define DWC3_DSTS_SOFFN_MASK (0x3fff << 3) 28372246da4SFelipe Balbi #define DWC3_DSTS_SOFFN(n) (((n) & DWC3_DSTS_SOFFN_MASK) >> 3) 28472246da4SFelipe Balbi 28572246da4SFelipe Balbi #define DWC3_DSTS_CONNECTSPD (7 << 0) 28672246da4SFelipe Balbi 28772246da4SFelipe Balbi #define DWC3_DSTS_SUPERSPEED (4 << 0) 28872246da4SFelipe Balbi #define DWC3_DSTS_HIGHSPEED (0 << 0) 28972246da4SFelipe Balbi #define DWC3_DSTS_FULLSPEED2 (1 << 0) 29072246da4SFelipe Balbi #define DWC3_DSTS_LOWSPEED (2 << 0) 29172246da4SFelipe Balbi #define DWC3_DSTS_FULLSPEED1 (3 << 0) 29272246da4SFelipe Balbi 29372246da4SFelipe Balbi /* Device Generic Command Register */ 29472246da4SFelipe Balbi #define DWC3_DGCMD_SET_LMP 0x01 29572246da4SFelipe Balbi #define DWC3_DGCMD_SET_PERIODIC_PAR 0x02 29672246da4SFelipe Balbi #define DWC3_DGCMD_XMIT_FUNCTION 0x03 2972c61a8efSPaul Zimmerman 2982c61a8efSPaul Zimmerman /* These apply for core versions 1.94a and later */ 2992c61a8efSPaul Zimmerman #define DWC3_DGCMD_SET_SCRATCHPAD_ADDR_LO 0x04 3002c61a8efSPaul Zimmerman #define DWC3_DGCMD_SET_SCRATCHPAD_ADDR_HI 0x05 3012c61a8efSPaul Zimmerman 30272246da4SFelipe Balbi #define DWC3_DGCMD_SELECTED_FIFO_FLUSH 0x09 30372246da4SFelipe Balbi #define DWC3_DGCMD_ALL_FIFO_FLUSH 0x0a 30472246da4SFelipe Balbi #define DWC3_DGCMD_SET_ENDPOINT_NRDY 0x0c 30572246da4SFelipe Balbi #define DWC3_DGCMD_RUN_SOC_BUS_LOOPBACK 0x10 30672246da4SFelipe Balbi 307b09bb642SFelipe Balbi #define DWC3_DGCMD_STATUS(n) (((n) >> 15) & 1) 308b09bb642SFelipe Balbi #define DWC3_DGCMD_CMDACT (1 << 10) 3092c61a8efSPaul Zimmerman #define DWC3_DGCMD_CMDIOC (1 << 8) 3102c61a8efSPaul Zimmerman 3112c61a8efSPaul Zimmerman /* Device Generic Command Parameter Register */ 3122c61a8efSPaul Zimmerman #define DWC3_DGCMDPAR_FORCE_LINKPM_ACCEPT (1 << 0) 3132c61a8efSPaul Zimmerman #define DWC3_DGCMDPAR_FIFO_NUM(n) ((n) << 0) 3142c61a8efSPaul Zimmerman #define DWC3_DGCMDPAR_RX_FIFO (0 << 5) 3152c61a8efSPaul Zimmerman #define DWC3_DGCMDPAR_TX_FIFO (1 << 5) 3162c61a8efSPaul Zimmerman #define DWC3_DGCMDPAR_LOOPBACK_DIS (0 << 0) 3172c61a8efSPaul Zimmerman #define DWC3_DGCMDPAR_LOOPBACK_ENA (1 << 0) 318b09bb642SFelipe Balbi 31972246da4SFelipe Balbi /* Device Endpoint Command Register */ 32072246da4SFelipe Balbi #define DWC3_DEPCMD_PARAM_SHIFT 16 3211d046793SPaul Zimmerman #define DWC3_DEPCMD_PARAM(x) ((x) << DWC3_DEPCMD_PARAM_SHIFT) 3221d046793SPaul Zimmerman #define DWC3_DEPCMD_GET_RSC_IDX(x) (((x) >> DWC3_DEPCMD_PARAM_SHIFT) & 0x7f) 323b09bb642SFelipe Balbi #define DWC3_DEPCMD_STATUS(x) (((x) >> 15) & 1) 32472246da4SFelipe Balbi #define DWC3_DEPCMD_HIPRI_FORCERM (1 << 11) 32572246da4SFelipe Balbi #define DWC3_DEPCMD_CMDACT (1 << 10) 32672246da4SFelipe Balbi #define DWC3_DEPCMD_CMDIOC (1 << 8) 32772246da4SFelipe Balbi 32872246da4SFelipe Balbi #define DWC3_DEPCMD_DEPSTARTCFG (0x09 << 0) 32972246da4SFelipe Balbi #define DWC3_DEPCMD_ENDTRANSFER (0x08 << 0) 33072246da4SFelipe Balbi #define DWC3_DEPCMD_UPDATETRANSFER (0x07 << 0) 33172246da4SFelipe Balbi #define DWC3_DEPCMD_STARTTRANSFER (0x06 << 0) 33272246da4SFelipe Balbi #define DWC3_DEPCMD_CLEARSTALL (0x05 << 0) 33372246da4SFelipe Balbi #define DWC3_DEPCMD_SETSTALL (0x04 << 0) 3342c61a8efSPaul Zimmerman /* This applies for core versions 1.90a and earlier */ 33572246da4SFelipe Balbi #define DWC3_DEPCMD_GETSEQNUMBER (0x03 << 0) 3362c61a8efSPaul Zimmerman /* This applies for core versions 1.94a and later */ 3372c61a8efSPaul Zimmerman #define DWC3_DEPCMD_GETEPSTATE (0x03 << 0) 33872246da4SFelipe Balbi #define DWC3_DEPCMD_SETTRANSFRESOURCE (0x02 << 0) 33972246da4SFelipe Balbi #define DWC3_DEPCMD_SETEPCONFIG (0x01 << 0) 34072246da4SFelipe Balbi 34172246da4SFelipe Balbi /* The EP number goes 0..31 so ep0 is always out and ep1 is always in */ 34272246da4SFelipe Balbi #define DWC3_DALEPENA_EP(n) (1 << n) 34372246da4SFelipe Balbi 34472246da4SFelipe Balbi #define DWC3_DEPCMD_TYPE_CONTROL 0 34572246da4SFelipe Balbi #define DWC3_DEPCMD_TYPE_ISOC 1 34672246da4SFelipe Balbi #define DWC3_DEPCMD_TYPE_BULK 2 34772246da4SFelipe Balbi #define DWC3_DEPCMD_TYPE_INTR 3 34872246da4SFelipe Balbi 34972246da4SFelipe Balbi /* Structures */ 35072246da4SFelipe Balbi 351f6bafc6aSFelipe Balbi struct dwc3_trb; 35272246da4SFelipe Balbi 35372246da4SFelipe Balbi /** 35472246da4SFelipe Balbi * struct dwc3_event_buffer - Software event buffer representation 35572246da4SFelipe Balbi * @buf: _THE_ buffer 35672246da4SFelipe Balbi * @length: size of this buffer 357abed4118SFelipe Balbi * @lpos: event offset 35860d04bbeSFelipe Balbi * @count: cache of last read event count register 359abed4118SFelipe Balbi * @flags: flags related to this event buffer 36072246da4SFelipe Balbi * @dma: dma_addr_t 36172246da4SFelipe Balbi * @dwc: pointer to DWC controller 36272246da4SFelipe Balbi */ 36372246da4SFelipe Balbi struct dwc3_event_buffer { 36472246da4SFelipe Balbi void *buf; 36572246da4SFelipe Balbi unsigned length; 36672246da4SFelipe Balbi unsigned int lpos; 36760d04bbeSFelipe Balbi unsigned int count; 368abed4118SFelipe Balbi unsigned int flags; 369abed4118SFelipe Balbi 370abed4118SFelipe Balbi #define DWC3_EVENT_PENDING BIT(0) 37172246da4SFelipe Balbi 37272246da4SFelipe Balbi dma_addr_t dma; 37372246da4SFelipe Balbi 37472246da4SFelipe Balbi struct dwc3 *dwc; 37572246da4SFelipe Balbi }; 37672246da4SFelipe Balbi 37772246da4SFelipe Balbi #define DWC3_EP_FLAG_STALLED (1 << 0) 37872246da4SFelipe Balbi #define DWC3_EP_FLAG_WEDGED (1 << 1) 37972246da4SFelipe Balbi 38072246da4SFelipe Balbi #define DWC3_EP_DIRECTION_TX true 38172246da4SFelipe Balbi #define DWC3_EP_DIRECTION_RX false 38272246da4SFelipe Balbi 38372246da4SFelipe Balbi #define DWC3_TRB_NUM 32 38472246da4SFelipe Balbi #define DWC3_TRB_MASK (DWC3_TRB_NUM - 1) 38572246da4SFelipe Balbi 38672246da4SFelipe Balbi /** 38772246da4SFelipe Balbi * struct dwc3_ep - device side endpoint representation 38872246da4SFelipe Balbi * @endpoint: usb endpoint 38972246da4SFelipe Balbi * @request_list: list of requests for this endpoint 39072246da4SFelipe Balbi * @req_queued: list of requests on this ep which have TRBs setup 39172246da4SFelipe Balbi * @trb_pool: array of transaction buffers 39272246da4SFelipe Balbi * @trb_pool_dma: dma address of @trb_pool 39372246da4SFelipe Balbi * @free_slot: next slot which is going to be used 39472246da4SFelipe Balbi * @busy_slot: first slot which is owned by HW 39572246da4SFelipe Balbi * @desc: usb_endpoint_descriptor pointer 39672246da4SFelipe Balbi * @dwc: pointer to DWC controller 39772246da4SFelipe Balbi * @flags: endpoint flags (wedged, stalled, ...) 39872246da4SFelipe Balbi * @current_trb: index of current used trb 39972246da4SFelipe Balbi * @number: endpoint number (1 - 15) 40072246da4SFelipe Balbi * @type: set to bmAttributes & USB_ENDPOINT_XFERTYPE_MASK 401b4996a86SFelipe Balbi * @resource_index: Resource transfer index 402c75f52fbSHuang Rui * @interval: the interval on which the ISOC transfer is started 40372246da4SFelipe Balbi * @name: a human readable name e.g. ep1out-bulk 40472246da4SFelipe Balbi * @direction: true for TX, false for RX 405879631aaSFelipe Balbi * @stream_capable: true when streams are enabled 40672246da4SFelipe Balbi */ 40772246da4SFelipe Balbi struct dwc3_ep { 40872246da4SFelipe Balbi struct usb_ep endpoint; 40972246da4SFelipe Balbi struct list_head request_list; 41072246da4SFelipe Balbi struct list_head req_queued; 41172246da4SFelipe Balbi 412f6bafc6aSFelipe Balbi struct dwc3_trb *trb_pool; 41372246da4SFelipe Balbi dma_addr_t trb_pool_dma; 41472246da4SFelipe Balbi u32 free_slot; 41572246da4SFelipe Balbi u32 busy_slot; 416c90bfaecSFelipe Balbi const struct usb_ss_ep_comp_descriptor *comp_desc; 41772246da4SFelipe Balbi struct dwc3 *dwc; 41872246da4SFelipe Balbi 41972246da4SFelipe Balbi unsigned flags; 42072246da4SFelipe Balbi #define DWC3_EP_ENABLED (1 << 0) 42172246da4SFelipe Balbi #define DWC3_EP_STALL (1 << 1) 42272246da4SFelipe Balbi #define DWC3_EP_WEDGE (1 << 2) 42372246da4SFelipe Balbi #define DWC3_EP_BUSY (1 << 4) 42472246da4SFelipe Balbi #define DWC3_EP_PENDING_REQUEST (1 << 5) 425d6d6ec7bSPratyush Anand #define DWC3_EP_MISSED_ISOC (1 << 6) 42672246da4SFelipe Balbi 427984f66a6SFelipe Balbi /* This last one is specific to EP0 */ 428984f66a6SFelipe Balbi #define DWC3_EP0_DIR_IN (1 << 31) 429984f66a6SFelipe Balbi 43072246da4SFelipe Balbi unsigned current_trb; 43172246da4SFelipe Balbi 43272246da4SFelipe Balbi u8 number; 43372246da4SFelipe Balbi u8 type; 434b4996a86SFelipe Balbi u8 resource_index; 43572246da4SFelipe Balbi u32 interval; 43672246da4SFelipe Balbi 43772246da4SFelipe Balbi char name[20]; 43872246da4SFelipe Balbi 43972246da4SFelipe Balbi unsigned direction:1; 440879631aaSFelipe Balbi unsigned stream_capable:1; 44172246da4SFelipe Balbi }; 44272246da4SFelipe Balbi 44372246da4SFelipe Balbi enum dwc3_phy { 44472246da4SFelipe Balbi DWC3_PHY_UNKNOWN = 0, 44572246da4SFelipe Balbi DWC3_PHY_USB3, 44672246da4SFelipe Balbi DWC3_PHY_USB2, 44772246da4SFelipe Balbi }; 44872246da4SFelipe Balbi 449b53c772dSFelipe Balbi enum dwc3_ep0_next { 450b53c772dSFelipe Balbi DWC3_EP0_UNKNOWN = 0, 451b53c772dSFelipe Balbi DWC3_EP0_COMPLETE, 452b53c772dSFelipe Balbi DWC3_EP0_NRDY_DATA, 453b53c772dSFelipe Balbi DWC3_EP0_NRDY_STATUS, 454b53c772dSFelipe Balbi }; 455b53c772dSFelipe Balbi 45672246da4SFelipe Balbi enum dwc3_ep0_state { 45772246da4SFelipe Balbi EP0_UNCONNECTED = 0, 458c7fcdeb2SFelipe Balbi EP0_SETUP_PHASE, 459c7fcdeb2SFelipe Balbi EP0_DATA_PHASE, 460c7fcdeb2SFelipe Balbi EP0_STATUS_PHASE, 46172246da4SFelipe Balbi }; 46272246da4SFelipe Balbi 46372246da4SFelipe Balbi enum dwc3_link_state { 46472246da4SFelipe Balbi /* In SuperSpeed */ 46572246da4SFelipe Balbi DWC3_LINK_STATE_U0 = 0x00, /* in HS, means ON */ 46672246da4SFelipe Balbi DWC3_LINK_STATE_U1 = 0x01, 46772246da4SFelipe Balbi DWC3_LINK_STATE_U2 = 0x02, /* in HS, means SLEEP */ 46872246da4SFelipe Balbi DWC3_LINK_STATE_U3 = 0x03, /* in HS, means SUSPEND */ 46972246da4SFelipe Balbi DWC3_LINK_STATE_SS_DIS = 0x04, 47072246da4SFelipe Balbi DWC3_LINK_STATE_RX_DET = 0x05, /* in HS, means Early Suspend */ 47172246da4SFelipe Balbi DWC3_LINK_STATE_SS_INACT = 0x06, 47272246da4SFelipe Balbi DWC3_LINK_STATE_POLL = 0x07, 47372246da4SFelipe Balbi DWC3_LINK_STATE_RECOV = 0x08, 47472246da4SFelipe Balbi DWC3_LINK_STATE_HRESET = 0x09, 47572246da4SFelipe Balbi DWC3_LINK_STATE_CMPLY = 0x0a, 47672246da4SFelipe Balbi DWC3_LINK_STATE_LPBK = 0x0b, 4772c61a8efSPaul Zimmerman DWC3_LINK_STATE_RESET = 0x0e, 4782c61a8efSPaul Zimmerman DWC3_LINK_STATE_RESUME = 0x0f, 47972246da4SFelipe Balbi DWC3_LINK_STATE_MASK = 0x0f, 48072246da4SFelipe Balbi }; 48172246da4SFelipe Balbi 482f6bafc6aSFelipe Balbi /* TRB Length, PCM and Status */ 483f6bafc6aSFelipe Balbi #define DWC3_TRB_SIZE_MASK (0x00ffffff) 484f6bafc6aSFelipe Balbi #define DWC3_TRB_SIZE_LENGTH(n) ((n) & DWC3_TRB_SIZE_MASK) 485f6bafc6aSFelipe Balbi #define DWC3_TRB_SIZE_PCM1(n) (((n) & 0x03) << 24) 486389f2828SPratyush Anand #define DWC3_TRB_SIZE_TRBSTS(n) (((n) & (0x0f << 28)) >> 28) 48772246da4SFelipe Balbi 488f6bafc6aSFelipe Balbi #define DWC3_TRBSTS_OK 0 489f6bafc6aSFelipe Balbi #define DWC3_TRBSTS_MISSED_ISOC 1 490f6bafc6aSFelipe Balbi #define DWC3_TRBSTS_SETUP_PENDING 2 4912c61a8efSPaul Zimmerman #define DWC3_TRB_STS_XFER_IN_PROG 4 49272246da4SFelipe Balbi 493f6bafc6aSFelipe Balbi /* TRB Control */ 494f6bafc6aSFelipe Balbi #define DWC3_TRB_CTRL_HWO (1 << 0) 495f6bafc6aSFelipe Balbi #define DWC3_TRB_CTRL_LST (1 << 1) 496f6bafc6aSFelipe Balbi #define DWC3_TRB_CTRL_CHN (1 << 2) 497f6bafc6aSFelipe Balbi #define DWC3_TRB_CTRL_CSP (1 << 3) 498f6bafc6aSFelipe Balbi #define DWC3_TRB_CTRL_TRBCTL(n) (((n) & 0x3f) << 4) 499f6bafc6aSFelipe Balbi #define DWC3_TRB_CTRL_ISP_IMI (1 << 10) 500f6bafc6aSFelipe Balbi #define DWC3_TRB_CTRL_IOC (1 << 11) 501f6bafc6aSFelipe Balbi #define DWC3_TRB_CTRL_SID_SOFN(n) (((n) & 0xffff) << 14) 502f6bafc6aSFelipe Balbi 503f6bafc6aSFelipe Balbi #define DWC3_TRBCTL_NORMAL DWC3_TRB_CTRL_TRBCTL(1) 504f6bafc6aSFelipe Balbi #define DWC3_TRBCTL_CONTROL_SETUP DWC3_TRB_CTRL_TRBCTL(2) 505f6bafc6aSFelipe Balbi #define DWC3_TRBCTL_CONTROL_STATUS2 DWC3_TRB_CTRL_TRBCTL(3) 506f6bafc6aSFelipe Balbi #define DWC3_TRBCTL_CONTROL_STATUS3 DWC3_TRB_CTRL_TRBCTL(4) 507f6bafc6aSFelipe Balbi #define DWC3_TRBCTL_CONTROL_DATA DWC3_TRB_CTRL_TRBCTL(5) 508f6bafc6aSFelipe Balbi #define DWC3_TRBCTL_ISOCHRONOUS_FIRST DWC3_TRB_CTRL_TRBCTL(6) 509f6bafc6aSFelipe Balbi #define DWC3_TRBCTL_ISOCHRONOUS DWC3_TRB_CTRL_TRBCTL(7) 510f6bafc6aSFelipe Balbi #define DWC3_TRBCTL_LINK_TRB DWC3_TRB_CTRL_TRBCTL(8) 51172246da4SFelipe Balbi 51272246da4SFelipe Balbi /** 513f6bafc6aSFelipe Balbi * struct dwc3_trb - transfer request block (hw format) 51472246da4SFelipe Balbi * @bpl: DW0-3 51572246da4SFelipe Balbi * @bph: DW4-7 51672246da4SFelipe Balbi * @size: DW8-B 51772246da4SFelipe Balbi * @trl: DWC-F 51872246da4SFelipe Balbi */ 519f6bafc6aSFelipe Balbi struct dwc3_trb { 520f6bafc6aSFelipe Balbi u32 bpl; 521f6bafc6aSFelipe Balbi u32 bph; 522f6bafc6aSFelipe Balbi u32 size; 523f6bafc6aSFelipe Balbi u32 ctrl; 52472246da4SFelipe Balbi } __packed; 52572246da4SFelipe Balbi 52672246da4SFelipe Balbi /** 527a3299499SFelipe Balbi * dwc3_hwparams - copy of HWPARAMS registers 528a3299499SFelipe Balbi * @hwparams0 - GHWPARAMS0 529a3299499SFelipe Balbi * @hwparams1 - GHWPARAMS1 530a3299499SFelipe Balbi * @hwparams2 - GHWPARAMS2 531a3299499SFelipe Balbi * @hwparams3 - GHWPARAMS3 532a3299499SFelipe Balbi * @hwparams4 - GHWPARAMS4 533a3299499SFelipe Balbi * @hwparams5 - GHWPARAMS5 534a3299499SFelipe Balbi * @hwparams6 - GHWPARAMS6 535a3299499SFelipe Balbi * @hwparams7 - GHWPARAMS7 536a3299499SFelipe Balbi * @hwparams8 - GHWPARAMS8 537a3299499SFelipe Balbi */ 538a3299499SFelipe Balbi struct dwc3_hwparams { 539a3299499SFelipe Balbi u32 hwparams0; 540a3299499SFelipe Balbi u32 hwparams1; 541a3299499SFelipe Balbi u32 hwparams2; 542a3299499SFelipe Balbi u32 hwparams3; 543a3299499SFelipe Balbi u32 hwparams4; 544a3299499SFelipe Balbi u32 hwparams5; 545a3299499SFelipe Balbi u32 hwparams6; 546a3299499SFelipe Balbi u32 hwparams7; 547a3299499SFelipe Balbi u32 hwparams8; 548a3299499SFelipe Balbi }; 549a3299499SFelipe Balbi 5500949e99bSFelipe Balbi /* HWPARAMS0 */ 5510949e99bSFelipe Balbi #define DWC3_MODE(n) ((n) & 0x7) 5520949e99bSFelipe Balbi 553457e84b6SFelipe Balbi #define DWC3_MDWIDTH(n) (((n) & 0xff00) >> 8) 554457e84b6SFelipe Balbi 5550949e99bSFelipe Balbi /* HWPARAMS1 */ 5569f622b2aSFelipe Balbi #define DWC3_NUM_INT(n) (((n) & (0x3f << 15)) >> 15) 5579f622b2aSFelipe Balbi 558789451f6SFelipe Balbi /* HWPARAMS3 */ 559789451f6SFelipe Balbi #define DWC3_NUM_IN_EPS_MASK (0x1f << 18) 560789451f6SFelipe Balbi #define DWC3_NUM_EPS_MASK (0x3f << 12) 561789451f6SFelipe Balbi #define DWC3_NUM_EPS(p) (((p)->hwparams3 & \ 562789451f6SFelipe Balbi (DWC3_NUM_EPS_MASK)) >> 12) 563789451f6SFelipe Balbi #define DWC3_NUM_IN_EPS(p) (((p)->hwparams3 & \ 564789451f6SFelipe Balbi (DWC3_NUM_IN_EPS_MASK)) >> 18) 565789451f6SFelipe Balbi 566457e84b6SFelipe Balbi /* HWPARAMS7 */ 567457e84b6SFelipe Balbi #define DWC3_RAM1_DEPTH(n) ((n) & 0xffff) 568457e84b6SFelipe Balbi 569e0ce0b0aSSebastian Andrzej Siewior struct dwc3_request { 570e0ce0b0aSSebastian Andrzej Siewior struct usb_request request; 571e0ce0b0aSSebastian Andrzej Siewior struct list_head list; 572e0ce0b0aSSebastian Andrzej Siewior struct dwc3_ep *dep; 573e5ba5ec8SPratyush Anand u32 start_slot; 574e0ce0b0aSSebastian Andrzej Siewior 575e0ce0b0aSSebastian Andrzej Siewior u8 epnum; 576f6bafc6aSFelipe Balbi struct dwc3_trb *trb; 577e0ce0b0aSSebastian Andrzej Siewior dma_addr_t trb_dma; 578e0ce0b0aSSebastian Andrzej Siewior 579e0ce0b0aSSebastian Andrzej Siewior unsigned direction:1; 580e0ce0b0aSSebastian Andrzej Siewior unsigned mapped:1; 581e0ce0b0aSSebastian Andrzej Siewior unsigned queued:1; 582e0ce0b0aSSebastian Andrzej Siewior }; 583e0ce0b0aSSebastian Andrzej Siewior 5842c61a8efSPaul Zimmerman /* 5852c61a8efSPaul Zimmerman * struct dwc3_scratchpad_array - hibernation scratchpad array 5862c61a8efSPaul Zimmerman * (format defined by hw) 5872c61a8efSPaul Zimmerman */ 5882c61a8efSPaul Zimmerman struct dwc3_scratchpad_array { 5892c61a8efSPaul Zimmerman __le64 dma_adr[DWC3_MAX_HIBER_SCRATCHBUFS]; 5902c61a8efSPaul Zimmerman }; 5912c61a8efSPaul Zimmerman 592a3299499SFelipe Balbi /** 59372246da4SFelipe Balbi * struct dwc3 - representation of our controller 59491db07dcSFelipe Balbi * @ctrl_req: usb control request which is used for ep0 59591db07dcSFelipe Balbi * @ep0_trb: trb which is used for the ctrl_req 5965812b1c2SFelipe Balbi * @ep0_bounce: bounce buffer for ep0 59791db07dcSFelipe Balbi * @setup_buf: used while precessing STD USB requests 59891db07dcSFelipe Balbi * @ctrl_req_addr: dma address of ctrl_req 59991db07dcSFelipe Balbi * @ep0_trb: dma address of ep0_trb 60091db07dcSFelipe Balbi * @ep0_usb_req: dummy req used while handling STD USB requests 6015812b1c2SFelipe Balbi * @ep0_bounce_addr: dma address of ep0_bounce 60272246da4SFelipe Balbi * @lock: for synchronizing 60372246da4SFelipe Balbi * @dev: pointer to our struct device 604d07e8819SFelipe Balbi * @xhci: pointer to our xHCI child 60572246da4SFelipe Balbi * @event_buffer_list: a list of event buffers 60672246da4SFelipe Balbi * @gadget: device side representation of the peripheral controller 60772246da4SFelipe Balbi * @gadget_driver: pointer to the gadget driver 60872246da4SFelipe Balbi * @regs: base address for our registers 60972246da4SFelipe Balbi * @regs_size: address space size 6109f622b2aSFelipe Balbi * @num_event_buffers: calculated number of event buffers 611fae2b904SFelipe Balbi * @u1u2: only used on revisions <1.83a for workaround 6126c167fc9SFelipe Balbi * @maximum_speed: maximum speed requested (mainly for testing purposes) 61372246da4SFelipe Balbi * @revision: revision register contents 614a45c82b8SRuchika Kharwar * @dr_mode: requested mode of operation 61551e1e7bcSFelipe Balbi * @usb2_phy: pointer to USB2 PHY 61651e1e7bcSFelipe Balbi * @usb3_phy: pointer to USB3 PHY 6177415f17cSFelipe Balbi * @dcfg: saved contents of DCFG register 6187415f17cSFelipe Balbi * @gctl: saved contents of GCTL register 61972246da4SFelipe Balbi * @is_selfpowered: true when we are selfpowered 62072246da4SFelipe Balbi * @three_stage_setup: set if we perform a three phase setup 6215812b1c2SFelipe Balbi * @ep0_bounced: true when we used bounce buffer 62255f3fba6SFelipe Balbi * @ep0_expect_in: true when we expect a DATA IN transfer 623b23c8439SPaul Zimmerman * @start_config_issued: true when StartConfig command has been issued 624df62df56SFelipe Balbi * @setup_packet_pending: true when there's a Setup Packet in FIFO. Workaround 625457e84b6SFelipe Balbi * @needs_fifo_resize: not all users might want fifo resizing, flag it 626457e84b6SFelipe Balbi * @resize_fifos: tells us it's ok to reconfigure our TxFIFO sizes. 627c12a0d86SFelipe Balbi * @isoch_delay: wValue from Set Isochronous Delay request; 628865e09e7SFelipe Balbi * @u2sel: parameter from Set SEL request. 629865e09e7SFelipe Balbi * @u2pel: parameter from Set SEL request. 630865e09e7SFelipe Balbi * @u1sel: parameter from Set SEL request. 631865e09e7SFelipe Balbi * @u1pel: parameter from Set SEL request. 632789451f6SFelipe Balbi * @num_out_eps: number of out endpoints 633789451f6SFelipe Balbi * @num_in_eps: number of in endpoints 634b53c772dSFelipe Balbi * @ep0_next_event: hold the next expected event 63572246da4SFelipe Balbi * @ep0state: state of endpoint zero 63672246da4SFelipe Balbi * @link_state: link state 63772246da4SFelipe Balbi * @speed: device speed (super, high, full, low) 63872246da4SFelipe Balbi * @mem: points to start of memory which is used for this struct. 639a3299499SFelipe Balbi * @hwparams: copy of hwparams registers 64072246da4SFelipe Balbi * @root: debugfs root folder pointer 64172246da4SFelipe Balbi */ 64272246da4SFelipe Balbi struct dwc3 { 64372246da4SFelipe Balbi struct usb_ctrlrequest *ctrl_req; 644f6bafc6aSFelipe Balbi struct dwc3_trb *ep0_trb; 6455812b1c2SFelipe Balbi void *ep0_bounce; 64672246da4SFelipe Balbi u8 *setup_buf; 64772246da4SFelipe Balbi dma_addr_t ctrl_req_addr; 64872246da4SFelipe Balbi dma_addr_t ep0_trb_addr; 6495812b1c2SFelipe Balbi dma_addr_t ep0_bounce_addr; 650e0ce0b0aSSebastian Andrzej Siewior struct dwc3_request ep0_usb_req; 651789451f6SFelipe Balbi 65272246da4SFelipe Balbi /* device lock */ 65372246da4SFelipe Balbi spinlock_t lock; 654789451f6SFelipe Balbi 65572246da4SFelipe Balbi struct device *dev; 65672246da4SFelipe Balbi 657d07e8819SFelipe Balbi struct platform_device *xhci; 65851249dcaSIdo Shayevitz struct resource xhci_resources[DWC3_XHCI_RESOURCES_NUM]; 659d07e8819SFelipe Balbi 660457d3f21SFelipe Balbi struct dwc3_event_buffer **ev_buffs; 66172246da4SFelipe Balbi struct dwc3_ep *eps[DWC3_ENDPOINTS_NUM]; 66272246da4SFelipe Balbi 66372246da4SFelipe Balbi struct usb_gadget gadget; 66472246da4SFelipe Balbi struct usb_gadget_driver *gadget_driver; 66572246da4SFelipe Balbi 66651e1e7bcSFelipe Balbi struct usb_phy *usb2_phy; 66751e1e7bcSFelipe Balbi struct usb_phy *usb3_phy; 66851e1e7bcSFelipe Balbi 66972246da4SFelipe Balbi void __iomem *regs; 67072246da4SFelipe Balbi size_t regs_size; 67172246da4SFelipe Balbi 672a45c82b8SRuchika Kharwar enum usb_dr_mode dr_mode; 673a45c82b8SRuchika Kharwar 6747415f17cSFelipe Balbi /* used for suspend/resume */ 6757415f17cSFelipe Balbi u32 dcfg; 6767415f17cSFelipe Balbi u32 gctl; 6777415f17cSFelipe Balbi 6789f622b2aSFelipe Balbi u32 num_event_buffers; 679fae2b904SFelipe Balbi u32 u1u2; 6806c167fc9SFelipe Balbi u32 maximum_speed; 68172246da4SFelipe Balbi u32 revision; 68272246da4SFelipe Balbi 68372246da4SFelipe Balbi #define DWC3_REVISION_173A 0x5533173a 68472246da4SFelipe Balbi #define DWC3_REVISION_175A 0x5533175a 68572246da4SFelipe Balbi #define DWC3_REVISION_180A 0x5533180a 68672246da4SFelipe Balbi #define DWC3_REVISION_183A 0x5533183a 68772246da4SFelipe Balbi #define DWC3_REVISION_185A 0x5533185a 6882c61a8efSPaul Zimmerman #define DWC3_REVISION_187A 0x5533187a 68972246da4SFelipe Balbi #define DWC3_REVISION_188A 0x5533188a 69072246da4SFelipe Balbi #define DWC3_REVISION_190A 0x5533190a 6912c61a8efSPaul Zimmerman #define DWC3_REVISION_194A 0x5533194a 6921522d703SFelipe Balbi #define DWC3_REVISION_200A 0x5533200a 6931522d703SFelipe Balbi #define DWC3_REVISION_202A 0x5533202a 6941522d703SFelipe Balbi #define DWC3_REVISION_210A 0x5533210a 6951522d703SFelipe Balbi #define DWC3_REVISION_220A 0x5533220a 6967ac6a593SFelipe Balbi #define DWC3_REVISION_230A 0x5533230a 6977ac6a593SFelipe Balbi #define DWC3_REVISION_240A 0x5533240a 6987ac6a593SFelipe Balbi #define DWC3_REVISION_250A 0x5533250a 69972246da4SFelipe Balbi 70072246da4SFelipe Balbi unsigned is_selfpowered:1; 70172246da4SFelipe Balbi unsigned three_stage_setup:1; 7025812b1c2SFelipe Balbi unsigned ep0_bounced:1; 70355f3fba6SFelipe Balbi unsigned ep0_expect_in:1; 704b23c8439SPaul Zimmerman unsigned start_config_issued:1; 705df62df56SFelipe Balbi unsigned setup_packet_pending:1; 7065bdb1dccSSebastian Andrzej Siewior unsigned delayed_status:1; 707457e84b6SFelipe Balbi unsigned needs_fifo_resize:1; 708457e84b6SFelipe Balbi unsigned resize_fifos:1; 7099fcb3bd8SFelipe Balbi unsigned pullups_connected:1; 71072246da4SFelipe Balbi 711b53c772dSFelipe Balbi enum dwc3_ep0_next ep0_next_event; 71272246da4SFelipe Balbi enum dwc3_ep0_state ep0state; 71372246da4SFelipe Balbi enum dwc3_link_state link_state; 71472246da4SFelipe Balbi 715c12a0d86SFelipe Balbi u16 isoch_delay; 716865e09e7SFelipe Balbi u16 u2sel; 717865e09e7SFelipe Balbi u16 u2pel; 718865e09e7SFelipe Balbi u8 u1sel; 719865e09e7SFelipe Balbi u8 u1pel; 720865e09e7SFelipe Balbi 72172246da4SFelipe Balbi u8 speed; 722865e09e7SFelipe Balbi 723789451f6SFelipe Balbi u8 num_out_eps; 724789451f6SFelipe Balbi u8 num_in_eps; 725789451f6SFelipe Balbi 72672246da4SFelipe Balbi void *mem; 72772246da4SFelipe Balbi 728a3299499SFelipe Balbi struct dwc3_hwparams hwparams; 72972246da4SFelipe Balbi struct dentry *root; 730d7668024SFelipe Balbi struct debugfs_regset32 *regset; 7313b637367SGerard Cauvy 7323b637367SGerard Cauvy u8 test_mode; 7333b637367SGerard Cauvy u8 test_mode_nr; 73472246da4SFelipe Balbi }; 73572246da4SFelipe Balbi 73672246da4SFelipe Balbi /* -------------------------------------------------------------------------- */ 73772246da4SFelipe Balbi 73872246da4SFelipe Balbi /* -------------------------------------------------------------------------- */ 73972246da4SFelipe Balbi 74072246da4SFelipe Balbi struct dwc3_event_type { 74172246da4SFelipe Balbi u32 is_devspec:1; 7421974d494SHuang Rui u32 type:7; 7431974d494SHuang Rui u32 reserved8_31:24; 74472246da4SFelipe Balbi } __packed; 74572246da4SFelipe Balbi 74672246da4SFelipe Balbi #define DWC3_DEPEVT_XFERCOMPLETE 0x01 74772246da4SFelipe Balbi #define DWC3_DEPEVT_XFERINPROGRESS 0x02 74872246da4SFelipe Balbi #define DWC3_DEPEVT_XFERNOTREADY 0x03 74972246da4SFelipe Balbi #define DWC3_DEPEVT_RXTXFIFOEVT 0x04 75072246da4SFelipe Balbi #define DWC3_DEPEVT_STREAMEVT 0x06 75172246da4SFelipe Balbi #define DWC3_DEPEVT_EPCMDCMPLT 0x07 75272246da4SFelipe Balbi 75372246da4SFelipe Balbi /** 75472246da4SFelipe Balbi * struct dwc3_event_depvt - Device Endpoint Events 75572246da4SFelipe Balbi * @one_bit: indicates this is an endpoint event (not used) 75672246da4SFelipe Balbi * @endpoint_number: number of the endpoint 75772246da4SFelipe Balbi * @endpoint_event: The event we have: 75872246da4SFelipe Balbi * 0x00 - Reserved 75972246da4SFelipe Balbi * 0x01 - XferComplete 76072246da4SFelipe Balbi * 0x02 - XferInProgress 76172246da4SFelipe Balbi * 0x03 - XferNotReady 76272246da4SFelipe Balbi * 0x04 - RxTxFifoEvt (IN->Underrun, OUT->Overrun) 76372246da4SFelipe Balbi * 0x05 - Reserved 76472246da4SFelipe Balbi * 0x06 - StreamEvt 76572246da4SFelipe Balbi * 0x07 - EPCmdCmplt 76672246da4SFelipe Balbi * @reserved11_10: Reserved, don't use. 76772246da4SFelipe Balbi * @status: Indicates the status of the event. Refer to databook for 76872246da4SFelipe Balbi * more information. 76972246da4SFelipe Balbi * @parameters: Parameters of the current event. Refer to databook for 77072246da4SFelipe Balbi * more information. 77172246da4SFelipe Balbi */ 77272246da4SFelipe Balbi struct dwc3_event_depevt { 77372246da4SFelipe Balbi u32 one_bit:1; 77472246da4SFelipe Balbi u32 endpoint_number:5; 77572246da4SFelipe Balbi u32 endpoint_event:4; 77672246da4SFelipe Balbi u32 reserved11_10:2; 77772246da4SFelipe Balbi u32 status:4; 77840aa41fbSFelipe Balbi 77940aa41fbSFelipe Balbi /* Within XferNotReady */ 78040aa41fbSFelipe Balbi #define DEPEVT_STATUS_TRANSFER_ACTIVE (1 << 3) 78140aa41fbSFelipe Balbi 78240aa41fbSFelipe Balbi /* Within XferComplete */ 78372246da4SFelipe Balbi #define DEPEVT_STATUS_BUSERR (1 << 0) 78472246da4SFelipe Balbi #define DEPEVT_STATUS_SHORT (1 << 1) 78572246da4SFelipe Balbi #define DEPEVT_STATUS_IOC (1 << 2) 78672246da4SFelipe Balbi #define DEPEVT_STATUS_LST (1 << 3) 787dc137f01SFelipe Balbi 788879631aaSFelipe Balbi /* Stream event only */ 789879631aaSFelipe Balbi #define DEPEVT_STREAMEVT_FOUND 1 790879631aaSFelipe Balbi #define DEPEVT_STREAMEVT_NOTFOUND 2 791879631aaSFelipe Balbi 792dc137f01SFelipe Balbi /* Control-only Status */ 793dc137f01SFelipe Balbi #define DEPEVT_STATUS_CONTROL_DATA 1 794dc137f01SFelipe Balbi #define DEPEVT_STATUS_CONTROL_STATUS 2 795dc137f01SFelipe Balbi 79672246da4SFelipe Balbi u32 parameters:16; 79772246da4SFelipe Balbi } __packed; 79872246da4SFelipe Balbi 79972246da4SFelipe Balbi /** 80072246da4SFelipe Balbi * struct dwc3_event_devt - Device Events 80172246da4SFelipe Balbi * @one_bit: indicates this is a non-endpoint event (not used) 80272246da4SFelipe Balbi * @device_event: indicates it's a device event. Should read as 0x00 80372246da4SFelipe Balbi * @type: indicates the type of device event. 80472246da4SFelipe Balbi * 0 - DisconnEvt 80572246da4SFelipe Balbi * 1 - USBRst 80672246da4SFelipe Balbi * 2 - ConnectDone 80772246da4SFelipe Balbi * 3 - ULStChng 80872246da4SFelipe Balbi * 4 - WkUpEvt 80972246da4SFelipe Balbi * 5 - Reserved 81072246da4SFelipe Balbi * 6 - EOPF 81172246da4SFelipe Balbi * 7 - SOF 81272246da4SFelipe Balbi * 8 - Reserved 81372246da4SFelipe Balbi * 9 - ErrticErr 81472246da4SFelipe Balbi * 10 - CmdCmplt 81572246da4SFelipe Balbi * 11 - EvntOverflow 81672246da4SFelipe Balbi * 12 - VndrDevTstRcved 81772246da4SFelipe Balbi * @reserved15_12: Reserved, not used 81872246da4SFelipe Balbi * @event_info: Information about this event 81906f9b6e5SHuang Rui * @reserved31_25: Reserved, not used 82072246da4SFelipe Balbi */ 82172246da4SFelipe Balbi struct dwc3_event_devt { 82272246da4SFelipe Balbi u32 one_bit:1; 82372246da4SFelipe Balbi u32 device_event:7; 82472246da4SFelipe Balbi u32 type:4; 82572246da4SFelipe Balbi u32 reserved15_12:4; 82606f9b6e5SHuang Rui u32 event_info:9; 82706f9b6e5SHuang Rui u32 reserved31_25:7; 82872246da4SFelipe Balbi } __packed; 82972246da4SFelipe Balbi 83072246da4SFelipe Balbi /** 83172246da4SFelipe Balbi * struct dwc3_event_gevt - Other Core Events 83272246da4SFelipe Balbi * @one_bit: indicates this is a non-endpoint event (not used) 83372246da4SFelipe Balbi * @device_event: indicates it's (0x03) Carkit or (0x04) I2C event. 83472246da4SFelipe Balbi * @phy_port_number: self-explanatory 83572246da4SFelipe Balbi * @reserved31_12: Reserved, not used. 83672246da4SFelipe Balbi */ 83772246da4SFelipe Balbi struct dwc3_event_gevt { 83872246da4SFelipe Balbi u32 one_bit:1; 83972246da4SFelipe Balbi u32 device_event:7; 84072246da4SFelipe Balbi u32 phy_port_number:4; 84172246da4SFelipe Balbi u32 reserved31_12:20; 84272246da4SFelipe Balbi } __packed; 84372246da4SFelipe Balbi 84472246da4SFelipe Balbi /** 84572246da4SFelipe Balbi * union dwc3_event - representation of Event Buffer contents 84672246da4SFelipe Balbi * @raw: raw 32-bit event 84772246da4SFelipe Balbi * @type: the type of the event 84872246da4SFelipe Balbi * @depevt: Device Endpoint Event 84972246da4SFelipe Balbi * @devt: Device Event 85072246da4SFelipe Balbi * @gevt: Global Event 85172246da4SFelipe Balbi */ 85272246da4SFelipe Balbi union dwc3_event { 85372246da4SFelipe Balbi u32 raw; 85472246da4SFelipe Balbi struct dwc3_event_type type; 85572246da4SFelipe Balbi struct dwc3_event_depevt depevt; 85672246da4SFelipe Balbi struct dwc3_event_devt devt; 85772246da4SFelipe Balbi struct dwc3_event_gevt gevt; 85872246da4SFelipe Balbi }; 85972246da4SFelipe Balbi 86072246da4SFelipe Balbi /* 86172246da4SFelipe Balbi * DWC3 Features to be used as Driver Data 86272246da4SFelipe Balbi */ 86372246da4SFelipe Balbi 86472246da4SFelipe Balbi #define DWC3_HAS_PERIPHERAL BIT(0) 86572246da4SFelipe Balbi #define DWC3_HAS_XHCI BIT(1) 86672246da4SFelipe Balbi #define DWC3_HAS_OTG BIT(3) 86772246da4SFelipe Balbi 868d07e8819SFelipe Balbi /* prototypes */ 8693140e8cbSSebastian Andrzej Siewior void dwc3_set_mode(struct dwc3 *dwc, u32 mode); 870457e84b6SFelipe Balbi int dwc3_gadget_resize_tx_fifos(struct dwc3 *dwc); 8713140e8cbSSebastian Andrzej Siewior 872388e5c51SVivek Gautam #if IS_ENABLED(CONFIG_USB_DWC3_HOST) || IS_ENABLED(CONFIG_USB_DWC3_DUAL_ROLE) 873d07e8819SFelipe Balbi int dwc3_host_init(struct dwc3 *dwc); 874d07e8819SFelipe Balbi void dwc3_host_exit(struct dwc3 *dwc); 875388e5c51SVivek Gautam #else 876388e5c51SVivek Gautam static inline int dwc3_host_init(struct dwc3 *dwc) 877388e5c51SVivek Gautam { return 0; } 878388e5c51SVivek Gautam static inline void dwc3_host_exit(struct dwc3 *dwc) 879388e5c51SVivek Gautam { } 880388e5c51SVivek Gautam #endif 881d07e8819SFelipe Balbi 882388e5c51SVivek Gautam #if IS_ENABLED(CONFIG_USB_DWC3_GADGET) || IS_ENABLED(CONFIG_USB_DWC3_DUAL_ROLE) 883f80b45e7SFelipe Balbi int dwc3_gadget_init(struct dwc3 *dwc); 884f80b45e7SFelipe Balbi void dwc3_gadget_exit(struct dwc3 *dwc); 885388e5c51SVivek Gautam #else 886388e5c51SVivek Gautam static inline int dwc3_gadget_init(struct dwc3 *dwc) 887388e5c51SVivek Gautam { return 0; } 888388e5c51SVivek Gautam static inline void dwc3_gadget_exit(struct dwc3 *dwc) 889388e5c51SVivek Gautam { } 890388e5c51SVivek Gautam #endif 891f80b45e7SFelipe Balbi 8927415f17cSFelipe Balbi /* power management interface */ 8937415f17cSFelipe Balbi #if !IS_ENABLED(CONFIG_USB_DWC3_HOST) 8947415f17cSFelipe Balbi int dwc3_gadget_prepare(struct dwc3 *dwc); 8957415f17cSFelipe Balbi void dwc3_gadget_complete(struct dwc3 *dwc); 8967415f17cSFelipe Balbi int dwc3_gadget_suspend(struct dwc3 *dwc); 8977415f17cSFelipe Balbi int dwc3_gadget_resume(struct dwc3 *dwc); 8987415f17cSFelipe Balbi #else 8997415f17cSFelipe Balbi static inline int dwc3_gadget_prepare(struct dwc3 *dwc) 9007415f17cSFelipe Balbi { 9017415f17cSFelipe Balbi return 0; 9027415f17cSFelipe Balbi } 9037415f17cSFelipe Balbi 9047415f17cSFelipe Balbi static inline void dwc3_gadget_complete(struct dwc3 *dwc) 9057415f17cSFelipe Balbi { 9067415f17cSFelipe Balbi } 9077415f17cSFelipe Balbi 9087415f17cSFelipe Balbi static inline int dwc3_gadget_suspend(struct dwc3 *dwc) 9097415f17cSFelipe Balbi { 9107415f17cSFelipe Balbi return 0; 9117415f17cSFelipe Balbi } 9127415f17cSFelipe Balbi 9137415f17cSFelipe Balbi static inline int dwc3_gadget_resume(struct dwc3 *dwc) 9147415f17cSFelipe Balbi { 9157415f17cSFelipe Balbi return 0; 9167415f17cSFelipe Balbi } 9177415f17cSFelipe Balbi #endif /* !IS_ENABLED(CONFIG_USB_DWC3_HOST) */ 9187415f17cSFelipe Balbi 91972246da4SFelipe Balbi #endif /* __DRIVERS_USB_DWC3_CORE_H */ 920