172246da4SFelipe Balbi /** 272246da4SFelipe Balbi * core.h - DesignWare USB3 DRD Core Header 372246da4SFelipe Balbi * 472246da4SFelipe Balbi * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com 572246da4SFelipe Balbi * 672246da4SFelipe Balbi * Authors: Felipe Balbi <balbi@ti.com>, 772246da4SFelipe Balbi * Sebastian Andrzej Siewior <bigeasy@linutronix.de> 872246da4SFelipe Balbi * 95945f789SFelipe Balbi * This program is free software: you can redistribute it and/or modify 105945f789SFelipe Balbi * it under the terms of the GNU General Public License version 2 of 115945f789SFelipe Balbi * the License as published by the Free Software Foundation. 1272246da4SFelipe Balbi * 135945f789SFelipe Balbi * This program is distributed in the hope that it will be useful, 145945f789SFelipe Balbi * but WITHOUT ANY WARRANTY; without even the implied warranty of 155945f789SFelipe Balbi * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 165945f789SFelipe Balbi * GNU General Public License for more details. 1772246da4SFelipe Balbi */ 1872246da4SFelipe Balbi 1972246da4SFelipe Balbi #ifndef __DRIVERS_USB_DWC3_CORE_H 2072246da4SFelipe Balbi #define __DRIVERS_USB_DWC3_CORE_H 2172246da4SFelipe Balbi 2272246da4SFelipe Balbi #include <linux/device.h> 2372246da4SFelipe Balbi #include <linux/spinlock.h> 24d07e8819SFelipe Balbi #include <linux/ioport.h> 2572246da4SFelipe Balbi #include <linux/list.h> 2672246da4SFelipe Balbi #include <linux/dma-mapping.h> 2772246da4SFelipe Balbi #include <linux/mm.h> 2872246da4SFelipe Balbi #include <linux/debugfs.h> 2972246da4SFelipe Balbi 3072246da4SFelipe Balbi #include <linux/usb/ch9.h> 3172246da4SFelipe Balbi #include <linux/usb/gadget.h> 32a45c82b8SRuchika Kharwar #include <linux/usb/otg.h> 3372246da4SFelipe Balbi 3457303488SKishon Vijay Abraham I #include <linux/phy/phy.h> 3557303488SKishon Vijay Abraham I 3672246da4SFelipe Balbi /* Global constants */ 373ef35fafSFelipe Balbi #define DWC3_EP0_BOUNCE_SIZE 512 3872246da4SFelipe Balbi #define DWC3_ENDPOINTS_NUM 32 3951249dcaSIdo Shayevitz #define DWC3_XHCI_RESOURCES_NUM 2 4072246da4SFelipe Balbi 410ffcaf37SFelipe Balbi #define DWC3_SCRATCHBUF_SIZE 4096 /* each buffer is assumed to be 4KiB */ 425da93478SFelipe Balbi #define DWC3_EVENT_SIZE 4 /* bytes */ 435da93478SFelipe Balbi #define DWC3_EVENT_MAX_NUM 64 /* 2 events/endpoint */ 445da93478SFelipe Balbi #define DWC3_EVENT_BUFFERS_SIZE (DWC3_EVENT_SIZE * DWC3_EVENT_MAX_NUM) 4572246da4SFelipe Balbi #define DWC3_EVENT_TYPE_MASK 0xfe 4672246da4SFelipe Balbi 4772246da4SFelipe Balbi #define DWC3_EVENT_TYPE_DEV 0 4872246da4SFelipe Balbi #define DWC3_EVENT_TYPE_CARKIT 3 4972246da4SFelipe Balbi #define DWC3_EVENT_TYPE_I2C 4 5072246da4SFelipe Balbi 5172246da4SFelipe Balbi #define DWC3_DEVICE_EVENT_DISCONNECT 0 5272246da4SFelipe Balbi #define DWC3_DEVICE_EVENT_RESET 1 5372246da4SFelipe Balbi #define DWC3_DEVICE_EVENT_CONNECT_DONE 2 5472246da4SFelipe Balbi #define DWC3_DEVICE_EVENT_LINK_STATUS_CHANGE 3 5572246da4SFelipe Balbi #define DWC3_DEVICE_EVENT_WAKEUP 4 562c61a8efSPaul Zimmerman #define DWC3_DEVICE_EVENT_HIBER_REQ 5 5772246da4SFelipe Balbi #define DWC3_DEVICE_EVENT_EOPF 6 5872246da4SFelipe Balbi #define DWC3_DEVICE_EVENT_SOF 7 5972246da4SFelipe Balbi #define DWC3_DEVICE_EVENT_ERRATIC_ERROR 9 6072246da4SFelipe Balbi #define DWC3_DEVICE_EVENT_CMD_CMPL 10 6172246da4SFelipe Balbi #define DWC3_DEVICE_EVENT_OVERFLOW 11 6272246da4SFelipe Balbi 6372246da4SFelipe Balbi #define DWC3_GEVNTCOUNT_MASK 0xfffc 6472246da4SFelipe Balbi #define DWC3_GSNPSID_MASK 0xffff0000 6572246da4SFelipe Balbi #define DWC3_GSNPSREV_MASK 0xffff 6672246da4SFelipe Balbi 6751249dcaSIdo Shayevitz /* DWC3 registers memory space boundries */ 6851249dcaSIdo Shayevitz #define DWC3_XHCI_REGS_START 0x0 6951249dcaSIdo Shayevitz #define DWC3_XHCI_REGS_END 0x7fff 7051249dcaSIdo Shayevitz #define DWC3_GLOBALS_REGS_START 0xc100 7151249dcaSIdo Shayevitz #define DWC3_GLOBALS_REGS_END 0xc6ff 7251249dcaSIdo Shayevitz #define DWC3_DEVICE_REGS_START 0xc700 7351249dcaSIdo Shayevitz #define DWC3_DEVICE_REGS_END 0xcbff 7451249dcaSIdo Shayevitz #define DWC3_OTG_REGS_START 0xcc00 7551249dcaSIdo Shayevitz #define DWC3_OTG_REGS_END 0xccff 7651249dcaSIdo Shayevitz 7772246da4SFelipe Balbi /* Global Registers */ 7872246da4SFelipe Balbi #define DWC3_GSBUSCFG0 0xc100 7972246da4SFelipe Balbi #define DWC3_GSBUSCFG1 0xc104 8072246da4SFelipe Balbi #define DWC3_GTXTHRCFG 0xc108 8172246da4SFelipe Balbi #define DWC3_GRXTHRCFG 0xc10c 8272246da4SFelipe Balbi #define DWC3_GCTL 0xc110 8372246da4SFelipe Balbi #define DWC3_GEVTEN 0xc114 8472246da4SFelipe Balbi #define DWC3_GSTS 0xc118 8572246da4SFelipe Balbi #define DWC3_GSNPSID 0xc120 8672246da4SFelipe Balbi #define DWC3_GGPIO 0xc124 8772246da4SFelipe Balbi #define DWC3_GUID 0xc128 8872246da4SFelipe Balbi #define DWC3_GUCTL 0xc12c 8972246da4SFelipe Balbi #define DWC3_GBUSERRADDR0 0xc130 9072246da4SFelipe Balbi #define DWC3_GBUSERRADDR1 0xc134 9172246da4SFelipe Balbi #define DWC3_GPRTBIMAP0 0xc138 9272246da4SFelipe Balbi #define DWC3_GPRTBIMAP1 0xc13c 9372246da4SFelipe Balbi #define DWC3_GHWPARAMS0 0xc140 9472246da4SFelipe Balbi #define DWC3_GHWPARAMS1 0xc144 9572246da4SFelipe Balbi #define DWC3_GHWPARAMS2 0xc148 9672246da4SFelipe Balbi #define DWC3_GHWPARAMS3 0xc14c 9772246da4SFelipe Balbi #define DWC3_GHWPARAMS4 0xc150 9872246da4SFelipe Balbi #define DWC3_GHWPARAMS5 0xc154 9972246da4SFelipe Balbi #define DWC3_GHWPARAMS6 0xc158 10072246da4SFelipe Balbi #define DWC3_GHWPARAMS7 0xc15c 10172246da4SFelipe Balbi #define DWC3_GDBGFIFOSPACE 0xc160 10272246da4SFelipe Balbi #define DWC3_GDBGLTSSM 0xc164 10372246da4SFelipe Balbi #define DWC3_GPRTBIMAP_HS0 0xc180 10472246da4SFelipe Balbi #define DWC3_GPRTBIMAP_HS1 0xc184 10572246da4SFelipe Balbi #define DWC3_GPRTBIMAP_FS0 0xc188 10672246da4SFelipe Balbi #define DWC3_GPRTBIMAP_FS1 0xc18c 10772246da4SFelipe Balbi 10872246da4SFelipe Balbi #define DWC3_GUSB2PHYCFG(n) (0xc200 + (n * 0x04)) 10972246da4SFelipe Balbi #define DWC3_GUSB2I2CCTL(n) (0xc240 + (n * 0x04)) 11072246da4SFelipe Balbi 11172246da4SFelipe Balbi #define DWC3_GUSB2PHYACC(n) (0xc280 + (n * 0x04)) 11272246da4SFelipe Balbi 11372246da4SFelipe Balbi #define DWC3_GUSB3PIPECTL(n) (0xc2c0 + (n * 0x04)) 11472246da4SFelipe Balbi 11572246da4SFelipe Balbi #define DWC3_GTXFIFOSIZ(n) (0xc300 + (n * 0x04)) 11672246da4SFelipe Balbi #define DWC3_GRXFIFOSIZ(n) (0xc380 + (n * 0x04)) 11772246da4SFelipe Balbi 11872246da4SFelipe Balbi #define DWC3_GEVNTADRLO(n) (0xc400 + (n * 0x10)) 11972246da4SFelipe Balbi #define DWC3_GEVNTADRHI(n) (0xc404 + (n * 0x10)) 12072246da4SFelipe Balbi #define DWC3_GEVNTSIZ(n) (0xc408 + (n * 0x10)) 12172246da4SFelipe Balbi #define DWC3_GEVNTCOUNT(n) (0xc40c + (n * 0x10)) 12272246da4SFelipe Balbi 12372246da4SFelipe Balbi #define DWC3_GHWPARAMS8 0xc600 12472246da4SFelipe Balbi 12572246da4SFelipe Balbi /* Device Registers */ 12672246da4SFelipe Balbi #define DWC3_DCFG 0xc700 12772246da4SFelipe Balbi #define DWC3_DCTL 0xc704 12872246da4SFelipe Balbi #define DWC3_DEVTEN 0xc708 12972246da4SFelipe Balbi #define DWC3_DSTS 0xc70c 13072246da4SFelipe Balbi #define DWC3_DGCMDPAR 0xc710 13172246da4SFelipe Balbi #define DWC3_DGCMD 0xc714 13272246da4SFelipe Balbi #define DWC3_DALEPENA 0xc720 13372246da4SFelipe Balbi #define DWC3_DEPCMDPAR2(n) (0xc800 + (n * 0x10)) 13472246da4SFelipe Balbi #define DWC3_DEPCMDPAR1(n) (0xc804 + (n * 0x10)) 13572246da4SFelipe Balbi #define DWC3_DEPCMDPAR0(n) (0xc808 + (n * 0x10)) 13672246da4SFelipe Balbi #define DWC3_DEPCMD(n) (0xc80c + (n * 0x10)) 13772246da4SFelipe Balbi 13872246da4SFelipe Balbi /* OTG Registers */ 13972246da4SFelipe Balbi #define DWC3_OCFG 0xcc00 14072246da4SFelipe Balbi #define DWC3_OCTL 0xcc04 141d4436c3aSGeorge Cherian #define DWC3_OEVT 0xcc08 142d4436c3aSGeorge Cherian #define DWC3_OEVTEN 0xcc0C 143d4436c3aSGeorge Cherian #define DWC3_OSTS 0xcc10 14472246da4SFelipe Balbi 14572246da4SFelipe Balbi /* Bit fields */ 14672246da4SFelipe Balbi 14772246da4SFelipe Balbi /* Global Configuration Register */ 1481d046793SPaul Zimmerman #define DWC3_GCTL_PWRDNSCALE(n) ((n) << 19) 149f4aadbe4SFelipe Balbi #define DWC3_GCTL_U2RSTECN (1 << 16) 1501d046793SPaul Zimmerman #define DWC3_GCTL_RAMCLKSEL(x) (((x) & DWC3_GCTL_CLK_MASK) << 6) 15172246da4SFelipe Balbi #define DWC3_GCTL_CLK_BUS (0) 15272246da4SFelipe Balbi #define DWC3_GCTL_CLK_PIPE (1) 15372246da4SFelipe Balbi #define DWC3_GCTL_CLK_PIPEHALF (2) 15472246da4SFelipe Balbi #define DWC3_GCTL_CLK_MASK (3) 15572246da4SFelipe Balbi 1560b9fe32dSFelipe Balbi #define DWC3_GCTL_PRTCAP(n) (((n) & (3 << 12)) >> 12) 1571d046793SPaul Zimmerman #define DWC3_GCTL_PRTCAPDIR(n) ((n) << 12) 15872246da4SFelipe Balbi #define DWC3_GCTL_PRTCAP_HOST 1 15972246da4SFelipe Balbi #define DWC3_GCTL_PRTCAP_DEVICE 2 16072246da4SFelipe Balbi #define DWC3_GCTL_PRTCAP_OTG 3 16172246da4SFelipe Balbi 16272246da4SFelipe Balbi #define DWC3_GCTL_CORESOFTRESET (1 << 11) 163183ca111SFelipe Balbi #define DWC3_GCTL_SOFITPSYNC (1 << 10) 1641d046793SPaul Zimmerman #define DWC3_GCTL_SCALEDOWN(n) ((n) << 4) 1653e87c42aSPaul Zimmerman #define DWC3_GCTL_SCALEDOWN_MASK DWC3_GCTL_SCALEDOWN(3) 16672246da4SFelipe Balbi #define DWC3_GCTL_DISSCRAMBLE (1 << 3) 1672c61a8efSPaul Zimmerman #define DWC3_GCTL_GBLHIBERNATIONEN (1 << 1) 168aabb7075SFelipe Balbi #define DWC3_GCTL_DSBLCLKGTNG (1 << 0) 16972246da4SFelipe Balbi 17072246da4SFelipe Balbi /* Global USB2 PHY Configuration Register */ 17172246da4SFelipe Balbi #define DWC3_GUSB2PHYCFG_PHYSOFTRST (1 << 31) 17272246da4SFelipe Balbi #define DWC3_GUSB2PHYCFG_SUSPHY (1 << 6) 17372246da4SFelipe Balbi 17472246da4SFelipe Balbi /* Global USB3 PIPE Control Register */ 17572246da4SFelipe Balbi #define DWC3_GUSB3PIPECTL_PHYSOFTRST (1 << 31) 17672246da4SFelipe Balbi #define DWC3_GUSB3PIPECTL_SUSPHY (1 << 17) 17772246da4SFelipe Balbi 178457e84b6SFelipe Balbi /* Global TX Fifo Size Register */ 179457e84b6SFelipe Balbi #define DWC3_GTXFIFOSIZ_TXFDEF(n) ((n) & 0xffff) 180457e84b6SFelipe Balbi #define DWC3_GTXFIFOSIZ_TXFSTADDR(n) ((n) & 0xffff0000) 181457e84b6SFelipe Balbi 18268d6a01bSFelipe Balbi /* Global Event Size Registers */ 18368d6a01bSFelipe Balbi #define DWC3_GEVNTSIZ_INTMASK (1 << 31) 18468d6a01bSFelipe Balbi #define DWC3_GEVNTSIZ_SIZE(n) ((n) & 0xffff) 18568d6a01bSFelipe Balbi 186aabb7075SFelipe Balbi /* Global HWPARAMS1 Register */ 1871d046793SPaul Zimmerman #define DWC3_GHWPARAMS1_EN_PWROPT(n) (((n) & (3 << 24)) >> 24) 188aabb7075SFelipe Balbi #define DWC3_GHWPARAMS1_EN_PWROPT_NO 0 189aabb7075SFelipe Balbi #define DWC3_GHWPARAMS1_EN_PWROPT_CLK 1 1902c61a8efSPaul Zimmerman #define DWC3_GHWPARAMS1_EN_PWROPT_HIB 2 1912c61a8efSPaul Zimmerman #define DWC3_GHWPARAMS1_PWROPT(n) ((n) << 24) 1922c61a8efSPaul Zimmerman #define DWC3_GHWPARAMS1_PWROPT_MASK DWC3_GHWPARAMS1_PWROPT(3) 1932c61a8efSPaul Zimmerman 1940e1e5c47SPaul Zimmerman /* Global HWPARAMS3 Register */ 1950e1e5c47SPaul Zimmerman #define DWC3_GHWPARAMS3_SSPHY_IFC(n) ((n) & 3) 1960e1e5c47SPaul Zimmerman #define DWC3_GHWPARAMS3_SSPHY_IFC_DIS 0 1970e1e5c47SPaul Zimmerman #define DWC3_GHWPARAMS3_SSPHY_IFC_ENA 1 1980e1e5c47SPaul Zimmerman #define DWC3_GHWPARAMS3_HSPHY_IFC(n) (((n) & (3 << 2)) >> 2) 1990e1e5c47SPaul Zimmerman #define DWC3_GHWPARAMS3_HSPHY_IFC_DIS 0 2000e1e5c47SPaul Zimmerman #define DWC3_GHWPARAMS3_HSPHY_IFC_UTMI 1 2010e1e5c47SPaul Zimmerman #define DWC3_GHWPARAMS3_HSPHY_IFC_ULPI 2 2020e1e5c47SPaul Zimmerman #define DWC3_GHWPARAMS3_HSPHY_IFC_UTMI_ULPI 3 2030e1e5c47SPaul Zimmerman #define DWC3_GHWPARAMS3_FSPHY_IFC(n) (((n) & (3 << 4)) >> 4) 2040e1e5c47SPaul Zimmerman #define DWC3_GHWPARAMS3_FSPHY_IFC_DIS 0 2050e1e5c47SPaul Zimmerman #define DWC3_GHWPARAMS3_FSPHY_IFC_ENA 1 2060e1e5c47SPaul Zimmerman 2072c61a8efSPaul Zimmerman /* Global HWPARAMS4 Register */ 2082c61a8efSPaul Zimmerman #define DWC3_GHWPARAMS4_HIBER_SCRATCHBUFS(n) (((n) & (0x0f << 13)) >> 13) 2092c61a8efSPaul Zimmerman #define DWC3_MAX_HIBER_SCRATCHBUFS 15 210aabb7075SFelipe Balbi 21172246da4SFelipe Balbi /* Device Configuration Register */ 21272246da4SFelipe Balbi #define DWC3_DCFG_DEVADDR(addr) ((addr) << 3) 21372246da4SFelipe Balbi #define DWC3_DCFG_DEVADDR_MASK DWC3_DCFG_DEVADDR(0x7f) 21472246da4SFelipe Balbi 21572246da4SFelipe Balbi #define DWC3_DCFG_SPEED_MASK (7 << 0) 21672246da4SFelipe Balbi #define DWC3_DCFG_SUPERSPEED (4 << 0) 21772246da4SFelipe Balbi #define DWC3_DCFG_HIGHSPEED (0 << 0) 21872246da4SFelipe Balbi #define DWC3_DCFG_FULLSPEED2 (1 << 0) 21972246da4SFelipe Balbi #define DWC3_DCFG_LOWSPEED (2 << 0) 22072246da4SFelipe Balbi #define DWC3_DCFG_FULLSPEED1 (3 << 0) 22172246da4SFelipe Balbi 2222c61a8efSPaul Zimmerman #define DWC3_DCFG_LPM_CAP (1 << 22) 2232c61a8efSPaul Zimmerman 22472246da4SFelipe Balbi /* Device Control Register */ 22572246da4SFelipe Balbi #define DWC3_DCTL_RUN_STOP (1 << 31) 22672246da4SFelipe Balbi #define DWC3_DCTL_CSFTRST (1 << 30) 22772246da4SFelipe Balbi #define DWC3_DCTL_LSFTRST (1 << 29) 22872246da4SFelipe Balbi 22972246da4SFelipe Balbi #define DWC3_DCTL_HIRD_THRES_MASK (0x1f << 24) 2307e39b817SPratyush Anand #define DWC3_DCTL_HIRD_THRES(n) ((n) << 24) 23172246da4SFelipe Balbi 23272246da4SFelipe Balbi #define DWC3_DCTL_APPL1RES (1 << 23) 23372246da4SFelipe Balbi 2342c61a8efSPaul Zimmerman /* These apply for core versions 1.87a and earlier */ 2358db7ed15SFelipe Balbi #define DWC3_DCTL_TRGTULST_MASK (0x0f << 17) 2368db7ed15SFelipe Balbi #define DWC3_DCTL_TRGTULST(n) ((n) << 17) 2378db7ed15SFelipe Balbi #define DWC3_DCTL_TRGTULST_U2 (DWC3_DCTL_TRGTULST(2)) 2388db7ed15SFelipe Balbi #define DWC3_DCTL_TRGTULST_U3 (DWC3_DCTL_TRGTULST(3)) 2398db7ed15SFelipe Balbi #define DWC3_DCTL_TRGTULST_SS_DIS (DWC3_DCTL_TRGTULST(4)) 2408db7ed15SFelipe Balbi #define DWC3_DCTL_TRGTULST_RX_DET (DWC3_DCTL_TRGTULST(5)) 2418db7ed15SFelipe Balbi #define DWC3_DCTL_TRGTULST_SS_INACT (DWC3_DCTL_TRGTULST(6)) 2428db7ed15SFelipe Balbi 2432c61a8efSPaul Zimmerman /* These apply for core versions 1.94a and later */ 2442c61a8efSPaul Zimmerman #define DWC3_DCTL_KEEP_CONNECT (1 << 19) 2452c61a8efSPaul Zimmerman #define DWC3_DCTL_L1_HIBER_EN (1 << 18) 2462c61a8efSPaul Zimmerman #define DWC3_DCTL_CRS (1 << 17) 2472c61a8efSPaul Zimmerman #define DWC3_DCTL_CSS (1 << 16) 2482c61a8efSPaul Zimmerman 24972246da4SFelipe Balbi #define DWC3_DCTL_INITU2ENA (1 << 12) 25072246da4SFelipe Balbi #define DWC3_DCTL_ACCEPTU2ENA (1 << 11) 25172246da4SFelipe Balbi #define DWC3_DCTL_INITU1ENA (1 << 10) 25272246da4SFelipe Balbi #define DWC3_DCTL_ACCEPTU1ENA (1 << 9) 25372246da4SFelipe Balbi #define DWC3_DCTL_TSTCTRL_MASK (0xf << 1) 25472246da4SFelipe Balbi 25572246da4SFelipe Balbi #define DWC3_DCTL_ULSTCHNGREQ_MASK (0x0f << 5) 25672246da4SFelipe Balbi #define DWC3_DCTL_ULSTCHNGREQ(n) (((n) << 5) & DWC3_DCTL_ULSTCHNGREQ_MASK) 25772246da4SFelipe Balbi 25872246da4SFelipe Balbi #define DWC3_DCTL_ULSTCHNG_NO_ACTION (DWC3_DCTL_ULSTCHNGREQ(0)) 25972246da4SFelipe Balbi #define DWC3_DCTL_ULSTCHNG_SS_DISABLED (DWC3_DCTL_ULSTCHNGREQ(4)) 26072246da4SFelipe Balbi #define DWC3_DCTL_ULSTCHNG_RX_DETECT (DWC3_DCTL_ULSTCHNGREQ(5)) 26172246da4SFelipe Balbi #define DWC3_DCTL_ULSTCHNG_SS_INACTIVE (DWC3_DCTL_ULSTCHNGREQ(6)) 26272246da4SFelipe Balbi #define DWC3_DCTL_ULSTCHNG_RECOVERY (DWC3_DCTL_ULSTCHNGREQ(8)) 26372246da4SFelipe Balbi #define DWC3_DCTL_ULSTCHNG_COMPLIANCE (DWC3_DCTL_ULSTCHNGREQ(10)) 26472246da4SFelipe Balbi #define DWC3_DCTL_ULSTCHNG_LOOPBACK (DWC3_DCTL_ULSTCHNGREQ(11)) 26572246da4SFelipe Balbi 26672246da4SFelipe Balbi /* Device Event Enable Register */ 26772246da4SFelipe Balbi #define DWC3_DEVTEN_VNDRDEVTSTRCVEDEN (1 << 12) 26872246da4SFelipe Balbi #define DWC3_DEVTEN_EVNTOVERFLOWEN (1 << 11) 26972246da4SFelipe Balbi #define DWC3_DEVTEN_CMDCMPLTEN (1 << 10) 27072246da4SFelipe Balbi #define DWC3_DEVTEN_ERRTICERREN (1 << 9) 27172246da4SFelipe Balbi #define DWC3_DEVTEN_SOFEN (1 << 7) 27272246da4SFelipe Balbi #define DWC3_DEVTEN_EOPFEN (1 << 6) 2732c61a8efSPaul Zimmerman #define DWC3_DEVTEN_HIBERNATIONREQEVTEN (1 << 5) 27472246da4SFelipe Balbi #define DWC3_DEVTEN_WKUPEVTEN (1 << 4) 27572246da4SFelipe Balbi #define DWC3_DEVTEN_ULSTCNGEN (1 << 3) 27672246da4SFelipe Balbi #define DWC3_DEVTEN_CONNECTDONEEN (1 << 2) 27772246da4SFelipe Balbi #define DWC3_DEVTEN_USBRSTEN (1 << 1) 27872246da4SFelipe Balbi #define DWC3_DEVTEN_DISCONNEVTEN (1 << 0) 27972246da4SFelipe Balbi 28072246da4SFelipe Balbi /* Device Status Register */ 2812c61a8efSPaul Zimmerman #define DWC3_DSTS_DCNRD (1 << 29) 2822c61a8efSPaul Zimmerman 2832c61a8efSPaul Zimmerman /* This applies for core versions 1.87a and earlier */ 28472246da4SFelipe Balbi #define DWC3_DSTS_PWRUPREQ (1 << 24) 2852c61a8efSPaul Zimmerman 2862c61a8efSPaul Zimmerman /* These apply for core versions 1.94a and later */ 2872c61a8efSPaul Zimmerman #define DWC3_DSTS_RSS (1 << 25) 2882c61a8efSPaul Zimmerman #define DWC3_DSTS_SSS (1 << 24) 2892c61a8efSPaul Zimmerman 29072246da4SFelipe Balbi #define DWC3_DSTS_COREIDLE (1 << 23) 29172246da4SFelipe Balbi #define DWC3_DSTS_DEVCTRLHLT (1 << 22) 29272246da4SFelipe Balbi 29372246da4SFelipe Balbi #define DWC3_DSTS_USBLNKST_MASK (0x0f << 18) 29472246da4SFelipe Balbi #define DWC3_DSTS_USBLNKST(n) (((n) & DWC3_DSTS_USBLNKST_MASK) >> 18) 29572246da4SFelipe Balbi 29672246da4SFelipe Balbi #define DWC3_DSTS_RXFIFOEMPTY (1 << 17) 29772246da4SFelipe Balbi 298d05b8182SPratyush Anand #define DWC3_DSTS_SOFFN_MASK (0x3fff << 3) 29972246da4SFelipe Balbi #define DWC3_DSTS_SOFFN(n) (((n) & DWC3_DSTS_SOFFN_MASK) >> 3) 30072246da4SFelipe Balbi 30172246da4SFelipe Balbi #define DWC3_DSTS_CONNECTSPD (7 << 0) 30272246da4SFelipe Balbi 30372246da4SFelipe Balbi #define DWC3_DSTS_SUPERSPEED (4 << 0) 30472246da4SFelipe Balbi #define DWC3_DSTS_HIGHSPEED (0 << 0) 30572246da4SFelipe Balbi #define DWC3_DSTS_FULLSPEED2 (1 << 0) 30672246da4SFelipe Balbi #define DWC3_DSTS_LOWSPEED (2 << 0) 30772246da4SFelipe Balbi #define DWC3_DSTS_FULLSPEED1 (3 << 0) 30872246da4SFelipe Balbi 30972246da4SFelipe Balbi /* Device Generic Command Register */ 31072246da4SFelipe Balbi #define DWC3_DGCMD_SET_LMP 0x01 31172246da4SFelipe Balbi #define DWC3_DGCMD_SET_PERIODIC_PAR 0x02 31272246da4SFelipe Balbi #define DWC3_DGCMD_XMIT_FUNCTION 0x03 3132c61a8efSPaul Zimmerman 3142c61a8efSPaul Zimmerman /* These apply for core versions 1.94a and later */ 3152c61a8efSPaul Zimmerman #define DWC3_DGCMD_SET_SCRATCHPAD_ADDR_LO 0x04 3162c61a8efSPaul Zimmerman #define DWC3_DGCMD_SET_SCRATCHPAD_ADDR_HI 0x05 3172c61a8efSPaul Zimmerman 31872246da4SFelipe Balbi #define DWC3_DGCMD_SELECTED_FIFO_FLUSH 0x09 31972246da4SFelipe Balbi #define DWC3_DGCMD_ALL_FIFO_FLUSH 0x0a 32072246da4SFelipe Balbi #define DWC3_DGCMD_SET_ENDPOINT_NRDY 0x0c 32172246da4SFelipe Balbi #define DWC3_DGCMD_RUN_SOC_BUS_LOOPBACK 0x10 32272246da4SFelipe Balbi 323b09bb642SFelipe Balbi #define DWC3_DGCMD_STATUS(n) (((n) >> 15) & 1) 324b09bb642SFelipe Balbi #define DWC3_DGCMD_CMDACT (1 << 10) 3252c61a8efSPaul Zimmerman #define DWC3_DGCMD_CMDIOC (1 << 8) 3262c61a8efSPaul Zimmerman 3272c61a8efSPaul Zimmerman /* Device Generic Command Parameter Register */ 3282c61a8efSPaul Zimmerman #define DWC3_DGCMDPAR_FORCE_LINKPM_ACCEPT (1 << 0) 3292c61a8efSPaul Zimmerman #define DWC3_DGCMDPAR_FIFO_NUM(n) ((n) << 0) 3302c61a8efSPaul Zimmerman #define DWC3_DGCMDPAR_RX_FIFO (0 << 5) 3312c61a8efSPaul Zimmerman #define DWC3_DGCMDPAR_TX_FIFO (1 << 5) 3322c61a8efSPaul Zimmerman #define DWC3_DGCMDPAR_LOOPBACK_DIS (0 << 0) 3332c61a8efSPaul Zimmerman #define DWC3_DGCMDPAR_LOOPBACK_ENA (1 << 0) 334b09bb642SFelipe Balbi 33572246da4SFelipe Balbi /* Device Endpoint Command Register */ 33672246da4SFelipe Balbi #define DWC3_DEPCMD_PARAM_SHIFT 16 3371d046793SPaul Zimmerman #define DWC3_DEPCMD_PARAM(x) ((x) << DWC3_DEPCMD_PARAM_SHIFT) 3381d046793SPaul Zimmerman #define DWC3_DEPCMD_GET_RSC_IDX(x) (((x) >> DWC3_DEPCMD_PARAM_SHIFT) & 0x7f) 339b09bb642SFelipe Balbi #define DWC3_DEPCMD_STATUS(x) (((x) >> 15) & 1) 34072246da4SFelipe Balbi #define DWC3_DEPCMD_HIPRI_FORCERM (1 << 11) 34172246da4SFelipe Balbi #define DWC3_DEPCMD_CMDACT (1 << 10) 34272246da4SFelipe Balbi #define DWC3_DEPCMD_CMDIOC (1 << 8) 34372246da4SFelipe Balbi 34472246da4SFelipe Balbi #define DWC3_DEPCMD_DEPSTARTCFG (0x09 << 0) 34572246da4SFelipe Balbi #define DWC3_DEPCMD_ENDTRANSFER (0x08 << 0) 34672246da4SFelipe Balbi #define DWC3_DEPCMD_UPDATETRANSFER (0x07 << 0) 34772246da4SFelipe Balbi #define DWC3_DEPCMD_STARTTRANSFER (0x06 << 0) 34872246da4SFelipe Balbi #define DWC3_DEPCMD_CLEARSTALL (0x05 << 0) 34972246da4SFelipe Balbi #define DWC3_DEPCMD_SETSTALL (0x04 << 0) 3502c61a8efSPaul Zimmerman /* This applies for core versions 1.90a and earlier */ 35172246da4SFelipe Balbi #define DWC3_DEPCMD_GETSEQNUMBER (0x03 << 0) 3522c61a8efSPaul Zimmerman /* This applies for core versions 1.94a and later */ 3532c61a8efSPaul Zimmerman #define DWC3_DEPCMD_GETEPSTATE (0x03 << 0) 35472246da4SFelipe Balbi #define DWC3_DEPCMD_SETTRANSFRESOURCE (0x02 << 0) 35572246da4SFelipe Balbi #define DWC3_DEPCMD_SETEPCONFIG (0x01 << 0) 35672246da4SFelipe Balbi 35772246da4SFelipe Balbi /* The EP number goes 0..31 so ep0 is always out and ep1 is always in */ 35872246da4SFelipe Balbi #define DWC3_DALEPENA_EP(n) (1 << n) 35972246da4SFelipe Balbi 36072246da4SFelipe Balbi #define DWC3_DEPCMD_TYPE_CONTROL 0 36172246da4SFelipe Balbi #define DWC3_DEPCMD_TYPE_ISOC 1 36272246da4SFelipe Balbi #define DWC3_DEPCMD_TYPE_BULK 2 36372246da4SFelipe Balbi #define DWC3_DEPCMD_TYPE_INTR 3 36472246da4SFelipe Balbi 36572246da4SFelipe Balbi /* Structures */ 36672246da4SFelipe Balbi 367f6bafc6aSFelipe Balbi struct dwc3_trb; 36872246da4SFelipe Balbi 36972246da4SFelipe Balbi /** 37072246da4SFelipe Balbi * struct dwc3_event_buffer - Software event buffer representation 37172246da4SFelipe Balbi * @buf: _THE_ buffer 37272246da4SFelipe Balbi * @length: size of this buffer 373abed4118SFelipe Balbi * @lpos: event offset 37460d04bbeSFelipe Balbi * @count: cache of last read event count register 375abed4118SFelipe Balbi * @flags: flags related to this event buffer 37672246da4SFelipe Balbi * @dma: dma_addr_t 37772246da4SFelipe Balbi * @dwc: pointer to DWC controller 37872246da4SFelipe Balbi */ 37972246da4SFelipe Balbi struct dwc3_event_buffer { 38072246da4SFelipe Balbi void *buf; 38172246da4SFelipe Balbi unsigned length; 38272246da4SFelipe Balbi unsigned int lpos; 38360d04bbeSFelipe Balbi unsigned int count; 384abed4118SFelipe Balbi unsigned int flags; 385abed4118SFelipe Balbi 386abed4118SFelipe Balbi #define DWC3_EVENT_PENDING BIT(0) 38772246da4SFelipe Balbi 38872246da4SFelipe Balbi dma_addr_t dma; 38972246da4SFelipe Balbi 39072246da4SFelipe Balbi struct dwc3 *dwc; 39172246da4SFelipe Balbi }; 39272246da4SFelipe Balbi 39372246da4SFelipe Balbi #define DWC3_EP_FLAG_STALLED (1 << 0) 39472246da4SFelipe Balbi #define DWC3_EP_FLAG_WEDGED (1 << 1) 39572246da4SFelipe Balbi 39672246da4SFelipe Balbi #define DWC3_EP_DIRECTION_TX true 39772246da4SFelipe Balbi #define DWC3_EP_DIRECTION_RX false 39872246da4SFelipe Balbi 39972246da4SFelipe Balbi #define DWC3_TRB_NUM 32 40072246da4SFelipe Balbi #define DWC3_TRB_MASK (DWC3_TRB_NUM - 1) 40172246da4SFelipe Balbi 40272246da4SFelipe Balbi /** 40372246da4SFelipe Balbi * struct dwc3_ep - device side endpoint representation 40472246da4SFelipe Balbi * @endpoint: usb endpoint 40572246da4SFelipe Balbi * @request_list: list of requests for this endpoint 40672246da4SFelipe Balbi * @req_queued: list of requests on this ep which have TRBs setup 40772246da4SFelipe Balbi * @trb_pool: array of transaction buffers 40872246da4SFelipe Balbi * @trb_pool_dma: dma address of @trb_pool 40972246da4SFelipe Balbi * @free_slot: next slot which is going to be used 41072246da4SFelipe Balbi * @busy_slot: first slot which is owned by HW 41172246da4SFelipe Balbi * @desc: usb_endpoint_descriptor pointer 41272246da4SFelipe Balbi * @dwc: pointer to DWC controller 4134cfcf876SPaul Zimmerman * @saved_state: ep state saved during hibernation 41472246da4SFelipe Balbi * @flags: endpoint flags (wedged, stalled, ...) 41572246da4SFelipe Balbi * @current_trb: index of current used trb 41672246da4SFelipe Balbi * @number: endpoint number (1 - 15) 41772246da4SFelipe Balbi * @type: set to bmAttributes & USB_ENDPOINT_XFERTYPE_MASK 418b4996a86SFelipe Balbi * @resource_index: Resource transfer index 419c75f52fbSHuang Rui * @interval: the interval on which the ISOC transfer is started 42072246da4SFelipe Balbi * @name: a human readable name e.g. ep1out-bulk 42172246da4SFelipe Balbi * @direction: true for TX, false for RX 422879631aaSFelipe Balbi * @stream_capable: true when streams are enabled 42372246da4SFelipe Balbi */ 42472246da4SFelipe Balbi struct dwc3_ep { 42572246da4SFelipe Balbi struct usb_ep endpoint; 42672246da4SFelipe Balbi struct list_head request_list; 42772246da4SFelipe Balbi struct list_head req_queued; 42872246da4SFelipe Balbi 429f6bafc6aSFelipe Balbi struct dwc3_trb *trb_pool; 43072246da4SFelipe Balbi dma_addr_t trb_pool_dma; 43172246da4SFelipe Balbi u32 free_slot; 43272246da4SFelipe Balbi u32 busy_slot; 433c90bfaecSFelipe Balbi const struct usb_ss_ep_comp_descriptor *comp_desc; 43472246da4SFelipe Balbi struct dwc3 *dwc; 43572246da4SFelipe Balbi 4364cfcf876SPaul Zimmerman u32 saved_state; 43772246da4SFelipe Balbi unsigned flags; 43872246da4SFelipe Balbi #define DWC3_EP_ENABLED (1 << 0) 43972246da4SFelipe Balbi #define DWC3_EP_STALL (1 << 1) 44072246da4SFelipe Balbi #define DWC3_EP_WEDGE (1 << 2) 44172246da4SFelipe Balbi #define DWC3_EP_BUSY (1 << 4) 44272246da4SFelipe Balbi #define DWC3_EP_PENDING_REQUEST (1 << 5) 443d6d6ec7bSPratyush Anand #define DWC3_EP_MISSED_ISOC (1 << 6) 44472246da4SFelipe Balbi 445984f66a6SFelipe Balbi /* This last one is specific to EP0 */ 446984f66a6SFelipe Balbi #define DWC3_EP0_DIR_IN (1 << 31) 447984f66a6SFelipe Balbi 44872246da4SFelipe Balbi unsigned current_trb; 44972246da4SFelipe Balbi 45072246da4SFelipe Balbi u8 number; 45172246da4SFelipe Balbi u8 type; 452b4996a86SFelipe Balbi u8 resource_index; 45372246da4SFelipe Balbi u32 interval; 45472246da4SFelipe Balbi 45572246da4SFelipe Balbi char name[20]; 45672246da4SFelipe Balbi 45772246da4SFelipe Balbi unsigned direction:1; 458879631aaSFelipe Balbi unsigned stream_capable:1; 45972246da4SFelipe Balbi }; 46072246da4SFelipe Balbi 46172246da4SFelipe Balbi enum dwc3_phy { 46272246da4SFelipe Balbi DWC3_PHY_UNKNOWN = 0, 46372246da4SFelipe Balbi DWC3_PHY_USB3, 46472246da4SFelipe Balbi DWC3_PHY_USB2, 46572246da4SFelipe Balbi }; 46672246da4SFelipe Balbi 467b53c772dSFelipe Balbi enum dwc3_ep0_next { 468b53c772dSFelipe Balbi DWC3_EP0_UNKNOWN = 0, 469b53c772dSFelipe Balbi DWC3_EP0_COMPLETE, 470b53c772dSFelipe Balbi DWC3_EP0_NRDY_DATA, 471b53c772dSFelipe Balbi DWC3_EP0_NRDY_STATUS, 472b53c772dSFelipe Balbi }; 473b53c772dSFelipe Balbi 47472246da4SFelipe Balbi enum dwc3_ep0_state { 47572246da4SFelipe Balbi EP0_UNCONNECTED = 0, 476c7fcdeb2SFelipe Balbi EP0_SETUP_PHASE, 477c7fcdeb2SFelipe Balbi EP0_DATA_PHASE, 478c7fcdeb2SFelipe Balbi EP0_STATUS_PHASE, 47972246da4SFelipe Balbi }; 48072246da4SFelipe Balbi 48172246da4SFelipe Balbi enum dwc3_link_state { 48272246da4SFelipe Balbi /* In SuperSpeed */ 48372246da4SFelipe Balbi DWC3_LINK_STATE_U0 = 0x00, /* in HS, means ON */ 48472246da4SFelipe Balbi DWC3_LINK_STATE_U1 = 0x01, 48572246da4SFelipe Balbi DWC3_LINK_STATE_U2 = 0x02, /* in HS, means SLEEP */ 48672246da4SFelipe Balbi DWC3_LINK_STATE_U3 = 0x03, /* in HS, means SUSPEND */ 48772246da4SFelipe Balbi DWC3_LINK_STATE_SS_DIS = 0x04, 48872246da4SFelipe Balbi DWC3_LINK_STATE_RX_DET = 0x05, /* in HS, means Early Suspend */ 48972246da4SFelipe Balbi DWC3_LINK_STATE_SS_INACT = 0x06, 49072246da4SFelipe Balbi DWC3_LINK_STATE_POLL = 0x07, 49172246da4SFelipe Balbi DWC3_LINK_STATE_RECOV = 0x08, 49272246da4SFelipe Balbi DWC3_LINK_STATE_HRESET = 0x09, 49372246da4SFelipe Balbi DWC3_LINK_STATE_CMPLY = 0x0a, 49472246da4SFelipe Balbi DWC3_LINK_STATE_LPBK = 0x0b, 4952c61a8efSPaul Zimmerman DWC3_LINK_STATE_RESET = 0x0e, 4962c61a8efSPaul Zimmerman DWC3_LINK_STATE_RESUME = 0x0f, 49772246da4SFelipe Balbi DWC3_LINK_STATE_MASK = 0x0f, 49872246da4SFelipe Balbi }; 49972246da4SFelipe Balbi 500f6bafc6aSFelipe Balbi /* TRB Length, PCM and Status */ 501f6bafc6aSFelipe Balbi #define DWC3_TRB_SIZE_MASK (0x00ffffff) 502f6bafc6aSFelipe Balbi #define DWC3_TRB_SIZE_LENGTH(n) ((n) & DWC3_TRB_SIZE_MASK) 503f6bafc6aSFelipe Balbi #define DWC3_TRB_SIZE_PCM1(n) (((n) & 0x03) << 24) 504389f2828SPratyush Anand #define DWC3_TRB_SIZE_TRBSTS(n) (((n) & (0x0f << 28)) >> 28) 50572246da4SFelipe Balbi 506f6bafc6aSFelipe Balbi #define DWC3_TRBSTS_OK 0 507f6bafc6aSFelipe Balbi #define DWC3_TRBSTS_MISSED_ISOC 1 508f6bafc6aSFelipe Balbi #define DWC3_TRBSTS_SETUP_PENDING 2 5092c61a8efSPaul Zimmerman #define DWC3_TRB_STS_XFER_IN_PROG 4 51072246da4SFelipe Balbi 511f6bafc6aSFelipe Balbi /* TRB Control */ 512f6bafc6aSFelipe Balbi #define DWC3_TRB_CTRL_HWO (1 << 0) 513f6bafc6aSFelipe Balbi #define DWC3_TRB_CTRL_LST (1 << 1) 514f6bafc6aSFelipe Balbi #define DWC3_TRB_CTRL_CHN (1 << 2) 515f6bafc6aSFelipe Balbi #define DWC3_TRB_CTRL_CSP (1 << 3) 516f6bafc6aSFelipe Balbi #define DWC3_TRB_CTRL_TRBCTL(n) (((n) & 0x3f) << 4) 517f6bafc6aSFelipe Balbi #define DWC3_TRB_CTRL_ISP_IMI (1 << 10) 518f6bafc6aSFelipe Balbi #define DWC3_TRB_CTRL_IOC (1 << 11) 519f6bafc6aSFelipe Balbi #define DWC3_TRB_CTRL_SID_SOFN(n) (((n) & 0xffff) << 14) 520f6bafc6aSFelipe Balbi 521f6bafc6aSFelipe Balbi #define DWC3_TRBCTL_NORMAL DWC3_TRB_CTRL_TRBCTL(1) 522f6bafc6aSFelipe Balbi #define DWC3_TRBCTL_CONTROL_SETUP DWC3_TRB_CTRL_TRBCTL(2) 523f6bafc6aSFelipe Balbi #define DWC3_TRBCTL_CONTROL_STATUS2 DWC3_TRB_CTRL_TRBCTL(3) 524f6bafc6aSFelipe Balbi #define DWC3_TRBCTL_CONTROL_STATUS3 DWC3_TRB_CTRL_TRBCTL(4) 525f6bafc6aSFelipe Balbi #define DWC3_TRBCTL_CONTROL_DATA DWC3_TRB_CTRL_TRBCTL(5) 526f6bafc6aSFelipe Balbi #define DWC3_TRBCTL_ISOCHRONOUS_FIRST DWC3_TRB_CTRL_TRBCTL(6) 527f6bafc6aSFelipe Balbi #define DWC3_TRBCTL_ISOCHRONOUS DWC3_TRB_CTRL_TRBCTL(7) 528f6bafc6aSFelipe Balbi #define DWC3_TRBCTL_LINK_TRB DWC3_TRB_CTRL_TRBCTL(8) 52972246da4SFelipe Balbi 53072246da4SFelipe Balbi /** 531f6bafc6aSFelipe Balbi * struct dwc3_trb - transfer request block (hw format) 53272246da4SFelipe Balbi * @bpl: DW0-3 53372246da4SFelipe Balbi * @bph: DW4-7 53472246da4SFelipe Balbi * @size: DW8-B 53572246da4SFelipe Balbi * @trl: DWC-F 53672246da4SFelipe Balbi */ 537f6bafc6aSFelipe Balbi struct dwc3_trb { 538f6bafc6aSFelipe Balbi u32 bpl; 539f6bafc6aSFelipe Balbi u32 bph; 540f6bafc6aSFelipe Balbi u32 size; 541f6bafc6aSFelipe Balbi u32 ctrl; 54272246da4SFelipe Balbi } __packed; 54372246da4SFelipe Balbi 54472246da4SFelipe Balbi /** 545a3299499SFelipe Balbi * dwc3_hwparams - copy of HWPARAMS registers 546a3299499SFelipe Balbi * @hwparams0 - GHWPARAMS0 547a3299499SFelipe Balbi * @hwparams1 - GHWPARAMS1 548a3299499SFelipe Balbi * @hwparams2 - GHWPARAMS2 549a3299499SFelipe Balbi * @hwparams3 - GHWPARAMS3 550a3299499SFelipe Balbi * @hwparams4 - GHWPARAMS4 551a3299499SFelipe Balbi * @hwparams5 - GHWPARAMS5 552a3299499SFelipe Balbi * @hwparams6 - GHWPARAMS6 553a3299499SFelipe Balbi * @hwparams7 - GHWPARAMS7 554a3299499SFelipe Balbi * @hwparams8 - GHWPARAMS8 555a3299499SFelipe Balbi */ 556a3299499SFelipe Balbi struct dwc3_hwparams { 557a3299499SFelipe Balbi u32 hwparams0; 558a3299499SFelipe Balbi u32 hwparams1; 559a3299499SFelipe Balbi u32 hwparams2; 560a3299499SFelipe Balbi u32 hwparams3; 561a3299499SFelipe Balbi u32 hwparams4; 562a3299499SFelipe Balbi u32 hwparams5; 563a3299499SFelipe Balbi u32 hwparams6; 564a3299499SFelipe Balbi u32 hwparams7; 565a3299499SFelipe Balbi u32 hwparams8; 566a3299499SFelipe Balbi }; 567a3299499SFelipe Balbi 5680949e99bSFelipe Balbi /* HWPARAMS0 */ 5690949e99bSFelipe Balbi #define DWC3_MODE(n) ((n) & 0x7) 5700949e99bSFelipe Balbi 571457e84b6SFelipe Balbi #define DWC3_MDWIDTH(n) (((n) & 0xff00) >> 8) 572457e84b6SFelipe Balbi 5730949e99bSFelipe Balbi /* HWPARAMS1 */ 5749f622b2aSFelipe Balbi #define DWC3_NUM_INT(n) (((n) & (0x3f << 15)) >> 15) 5759f622b2aSFelipe Balbi 576789451f6SFelipe Balbi /* HWPARAMS3 */ 577789451f6SFelipe Balbi #define DWC3_NUM_IN_EPS_MASK (0x1f << 18) 578789451f6SFelipe Balbi #define DWC3_NUM_EPS_MASK (0x3f << 12) 579789451f6SFelipe Balbi #define DWC3_NUM_EPS(p) (((p)->hwparams3 & \ 580789451f6SFelipe Balbi (DWC3_NUM_EPS_MASK)) >> 12) 581789451f6SFelipe Balbi #define DWC3_NUM_IN_EPS(p) (((p)->hwparams3 & \ 582789451f6SFelipe Balbi (DWC3_NUM_IN_EPS_MASK)) >> 18) 583789451f6SFelipe Balbi 584457e84b6SFelipe Balbi /* HWPARAMS7 */ 585457e84b6SFelipe Balbi #define DWC3_RAM1_DEPTH(n) ((n) & 0xffff) 586457e84b6SFelipe Balbi 587e0ce0b0aSSebastian Andrzej Siewior struct dwc3_request { 588e0ce0b0aSSebastian Andrzej Siewior struct usb_request request; 589e0ce0b0aSSebastian Andrzej Siewior struct list_head list; 590e0ce0b0aSSebastian Andrzej Siewior struct dwc3_ep *dep; 591e5ba5ec8SPratyush Anand u32 start_slot; 592e0ce0b0aSSebastian Andrzej Siewior 593e0ce0b0aSSebastian Andrzej Siewior u8 epnum; 594f6bafc6aSFelipe Balbi struct dwc3_trb *trb; 595e0ce0b0aSSebastian Andrzej Siewior dma_addr_t trb_dma; 596e0ce0b0aSSebastian Andrzej Siewior 597e0ce0b0aSSebastian Andrzej Siewior unsigned direction:1; 598e0ce0b0aSSebastian Andrzej Siewior unsigned mapped:1; 599e0ce0b0aSSebastian Andrzej Siewior unsigned queued:1; 600e0ce0b0aSSebastian Andrzej Siewior }; 601e0ce0b0aSSebastian Andrzej Siewior 6022c61a8efSPaul Zimmerman /* 6032c61a8efSPaul Zimmerman * struct dwc3_scratchpad_array - hibernation scratchpad array 6042c61a8efSPaul Zimmerman * (format defined by hw) 6052c61a8efSPaul Zimmerman */ 6062c61a8efSPaul Zimmerman struct dwc3_scratchpad_array { 6072c61a8efSPaul Zimmerman __le64 dma_adr[DWC3_MAX_HIBER_SCRATCHBUFS]; 6082c61a8efSPaul Zimmerman }; 6092c61a8efSPaul Zimmerman 610a3299499SFelipe Balbi /** 61172246da4SFelipe Balbi * struct dwc3 - representation of our controller 61291db07dcSFelipe Balbi * @ctrl_req: usb control request which is used for ep0 61391db07dcSFelipe Balbi * @ep0_trb: trb which is used for the ctrl_req 6145812b1c2SFelipe Balbi * @ep0_bounce: bounce buffer for ep0 61591db07dcSFelipe Balbi * @setup_buf: used while precessing STD USB requests 61691db07dcSFelipe Balbi * @ctrl_req_addr: dma address of ctrl_req 61791db07dcSFelipe Balbi * @ep0_trb: dma address of ep0_trb 61891db07dcSFelipe Balbi * @ep0_usb_req: dummy req used while handling STD USB requests 6195812b1c2SFelipe Balbi * @ep0_bounce_addr: dma address of ep0_bounce 6200ffcaf37SFelipe Balbi * @scratch_addr: dma address of scratchbuf 62172246da4SFelipe Balbi * @lock: for synchronizing 62272246da4SFelipe Balbi * @dev: pointer to our struct device 623d07e8819SFelipe Balbi * @xhci: pointer to our xHCI child 62472246da4SFelipe Balbi * @event_buffer_list: a list of event buffers 62572246da4SFelipe Balbi * @gadget: device side representation of the peripheral controller 62672246da4SFelipe Balbi * @gadget_driver: pointer to the gadget driver 62772246da4SFelipe Balbi * @regs: base address for our registers 62872246da4SFelipe Balbi * @regs_size: address space size 6290ffcaf37SFelipe Balbi * @nr_scratch: number of scratch buffers 6309f622b2aSFelipe Balbi * @num_event_buffers: calculated number of event buffers 631fae2b904SFelipe Balbi * @u1u2: only used on revisions <1.83a for workaround 6326c167fc9SFelipe Balbi * @maximum_speed: maximum speed requested (mainly for testing purposes) 63372246da4SFelipe Balbi * @revision: revision register contents 634a45c82b8SRuchika Kharwar * @dr_mode: requested mode of operation 63551e1e7bcSFelipe Balbi * @usb2_phy: pointer to USB2 PHY 63651e1e7bcSFelipe Balbi * @usb3_phy: pointer to USB3 PHY 63757303488SKishon Vijay Abraham I * @usb2_generic_phy: pointer to USB2 PHY 63857303488SKishon Vijay Abraham I * @usb3_generic_phy: pointer to USB3 PHY 6397415f17cSFelipe Balbi * @dcfg: saved contents of DCFG register 6407415f17cSFelipe Balbi * @gctl: saved contents of GCTL register 641c12a0d86SFelipe Balbi * @isoch_delay: wValue from Set Isochronous Delay request; 642865e09e7SFelipe Balbi * @u2sel: parameter from Set SEL request. 643865e09e7SFelipe Balbi * @u2pel: parameter from Set SEL request. 644865e09e7SFelipe Balbi * @u1sel: parameter from Set SEL request. 645865e09e7SFelipe Balbi * @u1pel: parameter from Set SEL request. 646789451f6SFelipe Balbi * @num_out_eps: number of out endpoints 647789451f6SFelipe Balbi * @num_in_eps: number of in endpoints 648b53c772dSFelipe Balbi * @ep0_next_event: hold the next expected event 64972246da4SFelipe Balbi * @ep0state: state of endpoint zero 65072246da4SFelipe Balbi * @link_state: link state 65172246da4SFelipe Balbi * @speed: device speed (super, high, full, low) 65272246da4SFelipe Balbi * @mem: points to start of memory which is used for this struct. 653a3299499SFelipe Balbi * @hwparams: copy of hwparams registers 65472246da4SFelipe Balbi * @root: debugfs root folder pointer 655f2b685d5SFelipe Balbi * @regset: debugfs pointer to regdump file 656f2b685d5SFelipe Balbi * @test_mode: true when we're entering a USB test mode 657f2b685d5SFelipe Balbi * @test_mode_nr: test feature selector 658f2b685d5SFelipe Balbi * @delayed_status: true when gadget driver asks for delayed status 659f2b685d5SFelipe Balbi * @ep0_bounced: true when we used bounce buffer 660f2b685d5SFelipe Balbi * @ep0_expect_in: true when we expect a DATA IN transfer 66181bc5599SFelipe Balbi * @has_hibernation: true when dwc3 was configured with Hibernation 662f2b685d5SFelipe Balbi * @is_selfpowered: true when we are selfpowered 663f2b685d5SFelipe Balbi * @needs_fifo_resize: not all users might want fifo resizing, flag it 664f2b685d5SFelipe Balbi * @pullups_connected: true when Run/Stop bit is set 665f2b685d5SFelipe Balbi * @resize_fifos: tells us it's ok to reconfigure our TxFIFO sizes. 666f2b685d5SFelipe Balbi * @setup_packet_pending: true when there's a Setup Packet in FIFO. Workaround 667f2b685d5SFelipe Balbi * @start_config_issued: true when StartConfig command has been issued 668f2b685d5SFelipe Balbi * @three_stage_setup: set if we perform a three phase setup 66972246da4SFelipe Balbi */ 67072246da4SFelipe Balbi struct dwc3 { 67172246da4SFelipe Balbi struct usb_ctrlrequest *ctrl_req; 672f6bafc6aSFelipe Balbi struct dwc3_trb *ep0_trb; 6735812b1c2SFelipe Balbi void *ep0_bounce; 6740ffcaf37SFelipe Balbi void *scratchbuf; 67572246da4SFelipe Balbi u8 *setup_buf; 67672246da4SFelipe Balbi dma_addr_t ctrl_req_addr; 67772246da4SFelipe Balbi dma_addr_t ep0_trb_addr; 6785812b1c2SFelipe Balbi dma_addr_t ep0_bounce_addr; 6790ffcaf37SFelipe Balbi dma_addr_t scratch_addr; 680e0ce0b0aSSebastian Andrzej Siewior struct dwc3_request ep0_usb_req; 681789451f6SFelipe Balbi 68272246da4SFelipe Balbi /* device lock */ 68372246da4SFelipe Balbi spinlock_t lock; 684789451f6SFelipe Balbi 68572246da4SFelipe Balbi struct device *dev; 68672246da4SFelipe Balbi 687d07e8819SFelipe Balbi struct platform_device *xhci; 68851249dcaSIdo Shayevitz struct resource xhci_resources[DWC3_XHCI_RESOURCES_NUM]; 689d07e8819SFelipe Balbi 690457d3f21SFelipe Balbi struct dwc3_event_buffer **ev_buffs; 69172246da4SFelipe Balbi struct dwc3_ep *eps[DWC3_ENDPOINTS_NUM]; 69272246da4SFelipe Balbi 69372246da4SFelipe Balbi struct usb_gadget gadget; 69472246da4SFelipe Balbi struct usb_gadget_driver *gadget_driver; 69572246da4SFelipe Balbi 69651e1e7bcSFelipe Balbi struct usb_phy *usb2_phy; 69751e1e7bcSFelipe Balbi struct usb_phy *usb3_phy; 69851e1e7bcSFelipe Balbi 69957303488SKishon Vijay Abraham I struct phy *usb2_generic_phy; 70057303488SKishon Vijay Abraham I struct phy *usb3_generic_phy; 70157303488SKishon Vijay Abraham I 70272246da4SFelipe Balbi void __iomem *regs; 70372246da4SFelipe Balbi size_t regs_size; 70472246da4SFelipe Balbi 705a45c82b8SRuchika Kharwar enum usb_dr_mode dr_mode; 706a45c82b8SRuchika Kharwar 7077415f17cSFelipe Balbi /* used for suspend/resume */ 7087415f17cSFelipe Balbi u32 dcfg; 7097415f17cSFelipe Balbi u32 gctl; 7107415f17cSFelipe Balbi 7110ffcaf37SFelipe Balbi u32 nr_scratch; 7129f622b2aSFelipe Balbi u32 num_event_buffers; 713fae2b904SFelipe Balbi u32 u1u2; 7146c167fc9SFelipe Balbi u32 maximum_speed; 71572246da4SFelipe Balbi u32 revision; 71672246da4SFelipe Balbi 71772246da4SFelipe Balbi #define DWC3_REVISION_173A 0x5533173a 71872246da4SFelipe Balbi #define DWC3_REVISION_175A 0x5533175a 71972246da4SFelipe Balbi #define DWC3_REVISION_180A 0x5533180a 72072246da4SFelipe Balbi #define DWC3_REVISION_183A 0x5533183a 72172246da4SFelipe Balbi #define DWC3_REVISION_185A 0x5533185a 7222c61a8efSPaul Zimmerman #define DWC3_REVISION_187A 0x5533187a 72372246da4SFelipe Balbi #define DWC3_REVISION_188A 0x5533188a 72472246da4SFelipe Balbi #define DWC3_REVISION_190A 0x5533190a 7252c61a8efSPaul Zimmerman #define DWC3_REVISION_194A 0x5533194a 7261522d703SFelipe Balbi #define DWC3_REVISION_200A 0x5533200a 7271522d703SFelipe Balbi #define DWC3_REVISION_202A 0x5533202a 7281522d703SFelipe Balbi #define DWC3_REVISION_210A 0x5533210a 7291522d703SFelipe Balbi #define DWC3_REVISION_220A 0x5533220a 7307ac6a593SFelipe Balbi #define DWC3_REVISION_230A 0x5533230a 7317ac6a593SFelipe Balbi #define DWC3_REVISION_240A 0x5533240a 7327ac6a593SFelipe Balbi #define DWC3_REVISION_250A 0x5533250a 733dbf5aaf7SFelipe Balbi #define DWC3_REVISION_260A 0x5533260a 734dbf5aaf7SFelipe Balbi #define DWC3_REVISION_270A 0x5533270a 735dbf5aaf7SFelipe Balbi #define DWC3_REVISION_280A 0x5533280a 73672246da4SFelipe Balbi 737b53c772dSFelipe Balbi enum dwc3_ep0_next ep0_next_event; 73872246da4SFelipe Balbi enum dwc3_ep0_state ep0state; 73972246da4SFelipe Balbi enum dwc3_link_state link_state; 74072246da4SFelipe Balbi 741c12a0d86SFelipe Balbi u16 isoch_delay; 742865e09e7SFelipe Balbi u16 u2sel; 743865e09e7SFelipe Balbi u16 u2pel; 744865e09e7SFelipe Balbi u8 u1sel; 745865e09e7SFelipe Balbi u8 u1pel; 746865e09e7SFelipe Balbi 74772246da4SFelipe Balbi u8 speed; 748865e09e7SFelipe Balbi 749789451f6SFelipe Balbi u8 num_out_eps; 750789451f6SFelipe Balbi u8 num_in_eps; 751789451f6SFelipe Balbi 75272246da4SFelipe Balbi void *mem; 75372246da4SFelipe Balbi 754a3299499SFelipe Balbi struct dwc3_hwparams hwparams; 75572246da4SFelipe Balbi struct dentry *root; 756d7668024SFelipe Balbi struct debugfs_regset32 *regset; 7573b637367SGerard Cauvy 7583b637367SGerard Cauvy u8 test_mode; 7593b637367SGerard Cauvy u8 test_mode_nr; 760f2b685d5SFelipe Balbi 761f2b685d5SFelipe Balbi unsigned delayed_status:1; 762f2b685d5SFelipe Balbi unsigned ep0_bounced:1; 763f2b685d5SFelipe Balbi unsigned ep0_expect_in:1; 76481bc5599SFelipe Balbi unsigned has_hibernation:1; 765f2b685d5SFelipe Balbi unsigned is_selfpowered:1; 766f2b685d5SFelipe Balbi unsigned needs_fifo_resize:1; 767f2b685d5SFelipe Balbi unsigned pullups_connected:1; 768f2b685d5SFelipe Balbi unsigned resize_fifos:1; 769f2b685d5SFelipe Balbi unsigned setup_packet_pending:1; 770f2b685d5SFelipe Balbi unsigned start_config_issued:1; 771f2b685d5SFelipe Balbi unsigned three_stage_setup:1; 77272246da4SFelipe Balbi }; 77372246da4SFelipe Balbi 77472246da4SFelipe Balbi /* -------------------------------------------------------------------------- */ 77572246da4SFelipe Balbi 77672246da4SFelipe Balbi /* -------------------------------------------------------------------------- */ 77772246da4SFelipe Balbi 77872246da4SFelipe Balbi struct dwc3_event_type { 77972246da4SFelipe Balbi u32 is_devspec:1; 7801974d494SHuang Rui u32 type:7; 7811974d494SHuang Rui u32 reserved8_31:24; 78272246da4SFelipe Balbi } __packed; 78372246da4SFelipe Balbi 78472246da4SFelipe Balbi #define DWC3_DEPEVT_XFERCOMPLETE 0x01 78572246da4SFelipe Balbi #define DWC3_DEPEVT_XFERINPROGRESS 0x02 78672246da4SFelipe Balbi #define DWC3_DEPEVT_XFERNOTREADY 0x03 78772246da4SFelipe Balbi #define DWC3_DEPEVT_RXTXFIFOEVT 0x04 78872246da4SFelipe Balbi #define DWC3_DEPEVT_STREAMEVT 0x06 78972246da4SFelipe Balbi #define DWC3_DEPEVT_EPCMDCMPLT 0x07 79072246da4SFelipe Balbi 79172246da4SFelipe Balbi /** 79272246da4SFelipe Balbi * struct dwc3_event_depvt - Device Endpoint Events 79372246da4SFelipe Balbi * @one_bit: indicates this is an endpoint event (not used) 79472246da4SFelipe Balbi * @endpoint_number: number of the endpoint 79572246da4SFelipe Balbi * @endpoint_event: The event we have: 79672246da4SFelipe Balbi * 0x00 - Reserved 79772246da4SFelipe Balbi * 0x01 - XferComplete 79872246da4SFelipe Balbi * 0x02 - XferInProgress 79972246da4SFelipe Balbi * 0x03 - XferNotReady 80072246da4SFelipe Balbi * 0x04 - RxTxFifoEvt (IN->Underrun, OUT->Overrun) 80172246da4SFelipe Balbi * 0x05 - Reserved 80272246da4SFelipe Balbi * 0x06 - StreamEvt 80372246da4SFelipe Balbi * 0x07 - EPCmdCmplt 80472246da4SFelipe Balbi * @reserved11_10: Reserved, don't use. 80572246da4SFelipe Balbi * @status: Indicates the status of the event. Refer to databook for 80672246da4SFelipe Balbi * more information. 80772246da4SFelipe Balbi * @parameters: Parameters of the current event. Refer to databook for 80872246da4SFelipe Balbi * more information. 80972246da4SFelipe Balbi */ 81072246da4SFelipe Balbi struct dwc3_event_depevt { 81172246da4SFelipe Balbi u32 one_bit:1; 81272246da4SFelipe Balbi u32 endpoint_number:5; 81372246da4SFelipe Balbi u32 endpoint_event:4; 81472246da4SFelipe Balbi u32 reserved11_10:2; 81572246da4SFelipe Balbi u32 status:4; 81640aa41fbSFelipe Balbi 81740aa41fbSFelipe Balbi /* Within XferNotReady */ 81840aa41fbSFelipe Balbi #define DEPEVT_STATUS_TRANSFER_ACTIVE (1 << 3) 81940aa41fbSFelipe Balbi 82040aa41fbSFelipe Balbi /* Within XferComplete */ 82172246da4SFelipe Balbi #define DEPEVT_STATUS_BUSERR (1 << 0) 82272246da4SFelipe Balbi #define DEPEVT_STATUS_SHORT (1 << 1) 82372246da4SFelipe Balbi #define DEPEVT_STATUS_IOC (1 << 2) 82472246da4SFelipe Balbi #define DEPEVT_STATUS_LST (1 << 3) 825dc137f01SFelipe Balbi 826879631aaSFelipe Balbi /* Stream event only */ 827879631aaSFelipe Balbi #define DEPEVT_STREAMEVT_FOUND 1 828879631aaSFelipe Balbi #define DEPEVT_STREAMEVT_NOTFOUND 2 829879631aaSFelipe Balbi 830dc137f01SFelipe Balbi /* Control-only Status */ 831dc137f01SFelipe Balbi #define DEPEVT_STATUS_CONTROL_DATA 1 832dc137f01SFelipe Balbi #define DEPEVT_STATUS_CONTROL_STATUS 2 833dc137f01SFelipe Balbi 83472246da4SFelipe Balbi u32 parameters:16; 83572246da4SFelipe Balbi } __packed; 83672246da4SFelipe Balbi 83772246da4SFelipe Balbi /** 83872246da4SFelipe Balbi * struct dwc3_event_devt - Device Events 83972246da4SFelipe Balbi * @one_bit: indicates this is a non-endpoint event (not used) 84072246da4SFelipe Balbi * @device_event: indicates it's a device event. Should read as 0x00 84172246da4SFelipe Balbi * @type: indicates the type of device event. 84272246da4SFelipe Balbi * 0 - DisconnEvt 84372246da4SFelipe Balbi * 1 - USBRst 84472246da4SFelipe Balbi * 2 - ConnectDone 84572246da4SFelipe Balbi * 3 - ULStChng 84672246da4SFelipe Balbi * 4 - WkUpEvt 84772246da4SFelipe Balbi * 5 - Reserved 84872246da4SFelipe Balbi * 6 - EOPF 84972246da4SFelipe Balbi * 7 - SOF 85072246da4SFelipe Balbi * 8 - Reserved 85172246da4SFelipe Balbi * 9 - ErrticErr 85272246da4SFelipe Balbi * 10 - CmdCmplt 85372246da4SFelipe Balbi * 11 - EvntOverflow 85472246da4SFelipe Balbi * 12 - VndrDevTstRcved 85572246da4SFelipe Balbi * @reserved15_12: Reserved, not used 85672246da4SFelipe Balbi * @event_info: Information about this event 85706f9b6e5SHuang Rui * @reserved31_25: Reserved, not used 85872246da4SFelipe Balbi */ 85972246da4SFelipe Balbi struct dwc3_event_devt { 86072246da4SFelipe Balbi u32 one_bit:1; 86172246da4SFelipe Balbi u32 device_event:7; 86272246da4SFelipe Balbi u32 type:4; 86372246da4SFelipe Balbi u32 reserved15_12:4; 86406f9b6e5SHuang Rui u32 event_info:9; 86506f9b6e5SHuang Rui u32 reserved31_25:7; 86672246da4SFelipe Balbi } __packed; 86772246da4SFelipe Balbi 86872246da4SFelipe Balbi /** 86972246da4SFelipe Balbi * struct dwc3_event_gevt - Other Core Events 87072246da4SFelipe Balbi * @one_bit: indicates this is a non-endpoint event (not used) 87172246da4SFelipe Balbi * @device_event: indicates it's (0x03) Carkit or (0x04) I2C event. 87272246da4SFelipe Balbi * @phy_port_number: self-explanatory 87372246da4SFelipe Balbi * @reserved31_12: Reserved, not used. 87472246da4SFelipe Balbi */ 87572246da4SFelipe Balbi struct dwc3_event_gevt { 87672246da4SFelipe Balbi u32 one_bit:1; 87772246da4SFelipe Balbi u32 device_event:7; 87872246da4SFelipe Balbi u32 phy_port_number:4; 87972246da4SFelipe Balbi u32 reserved31_12:20; 88072246da4SFelipe Balbi } __packed; 88172246da4SFelipe Balbi 88272246da4SFelipe Balbi /** 88372246da4SFelipe Balbi * union dwc3_event - representation of Event Buffer contents 88472246da4SFelipe Balbi * @raw: raw 32-bit event 88572246da4SFelipe Balbi * @type: the type of the event 88672246da4SFelipe Balbi * @depevt: Device Endpoint Event 88772246da4SFelipe Balbi * @devt: Device Event 88872246da4SFelipe Balbi * @gevt: Global Event 88972246da4SFelipe Balbi */ 89072246da4SFelipe Balbi union dwc3_event { 89172246da4SFelipe Balbi u32 raw; 89272246da4SFelipe Balbi struct dwc3_event_type type; 89372246da4SFelipe Balbi struct dwc3_event_depevt depevt; 89472246da4SFelipe Balbi struct dwc3_event_devt devt; 89572246da4SFelipe Balbi struct dwc3_event_gevt gevt; 89672246da4SFelipe Balbi }; 89772246da4SFelipe Balbi 89861018305SFelipe Balbi /** 89961018305SFelipe Balbi * struct dwc3_gadget_ep_cmd_params - representation of endpoint command 90061018305SFelipe Balbi * parameters 90161018305SFelipe Balbi * @param2: third parameter 90261018305SFelipe Balbi * @param1: second parameter 90361018305SFelipe Balbi * @param0: first parameter 90461018305SFelipe Balbi */ 90561018305SFelipe Balbi struct dwc3_gadget_ep_cmd_params { 90661018305SFelipe Balbi u32 param2; 90761018305SFelipe Balbi u32 param1; 90861018305SFelipe Balbi u32 param0; 90961018305SFelipe Balbi }; 91061018305SFelipe Balbi 91172246da4SFelipe Balbi /* 91272246da4SFelipe Balbi * DWC3 Features to be used as Driver Data 91372246da4SFelipe Balbi */ 91472246da4SFelipe Balbi 91572246da4SFelipe Balbi #define DWC3_HAS_PERIPHERAL BIT(0) 91672246da4SFelipe Balbi #define DWC3_HAS_XHCI BIT(1) 91772246da4SFelipe Balbi #define DWC3_HAS_OTG BIT(3) 91872246da4SFelipe Balbi 919d07e8819SFelipe Balbi /* prototypes */ 9203140e8cbSSebastian Andrzej Siewior void dwc3_set_mode(struct dwc3 *dwc, u32 mode); 921457e84b6SFelipe Balbi int dwc3_gadget_resize_tx_fifos(struct dwc3 *dwc); 9223140e8cbSSebastian Andrzej Siewior 923388e5c51SVivek Gautam #if IS_ENABLED(CONFIG_USB_DWC3_HOST) || IS_ENABLED(CONFIG_USB_DWC3_DUAL_ROLE) 924d07e8819SFelipe Balbi int dwc3_host_init(struct dwc3 *dwc); 925d07e8819SFelipe Balbi void dwc3_host_exit(struct dwc3 *dwc); 926388e5c51SVivek Gautam #else 927388e5c51SVivek Gautam static inline int dwc3_host_init(struct dwc3 *dwc) 928388e5c51SVivek Gautam { return 0; } 929388e5c51SVivek Gautam static inline void dwc3_host_exit(struct dwc3 *dwc) 930388e5c51SVivek Gautam { } 931388e5c51SVivek Gautam #endif 932d07e8819SFelipe Balbi 933388e5c51SVivek Gautam #if IS_ENABLED(CONFIG_USB_DWC3_GADGET) || IS_ENABLED(CONFIG_USB_DWC3_DUAL_ROLE) 934f80b45e7SFelipe Balbi int dwc3_gadget_init(struct dwc3 *dwc); 935f80b45e7SFelipe Balbi void dwc3_gadget_exit(struct dwc3 *dwc); 93661018305SFelipe Balbi int dwc3_gadget_set_test_mode(struct dwc3 *dwc, int mode); 93761018305SFelipe Balbi int dwc3_gadget_get_link_state(struct dwc3 *dwc); 93861018305SFelipe Balbi int dwc3_gadget_set_link_state(struct dwc3 *dwc, enum dwc3_link_state state); 93961018305SFelipe Balbi int dwc3_send_gadget_ep_cmd(struct dwc3 *dwc, unsigned ep, 94061018305SFelipe Balbi unsigned cmd, struct dwc3_gadget_ep_cmd_params *params); 94161018305SFelipe Balbi int dwc3_send_gadget_generic_command(struct dwc3 *dwc, int cmd, u32 param); 942388e5c51SVivek Gautam #else 943388e5c51SVivek Gautam static inline int dwc3_gadget_init(struct dwc3 *dwc) 944388e5c51SVivek Gautam { return 0; } 945388e5c51SVivek Gautam static inline void dwc3_gadget_exit(struct dwc3 *dwc) 946388e5c51SVivek Gautam { } 94761018305SFelipe Balbi static inline int dwc3_gadget_set_test_mode(struct dwc3 *dwc, int mode) 94861018305SFelipe Balbi { return 0; } 94961018305SFelipe Balbi static inline int dwc3_gadget_get_link_state(struct dwc3 *dwc) 95061018305SFelipe Balbi { return 0; } 95161018305SFelipe Balbi static inline int dwc3_gadget_set_link_state(struct dwc3 *dwc, 95261018305SFelipe Balbi enum dwc3_link_state state) 95361018305SFelipe Balbi { return 0; } 95461018305SFelipe Balbi 95561018305SFelipe Balbi static inline int dwc3_send_gadget_ep_cmd(struct dwc3 *dwc, unsigned ep, 95661018305SFelipe Balbi unsigned cmd, struct dwc3_gadget_ep_cmd_params *params) 95761018305SFelipe Balbi { return 0; } 95861018305SFelipe Balbi static inline int dwc3_send_gadget_generic_command(struct dwc3 *dwc, 95961018305SFelipe Balbi int cmd, u32 param) 96061018305SFelipe Balbi { return 0; } 961388e5c51SVivek Gautam #endif 962f80b45e7SFelipe Balbi 9637415f17cSFelipe Balbi /* power management interface */ 9647415f17cSFelipe Balbi #if !IS_ENABLED(CONFIG_USB_DWC3_HOST) 9657415f17cSFelipe Balbi int dwc3_gadget_prepare(struct dwc3 *dwc); 9667415f17cSFelipe Balbi void dwc3_gadget_complete(struct dwc3 *dwc); 9677415f17cSFelipe Balbi int dwc3_gadget_suspend(struct dwc3 *dwc); 9687415f17cSFelipe Balbi int dwc3_gadget_resume(struct dwc3 *dwc); 9697415f17cSFelipe Balbi #else 9707415f17cSFelipe Balbi static inline int dwc3_gadget_prepare(struct dwc3 *dwc) 9717415f17cSFelipe Balbi { 9727415f17cSFelipe Balbi return 0; 9737415f17cSFelipe Balbi } 9747415f17cSFelipe Balbi 9757415f17cSFelipe Balbi static inline void dwc3_gadget_complete(struct dwc3 *dwc) 9767415f17cSFelipe Balbi { 9777415f17cSFelipe Balbi } 9787415f17cSFelipe Balbi 9797415f17cSFelipe Balbi static inline int dwc3_gadget_suspend(struct dwc3 *dwc) 9807415f17cSFelipe Balbi { 9817415f17cSFelipe Balbi return 0; 9827415f17cSFelipe Balbi } 9837415f17cSFelipe Balbi 9847415f17cSFelipe Balbi static inline int dwc3_gadget_resume(struct dwc3 *dwc) 9857415f17cSFelipe Balbi { 9867415f17cSFelipe Balbi return 0; 9877415f17cSFelipe Balbi } 9887415f17cSFelipe Balbi #endif /* !IS_ENABLED(CONFIG_USB_DWC3_HOST) */ 9897415f17cSFelipe Balbi 99072246da4SFelipe Balbi #endif /* __DRIVERS_USB_DWC3_CORE_H */ 991