1 /** 2 * core.c - DesignWare USB3 DRD Controller Core file 3 * 4 * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com 5 * 6 * Authors: Felipe Balbi <balbi@ti.com>, 7 * Sebastian Andrzej Siewior <bigeasy@linutronix.de> 8 * 9 * This program is free software: you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License version 2 of 11 * the License as published by the Free Software Foundation. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program. If not, see <http://www.gnu.org/licenses/>. 20 */ 21 22 #include <linux/version.h> 23 #include <linux/module.h> 24 #include <linux/kernel.h> 25 #include <linux/slab.h> 26 #include <linux/spinlock.h> 27 #include <linux/platform_device.h> 28 #include <linux/pm_runtime.h> 29 #include <linux/interrupt.h> 30 #include <linux/ioport.h> 31 #include <linux/io.h> 32 #include <linux/list.h> 33 #include <linux/delay.h> 34 #include <linux/dma-mapping.h> 35 #include <linux/of.h> 36 #include <linux/acpi.h> 37 #include <linux/pinctrl/consumer.h> 38 39 #include <linux/usb/ch9.h> 40 #include <linux/usb/gadget.h> 41 #include <linux/usb/of.h> 42 #include <linux/usb/otg.h> 43 44 #include "core.h" 45 #include "gadget.h" 46 #include "io.h" 47 48 #include "debug.h" 49 50 #define DWC3_DEFAULT_AUTOSUSPEND_DELAY 5000 /* ms */ 51 52 /** 53 * dwc3_get_dr_mode - Validates and sets dr_mode 54 * @dwc: pointer to our context structure 55 */ 56 static int dwc3_get_dr_mode(struct dwc3 *dwc) 57 { 58 enum usb_dr_mode mode; 59 struct device *dev = dwc->dev; 60 unsigned int hw_mode; 61 62 if (dwc->dr_mode == USB_DR_MODE_UNKNOWN) 63 dwc->dr_mode = USB_DR_MODE_OTG; 64 65 mode = dwc->dr_mode; 66 hw_mode = DWC3_GHWPARAMS0_MODE(dwc->hwparams.hwparams0); 67 68 switch (hw_mode) { 69 case DWC3_GHWPARAMS0_MODE_GADGET: 70 if (IS_ENABLED(CONFIG_USB_DWC3_HOST)) { 71 dev_err(dev, 72 "Controller does not support host mode.\n"); 73 return -EINVAL; 74 } 75 mode = USB_DR_MODE_PERIPHERAL; 76 break; 77 case DWC3_GHWPARAMS0_MODE_HOST: 78 if (IS_ENABLED(CONFIG_USB_DWC3_GADGET)) { 79 dev_err(dev, 80 "Controller does not support device mode.\n"); 81 return -EINVAL; 82 } 83 mode = USB_DR_MODE_HOST; 84 break; 85 default: 86 if (IS_ENABLED(CONFIG_USB_DWC3_HOST)) 87 mode = USB_DR_MODE_HOST; 88 else if (IS_ENABLED(CONFIG_USB_DWC3_GADGET)) 89 mode = USB_DR_MODE_PERIPHERAL; 90 } 91 92 if (mode != dwc->dr_mode) { 93 dev_warn(dev, 94 "Configuration mismatch. dr_mode forced to %s\n", 95 mode == USB_DR_MODE_HOST ? "host" : "gadget"); 96 97 dwc->dr_mode = mode; 98 } 99 100 return 0; 101 } 102 103 static void dwc3_event_buffers_cleanup(struct dwc3 *dwc); 104 static int dwc3_event_buffers_setup(struct dwc3 *dwc); 105 106 static void dwc3_set_prtcap(struct dwc3 *dwc, u32 mode) 107 { 108 u32 reg; 109 110 reg = dwc3_readl(dwc->regs, DWC3_GCTL); 111 reg &= ~(DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_OTG)); 112 reg |= DWC3_GCTL_PRTCAPDIR(mode); 113 dwc3_writel(dwc->regs, DWC3_GCTL, reg); 114 } 115 116 static void __dwc3_set_mode(struct work_struct *work) 117 { 118 struct dwc3 *dwc = work_to_dwc(work); 119 unsigned long flags; 120 int ret; 121 122 if (!dwc->desired_dr_role) 123 return; 124 125 if (dwc->desired_dr_role == dwc->current_dr_role) 126 return; 127 128 if (dwc->dr_mode != USB_DR_MODE_OTG) 129 return; 130 131 switch (dwc->current_dr_role) { 132 case DWC3_GCTL_PRTCAP_HOST: 133 dwc3_host_exit(dwc); 134 break; 135 case DWC3_GCTL_PRTCAP_DEVICE: 136 dwc3_gadget_exit(dwc); 137 dwc3_event_buffers_cleanup(dwc); 138 break; 139 default: 140 break; 141 } 142 143 spin_lock_irqsave(&dwc->lock, flags); 144 145 dwc3_set_prtcap(dwc, dwc->desired_dr_role); 146 147 dwc->current_dr_role = dwc->desired_dr_role; 148 149 spin_unlock_irqrestore(&dwc->lock, flags); 150 151 switch (dwc->desired_dr_role) { 152 case DWC3_GCTL_PRTCAP_HOST: 153 ret = dwc3_host_init(dwc); 154 if (ret) 155 dev_err(dwc->dev, "failed to initialize host\n"); 156 break; 157 case DWC3_GCTL_PRTCAP_DEVICE: 158 dwc3_event_buffers_setup(dwc); 159 ret = dwc3_gadget_init(dwc); 160 if (ret) 161 dev_err(dwc->dev, "failed to initialize peripheral\n"); 162 break; 163 default: 164 break; 165 } 166 } 167 168 void dwc3_set_mode(struct dwc3 *dwc, u32 mode) 169 { 170 unsigned long flags; 171 172 spin_lock_irqsave(&dwc->lock, flags); 173 dwc->desired_dr_role = mode; 174 spin_unlock_irqrestore(&dwc->lock, flags); 175 176 queue_work(system_power_efficient_wq, &dwc->drd_work); 177 } 178 179 u32 dwc3_core_fifo_space(struct dwc3_ep *dep, u8 type) 180 { 181 struct dwc3 *dwc = dep->dwc; 182 u32 reg; 183 184 dwc3_writel(dwc->regs, DWC3_GDBGFIFOSPACE, 185 DWC3_GDBGFIFOSPACE_NUM(dep->number) | 186 DWC3_GDBGFIFOSPACE_TYPE(type)); 187 188 reg = dwc3_readl(dwc->regs, DWC3_GDBGFIFOSPACE); 189 190 return DWC3_GDBGFIFOSPACE_SPACE_AVAILABLE(reg); 191 } 192 193 /** 194 * dwc3_core_soft_reset - Issues core soft reset and PHY reset 195 * @dwc: pointer to our context structure 196 */ 197 static int dwc3_core_soft_reset(struct dwc3 *dwc) 198 { 199 u32 reg; 200 int retries = 1000; 201 int ret; 202 203 usb_phy_init(dwc->usb2_phy); 204 usb_phy_init(dwc->usb3_phy); 205 ret = phy_init(dwc->usb2_generic_phy); 206 if (ret < 0) 207 return ret; 208 209 ret = phy_init(dwc->usb3_generic_phy); 210 if (ret < 0) { 211 phy_exit(dwc->usb2_generic_phy); 212 return ret; 213 } 214 215 /* 216 * We're resetting only the device side because, if we're in host mode, 217 * XHCI driver will reset the host block. If dwc3 was configured for 218 * host-only mode, then we can return early. 219 */ 220 if (dwc->dr_mode == USB_DR_MODE_HOST) 221 return 0; 222 223 reg = dwc3_readl(dwc->regs, DWC3_DCTL); 224 reg |= DWC3_DCTL_CSFTRST; 225 dwc3_writel(dwc->regs, DWC3_DCTL, reg); 226 227 do { 228 reg = dwc3_readl(dwc->regs, DWC3_DCTL); 229 if (!(reg & DWC3_DCTL_CSFTRST)) 230 return 0; 231 232 udelay(1); 233 } while (--retries); 234 235 return -ETIMEDOUT; 236 } 237 238 /* 239 * dwc3_frame_length_adjustment - Adjusts frame length if required 240 * @dwc3: Pointer to our controller context structure 241 */ 242 static void dwc3_frame_length_adjustment(struct dwc3 *dwc) 243 { 244 u32 reg; 245 u32 dft; 246 247 if (dwc->revision < DWC3_REVISION_250A) 248 return; 249 250 if (dwc->fladj == 0) 251 return; 252 253 reg = dwc3_readl(dwc->regs, DWC3_GFLADJ); 254 dft = reg & DWC3_GFLADJ_30MHZ_MASK; 255 if (!dev_WARN_ONCE(dwc->dev, dft == dwc->fladj, 256 "request value same as default, ignoring\n")) { 257 reg &= ~DWC3_GFLADJ_30MHZ_MASK; 258 reg |= DWC3_GFLADJ_30MHZ_SDBND_SEL | dwc->fladj; 259 dwc3_writel(dwc->regs, DWC3_GFLADJ, reg); 260 } 261 } 262 263 /** 264 * dwc3_free_one_event_buffer - Frees one event buffer 265 * @dwc: Pointer to our controller context structure 266 * @evt: Pointer to event buffer to be freed 267 */ 268 static void dwc3_free_one_event_buffer(struct dwc3 *dwc, 269 struct dwc3_event_buffer *evt) 270 { 271 dma_free_coherent(dwc->sysdev, evt->length, evt->buf, evt->dma); 272 } 273 274 /** 275 * dwc3_alloc_one_event_buffer - Allocates one event buffer structure 276 * @dwc: Pointer to our controller context structure 277 * @length: size of the event buffer 278 * 279 * Returns a pointer to the allocated event buffer structure on success 280 * otherwise ERR_PTR(errno). 281 */ 282 static struct dwc3_event_buffer *dwc3_alloc_one_event_buffer(struct dwc3 *dwc, 283 unsigned length) 284 { 285 struct dwc3_event_buffer *evt; 286 287 evt = devm_kzalloc(dwc->dev, sizeof(*evt), GFP_KERNEL); 288 if (!evt) 289 return ERR_PTR(-ENOMEM); 290 291 evt->dwc = dwc; 292 evt->length = length; 293 evt->cache = devm_kzalloc(dwc->dev, length, GFP_KERNEL); 294 if (!evt->cache) 295 return ERR_PTR(-ENOMEM); 296 297 evt->buf = dma_alloc_coherent(dwc->sysdev, length, 298 &evt->dma, GFP_KERNEL); 299 if (!evt->buf) 300 return ERR_PTR(-ENOMEM); 301 302 return evt; 303 } 304 305 /** 306 * dwc3_free_event_buffers - frees all allocated event buffers 307 * @dwc: Pointer to our controller context structure 308 */ 309 static void dwc3_free_event_buffers(struct dwc3 *dwc) 310 { 311 struct dwc3_event_buffer *evt; 312 313 evt = dwc->ev_buf; 314 if (evt) 315 dwc3_free_one_event_buffer(dwc, evt); 316 } 317 318 /** 319 * dwc3_alloc_event_buffers - Allocates @num event buffers of size @length 320 * @dwc: pointer to our controller context structure 321 * @length: size of event buffer 322 * 323 * Returns 0 on success otherwise negative errno. In the error case, dwc 324 * may contain some buffers allocated but not all which were requested. 325 */ 326 static int dwc3_alloc_event_buffers(struct dwc3 *dwc, unsigned length) 327 { 328 struct dwc3_event_buffer *evt; 329 330 evt = dwc3_alloc_one_event_buffer(dwc, length); 331 if (IS_ERR(evt)) { 332 dev_err(dwc->dev, "can't allocate event buffer\n"); 333 return PTR_ERR(evt); 334 } 335 dwc->ev_buf = evt; 336 337 return 0; 338 } 339 340 /** 341 * dwc3_event_buffers_setup - setup our allocated event buffers 342 * @dwc: pointer to our controller context structure 343 * 344 * Returns 0 on success otherwise negative errno. 345 */ 346 static int dwc3_event_buffers_setup(struct dwc3 *dwc) 347 { 348 struct dwc3_event_buffer *evt; 349 350 evt = dwc->ev_buf; 351 evt->lpos = 0; 352 dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(0), 353 lower_32_bits(evt->dma)); 354 dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(0), 355 upper_32_bits(evt->dma)); 356 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0), 357 DWC3_GEVNTSIZ_SIZE(evt->length)); 358 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), 0); 359 360 return 0; 361 } 362 363 static void dwc3_event_buffers_cleanup(struct dwc3 *dwc) 364 { 365 struct dwc3_event_buffer *evt; 366 367 evt = dwc->ev_buf; 368 369 evt->lpos = 0; 370 371 dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(0), 0); 372 dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(0), 0); 373 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0), DWC3_GEVNTSIZ_INTMASK 374 | DWC3_GEVNTSIZ_SIZE(0)); 375 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), 0); 376 } 377 378 static int dwc3_alloc_scratch_buffers(struct dwc3 *dwc) 379 { 380 if (!dwc->has_hibernation) 381 return 0; 382 383 if (!dwc->nr_scratch) 384 return 0; 385 386 dwc->scratchbuf = kmalloc_array(dwc->nr_scratch, 387 DWC3_SCRATCHBUF_SIZE, GFP_KERNEL); 388 if (!dwc->scratchbuf) 389 return -ENOMEM; 390 391 return 0; 392 } 393 394 static int dwc3_setup_scratch_buffers(struct dwc3 *dwc) 395 { 396 dma_addr_t scratch_addr; 397 u32 param; 398 int ret; 399 400 if (!dwc->has_hibernation) 401 return 0; 402 403 if (!dwc->nr_scratch) 404 return 0; 405 406 /* should never fall here */ 407 if (!WARN_ON(dwc->scratchbuf)) 408 return 0; 409 410 scratch_addr = dma_map_single(dwc->sysdev, dwc->scratchbuf, 411 dwc->nr_scratch * DWC3_SCRATCHBUF_SIZE, 412 DMA_BIDIRECTIONAL); 413 if (dma_mapping_error(dwc->sysdev, scratch_addr)) { 414 dev_err(dwc->sysdev, "failed to map scratch buffer\n"); 415 ret = -EFAULT; 416 goto err0; 417 } 418 419 dwc->scratch_addr = scratch_addr; 420 421 param = lower_32_bits(scratch_addr); 422 423 ret = dwc3_send_gadget_generic_command(dwc, 424 DWC3_DGCMD_SET_SCRATCHPAD_ADDR_LO, param); 425 if (ret < 0) 426 goto err1; 427 428 param = upper_32_bits(scratch_addr); 429 430 ret = dwc3_send_gadget_generic_command(dwc, 431 DWC3_DGCMD_SET_SCRATCHPAD_ADDR_HI, param); 432 if (ret < 0) 433 goto err1; 434 435 return 0; 436 437 err1: 438 dma_unmap_single(dwc->sysdev, dwc->scratch_addr, dwc->nr_scratch * 439 DWC3_SCRATCHBUF_SIZE, DMA_BIDIRECTIONAL); 440 441 err0: 442 return ret; 443 } 444 445 static void dwc3_free_scratch_buffers(struct dwc3 *dwc) 446 { 447 if (!dwc->has_hibernation) 448 return; 449 450 if (!dwc->nr_scratch) 451 return; 452 453 /* should never fall here */ 454 if (!WARN_ON(dwc->scratchbuf)) 455 return; 456 457 dma_unmap_single(dwc->sysdev, dwc->scratch_addr, dwc->nr_scratch * 458 DWC3_SCRATCHBUF_SIZE, DMA_BIDIRECTIONAL); 459 kfree(dwc->scratchbuf); 460 } 461 462 static void dwc3_core_num_eps(struct dwc3 *dwc) 463 { 464 struct dwc3_hwparams *parms = &dwc->hwparams; 465 466 dwc->num_eps = DWC3_NUM_EPS(parms); 467 } 468 469 static void dwc3_cache_hwparams(struct dwc3 *dwc) 470 { 471 struct dwc3_hwparams *parms = &dwc->hwparams; 472 473 parms->hwparams0 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS0); 474 parms->hwparams1 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS1); 475 parms->hwparams2 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS2); 476 parms->hwparams3 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS3); 477 parms->hwparams4 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS4); 478 parms->hwparams5 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS5); 479 parms->hwparams6 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS6); 480 parms->hwparams7 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS7); 481 parms->hwparams8 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS8); 482 } 483 484 /** 485 * dwc3_phy_setup - Configure USB PHY Interface of DWC3 Core 486 * @dwc: Pointer to our controller context structure 487 * 488 * Returns 0 on success. The USB PHY interfaces are configured but not 489 * initialized. The PHY interfaces and the PHYs get initialized together with 490 * the core in dwc3_core_init. 491 */ 492 static int dwc3_phy_setup(struct dwc3 *dwc) 493 { 494 u32 reg; 495 int ret; 496 497 reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0)); 498 499 /* 500 * Make sure UX_EXIT_PX is cleared as that causes issues with some 501 * PHYs. Also, this bit is not supposed to be used in normal operation. 502 */ 503 reg &= ~DWC3_GUSB3PIPECTL_UX_EXIT_PX; 504 505 /* 506 * Above 1.94a, it is recommended to set DWC3_GUSB3PIPECTL_SUSPHY 507 * to '0' during coreConsultant configuration. So default value 508 * will be '0' when the core is reset. Application needs to set it 509 * to '1' after the core initialization is completed. 510 */ 511 if (dwc->revision > DWC3_REVISION_194A) 512 reg |= DWC3_GUSB3PIPECTL_SUSPHY; 513 514 if (dwc->u2ss_inp3_quirk) 515 reg |= DWC3_GUSB3PIPECTL_U2SSINP3OK; 516 517 if (dwc->dis_rxdet_inp3_quirk) 518 reg |= DWC3_GUSB3PIPECTL_DISRXDETINP3; 519 520 if (dwc->req_p1p2p3_quirk) 521 reg |= DWC3_GUSB3PIPECTL_REQP1P2P3; 522 523 if (dwc->del_p1p2p3_quirk) 524 reg |= DWC3_GUSB3PIPECTL_DEP1P2P3_EN; 525 526 if (dwc->del_phy_power_chg_quirk) 527 reg |= DWC3_GUSB3PIPECTL_DEPOCHANGE; 528 529 if (dwc->lfps_filter_quirk) 530 reg |= DWC3_GUSB3PIPECTL_LFPSFILT; 531 532 if (dwc->rx_detect_poll_quirk) 533 reg |= DWC3_GUSB3PIPECTL_RX_DETOPOLL; 534 535 if (dwc->tx_de_emphasis_quirk) 536 reg |= DWC3_GUSB3PIPECTL_TX_DEEPH(dwc->tx_de_emphasis); 537 538 if (dwc->dis_u3_susphy_quirk) 539 reg &= ~DWC3_GUSB3PIPECTL_SUSPHY; 540 541 if (dwc->dis_del_phy_power_chg_quirk) 542 reg &= ~DWC3_GUSB3PIPECTL_DEPOCHANGE; 543 544 dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg); 545 546 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0)); 547 548 /* Select the HS PHY interface */ 549 switch (DWC3_GHWPARAMS3_HSPHY_IFC(dwc->hwparams.hwparams3)) { 550 case DWC3_GHWPARAMS3_HSPHY_IFC_UTMI_ULPI: 551 if (dwc->hsphy_interface && 552 !strncmp(dwc->hsphy_interface, "utmi", 4)) { 553 reg &= ~DWC3_GUSB2PHYCFG_ULPI_UTMI; 554 break; 555 } else if (dwc->hsphy_interface && 556 !strncmp(dwc->hsphy_interface, "ulpi", 4)) { 557 reg |= DWC3_GUSB2PHYCFG_ULPI_UTMI; 558 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg); 559 } else { 560 /* Relying on default value. */ 561 if (!(reg & DWC3_GUSB2PHYCFG_ULPI_UTMI)) 562 break; 563 } 564 /* FALLTHROUGH */ 565 case DWC3_GHWPARAMS3_HSPHY_IFC_ULPI: 566 ret = dwc3_ulpi_init(dwc); 567 if (ret) 568 return ret; 569 /* FALLTHROUGH */ 570 default: 571 break; 572 } 573 574 switch (dwc->hsphy_mode) { 575 case USBPHY_INTERFACE_MODE_UTMI: 576 reg &= ~(DWC3_GUSB2PHYCFG_PHYIF_MASK | 577 DWC3_GUSB2PHYCFG_USBTRDTIM_MASK); 578 reg |= DWC3_GUSB2PHYCFG_PHYIF(UTMI_PHYIF_8_BIT) | 579 DWC3_GUSB2PHYCFG_USBTRDTIM(USBTRDTIM_UTMI_8_BIT); 580 break; 581 case USBPHY_INTERFACE_MODE_UTMIW: 582 reg &= ~(DWC3_GUSB2PHYCFG_PHYIF_MASK | 583 DWC3_GUSB2PHYCFG_USBTRDTIM_MASK); 584 reg |= DWC3_GUSB2PHYCFG_PHYIF(UTMI_PHYIF_16_BIT) | 585 DWC3_GUSB2PHYCFG_USBTRDTIM(USBTRDTIM_UTMI_16_BIT); 586 break; 587 default: 588 break; 589 } 590 591 /* 592 * Above 1.94a, it is recommended to set DWC3_GUSB2PHYCFG_SUSPHY to 593 * '0' during coreConsultant configuration. So default value will 594 * be '0' when the core is reset. Application needs to set it to 595 * '1' after the core initialization is completed. 596 */ 597 if (dwc->revision > DWC3_REVISION_194A) 598 reg |= DWC3_GUSB2PHYCFG_SUSPHY; 599 600 if (dwc->dis_u2_susphy_quirk) 601 reg &= ~DWC3_GUSB2PHYCFG_SUSPHY; 602 603 if (dwc->dis_enblslpm_quirk) 604 reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM; 605 606 if (dwc->dis_u2_freeclk_exists_quirk) 607 reg &= ~DWC3_GUSB2PHYCFG_U2_FREECLK_EXISTS; 608 609 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg); 610 611 return 0; 612 } 613 614 static void dwc3_core_exit(struct dwc3 *dwc) 615 { 616 dwc3_event_buffers_cleanup(dwc); 617 618 usb_phy_shutdown(dwc->usb2_phy); 619 usb_phy_shutdown(dwc->usb3_phy); 620 phy_exit(dwc->usb2_generic_phy); 621 phy_exit(dwc->usb3_generic_phy); 622 623 usb_phy_set_suspend(dwc->usb2_phy, 1); 624 usb_phy_set_suspend(dwc->usb3_phy, 1); 625 phy_power_off(dwc->usb2_generic_phy); 626 phy_power_off(dwc->usb3_generic_phy); 627 } 628 629 static bool dwc3_core_is_valid(struct dwc3 *dwc) 630 { 631 u32 reg; 632 633 reg = dwc3_readl(dwc->regs, DWC3_GSNPSID); 634 635 /* This should read as U3 followed by revision number */ 636 if ((reg & DWC3_GSNPSID_MASK) == 0x55330000) { 637 /* Detected DWC_usb3 IP */ 638 dwc->revision = reg; 639 } else if ((reg & DWC3_GSNPSID_MASK) == 0x33310000) { 640 /* Detected DWC_usb31 IP */ 641 dwc->revision = dwc3_readl(dwc->regs, DWC3_VER_NUMBER); 642 dwc->revision |= DWC3_REVISION_IS_DWC31; 643 } else { 644 return false; 645 } 646 647 return true; 648 } 649 650 static void dwc3_core_setup_global_control(struct dwc3 *dwc) 651 { 652 u32 hwparams4 = dwc->hwparams.hwparams4; 653 u32 reg; 654 655 reg = dwc3_readl(dwc->regs, DWC3_GCTL); 656 reg &= ~DWC3_GCTL_SCALEDOWN_MASK; 657 658 switch (DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1)) { 659 case DWC3_GHWPARAMS1_EN_PWROPT_CLK: 660 /** 661 * WORKAROUND: DWC3 revisions between 2.10a and 2.50a have an 662 * issue which would cause xHCI compliance tests to fail. 663 * 664 * Because of that we cannot enable clock gating on such 665 * configurations. 666 * 667 * Refers to: 668 * 669 * STAR#9000588375: Clock Gating, SOF Issues when ref_clk-Based 670 * SOF/ITP Mode Used 671 */ 672 if ((dwc->dr_mode == USB_DR_MODE_HOST || 673 dwc->dr_mode == USB_DR_MODE_OTG) && 674 (dwc->revision >= DWC3_REVISION_210A && 675 dwc->revision <= DWC3_REVISION_250A)) 676 reg |= DWC3_GCTL_DSBLCLKGTNG | DWC3_GCTL_SOFITPSYNC; 677 else 678 reg &= ~DWC3_GCTL_DSBLCLKGTNG; 679 break; 680 case DWC3_GHWPARAMS1_EN_PWROPT_HIB: 681 /* enable hibernation here */ 682 dwc->nr_scratch = DWC3_GHWPARAMS4_HIBER_SCRATCHBUFS(hwparams4); 683 684 /* 685 * REVISIT Enabling this bit so that host-mode hibernation 686 * will work. Device-mode hibernation is not yet implemented. 687 */ 688 reg |= DWC3_GCTL_GBLHIBERNATIONEN; 689 break; 690 default: 691 /* nothing */ 692 break; 693 } 694 695 /* check if current dwc3 is on simulation board */ 696 if (dwc->hwparams.hwparams6 & DWC3_GHWPARAMS6_EN_FPGA) { 697 dev_info(dwc->dev, "Running with FPGA optmizations\n"); 698 dwc->is_fpga = true; 699 } 700 701 WARN_ONCE(dwc->disable_scramble_quirk && !dwc->is_fpga, 702 "disable_scramble cannot be used on non-FPGA builds\n"); 703 704 if (dwc->disable_scramble_quirk && dwc->is_fpga) 705 reg |= DWC3_GCTL_DISSCRAMBLE; 706 else 707 reg &= ~DWC3_GCTL_DISSCRAMBLE; 708 709 if (dwc->u2exit_lfps_quirk) 710 reg |= DWC3_GCTL_U2EXIT_LFPS; 711 712 /* 713 * WORKAROUND: DWC3 revisions <1.90a have a bug 714 * where the device can fail to connect at SuperSpeed 715 * and falls back to high-speed mode which causes 716 * the device to enter a Connect/Disconnect loop 717 */ 718 if (dwc->revision < DWC3_REVISION_190A) 719 reg |= DWC3_GCTL_U2RSTECN; 720 721 dwc3_writel(dwc->regs, DWC3_GCTL, reg); 722 } 723 724 /** 725 * dwc3_core_init - Low-level initialization of DWC3 Core 726 * @dwc: Pointer to our controller context structure 727 * 728 * Returns 0 on success otherwise negative errno. 729 */ 730 static int dwc3_core_init(struct dwc3 *dwc) 731 { 732 u32 reg; 733 int ret; 734 735 if (!dwc3_core_is_valid(dwc)) { 736 dev_err(dwc->dev, "this is not a DesignWare USB3 DRD Core\n"); 737 ret = -ENODEV; 738 goto err0; 739 } 740 741 /* 742 * Write Linux Version Code to our GUID register so it's easy to figure 743 * out which kernel version a bug was found. 744 */ 745 dwc3_writel(dwc->regs, DWC3_GUID, LINUX_VERSION_CODE); 746 747 /* Handle USB2.0-only core configuration */ 748 if (DWC3_GHWPARAMS3_SSPHY_IFC(dwc->hwparams.hwparams3) == 749 DWC3_GHWPARAMS3_SSPHY_IFC_DIS) { 750 if (dwc->maximum_speed == USB_SPEED_SUPER) 751 dwc->maximum_speed = USB_SPEED_HIGH; 752 } 753 754 ret = dwc3_core_soft_reset(dwc); 755 if (ret) 756 goto err0; 757 758 ret = dwc3_phy_setup(dwc); 759 if (ret) 760 goto err0; 761 762 dwc3_core_setup_global_control(dwc); 763 dwc3_core_num_eps(dwc); 764 765 ret = dwc3_setup_scratch_buffers(dwc); 766 if (ret) 767 goto err1; 768 769 /* Adjust Frame Length */ 770 dwc3_frame_length_adjustment(dwc); 771 772 usb_phy_set_suspend(dwc->usb2_phy, 0); 773 usb_phy_set_suspend(dwc->usb3_phy, 0); 774 ret = phy_power_on(dwc->usb2_generic_phy); 775 if (ret < 0) 776 goto err2; 777 778 ret = phy_power_on(dwc->usb3_generic_phy); 779 if (ret < 0) 780 goto err3; 781 782 ret = dwc3_event_buffers_setup(dwc); 783 if (ret) { 784 dev_err(dwc->dev, "failed to setup event buffers\n"); 785 goto err4; 786 } 787 788 /* 789 * ENDXFER polling is available on version 3.10a and later of 790 * the DWC_usb3 controller. It is NOT available in the 791 * DWC_usb31 controller. 792 */ 793 if (!dwc3_is_usb31(dwc) && dwc->revision >= DWC3_REVISION_310A) { 794 reg = dwc3_readl(dwc->regs, DWC3_GUCTL2); 795 reg |= DWC3_GUCTL2_RST_ACTBITLATER; 796 dwc3_writel(dwc->regs, DWC3_GUCTL2, reg); 797 } 798 799 /* 800 * Enable hardware control of sending remote wakeup in HS when 801 * the device is in the L1 state. 802 */ 803 if (dwc->revision >= DWC3_REVISION_290A) { 804 reg = dwc3_readl(dwc->regs, DWC3_GUCTL1); 805 reg |= DWC3_GUCTL1_DEV_L1_EXIT_BY_HW; 806 dwc3_writel(dwc->regs, DWC3_GUCTL1, reg); 807 } 808 809 return 0; 810 811 err4: 812 phy_power_off(dwc->usb3_generic_phy); 813 814 err3: 815 phy_power_off(dwc->usb2_generic_phy); 816 817 err2: 818 usb_phy_set_suspend(dwc->usb2_phy, 1); 819 usb_phy_set_suspend(dwc->usb3_phy, 1); 820 821 err1: 822 usb_phy_shutdown(dwc->usb2_phy); 823 usb_phy_shutdown(dwc->usb3_phy); 824 phy_exit(dwc->usb2_generic_phy); 825 phy_exit(dwc->usb3_generic_phy); 826 827 err0: 828 return ret; 829 } 830 831 static int dwc3_core_get_phy(struct dwc3 *dwc) 832 { 833 struct device *dev = dwc->dev; 834 struct device_node *node = dev->of_node; 835 int ret; 836 837 if (node) { 838 dwc->usb2_phy = devm_usb_get_phy_by_phandle(dev, "usb-phy", 0); 839 dwc->usb3_phy = devm_usb_get_phy_by_phandle(dev, "usb-phy", 1); 840 } else { 841 dwc->usb2_phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB2); 842 dwc->usb3_phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB3); 843 } 844 845 if (IS_ERR(dwc->usb2_phy)) { 846 ret = PTR_ERR(dwc->usb2_phy); 847 if (ret == -ENXIO || ret == -ENODEV) { 848 dwc->usb2_phy = NULL; 849 } else if (ret == -EPROBE_DEFER) { 850 return ret; 851 } else { 852 dev_err(dev, "no usb2 phy configured\n"); 853 return ret; 854 } 855 } 856 857 if (IS_ERR(dwc->usb3_phy)) { 858 ret = PTR_ERR(dwc->usb3_phy); 859 if (ret == -ENXIO || ret == -ENODEV) { 860 dwc->usb3_phy = NULL; 861 } else if (ret == -EPROBE_DEFER) { 862 return ret; 863 } else { 864 dev_err(dev, "no usb3 phy configured\n"); 865 return ret; 866 } 867 } 868 869 dwc->usb2_generic_phy = devm_phy_get(dev, "usb2-phy"); 870 if (IS_ERR(dwc->usb2_generic_phy)) { 871 ret = PTR_ERR(dwc->usb2_generic_phy); 872 if (ret == -ENOSYS || ret == -ENODEV) { 873 dwc->usb2_generic_phy = NULL; 874 } else if (ret == -EPROBE_DEFER) { 875 return ret; 876 } else { 877 dev_err(dev, "no usb2 phy configured\n"); 878 return ret; 879 } 880 } 881 882 dwc->usb3_generic_phy = devm_phy_get(dev, "usb3-phy"); 883 if (IS_ERR(dwc->usb3_generic_phy)) { 884 ret = PTR_ERR(dwc->usb3_generic_phy); 885 if (ret == -ENOSYS || ret == -ENODEV) { 886 dwc->usb3_generic_phy = NULL; 887 } else if (ret == -EPROBE_DEFER) { 888 return ret; 889 } else { 890 dev_err(dev, "no usb3 phy configured\n"); 891 return ret; 892 } 893 } 894 895 return 0; 896 } 897 898 static int dwc3_core_init_mode(struct dwc3 *dwc) 899 { 900 struct device *dev = dwc->dev; 901 int ret; 902 903 switch (dwc->dr_mode) { 904 case USB_DR_MODE_PERIPHERAL: 905 dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_DEVICE); 906 ret = dwc3_gadget_init(dwc); 907 if (ret) { 908 if (ret != -EPROBE_DEFER) 909 dev_err(dev, "failed to initialize gadget\n"); 910 return ret; 911 } 912 break; 913 case USB_DR_MODE_HOST: 914 dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_HOST); 915 ret = dwc3_host_init(dwc); 916 if (ret) { 917 if (ret != -EPROBE_DEFER) 918 dev_err(dev, "failed to initialize host\n"); 919 return ret; 920 } 921 break; 922 case USB_DR_MODE_OTG: 923 INIT_WORK(&dwc->drd_work, __dwc3_set_mode); 924 ret = dwc3_drd_init(dwc); 925 if (ret) { 926 if (ret != -EPROBE_DEFER) 927 dev_err(dev, "failed to initialize dual-role\n"); 928 return ret; 929 } 930 break; 931 default: 932 dev_err(dev, "Unsupported mode of operation %d\n", dwc->dr_mode); 933 return -EINVAL; 934 } 935 936 return 0; 937 } 938 939 static void dwc3_core_exit_mode(struct dwc3 *dwc) 940 { 941 switch (dwc->dr_mode) { 942 case USB_DR_MODE_PERIPHERAL: 943 dwc3_gadget_exit(dwc); 944 break; 945 case USB_DR_MODE_HOST: 946 dwc3_host_exit(dwc); 947 break; 948 case USB_DR_MODE_OTG: 949 dwc3_drd_exit(dwc); 950 break; 951 default: 952 /* do nothing */ 953 break; 954 } 955 } 956 957 static void dwc3_get_properties(struct dwc3 *dwc) 958 { 959 struct device *dev = dwc->dev; 960 u8 lpm_nyet_threshold; 961 u8 tx_de_emphasis; 962 u8 hird_threshold; 963 964 /* default to highest possible threshold */ 965 lpm_nyet_threshold = 0xff; 966 967 /* default to -3.5dB de-emphasis */ 968 tx_de_emphasis = 1; 969 970 /* 971 * default to assert utmi_sleep_n and use maximum allowed HIRD 972 * threshold value of 0b1100 973 */ 974 hird_threshold = 12; 975 976 dwc->maximum_speed = usb_get_maximum_speed(dev); 977 dwc->dr_mode = usb_get_dr_mode(dev); 978 dwc->hsphy_mode = of_usb_get_phy_mode(dev->of_node); 979 980 dwc->sysdev_is_parent = device_property_read_bool(dev, 981 "linux,sysdev_is_parent"); 982 if (dwc->sysdev_is_parent) 983 dwc->sysdev = dwc->dev->parent; 984 else 985 dwc->sysdev = dwc->dev; 986 987 dwc->has_lpm_erratum = device_property_read_bool(dev, 988 "snps,has-lpm-erratum"); 989 device_property_read_u8(dev, "snps,lpm-nyet-threshold", 990 &lpm_nyet_threshold); 991 dwc->is_utmi_l1_suspend = device_property_read_bool(dev, 992 "snps,is-utmi-l1-suspend"); 993 device_property_read_u8(dev, "snps,hird-threshold", 994 &hird_threshold); 995 dwc->usb3_lpm_capable = device_property_read_bool(dev, 996 "snps,usb3_lpm_capable"); 997 998 dwc->disable_scramble_quirk = device_property_read_bool(dev, 999 "snps,disable_scramble_quirk"); 1000 dwc->u2exit_lfps_quirk = device_property_read_bool(dev, 1001 "snps,u2exit_lfps_quirk"); 1002 dwc->u2ss_inp3_quirk = device_property_read_bool(dev, 1003 "snps,u2ss_inp3_quirk"); 1004 dwc->req_p1p2p3_quirk = device_property_read_bool(dev, 1005 "snps,req_p1p2p3_quirk"); 1006 dwc->del_p1p2p3_quirk = device_property_read_bool(dev, 1007 "snps,del_p1p2p3_quirk"); 1008 dwc->del_phy_power_chg_quirk = device_property_read_bool(dev, 1009 "snps,del_phy_power_chg_quirk"); 1010 dwc->lfps_filter_quirk = device_property_read_bool(dev, 1011 "snps,lfps_filter_quirk"); 1012 dwc->rx_detect_poll_quirk = device_property_read_bool(dev, 1013 "snps,rx_detect_poll_quirk"); 1014 dwc->dis_u3_susphy_quirk = device_property_read_bool(dev, 1015 "snps,dis_u3_susphy_quirk"); 1016 dwc->dis_u2_susphy_quirk = device_property_read_bool(dev, 1017 "snps,dis_u2_susphy_quirk"); 1018 dwc->dis_enblslpm_quirk = device_property_read_bool(dev, 1019 "snps,dis_enblslpm_quirk"); 1020 dwc->dis_rxdet_inp3_quirk = device_property_read_bool(dev, 1021 "snps,dis_rxdet_inp3_quirk"); 1022 dwc->dis_u2_freeclk_exists_quirk = device_property_read_bool(dev, 1023 "snps,dis-u2-freeclk-exists-quirk"); 1024 dwc->dis_del_phy_power_chg_quirk = device_property_read_bool(dev, 1025 "snps,dis-del-phy-power-chg-quirk"); 1026 1027 dwc->tx_de_emphasis_quirk = device_property_read_bool(dev, 1028 "snps,tx_de_emphasis_quirk"); 1029 device_property_read_u8(dev, "snps,tx_de_emphasis", 1030 &tx_de_emphasis); 1031 device_property_read_string(dev, "snps,hsphy_interface", 1032 &dwc->hsphy_interface); 1033 device_property_read_u32(dev, "snps,quirk-frame-length-adjustment", 1034 &dwc->fladj); 1035 1036 dwc->lpm_nyet_threshold = lpm_nyet_threshold; 1037 dwc->tx_de_emphasis = tx_de_emphasis; 1038 1039 dwc->hird_threshold = hird_threshold 1040 | (dwc->is_utmi_l1_suspend << 4); 1041 1042 dwc->imod_interval = 0; 1043 } 1044 1045 /* check whether the core supports IMOD */ 1046 bool dwc3_has_imod(struct dwc3 *dwc) 1047 { 1048 return ((dwc3_is_usb3(dwc) && 1049 dwc->revision >= DWC3_REVISION_300A) || 1050 (dwc3_is_usb31(dwc) && 1051 dwc->revision >= DWC3_USB31_REVISION_120A)); 1052 } 1053 1054 static void dwc3_check_params(struct dwc3 *dwc) 1055 { 1056 struct device *dev = dwc->dev; 1057 1058 /* Check for proper value of imod_interval */ 1059 if (dwc->imod_interval && !dwc3_has_imod(dwc)) { 1060 dev_warn(dwc->dev, "Interrupt moderation not supported\n"); 1061 dwc->imod_interval = 0; 1062 } 1063 1064 /* 1065 * Workaround for STAR 9000961433 which affects only version 1066 * 3.00a of the DWC_usb3 core. This prevents the controller 1067 * interrupt from being masked while handling events. IMOD 1068 * allows us to work around this issue. Enable it for the 1069 * affected version. 1070 */ 1071 if (!dwc->imod_interval && 1072 (dwc->revision == DWC3_REVISION_300A)) 1073 dwc->imod_interval = 1; 1074 1075 /* Check the maximum_speed parameter */ 1076 switch (dwc->maximum_speed) { 1077 case USB_SPEED_LOW: 1078 case USB_SPEED_FULL: 1079 case USB_SPEED_HIGH: 1080 case USB_SPEED_SUPER: 1081 case USB_SPEED_SUPER_PLUS: 1082 break; 1083 default: 1084 dev_err(dev, "invalid maximum_speed parameter %d\n", 1085 dwc->maximum_speed); 1086 /* fall through */ 1087 case USB_SPEED_UNKNOWN: 1088 /* default to superspeed */ 1089 dwc->maximum_speed = USB_SPEED_SUPER; 1090 1091 /* 1092 * default to superspeed plus if we are capable. 1093 */ 1094 if (dwc3_is_usb31(dwc) && 1095 (DWC3_GHWPARAMS3_SSPHY_IFC(dwc->hwparams.hwparams3) == 1096 DWC3_GHWPARAMS3_SSPHY_IFC_GEN2)) 1097 dwc->maximum_speed = USB_SPEED_SUPER_PLUS; 1098 1099 break; 1100 } 1101 } 1102 1103 static int dwc3_probe(struct platform_device *pdev) 1104 { 1105 struct device *dev = &pdev->dev; 1106 struct resource *res; 1107 struct dwc3 *dwc; 1108 1109 int ret; 1110 1111 void __iomem *regs; 1112 1113 dwc = devm_kzalloc(dev, sizeof(*dwc), GFP_KERNEL); 1114 if (!dwc) 1115 return -ENOMEM; 1116 1117 dwc->dev = dev; 1118 1119 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1120 if (!res) { 1121 dev_err(dev, "missing memory resource\n"); 1122 return -ENODEV; 1123 } 1124 1125 dwc->xhci_resources[0].start = res->start; 1126 dwc->xhci_resources[0].end = dwc->xhci_resources[0].start + 1127 DWC3_XHCI_REGS_END; 1128 dwc->xhci_resources[0].flags = res->flags; 1129 dwc->xhci_resources[0].name = res->name; 1130 1131 res->start += DWC3_GLOBALS_REGS_START; 1132 1133 /* 1134 * Request memory region but exclude xHCI regs, 1135 * since it will be requested by the xhci-plat driver. 1136 */ 1137 regs = devm_ioremap_resource(dev, res); 1138 if (IS_ERR(regs)) { 1139 ret = PTR_ERR(regs); 1140 goto err0; 1141 } 1142 1143 dwc->regs = regs; 1144 dwc->regs_size = resource_size(res); 1145 1146 dwc3_get_properties(dwc); 1147 1148 platform_set_drvdata(pdev, dwc); 1149 dwc3_cache_hwparams(dwc); 1150 1151 ret = dwc3_core_get_phy(dwc); 1152 if (ret) 1153 goto err0; 1154 1155 spin_lock_init(&dwc->lock); 1156 1157 pm_runtime_set_active(dev); 1158 pm_runtime_use_autosuspend(dev); 1159 pm_runtime_set_autosuspend_delay(dev, DWC3_DEFAULT_AUTOSUSPEND_DELAY); 1160 pm_runtime_enable(dev); 1161 ret = pm_runtime_get_sync(dev); 1162 if (ret < 0) 1163 goto err1; 1164 1165 pm_runtime_forbid(dev); 1166 1167 ret = dwc3_alloc_event_buffers(dwc, DWC3_EVENT_BUFFERS_SIZE); 1168 if (ret) { 1169 dev_err(dwc->dev, "failed to allocate event buffers\n"); 1170 ret = -ENOMEM; 1171 goto err2; 1172 } 1173 1174 ret = dwc3_get_dr_mode(dwc); 1175 if (ret) 1176 goto err3; 1177 1178 ret = dwc3_alloc_scratch_buffers(dwc); 1179 if (ret) 1180 goto err3; 1181 1182 ret = dwc3_core_init(dwc); 1183 if (ret) { 1184 dev_err(dev, "failed to initialize core\n"); 1185 goto err4; 1186 } 1187 1188 dwc3_check_params(dwc); 1189 1190 ret = dwc3_core_init_mode(dwc); 1191 if (ret) 1192 goto err5; 1193 1194 dwc3_debugfs_init(dwc); 1195 pm_runtime_put(dev); 1196 1197 return 0; 1198 1199 err5: 1200 dwc3_event_buffers_cleanup(dwc); 1201 1202 err4: 1203 dwc3_free_scratch_buffers(dwc); 1204 1205 err3: 1206 dwc3_free_event_buffers(dwc); 1207 dwc3_ulpi_exit(dwc); 1208 1209 err2: 1210 pm_runtime_allow(&pdev->dev); 1211 1212 err1: 1213 pm_runtime_put_sync(&pdev->dev); 1214 pm_runtime_disable(&pdev->dev); 1215 1216 err0: 1217 /* 1218 * restore res->start back to its original value so that, in case the 1219 * probe is deferred, we don't end up getting error in request the 1220 * memory region the next time probe is called. 1221 */ 1222 res->start -= DWC3_GLOBALS_REGS_START; 1223 1224 return ret; 1225 } 1226 1227 static int dwc3_remove(struct platform_device *pdev) 1228 { 1229 struct dwc3 *dwc = platform_get_drvdata(pdev); 1230 struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1231 1232 pm_runtime_get_sync(&pdev->dev); 1233 /* 1234 * restore res->start back to its original value so that, in case the 1235 * probe is deferred, we don't end up getting error in request the 1236 * memory region the next time probe is called. 1237 */ 1238 res->start -= DWC3_GLOBALS_REGS_START; 1239 1240 dwc3_debugfs_exit(dwc); 1241 dwc3_core_exit_mode(dwc); 1242 1243 dwc3_core_exit(dwc); 1244 dwc3_ulpi_exit(dwc); 1245 1246 pm_runtime_put_sync(&pdev->dev); 1247 pm_runtime_allow(&pdev->dev); 1248 pm_runtime_disable(&pdev->dev); 1249 1250 dwc3_free_event_buffers(dwc); 1251 dwc3_free_scratch_buffers(dwc); 1252 1253 return 0; 1254 } 1255 1256 #ifdef CONFIG_PM 1257 static int dwc3_suspend_common(struct dwc3 *dwc) 1258 { 1259 unsigned long flags; 1260 1261 switch (dwc->dr_mode) { 1262 case USB_DR_MODE_PERIPHERAL: 1263 case USB_DR_MODE_OTG: 1264 spin_lock_irqsave(&dwc->lock, flags); 1265 dwc3_gadget_suspend(dwc); 1266 spin_unlock_irqrestore(&dwc->lock, flags); 1267 break; 1268 case USB_DR_MODE_HOST: 1269 default: 1270 /* do nothing */ 1271 break; 1272 } 1273 1274 dwc3_core_exit(dwc); 1275 1276 return 0; 1277 } 1278 1279 static int dwc3_resume_common(struct dwc3 *dwc) 1280 { 1281 unsigned long flags; 1282 int ret; 1283 1284 ret = dwc3_core_init(dwc); 1285 if (ret) 1286 return ret; 1287 1288 switch (dwc->dr_mode) { 1289 case USB_DR_MODE_PERIPHERAL: 1290 case USB_DR_MODE_OTG: 1291 spin_lock_irqsave(&dwc->lock, flags); 1292 dwc3_gadget_resume(dwc); 1293 spin_unlock_irqrestore(&dwc->lock, flags); 1294 /* FALLTHROUGH */ 1295 case USB_DR_MODE_HOST: 1296 default: 1297 /* do nothing */ 1298 break; 1299 } 1300 1301 return 0; 1302 } 1303 1304 static int dwc3_runtime_checks(struct dwc3 *dwc) 1305 { 1306 switch (dwc->dr_mode) { 1307 case USB_DR_MODE_PERIPHERAL: 1308 case USB_DR_MODE_OTG: 1309 if (dwc->connected) 1310 return -EBUSY; 1311 break; 1312 case USB_DR_MODE_HOST: 1313 default: 1314 /* do nothing */ 1315 break; 1316 } 1317 1318 return 0; 1319 } 1320 1321 static int dwc3_runtime_suspend(struct device *dev) 1322 { 1323 struct dwc3 *dwc = dev_get_drvdata(dev); 1324 int ret; 1325 1326 if (dwc3_runtime_checks(dwc)) 1327 return -EBUSY; 1328 1329 ret = dwc3_suspend_common(dwc); 1330 if (ret) 1331 return ret; 1332 1333 device_init_wakeup(dev, true); 1334 1335 return 0; 1336 } 1337 1338 static int dwc3_runtime_resume(struct device *dev) 1339 { 1340 struct dwc3 *dwc = dev_get_drvdata(dev); 1341 int ret; 1342 1343 device_init_wakeup(dev, false); 1344 1345 ret = dwc3_resume_common(dwc); 1346 if (ret) 1347 return ret; 1348 1349 switch (dwc->dr_mode) { 1350 case USB_DR_MODE_PERIPHERAL: 1351 case USB_DR_MODE_OTG: 1352 dwc3_gadget_process_pending_events(dwc); 1353 break; 1354 case USB_DR_MODE_HOST: 1355 default: 1356 /* do nothing */ 1357 break; 1358 } 1359 1360 pm_runtime_mark_last_busy(dev); 1361 pm_runtime_put(dev); 1362 1363 return 0; 1364 } 1365 1366 static int dwc3_runtime_idle(struct device *dev) 1367 { 1368 struct dwc3 *dwc = dev_get_drvdata(dev); 1369 1370 switch (dwc->dr_mode) { 1371 case USB_DR_MODE_PERIPHERAL: 1372 case USB_DR_MODE_OTG: 1373 if (dwc3_runtime_checks(dwc)) 1374 return -EBUSY; 1375 break; 1376 case USB_DR_MODE_HOST: 1377 default: 1378 /* do nothing */ 1379 break; 1380 } 1381 1382 pm_runtime_mark_last_busy(dev); 1383 pm_runtime_autosuspend(dev); 1384 1385 return 0; 1386 } 1387 #endif /* CONFIG_PM */ 1388 1389 #ifdef CONFIG_PM_SLEEP 1390 static int dwc3_suspend(struct device *dev) 1391 { 1392 struct dwc3 *dwc = dev_get_drvdata(dev); 1393 int ret; 1394 1395 ret = dwc3_suspend_common(dwc); 1396 if (ret) 1397 return ret; 1398 1399 pinctrl_pm_select_sleep_state(dev); 1400 1401 return 0; 1402 } 1403 1404 static int dwc3_resume(struct device *dev) 1405 { 1406 struct dwc3 *dwc = dev_get_drvdata(dev); 1407 int ret; 1408 1409 pinctrl_pm_select_default_state(dev); 1410 1411 ret = dwc3_resume_common(dwc); 1412 if (ret) 1413 return ret; 1414 1415 pm_runtime_disable(dev); 1416 pm_runtime_set_active(dev); 1417 pm_runtime_enable(dev); 1418 1419 return 0; 1420 } 1421 #endif /* CONFIG_PM_SLEEP */ 1422 1423 static const struct dev_pm_ops dwc3_dev_pm_ops = { 1424 SET_SYSTEM_SLEEP_PM_OPS(dwc3_suspend, dwc3_resume) 1425 SET_RUNTIME_PM_OPS(dwc3_runtime_suspend, dwc3_runtime_resume, 1426 dwc3_runtime_idle) 1427 }; 1428 1429 #ifdef CONFIG_OF 1430 static const struct of_device_id of_dwc3_match[] = { 1431 { 1432 .compatible = "snps,dwc3" 1433 }, 1434 { 1435 .compatible = "synopsys,dwc3" 1436 }, 1437 { }, 1438 }; 1439 MODULE_DEVICE_TABLE(of, of_dwc3_match); 1440 #endif 1441 1442 #ifdef CONFIG_ACPI 1443 1444 #define ACPI_ID_INTEL_BSW "808622B7" 1445 1446 static const struct acpi_device_id dwc3_acpi_match[] = { 1447 { ACPI_ID_INTEL_BSW, 0 }, 1448 { }, 1449 }; 1450 MODULE_DEVICE_TABLE(acpi, dwc3_acpi_match); 1451 #endif 1452 1453 static struct platform_driver dwc3_driver = { 1454 .probe = dwc3_probe, 1455 .remove = dwc3_remove, 1456 .driver = { 1457 .name = "dwc3", 1458 .of_match_table = of_match_ptr(of_dwc3_match), 1459 .acpi_match_table = ACPI_PTR(dwc3_acpi_match), 1460 .pm = &dwc3_dev_pm_ops, 1461 }, 1462 }; 1463 1464 module_platform_driver(dwc3_driver); 1465 1466 MODULE_ALIAS("platform:dwc3"); 1467 MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>"); 1468 MODULE_LICENSE("GPL v2"); 1469 MODULE_DESCRIPTION("DesignWare USB3 DRD Controller Driver"); 1470