1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * core.c - DesignWare USB3 DRD Controller Core file 4 * 5 * Copyright (C) 2010-2011 Texas Instruments Incorporated - https://www.ti.com 6 * 7 * Authors: Felipe Balbi <balbi@ti.com>, 8 * Sebastian Andrzej Siewior <bigeasy@linutronix.de> 9 */ 10 11 #include <linux/clk.h> 12 #include <linux/version.h> 13 #include <linux/module.h> 14 #include <linux/kernel.h> 15 #include <linux/slab.h> 16 #include <linux/spinlock.h> 17 #include <linux/platform_device.h> 18 #include <linux/pm_runtime.h> 19 #include <linux/interrupt.h> 20 #include <linux/ioport.h> 21 #include <linux/io.h> 22 #include <linux/list.h> 23 #include <linux/delay.h> 24 #include <linux/dma-mapping.h> 25 #include <linux/of.h> 26 #include <linux/of_graph.h> 27 #include <linux/acpi.h> 28 #include <linux/pinctrl/consumer.h> 29 #include <linux/reset.h> 30 #include <linux/bitfield.h> 31 32 #include <linux/usb/ch9.h> 33 #include <linux/usb/gadget.h> 34 #include <linux/usb/of.h> 35 #include <linux/usb/otg.h> 36 37 #include "core.h" 38 #include "gadget.h" 39 #include "io.h" 40 41 #include "debug.h" 42 43 #define DWC3_DEFAULT_AUTOSUSPEND_DELAY 5000 /* ms */ 44 45 /** 46 * dwc3_get_dr_mode - Validates and sets dr_mode 47 * @dwc: pointer to our context structure 48 */ 49 static int dwc3_get_dr_mode(struct dwc3 *dwc) 50 { 51 enum usb_dr_mode mode; 52 struct device *dev = dwc->dev; 53 unsigned int hw_mode; 54 55 if (dwc->dr_mode == USB_DR_MODE_UNKNOWN) 56 dwc->dr_mode = USB_DR_MODE_OTG; 57 58 mode = dwc->dr_mode; 59 hw_mode = DWC3_GHWPARAMS0_MODE(dwc->hwparams.hwparams0); 60 61 switch (hw_mode) { 62 case DWC3_GHWPARAMS0_MODE_GADGET: 63 if (IS_ENABLED(CONFIG_USB_DWC3_HOST)) { 64 dev_err(dev, 65 "Controller does not support host mode.\n"); 66 return -EINVAL; 67 } 68 mode = USB_DR_MODE_PERIPHERAL; 69 break; 70 case DWC3_GHWPARAMS0_MODE_HOST: 71 if (IS_ENABLED(CONFIG_USB_DWC3_GADGET)) { 72 dev_err(dev, 73 "Controller does not support device mode.\n"); 74 return -EINVAL; 75 } 76 mode = USB_DR_MODE_HOST; 77 break; 78 default: 79 if (IS_ENABLED(CONFIG_USB_DWC3_HOST)) 80 mode = USB_DR_MODE_HOST; 81 else if (IS_ENABLED(CONFIG_USB_DWC3_GADGET)) 82 mode = USB_DR_MODE_PERIPHERAL; 83 84 /* 85 * DWC_usb31 and DWC_usb3 v3.30a and higher do not support OTG 86 * mode. If the controller supports DRD but the dr_mode is not 87 * specified or set to OTG, then set the mode to peripheral. 88 */ 89 if (mode == USB_DR_MODE_OTG && !dwc->edev && 90 (!IS_ENABLED(CONFIG_USB_ROLE_SWITCH) || 91 !device_property_read_bool(dwc->dev, "usb-role-switch")) && 92 !DWC3_VER_IS_PRIOR(DWC3, 330A)) 93 mode = USB_DR_MODE_PERIPHERAL; 94 } 95 96 if (mode != dwc->dr_mode) { 97 dev_warn(dev, 98 "Configuration mismatch. dr_mode forced to %s\n", 99 mode == USB_DR_MODE_HOST ? "host" : "gadget"); 100 101 dwc->dr_mode = mode; 102 } 103 104 return 0; 105 } 106 107 void dwc3_set_prtcap(struct dwc3 *dwc, u32 mode) 108 { 109 u32 reg; 110 111 reg = dwc3_readl(dwc->regs, DWC3_GCTL); 112 reg &= ~(DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_OTG)); 113 reg |= DWC3_GCTL_PRTCAPDIR(mode); 114 dwc3_writel(dwc->regs, DWC3_GCTL, reg); 115 116 dwc->current_dr_role = mode; 117 } 118 119 static void __dwc3_set_mode(struct work_struct *work) 120 { 121 struct dwc3 *dwc = work_to_dwc(work); 122 unsigned long flags; 123 int ret; 124 u32 reg; 125 u32 desired_dr_role; 126 127 mutex_lock(&dwc->mutex); 128 spin_lock_irqsave(&dwc->lock, flags); 129 desired_dr_role = dwc->desired_dr_role; 130 spin_unlock_irqrestore(&dwc->lock, flags); 131 132 pm_runtime_get_sync(dwc->dev); 133 134 if (dwc->current_dr_role == DWC3_GCTL_PRTCAP_OTG) 135 dwc3_otg_update(dwc, 0); 136 137 if (!desired_dr_role) 138 goto out; 139 140 if (desired_dr_role == dwc->current_dr_role) 141 goto out; 142 143 if (desired_dr_role == DWC3_GCTL_PRTCAP_OTG && dwc->edev) 144 goto out; 145 146 switch (dwc->current_dr_role) { 147 case DWC3_GCTL_PRTCAP_HOST: 148 dwc3_host_exit(dwc); 149 break; 150 case DWC3_GCTL_PRTCAP_DEVICE: 151 dwc3_gadget_exit(dwc); 152 dwc3_event_buffers_cleanup(dwc); 153 break; 154 case DWC3_GCTL_PRTCAP_OTG: 155 dwc3_otg_exit(dwc); 156 spin_lock_irqsave(&dwc->lock, flags); 157 dwc->desired_otg_role = DWC3_OTG_ROLE_IDLE; 158 spin_unlock_irqrestore(&dwc->lock, flags); 159 dwc3_otg_update(dwc, 1); 160 break; 161 default: 162 break; 163 } 164 165 /* 166 * When current_dr_role is not set, there's no role switching. 167 * Only perform GCTL.CoreSoftReset when there's DRD role switching. 168 */ 169 if (dwc->current_dr_role && ((DWC3_IP_IS(DWC3) || 170 DWC3_VER_IS_PRIOR(DWC31, 190A)) && 171 desired_dr_role != DWC3_GCTL_PRTCAP_OTG)) { 172 reg = dwc3_readl(dwc->regs, DWC3_GCTL); 173 reg |= DWC3_GCTL_CORESOFTRESET; 174 dwc3_writel(dwc->regs, DWC3_GCTL, reg); 175 176 /* 177 * Wait for internal clocks to synchronized. DWC_usb31 and 178 * DWC_usb32 may need at least 50ms (less for DWC_usb3). To 179 * keep it consistent across different IPs, let's wait up to 180 * 100ms before clearing GCTL.CORESOFTRESET. 181 */ 182 msleep(100); 183 184 reg = dwc3_readl(dwc->regs, DWC3_GCTL); 185 reg &= ~DWC3_GCTL_CORESOFTRESET; 186 dwc3_writel(dwc->regs, DWC3_GCTL, reg); 187 } 188 189 spin_lock_irqsave(&dwc->lock, flags); 190 191 dwc3_set_prtcap(dwc, desired_dr_role); 192 193 spin_unlock_irqrestore(&dwc->lock, flags); 194 195 switch (desired_dr_role) { 196 case DWC3_GCTL_PRTCAP_HOST: 197 ret = dwc3_host_init(dwc); 198 if (ret) { 199 dev_err(dwc->dev, "failed to initialize host\n"); 200 } else { 201 if (dwc->usb2_phy) 202 otg_set_vbus(dwc->usb2_phy->otg, true); 203 phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_HOST); 204 phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_HOST); 205 if (dwc->dis_split_quirk) { 206 reg = dwc3_readl(dwc->regs, DWC3_GUCTL3); 207 reg |= DWC3_GUCTL3_SPLITDISABLE; 208 dwc3_writel(dwc->regs, DWC3_GUCTL3, reg); 209 } 210 } 211 break; 212 case DWC3_GCTL_PRTCAP_DEVICE: 213 dwc3_core_soft_reset(dwc); 214 215 dwc3_event_buffers_setup(dwc); 216 217 if (dwc->usb2_phy) 218 otg_set_vbus(dwc->usb2_phy->otg, false); 219 phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_DEVICE); 220 phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_DEVICE); 221 222 ret = dwc3_gadget_init(dwc); 223 if (ret) 224 dev_err(dwc->dev, "failed to initialize peripheral\n"); 225 break; 226 case DWC3_GCTL_PRTCAP_OTG: 227 dwc3_otg_init(dwc); 228 dwc3_otg_update(dwc, 0); 229 break; 230 default: 231 break; 232 } 233 234 out: 235 pm_runtime_mark_last_busy(dwc->dev); 236 pm_runtime_put_autosuspend(dwc->dev); 237 mutex_unlock(&dwc->mutex); 238 } 239 240 void dwc3_set_mode(struct dwc3 *dwc, u32 mode) 241 { 242 unsigned long flags; 243 244 if (dwc->dr_mode != USB_DR_MODE_OTG) 245 return; 246 247 spin_lock_irqsave(&dwc->lock, flags); 248 dwc->desired_dr_role = mode; 249 spin_unlock_irqrestore(&dwc->lock, flags); 250 251 queue_work(system_freezable_wq, &dwc->drd_work); 252 } 253 254 u32 dwc3_core_fifo_space(struct dwc3_ep *dep, u8 type) 255 { 256 struct dwc3 *dwc = dep->dwc; 257 u32 reg; 258 259 dwc3_writel(dwc->regs, DWC3_GDBGFIFOSPACE, 260 DWC3_GDBGFIFOSPACE_NUM(dep->number) | 261 DWC3_GDBGFIFOSPACE_TYPE(type)); 262 263 reg = dwc3_readl(dwc->regs, DWC3_GDBGFIFOSPACE); 264 265 return DWC3_GDBGFIFOSPACE_SPACE_AVAILABLE(reg); 266 } 267 268 /** 269 * dwc3_core_soft_reset - Issues core soft reset and PHY reset 270 * @dwc: pointer to our context structure 271 */ 272 int dwc3_core_soft_reset(struct dwc3 *dwc) 273 { 274 u32 reg; 275 int retries = 1000; 276 277 /* 278 * We're resetting only the device side because, if we're in host mode, 279 * XHCI driver will reset the host block. If dwc3 was configured for 280 * host-only mode, then we can return early. 281 */ 282 if (dwc->current_dr_role == DWC3_GCTL_PRTCAP_HOST) 283 return 0; 284 285 reg = dwc3_readl(dwc->regs, DWC3_DCTL); 286 reg |= DWC3_DCTL_CSFTRST; 287 reg &= ~DWC3_DCTL_RUN_STOP; 288 dwc3_gadget_dctl_write_safe(dwc, reg); 289 290 /* 291 * For DWC_usb31 controller 1.90a and later, the DCTL.CSFRST bit 292 * is cleared only after all the clocks are synchronized. This can 293 * take a little more than 50ms. Set the polling rate at 20ms 294 * for 10 times instead. 295 */ 296 if (DWC3_VER_IS_WITHIN(DWC31, 190A, ANY) || DWC3_IP_IS(DWC32)) 297 retries = 10; 298 299 do { 300 reg = dwc3_readl(dwc->regs, DWC3_DCTL); 301 if (!(reg & DWC3_DCTL_CSFTRST)) 302 goto done; 303 304 if (DWC3_VER_IS_WITHIN(DWC31, 190A, ANY) || DWC3_IP_IS(DWC32)) 305 msleep(20); 306 else 307 udelay(1); 308 } while (--retries); 309 310 dev_warn(dwc->dev, "DWC3 controller soft reset failed.\n"); 311 return -ETIMEDOUT; 312 313 done: 314 /* 315 * For DWC_usb31 controller 1.80a and prior, once DCTL.CSFRST bit 316 * is cleared, we must wait at least 50ms before accessing the PHY 317 * domain (synchronization delay). 318 */ 319 if (DWC3_VER_IS_WITHIN(DWC31, ANY, 180A)) 320 msleep(50); 321 322 return 0; 323 } 324 325 /* 326 * dwc3_frame_length_adjustment - Adjusts frame length if required 327 * @dwc3: Pointer to our controller context structure 328 */ 329 static void dwc3_frame_length_adjustment(struct dwc3 *dwc) 330 { 331 u32 reg; 332 u32 dft; 333 334 if (DWC3_VER_IS_PRIOR(DWC3, 250A)) 335 return; 336 337 if (dwc->fladj == 0) 338 return; 339 340 reg = dwc3_readl(dwc->regs, DWC3_GFLADJ); 341 dft = reg & DWC3_GFLADJ_30MHZ_MASK; 342 if (dft != dwc->fladj) { 343 reg &= ~DWC3_GFLADJ_30MHZ_MASK; 344 reg |= DWC3_GFLADJ_30MHZ_SDBND_SEL | dwc->fladj; 345 dwc3_writel(dwc->regs, DWC3_GFLADJ, reg); 346 } 347 } 348 349 /** 350 * dwc3_ref_clk_period - Reference clock period configuration 351 * Default reference clock period depends on hardware 352 * configuration. For systems with reference clock that differs 353 * from the default, this will set clock period in DWC3_GUCTL 354 * register. 355 * @dwc: Pointer to our controller context structure 356 */ 357 static void dwc3_ref_clk_period(struct dwc3 *dwc) 358 { 359 unsigned long period; 360 unsigned long fladj; 361 unsigned long decr; 362 unsigned long rate; 363 u32 reg; 364 365 if (dwc->ref_clk) { 366 rate = clk_get_rate(dwc->ref_clk); 367 if (!rate) 368 return; 369 period = NSEC_PER_SEC / rate; 370 } else if (dwc->ref_clk_per) { 371 period = dwc->ref_clk_per; 372 rate = NSEC_PER_SEC / period; 373 } else { 374 return; 375 } 376 377 reg = dwc3_readl(dwc->regs, DWC3_GUCTL); 378 reg &= ~DWC3_GUCTL_REFCLKPER_MASK; 379 reg |= FIELD_PREP(DWC3_GUCTL_REFCLKPER_MASK, period); 380 dwc3_writel(dwc->regs, DWC3_GUCTL, reg); 381 382 if (DWC3_VER_IS_PRIOR(DWC3, 250A)) 383 return; 384 385 /* 386 * The calculation below is 387 * 388 * 125000 * (NSEC_PER_SEC / (rate * period) - 1) 389 * 390 * but rearranged for fixed-point arithmetic. The division must be 391 * 64-bit because 125000 * NSEC_PER_SEC doesn't fit in 32 bits (and 392 * neither does rate * period). 393 * 394 * Note that rate * period ~= NSEC_PER_SECOND, minus the number of 395 * nanoseconds of error caused by the truncation which happened during 396 * the division when calculating rate or period (whichever one was 397 * derived from the other). We first calculate the relative error, then 398 * scale it to units of 8 ppm. 399 */ 400 fladj = div64_u64(125000ULL * NSEC_PER_SEC, (u64)rate * period); 401 fladj -= 125000; 402 403 /* 404 * The documented 240MHz constant is scaled by 2 to get PLS1 as well. 405 */ 406 decr = 480000000 / rate; 407 408 reg = dwc3_readl(dwc->regs, DWC3_GFLADJ); 409 reg &= ~DWC3_GFLADJ_REFCLK_FLADJ_MASK 410 & ~DWC3_GFLADJ_240MHZDECR 411 & ~DWC3_GFLADJ_240MHZDECR_PLS1; 412 reg |= FIELD_PREP(DWC3_GFLADJ_REFCLK_FLADJ_MASK, fladj) 413 | FIELD_PREP(DWC3_GFLADJ_240MHZDECR, decr >> 1) 414 | FIELD_PREP(DWC3_GFLADJ_240MHZDECR_PLS1, decr & 1); 415 416 if (dwc->gfladj_refclk_lpm_sel) 417 reg |= DWC3_GFLADJ_REFCLK_LPM_SEL; 418 419 dwc3_writel(dwc->regs, DWC3_GFLADJ, reg); 420 } 421 422 /** 423 * dwc3_free_one_event_buffer - Frees one event buffer 424 * @dwc: Pointer to our controller context structure 425 * @evt: Pointer to event buffer to be freed 426 */ 427 static void dwc3_free_one_event_buffer(struct dwc3 *dwc, 428 struct dwc3_event_buffer *evt) 429 { 430 dma_free_coherent(dwc->sysdev, evt->length, evt->buf, evt->dma); 431 } 432 433 /** 434 * dwc3_alloc_one_event_buffer - Allocates one event buffer structure 435 * @dwc: Pointer to our controller context structure 436 * @length: size of the event buffer 437 * 438 * Returns a pointer to the allocated event buffer structure on success 439 * otherwise ERR_PTR(errno). 440 */ 441 static struct dwc3_event_buffer *dwc3_alloc_one_event_buffer(struct dwc3 *dwc, 442 unsigned int length) 443 { 444 struct dwc3_event_buffer *evt; 445 446 evt = devm_kzalloc(dwc->dev, sizeof(*evt), GFP_KERNEL); 447 if (!evt) 448 return ERR_PTR(-ENOMEM); 449 450 evt->dwc = dwc; 451 evt->length = length; 452 evt->cache = devm_kzalloc(dwc->dev, length, GFP_KERNEL); 453 if (!evt->cache) 454 return ERR_PTR(-ENOMEM); 455 456 evt->buf = dma_alloc_coherent(dwc->sysdev, length, 457 &evt->dma, GFP_KERNEL); 458 if (!evt->buf) 459 return ERR_PTR(-ENOMEM); 460 461 return evt; 462 } 463 464 /** 465 * dwc3_free_event_buffers - frees all allocated event buffers 466 * @dwc: Pointer to our controller context structure 467 */ 468 static void dwc3_free_event_buffers(struct dwc3 *dwc) 469 { 470 struct dwc3_event_buffer *evt; 471 472 evt = dwc->ev_buf; 473 if (evt) 474 dwc3_free_one_event_buffer(dwc, evt); 475 } 476 477 /** 478 * dwc3_alloc_event_buffers - Allocates @num event buffers of size @length 479 * @dwc: pointer to our controller context structure 480 * @length: size of event buffer 481 * 482 * Returns 0 on success otherwise negative errno. In the error case, dwc 483 * may contain some buffers allocated but not all which were requested. 484 */ 485 static int dwc3_alloc_event_buffers(struct dwc3 *dwc, unsigned int length) 486 { 487 struct dwc3_event_buffer *evt; 488 489 evt = dwc3_alloc_one_event_buffer(dwc, length); 490 if (IS_ERR(evt)) { 491 dev_err(dwc->dev, "can't allocate event buffer\n"); 492 return PTR_ERR(evt); 493 } 494 dwc->ev_buf = evt; 495 496 return 0; 497 } 498 499 /** 500 * dwc3_event_buffers_setup - setup our allocated event buffers 501 * @dwc: pointer to our controller context structure 502 * 503 * Returns 0 on success otherwise negative errno. 504 */ 505 int dwc3_event_buffers_setup(struct dwc3 *dwc) 506 { 507 struct dwc3_event_buffer *evt; 508 509 evt = dwc->ev_buf; 510 evt->lpos = 0; 511 dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(0), 512 lower_32_bits(evt->dma)); 513 dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(0), 514 upper_32_bits(evt->dma)); 515 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0), 516 DWC3_GEVNTSIZ_SIZE(evt->length)); 517 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), 0); 518 519 return 0; 520 } 521 522 void dwc3_event_buffers_cleanup(struct dwc3 *dwc) 523 { 524 struct dwc3_event_buffer *evt; 525 526 evt = dwc->ev_buf; 527 528 evt->lpos = 0; 529 530 dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(0), 0); 531 dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(0), 0); 532 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0), DWC3_GEVNTSIZ_INTMASK 533 | DWC3_GEVNTSIZ_SIZE(0)); 534 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), 0); 535 } 536 537 static int dwc3_alloc_scratch_buffers(struct dwc3 *dwc) 538 { 539 if (!dwc->has_hibernation) 540 return 0; 541 542 if (!dwc->nr_scratch) 543 return 0; 544 545 dwc->scratchbuf = kmalloc_array(dwc->nr_scratch, 546 DWC3_SCRATCHBUF_SIZE, GFP_KERNEL); 547 if (!dwc->scratchbuf) 548 return -ENOMEM; 549 550 return 0; 551 } 552 553 static int dwc3_setup_scratch_buffers(struct dwc3 *dwc) 554 { 555 dma_addr_t scratch_addr; 556 u32 param; 557 int ret; 558 559 if (!dwc->has_hibernation) 560 return 0; 561 562 if (!dwc->nr_scratch) 563 return 0; 564 565 /* should never fall here */ 566 if (!WARN_ON(dwc->scratchbuf)) 567 return 0; 568 569 scratch_addr = dma_map_single(dwc->sysdev, dwc->scratchbuf, 570 dwc->nr_scratch * DWC3_SCRATCHBUF_SIZE, 571 DMA_BIDIRECTIONAL); 572 if (dma_mapping_error(dwc->sysdev, scratch_addr)) { 573 dev_err(dwc->sysdev, "failed to map scratch buffer\n"); 574 ret = -EFAULT; 575 goto err0; 576 } 577 578 dwc->scratch_addr = scratch_addr; 579 580 param = lower_32_bits(scratch_addr); 581 582 ret = dwc3_send_gadget_generic_command(dwc, 583 DWC3_DGCMD_SET_SCRATCHPAD_ADDR_LO, param); 584 if (ret < 0) 585 goto err1; 586 587 param = upper_32_bits(scratch_addr); 588 589 ret = dwc3_send_gadget_generic_command(dwc, 590 DWC3_DGCMD_SET_SCRATCHPAD_ADDR_HI, param); 591 if (ret < 0) 592 goto err1; 593 594 return 0; 595 596 err1: 597 dma_unmap_single(dwc->sysdev, dwc->scratch_addr, dwc->nr_scratch * 598 DWC3_SCRATCHBUF_SIZE, DMA_BIDIRECTIONAL); 599 600 err0: 601 return ret; 602 } 603 604 static void dwc3_free_scratch_buffers(struct dwc3 *dwc) 605 { 606 if (!dwc->has_hibernation) 607 return; 608 609 if (!dwc->nr_scratch) 610 return; 611 612 /* should never fall here */ 613 if (!WARN_ON(dwc->scratchbuf)) 614 return; 615 616 dma_unmap_single(dwc->sysdev, dwc->scratch_addr, dwc->nr_scratch * 617 DWC3_SCRATCHBUF_SIZE, DMA_BIDIRECTIONAL); 618 kfree(dwc->scratchbuf); 619 } 620 621 static void dwc3_core_num_eps(struct dwc3 *dwc) 622 { 623 struct dwc3_hwparams *parms = &dwc->hwparams; 624 625 dwc->num_eps = DWC3_NUM_EPS(parms); 626 } 627 628 static void dwc3_cache_hwparams(struct dwc3 *dwc) 629 { 630 struct dwc3_hwparams *parms = &dwc->hwparams; 631 632 parms->hwparams0 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS0); 633 parms->hwparams1 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS1); 634 parms->hwparams2 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS2); 635 parms->hwparams3 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS3); 636 parms->hwparams4 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS4); 637 parms->hwparams5 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS5); 638 parms->hwparams6 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS6); 639 parms->hwparams7 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS7); 640 parms->hwparams8 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS8); 641 642 if (DWC3_IP_IS(DWC32)) 643 parms->hwparams9 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS9); 644 } 645 646 static int dwc3_core_ulpi_init(struct dwc3 *dwc) 647 { 648 int intf; 649 int ret = 0; 650 651 intf = DWC3_GHWPARAMS3_HSPHY_IFC(dwc->hwparams.hwparams3); 652 653 if (intf == DWC3_GHWPARAMS3_HSPHY_IFC_ULPI || 654 (intf == DWC3_GHWPARAMS3_HSPHY_IFC_UTMI_ULPI && 655 dwc->hsphy_interface && 656 !strncmp(dwc->hsphy_interface, "ulpi", 4))) 657 ret = dwc3_ulpi_init(dwc); 658 659 return ret; 660 } 661 662 /** 663 * dwc3_phy_setup - Configure USB PHY Interface of DWC3 Core 664 * @dwc: Pointer to our controller context structure 665 * 666 * Returns 0 on success. The USB PHY interfaces are configured but not 667 * initialized. The PHY interfaces and the PHYs get initialized together with 668 * the core in dwc3_core_init. 669 */ 670 static int dwc3_phy_setup(struct dwc3 *dwc) 671 { 672 unsigned int hw_mode; 673 u32 reg; 674 675 hw_mode = DWC3_GHWPARAMS0_MODE(dwc->hwparams.hwparams0); 676 677 reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0)); 678 679 /* 680 * Make sure UX_EXIT_PX is cleared as that causes issues with some 681 * PHYs. Also, this bit is not supposed to be used in normal operation. 682 */ 683 reg &= ~DWC3_GUSB3PIPECTL_UX_EXIT_PX; 684 685 /* 686 * Above 1.94a, it is recommended to set DWC3_GUSB3PIPECTL_SUSPHY 687 * to '0' during coreConsultant configuration. So default value 688 * will be '0' when the core is reset. Application needs to set it 689 * to '1' after the core initialization is completed. 690 */ 691 if (!DWC3_VER_IS_WITHIN(DWC3, ANY, 194A)) 692 reg |= DWC3_GUSB3PIPECTL_SUSPHY; 693 694 /* 695 * For DRD controllers, GUSB3PIPECTL.SUSPENDENABLE must be cleared after 696 * power-on reset, and it can be set after core initialization, which is 697 * after device soft-reset during initialization. 698 */ 699 if (hw_mode == DWC3_GHWPARAMS0_MODE_DRD) 700 reg &= ~DWC3_GUSB3PIPECTL_SUSPHY; 701 702 if (dwc->u2ss_inp3_quirk) 703 reg |= DWC3_GUSB3PIPECTL_U2SSINP3OK; 704 705 if (dwc->dis_rxdet_inp3_quirk) 706 reg |= DWC3_GUSB3PIPECTL_DISRXDETINP3; 707 708 if (dwc->req_p1p2p3_quirk) 709 reg |= DWC3_GUSB3PIPECTL_REQP1P2P3; 710 711 if (dwc->del_p1p2p3_quirk) 712 reg |= DWC3_GUSB3PIPECTL_DEP1P2P3_EN; 713 714 if (dwc->del_phy_power_chg_quirk) 715 reg |= DWC3_GUSB3PIPECTL_DEPOCHANGE; 716 717 if (dwc->lfps_filter_quirk) 718 reg |= DWC3_GUSB3PIPECTL_LFPSFILT; 719 720 if (dwc->rx_detect_poll_quirk) 721 reg |= DWC3_GUSB3PIPECTL_RX_DETOPOLL; 722 723 if (dwc->tx_de_emphasis_quirk) 724 reg |= DWC3_GUSB3PIPECTL_TX_DEEPH(dwc->tx_de_emphasis); 725 726 if (dwc->dis_u3_susphy_quirk) 727 reg &= ~DWC3_GUSB3PIPECTL_SUSPHY; 728 729 if (dwc->dis_del_phy_power_chg_quirk) 730 reg &= ~DWC3_GUSB3PIPECTL_DEPOCHANGE; 731 732 dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg); 733 734 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0)); 735 736 /* Select the HS PHY interface */ 737 switch (DWC3_GHWPARAMS3_HSPHY_IFC(dwc->hwparams.hwparams3)) { 738 case DWC3_GHWPARAMS3_HSPHY_IFC_UTMI_ULPI: 739 if (dwc->hsphy_interface && 740 !strncmp(dwc->hsphy_interface, "utmi", 4)) { 741 reg &= ~DWC3_GUSB2PHYCFG_ULPI_UTMI; 742 break; 743 } else if (dwc->hsphy_interface && 744 !strncmp(dwc->hsphy_interface, "ulpi", 4)) { 745 reg |= DWC3_GUSB2PHYCFG_ULPI_UTMI; 746 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg); 747 } else { 748 /* Relying on default value. */ 749 if (!(reg & DWC3_GUSB2PHYCFG_ULPI_UTMI)) 750 break; 751 } 752 fallthrough; 753 case DWC3_GHWPARAMS3_HSPHY_IFC_ULPI: 754 default: 755 break; 756 } 757 758 switch (dwc->hsphy_mode) { 759 case USBPHY_INTERFACE_MODE_UTMI: 760 reg &= ~(DWC3_GUSB2PHYCFG_PHYIF_MASK | 761 DWC3_GUSB2PHYCFG_USBTRDTIM_MASK); 762 reg |= DWC3_GUSB2PHYCFG_PHYIF(UTMI_PHYIF_8_BIT) | 763 DWC3_GUSB2PHYCFG_USBTRDTIM(USBTRDTIM_UTMI_8_BIT); 764 break; 765 case USBPHY_INTERFACE_MODE_UTMIW: 766 reg &= ~(DWC3_GUSB2PHYCFG_PHYIF_MASK | 767 DWC3_GUSB2PHYCFG_USBTRDTIM_MASK); 768 reg |= DWC3_GUSB2PHYCFG_PHYIF(UTMI_PHYIF_16_BIT) | 769 DWC3_GUSB2PHYCFG_USBTRDTIM(USBTRDTIM_UTMI_16_BIT); 770 break; 771 default: 772 break; 773 } 774 775 /* 776 * Above 1.94a, it is recommended to set DWC3_GUSB2PHYCFG_SUSPHY to 777 * '0' during coreConsultant configuration. So default value will 778 * be '0' when the core is reset. Application needs to set it to 779 * '1' after the core initialization is completed. 780 */ 781 if (!DWC3_VER_IS_WITHIN(DWC3, ANY, 194A)) 782 reg |= DWC3_GUSB2PHYCFG_SUSPHY; 783 784 /* 785 * For DRD controllers, GUSB2PHYCFG.SUSPHY must be cleared after 786 * power-on reset, and it can be set after core initialization, which is 787 * after device soft-reset during initialization. 788 */ 789 if (hw_mode == DWC3_GHWPARAMS0_MODE_DRD) 790 reg &= ~DWC3_GUSB2PHYCFG_SUSPHY; 791 792 if (dwc->dis_u2_susphy_quirk) 793 reg &= ~DWC3_GUSB2PHYCFG_SUSPHY; 794 795 if (dwc->dis_enblslpm_quirk) 796 reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM; 797 else 798 reg |= DWC3_GUSB2PHYCFG_ENBLSLPM; 799 800 if (dwc->dis_u2_freeclk_exists_quirk || dwc->gfladj_refclk_lpm_sel) 801 reg &= ~DWC3_GUSB2PHYCFG_U2_FREECLK_EXISTS; 802 803 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg); 804 805 return 0; 806 } 807 808 static int dwc3_clk_enable(struct dwc3 *dwc) 809 { 810 int ret; 811 812 ret = clk_prepare_enable(dwc->bus_clk); 813 if (ret) 814 return ret; 815 816 ret = clk_prepare_enable(dwc->ref_clk); 817 if (ret) 818 goto disable_bus_clk; 819 820 ret = clk_prepare_enable(dwc->susp_clk); 821 if (ret) 822 goto disable_ref_clk; 823 824 return 0; 825 826 disable_ref_clk: 827 clk_disable_unprepare(dwc->ref_clk); 828 disable_bus_clk: 829 clk_disable_unprepare(dwc->bus_clk); 830 return ret; 831 } 832 833 static void dwc3_clk_disable(struct dwc3 *dwc) 834 { 835 clk_disable_unprepare(dwc->susp_clk); 836 clk_disable_unprepare(dwc->ref_clk); 837 clk_disable_unprepare(dwc->bus_clk); 838 } 839 840 static void dwc3_core_exit(struct dwc3 *dwc) 841 { 842 dwc3_event_buffers_cleanup(dwc); 843 844 usb_phy_set_suspend(dwc->usb2_phy, 1); 845 usb_phy_set_suspend(dwc->usb3_phy, 1); 846 phy_power_off(dwc->usb2_generic_phy); 847 phy_power_off(dwc->usb3_generic_phy); 848 849 usb_phy_shutdown(dwc->usb2_phy); 850 usb_phy_shutdown(dwc->usb3_phy); 851 phy_exit(dwc->usb2_generic_phy); 852 phy_exit(dwc->usb3_generic_phy); 853 854 dwc3_clk_disable(dwc); 855 reset_control_assert(dwc->reset); 856 } 857 858 static bool dwc3_core_is_valid(struct dwc3 *dwc) 859 { 860 u32 reg; 861 862 reg = dwc3_readl(dwc->regs, DWC3_GSNPSID); 863 dwc->ip = DWC3_GSNPS_ID(reg); 864 865 /* This should read as U3 followed by revision number */ 866 if (DWC3_IP_IS(DWC3)) { 867 dwc->revision = reg; 868 } else if (DWC3_IP_IS(DWC31) || DWC3_IP_IS(DWC32)) { 869 dwc->revision = dwc3_readl(dwc->regs, DWC3_VER_NUMBER); 870 dwc->version_type = dwc3_readl(dwc->regs, DWC3_VER_TYPE); 871 } else { 872 return false; 873 } 874 875 return true; 876 } 877 878 static void dwc3_core_setup_global_control(struct dwc3 *dwc) 879 { 880 u32 hwparams4 = dwc->hwparams.hwparams4; 881 u32 reg; 882 883 reg = dwc3_readl(dwc->regs, DWC3_GCTL); 884 reg &= ~DWC3_GCTL_SCALEDOWN_MASK; 885 886 switch (DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1)) { 887 case DWC3_GHWPARAMS1_EN_PWROPT_CLK: 888 /** 889 * WORKAROUND: DWC3 revisions between 2.10a and 2.50a have an 890 * issue which would cause xHCI compliance tests to fail. 891 * 892 * Because of that we cannot enable clock gating on such 893 * configurations. 894 * 895 * Refers to: 896 * 897 * STAR#9000588375: Clock Gating, SOF Issues when ref_clk-Based 898 * SOF/ITP Mode Used 899 */ 900 if ((dwc->dr_mode == USB_DR_MODE_HOST || 901 dwc->dr_mode == USB_DR_MODE_OTG) && 902 DWC3_VER_IS_WITHIN(DWC3, 210A, 250A)) 903 reg |= DWC3_GCTL_DSBLCLKGTNG | DWC3_GCTL_SOFITPSYNC; 904 else 905 reg &= ~DWC3_GCTL_DSBLCLKGTNG; 906 break; 907 case DWC3_GHWPARAMS1_EN_PWROPT_HIB: 908 /* enable hibernation here */ 909 dwc->nr_scratch = DWC3_GHWPARAMS4_HIBER_SCRATCHBUFS(hwparams4); 910 911 /* 912 * REVISIT Enabling this bit so that host-mode hibernation 913 * will work. Device-mode hibernation is not yet implemented. 914 */ 915 reg |= DWC3_GCTL_GBLHIBERNATIONEN; 916 break; 917 default: 918 /* nothing */ 919 break; 920 } 921 922 /* check if current dwc3 is on simulation board */ 923 if (dwc->hwparams.hwparams6 & DWC3_GHWPARAMS6_EN_FPGA) { 924 dev_info(dwc->dev, "Running with FPGA optimizations\n"); 925 dwc->is_fpga = true; 926 } 927 928 WARN_ONCE(dwc->disable_scramble_quirk && !dwc->is_fpga, 929 "disable_scramble cannot be used on non-FPGA builds\n"); 930 931 if (dwc->disable_scramble_quirk && dwc->is_fpga) 932 reg |= DWC3_GCTL_DISSCRAMBLE; 933 else 934 reg &= ~DWC3_GCTL_DISSCRAMBLE; 935 936 if (dwc->u2exit_lfps_quirk) 937 reg |= DWC3_GCTL_U2EXIT_LFPS; 938 939 /* 940 * WORKAROUND: DWC3 revisions <1.90a have a bug 941 * where the device can fail to connect at SuperSpeed 942 * and falls back to high-speed mode which causes 943 * the device to enter a Connect/Disconnect loop 944 */ 945 if (DWC3_VER_IS_PRIOR(DWC3, 190A)) 946 reg |= DWC3_GCTL_U2RSTECN; 947 948 dwc3_writel(dwc->regs, DWC3_GCTL, reg); 949 } 950 951 static int dwc3_core_get_phy(struct dwc3 *dwc); 952 static int dwc3_core_ulpi_init(struct dwc3 *dwc); 953 954 /* set global incr burst type configuration registers */ 955 static void dwc3_set_incr_burst_type(struct dwc3 *dwc) 956 { 957 struct device *dev = dwc->dev; 958 /* incrx_mode : for INCR burst type. */ 959 bool incrx_mode; 960 /* incrx_size : for size of INCRX burst. */ 961 u32 incrx_size; 962 u32 *vals; 963 u32 cfg; 964 int ntype; 965 int ret; 966 int i; 967 968 cfg = dwc3_readl(dwc->regs, DWC3_GSBUSCFG0); 969 970 /* 971 * Handle property "snps,incr-burst-type-adjustment". 972 * Get the number of value from this property: 973 * result <= 0, means this property is not supported. 974 * result = 1, means INCRx burst mode supported. 975 * result > 1, means undefined length burst mode supported. 976 */ 977 ntype = device_property_count_u32(dev, "snps,incr-burst-type-adjustment"); 978 if (ntype <= 0) 979 return; 980 981 vals = kcalloc(ntype, sizeof(u32), GFP_KERNEL); 982 if (!vals) 983 return; 984 985 /* Get INCR burst type, and parse it */ 986 ret = device_property_read_u32_array(dev, 987 "snps,incr-burst-type-adjustment", vals, ntype); 988 if (ret) { 989 kfree(vals); 990 dev_err(dev, "Error to get property\n"); 991 return; 992 } 993 994 incrx_size = *vals; 995 996 if (ntype > 1) { 997 /* INCRX (undefined length) burst mode */ 998 incrx_mode = INCRX_UNDEF_LENGTH_BURST_MODE; 999 for (i = 1; i < ntype; i++) { 1000 if (vals[i] > incrx_size) 1001 incrx_size = vals[i]; 1002 } 1003 } else { 1004 /* INCRX burst mode */ 1005 incrx_mode = INCRX_BURST_MODE; 1006 } 1007 1008 kfree(vals); 1009 1010 /* Enable Undefined Length INCR Burst and Enable INCRx Burst */ 1011 cfg &= ~DWC3_GSBUSCFG0_INCRBRST_MASK; 1012 if (incrx_mode) 1013 cfg |= DWC3_GSBUSCFG0_INCRBRSTENA; 1014 switch (incrx_size) { 1015 case 256: 1016 cfg |= DWC3_GSBUSCFG0_INCR256BRSTENA; 1017 break; 1018 case 128: 1019 cfg |= DWC3_GSBUSCFG0_INCR128BRSTENA; 1020 break; 1021 case 64: 1022 cfg |= DWC3_GSBUSCFG0_INCR64BRSTENA; 1023 break; 1024 case 32: 1025 cfg |= DWC3_GSBUSCFG0_INCR32BRSTENA; 1026 break; 1027 case 16: 1028 cfg |= DWC3_GSBUSCFG0_INCR16BRSTENA; 1029 break; 1030 case 8: 1031 cfg |= DWC3_GSBUSCFG0_INCR8BRSTENA; 1032 break; 1033 case 4: 1034 cfg |= DWC3_GSBUSCFG0_INCR4BRSTENA; 1035 break; 1036 case 1: 1037 break; 1038 default: 1039 dev_err(dev, "Invalid property\n"); 1040 break; 1041 } 1042 1043 dwc3_writel(dwc->regs, DWC3_GSBUSCFG0, cfg); 1044 } 1045 1046 static void dwc3_set_power_down_clk_scale(struct dwc3 *dwc) 1047 { 1048 u32 scale; 1049 u32 reg; 1050 1051 if (!dwc->susp_clk) 1052 return; 1053 1054 /* 1055 * The power down scale field specifies how many suspend_clk 1056 * periods fit into a 16KHz clock period. When performing 1057 * the division, round up the remainder. 1058 * 1059 * The power down scale value is calculated using the fastest 1060 * frequency of the suspend_clk. If it isn't fixed (but within 1061 * the accuracy requirement), the driver may not know the max 1062 * rate of the suspend_clk, so only update the power down scale 1063 * if the default is less than the calculated value from 1064 * clk_get_rate() or if the default is questionably high 1065 * (3x or more) to be within the requirement. 1066 */ 1067 scale = DIV_ROUND_UP(clk_get_rate(dwc->susp_clk), 16000); 1068 reg = dwc3_readl(dwc->regs, DWC3_GCTL); 1069 if ((reg & DWC3_GCTL_PWRDNSCALE_MASK) < DWC3_GCTL_PWRDNSCALE(scale) || 1070 (reg & DWC3_GCTL_PWRDNSCALE_MASK) > DWC3_GCTL_PWRDNSCALE(scale*3)) { 1071 reg &= ~(DWC3_GCTL_PWRDNSCALE_MASK); 1072 reg |= DWC3_GCTL_PWRDNSCALE(scale); 1073 dwc3_writel(dwc->regs, DWC3_GCTL, reg); 1074 } 1075 } 1076 1077 /** 1078 * dwc3_core_init - Low-level initialization of DWC3 Core 1079 * @dwc: Pointer to our controller context structure 1080 * 1081 * Returns 0 on success otherwise negative errno. 1082 */ 1083 static int dwc3_core_init(struct dwc3 *dwc) 1084 { 1085 unsigned int hw_mode; 1086 u32 reg; 1087 int ret; 1088 1089 hw_mode = DWC3_GHWPARAMS0_MODE(dwc->hwparams.hwparams0); 1090 1091 /* 1092 * Write Linux Version Code to our GUID register so it's easy to figure 1093 * out which kernel version a bug was found. 1094 */ 1095 dwc3_writel(dwc->regs, DWC3_GUID, LINUX_VERSION_CODE); 1096 1097 ret = dwc3_phy_setup(dwc); 1098 if (ret) 1099 goto err0; 1100 1101 if (!dwc->ulpi_ready) { 1102 ret = dwc3_core_ulpi_init(dwc); 1103 if (ret) { 1104 if (ret == -ETIMEDOUT) { 1105 dwc3_core_soft_reset(dwc); 1106 ret = -EPROBE_DEFER; 1107 } 1108 goto err0; 1109 } 1110 dwc->ulpi_ready = true; 1111 } 1112 1113 if (!dwc->phys_ready) { 1114 ret = dwc3_core_get_phy(dwc); 1115 if (ret) 1116 goto err0a; 1117 dwc->phys_ready = true; 1118 } 1119 1120 usb_phy_init(dwc->usb2_phy); 1121 usb_phy_init(dwc->usb3_phy); 1122 ret = phy_init(dwc->usb2_generic_phy); 1123 if (ret < 0) 1124 goto err0a; 1125 1126 ret = phy_init(dwc->usb3_generic_phy); 1127 if (ret < 0) { 1128 phy_exit(dwc->usb2_generic_phy); 1129 goto err0a; 1130 } 1131 1132 ret = dwc3_core_soft_reset(dwc); 1133 if (ret) 1134 goto err1; 1135 1136 if (hw_mode == DWC3_GHWPARAMS0_MODE_DRD && 1137 !DWC3_VER_IS_WITHIN(DWC3, ANY, 194A)) { 1138 if (!dwc->dis_u3_susphy_quirk) { 1139 reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0)); 1140 reg |= DWC3_GUSB3PIPECTL_SUSPHY; 1141 dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg); 1142 } 1143 1144 if (!dwc->dis_u2_susphy_quirk) { 1145 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0)); 1146 reg |= DWC3_GUSB2PHYCFG_SUSPHY; 1147 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg); 1148 } 1149 } 1150 1151 dwc3_core_setup_global_control(dwc); 1152 dwc3_core_num_eps(dwc); 1153 1154 ret = dwc3_setup_scratch_buffers(dwc); 1155 if (ret) 1156 goto err1; 1157 1158 /* Set power down scale of suspend_clk */ 1159 dwc3_set_power_down_clk_scale(dwc); 1160 1161 /* Adjust Frame Length */ 1162 dwc3_frame_length_adjustment(dwc); 1163 1164 /* Adjust Reference Clock Period */ 1165 dwc3_ref_clk_period(dwc); 1166 1167 dwc3_set_incr_burst_type(dwc); 1168 1169 usb_phy_set_suspend(dwc->usb2_phy, 0); 1170 usb_phy_set_suspend(dwc->usb3_phy, 0); 1171 ret = phy_power_on(dwc->usb2_generic_phy); 1172 if (ret < 0) 1173 goto err2; 1174 1175 ret = phy_power_on(dwc->usb3_generic_phy); 1176 if (ret < 0) 1177 goto err3; 1178 1179 ret = dwc3_event_buffers_setup(dwc); 1180 if (ret) { 1181 dev_err(dwc->dev, "failed to setup event buffers\n"); 1182 goto err4; 1183 } 1184 1185 /* 1186 * ENDXFER polling is available on version 3.10a and later of 1187 * the DWC_usb3 controller. It is NOT available in the 1188 * DWC_usb31 controller. 1189 */ 1190 if (DWC3_VER_IS_WITHIN(DWC3, 310A, ANY)) { 1191 reg = dwc3_readl(dwc->regs, DWC3_GUCTL2); 1192 reg |= DWC3_GUCTL2_RST_ACTBITLATER; 1193 dwc3_writel(dwc->regs, DWC3_GUCTL2, reg); 1194 } 1195 1196 /* 1197 * When configured in HOST mode, after issuing U3/L2 exit controller 1198 * fails to send proper CRC checksum in CRC5 feild. Because of this 1199 * behaviour Transaction Error is generated, resulting in reset and 1200 * re-enumeration of usb device attached. All the termsel, xcvrsel, 1201 * opmode becomes 0 during end of resume. Enabling bit 10 of GUCTL1 1202 * will correct this problem. This option is to support certain 1203 * legacy ULPI PHYs. 1204 */ 1205 if (dwc->resume_hs_terminations) { 1206 reg = dwc3_readl(dwc->regs, DWC3_GUCTL1); 1207 reg |= DWC3_GUCTL1_RESUME_OPMODE_HS_HOST; 1208 dwc3_writel(dwc->regs, DWC3_GUCTL1, reg); 1209 } 1210 1211 if (!DWC3_VER_IS_PRIOR(DWC3, 250A)) { 1212 reg = dwc3_readl(dwc->regs, DWC3_GUCTL1); 1213 1214 /* 1215 * Enable hardware control of sending remote wakeup 1216 * in HS when the device is in the L1 state. 1217 */ 1218 if (!DWC3_VER_IS_PRIOR(DWC3, 290A)) 1219 reg |= DWC3_GUCTL1_DEV_L1_EXIT_BY_HW; 1220 1221 /* 1222 * Decouple USB 2.0 L1 & L2 events which will allow for 1223 * gadget driver to only receive U3/L2 suspend & wakeup 1224 * events and prevent the more frequent L1 LPM transitions 1225 * from interrupting the driver. 1226 */ 1227 if (!DWC3_VER_IS_PRIOR(DWC3, 300A)) 1228 reg |= DWC3_GUCTL1_DEV_DECOUPLE_L1L2_EVT; 1229 1230 if (dwc->dis_tx_ipgap_linecheck_quirk) 1231 reg |= DWC3_GUCTL1_TX_IPGAP_LINECHECK_DIS; 1232 1233 if (dwc->parkmode_disable_ss_quirk) 1234 reg |= DWC3_GUCTL1_PARKMODE_DISABLE_SS; 1235 1236 if (DWC3_VER_IS_WITHIN(DWC3, 290A, ANY) && 1237 (dwc->maximum_speed == USB_SPEED_HIGH || 1238 dwc->maximum_speed == USB_SPEED_FULL)) 1239 reg |= DWC3_GUCTL1_DEV_FORCE_20_CLK_FOR_30_CLK; 1240 1241 dwc3_writel(dwc->regs, DWC3_GUCTL1, reg); 1242 } 1243 1244 if (dwc->dr_mode == USB_DR_MODE_HOST || 1245 dwc->dr_mode == USB_DR_MODE_OTG) { 1246 reg = dwc3_readl(dwc->regs, DWC3_GUCTL); 1247 1248 /* 1249 * Enable Auto retry Feature to make the controller operating in 1250 * Host mode on seeing transaction errors(CRC errors or internal 1251 * overrun scenerios) on IN transfers to reply to the device 1252 * with a non-terminating retry ACK (i.e, an ACK transcation 1253 * packet with Retry=1 & Nump != 0) 1254 */ 1255 reg |= DWC3_GUCTL_HSTINAUTORETRY; 1256 1257 dwc3_writel(dwc->regs, DWC3_GUCTL, reg); 1258 } 1259 1260 /* 1261 * Must config both number of packets and max burst settings to enable 1262 * RX and/or TX threshold. 1263 */ 1264 if (!DWC3_IP_IS(DWC3) && dwc->dr_mode == USB_DR_MODE_HOST) { 1265 u8 rx_thr_num = dwc->rx_thr_num_pkt_prd; 1266 u8 rx_maxburst = dwc->rx_max_burst_prd; 1267 u8 tx_thr_num = dwc->tx_thr_num_pkt_prd; 1268 u8 tx_maxburst = dwc->tx_max_burst_prd; 1269 1270 if (rx_thr_num && rx_maxburst) { 1271 reg = dwc3_readl(dwc->regs, DWC3_GRXTHRCFG); 1272 reg |= DWC31_RXTHRNUMPKTSEL_PRD; 1273 1274 reg &= ~DWC31_RXTHRNUMPKT_PRD(~0); 1275 reg |= DWC31_RXTHRNUMPKT_PRD(rx_thr_num); 1276 1277 reg &= ~DWC31_MAXRXBURSTSIZE_PRD(~0); 1278 reg |= DWC31_MAXRXBURSTSIZE_PRD(rx_maxburst); 1279 1280 dwc3_writel(dwc->regs, DWC3_GRXTHRCFG, reg); 1281 } 1282 1283 if (tx_thr_num && tx_maxburst) { 1284 reg = dwc3_readl(dwc->regs, DWC3_GTXTHRCFG); 1285 reg |= DWC31_TXTHRNUMPKTSEL_PRD; 1286 1287 reg &= ~DWC31_TXTHRNUMPKT_PRD(~0); 1288 reg |= DWC31_TXTHRNUMPKT_PRD(tx_thr_num); 1289 1290 reg &= ~DWC31_MAXTXBURSTSIZE_PRD(~0); 1291 reg |= DWC31_MAXTXBURSTSIZE_PRD(tx_maxburst); 1292 1293 dwc3_writel(dwc->regs, DWC3_GTXTHRCFG, reg); 1294 } 1295 } 1296 1297 return 0; 1298 1299 err4: 1300 phy_power_off(dwc->usb3_generic_phy); 1301 1302 err3: 1303 phy_power_off(dwc->usb2_generic_phy); 1304 1305 err2: 1306 usb_phy_set_suspend(dwc->usb2_phy, 1); 1307 usb_phy_set_suspend(dwc->usb3_phy, 1); 1308 1309 err1: 1310 usb_phy_shutdown(dwc->usb2_phy); 1311 usb_phy_shutdown(dwc->usb3_phy); 1312 phy_exit(dwc->usb2_generic_phy); 1313 phy_exit(dwc->usb3_generic_phy); 1314 1315 err0a: 1316 dwc3_ulpi_exit(dwc); 1317 1318 err0: 1319 return ret; 1320 } 1321 1322 static int dwc3_core_get_phy(struct dwc3 *dwc) 1323 { 1324 struct device *dev = dwc->dev; 1325 struct device_node *node = dev->of_node; 1326 int ret; 1327 1328 if (node) { 1329 dwc->usb2_phy = devm_usb_get_phy_by_phandle(dev, "usb-phy", 0); 1330 dwc->usb3_phy = devm_usb_get_phy_by_phandle(dev, "usb-phy", 1); 1331 } else { 1332 dwc->usb2_phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB2); 1333 dwc->usb3_phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB3); 1334 } 1335 1336 if (IS_ERR(dwc->usb2_phy)) { 1337 ret = PTR_ERR(dwc->usb2_phy); 1338 if (ret == -ENXIO || ret == -ENODEV) 1339 dwc->usb2_phy = NULL; 1340 else 1341 return dev_err_probe(dev, ret, "no usb2 phy configured\n"); 1342 } 1343 1344 if (IS_ERR(dwc->usb3_phy)) { 1345 ret = PTR_ERR(dwc->usb3_phy); 1346 if (ret == -ENXIO || ret == -ENODEV) 1347 dwc->usb3_phy = NULL; 1348 else 1349 return dev_err_probe(dev, ret, "no usb3 phy configured\n"); 1350 } 1351 1352 dwc->usb2_generic_phy = devm_phy_get(dev, "usb2-phy"); 1353 if (IS_ERR(dwc->usb2_generic_phy)) { 1354 ret = PTR_ERR(dwc->usb2_generic_phy); 1355 if (ret == -ENOSYS || ret == -ENODEV) 1356 dwc->usb2_generic_phy = NULL; 1357 else 1358 return dev_err_probe(dev, ret, "no usb2 phy configured\n"); 1359 } 1360 1361 dwc->usb3_generic_phy = devm_phy_get(dev, "usb3-phy"); 1362 if (IS_ERR(dwc->usb3_generic_phy)) { 1363 ret = PTR_ERR(dwc->usb3_generic_phy); 1364 if (ret == -ENOSYS || ret == -ENODEV) 1365 dwc->usb3_generic_phy = NULL; 1366 else 1367 return dev_err_probe(dev, ret, "no usb3 phy configured\n"); 1368 } 1369 1370 return 0; 1371 } 1372 1373 static int dwc3_core_init_mode(struct dwc3 *dwc) 1374 { 1375 struct device *dev = dwc->dev; 1376 int ret; 1377 1378 switch (dwc->dr_mode) { 1379 case USB_DR_MODE_PERIPHERAL: 1380 dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_DEVICE); 1381 1382 if (dwc->usb2_phy) 1383 otg_set_vbus(dwc->usb2_phy->otg, false); 1384 phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_DEVICE); 1385 phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_DEVICE); 1386 1387 ret = dwc3_gadget_init(dwc); 1388 if (ret) 1389 return dev_err_probe(dev, ret, "failed to initialize gadget\n"); 1390 break; 1391 case USB_DR_MODE_HOST: 1392 dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_HOST); 1393 1394 if (dwc->usb2_phy) 1395 otg_set_vbus(dwc->usb2_phy->otg, true); 1396 phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_HOST); 1397 phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_HOST); 1398 1399 ret = dwc3_host_init(dwc); 1400 if (ret) 1401 return dev_err_probe(dev, ret, "failed to initialize host\n"); 1402 break; 1403 case USB_DR_MODE_OTG: 1404 INIT_WORK(&dwc->drd_work, __dwc3_set_mode); 1405 ret = dwc3_drd_init(dwc); 1406 if (ret) 1407 return dev_err_probe(dev, ret, "failed to initialize dual-role\n"); 1408 break; 1409 default: 1410 dev_err(dev, "Unsupported mode of operation %d\n", dwc->dr_mode); 1411 return -EINVAL; 1412 } 1413 1414 return 0; 1415 } 1416 1417 static void dwc3_core_exit_mode(struct dwc3 *dwc) 1418 { 1419 switch (dwc->dr_mode) { 1420 case USB_DR_MODE_PERIPHERAL: 1421 dwc3_gadget_exit(dwc); 1422 break; 1423 case USB_DR_MODE_HOST: 1424 dwc3_host_exit(dwc); 1425 break; 1426 case USB_DR_MODE_OTG: 1427 dwc3_drd_exit(dwc); 1428 break; 1429 default: 1430 /* do nothing */ 1431 break; 1432 } 1433 1434 /* de-assert DRVVBUS for HOST and OTG mode */ 1435 dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_DEVICE); 1436 } 1437 1438 static void dwc3_get_properties(struct dwc3 *dwc) 1439 { 1440 struct device *dev = dwc->dev; 1441 u8 lpm_nyet_threshold; 1442 u8 tx_de_emphasis; 1443 u8 hird_threshold; 1444 u8 rx_thr_num_pkt_prd = 0; 1445 u8 rx_max_burst_prd = 0; 1446 u8 tx_thr_num_pkt_prd = 0; 1447 u8 tx_max_burst_prd = 0; 1448 u8 tx_fifo_resize_max_num; 1449 const char *usb_psy_name; 1450 int ret; 1451 1452 /* default to highest possible threshold */ 1453 lpm_nyet_threshold = 0xf; 1454 1455 /* default to -3.5dB de-emphasis */ 1456 tx_de_emphasis = 1; 1457 1458 /* 1459 * default to assert utmi_sleep_n and use maximum allowed HIRD 1460 * threshold value of 0b1100 1461 */ 1462 hird_threshold = 12; 1463 1464 /* 1465 * default to a TXFIFO size large enough to fit 6 max packets. This 1466 * allows for systems with larger bus latencies to have some headroom 1467 * for endpoints that have a large bMaxBurst value. 1468 */ 1469 tx_fifo_resize_max_num = 6; 1470 1471 dwc->maximum_speed = usb_get_maximum_speed(dev); 1472 dwc->max_ssp_rate = usb_get_maximum_ssp_rate(dev); 1473 dwc->dr_mode = usb_get_dr_mode(dev); 1474 dwc->hsphy_mode = of_usb_get_phy_mode(dev->of_node); 1475 1476 dwc->sysdev_is_parent = device_property_read_bool(dev, 1477 "linux,sysdev_is_parent"); 1478 if (dwc->sysdev_is_parent) 1479 dwc->sysdev = dwc->dev->parent; 1480 else 1481 dwc->sysdev = dwc->dev; 1482 1483 ret = device_property_read_string(dev, "usb-psy-name", &usb_psy_name); 1484 if (ret >= 0) { 1485 dwc->usb_psy = power_supply_get_by_name(usb_psy_name); 1486 if (!dwc->usb_psy) 1487 dev_err(dev, "couldn't get usb power supply\n"); 1488 } 1489 1490 dwc->has_lpm_erratum = device_property_read_bool(dev, 1491 "snps,has-lpm-erratum"); 1492 device_property_read_u8(dev, "snps,lpm-nyet-threshold", 1493 &lpm_nyet_threshold); 1494 dwc->is_utmi_l1_suspend = device_property_read_bool(dev, 1495 "snps,is-utmi-l1-suspend"); 1496 device_property_read_u8(dev, "snps,hird-threshold", 1497 &hird_threshold); 1498 dwc->dis_start_transfer_quirk = device_property_read_bool(dev, 1499 "snps,dis-start-transfer-quirk"); 1500 dwc->usb3_lpm_capable = device_property_read_bool(dev, 1501 "snps,usb3_lpm_capable"); 1502 dwc->usb2_lpm_disable = device_property_read_bool(dev, 1503 "snps,usb2-lpm-disable"); 1504 dwc->usb2_gadget_lpm_disable = device_property_read_bool(dev, 1505 "snps,usb2-gadget-lpm-disable"); 1506 device_property_read_u8(dev, "snps,rx-thr-num-pkt-prd", 1507 &rx_thr_num_pkt_prd); 1508 device_property_read_u8(dev, "snps,rx-max-burst-prd", 1509 &rx_max_burst_prd); 1510 device_property_read_u8(dev, "snps,tx-thr-num-pkt-prd", 1511 &tx_thr_num_pkt_prd); 1512 device_property_read_u8(dev, "snps,tx-max-burst-prd", 1513 &tx_max_burst_prd); 1514 dwc->do_fifo_resize = device_property_read_bool(dev, 1515 "tx-fifo-resize"); 1516 if (dwc->do_fifo_resize) 1517 device_property_read_u8(dev, "tx-fifo-max-num", 1518 &tx_fifo_resize_max_num); 1519 1520 dwc->disable_scramble_quirk = device_property_read_bool(dev, 1521 "snps,disable_scramble_quirk"); 1522 dwc->u2exit_lfps_quirk = device_property_read_bool(dev, 1523 "snps,u2exit_lfps_quirk"); 1524 dwc->u2ss_inp3_quirk = device_property_read_bool(dev, 1525 "snps,u2ss_inp3_quirk"); 1526 dwc->req_p1p2p3_quirk = device_property_read_bool(dev, 1527 "snps,req_p1p2p3_quirk"); 1528 dwc->del_p1p2p3_quirk = device_property_read_bool(dev, 1529 "snps,del_p1p2p3_quirk"); 1530 dwc->del_phy_power_chg_quirk = device_property_read_bool(dev, 1531 "snps,del_phy_power_chg_quirk"); 1532 dwc->lfps_filter_quirk = device_property_read_bool(dev, 1533 "snps,lfps_filter_quirk"); 1534 dwc->rx_detect_poll_quirk = device_property_read_bool(dev, 1535 "snps,rx_detect_poll_quirk"); 1536 dwc->dis_u3_susphy_quirk = device_property_read_bool(dev, 1537 "snps,dis_u3_susphy_quirk"); 1538 dwc->dis_u2_susphy_quirk = device_property_read_bool(dev, 1539 "snps,dis_u2_susphy_quirk"); 1540 dwc->dis_enblslpm_quirk = device_property_read_bool(dev, 1541 "snps,dis_enblslpm_quirk"); 1542 dwc->dis_u1_entry_quirk = device_property_read_bool(dev, 1543 "snps,dis-u1-entry-quirk"); 1544 dwc->dis_u2_entry_quirk = device_property_read_bool(dev, 1545 "snps,dis-u2-entry-quirk"); 1546 dwc->dis_rxdet_inp3_quirk = device_property_read_bool(dev, 1547 "snps,dis_rxdet_inp3_quirk"); 1548 dwc->dis_u2_freeclk_exists_quirk = device_property_read_bool(dev, 1549 "snps,dis-u2-freeclk-exists-quirk"); 1550 dwc->dis_del_phy_power_chg_quirk = device_property_read_bool(dev, 1551 "snps,dis-del-phy-power-chg-quirk"); 1552 dwc->dis_tx_ipgap_linecheck_quirk = device_property_read_bool(dev, 1553 "snps,dis-tx-ipgap-linecheck-quirk"); 1554 dwc->resume_hs_terminations = device_property_read_bool(dev, 1555 "snps,resume-hs-terminations"); 1556 dwc->parkmode_disable_ss_quirk = device_property_read_bool(dev, 1557 "snps,parkmode-disable-ss-quirk"); 1558 dwc->gfladj_refclk_lpm_sel = device_property_read_bool(dev, 1559 "snps,gfladj-refclk-lpm-sel-quirk"); 1560 1561 dwc->tx_de_emphasis_quirk = device_property_read_bool(dev, 1562 "snps,tx_de_emphasis_quirk"); 1563 device_property_read_u8(dev, "snps,tx_de_emphasis", 1564 &tx_de_emphasis); 1565 device_property_read_string(dev, "snps,hsphy_interface", 1566 &dwc->hsphy_interface); 1567 device_property_read_u32(dev, "snps,quirk-frame-length-adjustment", 1568 &dwc->fladj); 1569 device_property_read_u32(dev, "snps,ref-clock-period-ns", 1570 &dwc->ref_clk_per); 1571 1572 dwc->dis_metastability_quirk = device_property_read_bool(dev, 1573 "snps,dis_metastability_quirk"); 1574 1575 dwc->dis_split_quirk = device_property_read_bool(dev, 1576 "snps,dis-split-quirk"); 1577 1578 dwc->lpm_nyet_threshold = lpm_nyet_threshold; 1579 dwc->tx_de_emphasis = tx_de_emphasis; 1580 1581 dwc->hird_threshold = hird_threshold; 1582 1583 dwc->rx_thr_num_pkt_prd = rx_thr_num_pkt_prd; 1584 dwc->rx_max_burst_prd = rx_max_burst_prd; 1585 1586 dwc->tx_thr_num_pkt_prd = tx_thr_num_pkt_prd; 1587 dwc->tx_max_burst_prd = tx_max_burst_prd; 1588 1589 dwc->imod_interval = 0; 1590 1591 dwc->tx_fifo_resize_max_num = tx_fifo_resize_max_num; 1592 } 1593 1594 /* check whether the core supports IMOD */ 1595 bool dwc3_has_imod(struct dwc3 *dwc) 1596 { 1597 return DWC3_VER_IS_WITHIN(DWC3, 300A, ANY) || 1598 DWC3_VER_IS_WITHIN(DWC31, 120A, ANY) || 1599 DWC3_IP_IS(DWC32); 1600 } 1601 1602 static void dwc3_check_params(struct dwc3 *dwc) 1603 { 1604 struct device *dev = dwc->dev; 1605 unsigned int hwparam_gen = 1606 DWC3_GHWPARAMS3_SSPHY_IFC(dwc->hwparams.hwparams3); 1607 1608 /* Check for proper value of imod_interval */ 1609 if (dwc->imod_interval && !dwc3_has_imod(dwc)) { 1610 dev_warn(dwc->dev, "Interrupt moderation not supported\n"); 1611 dwc->imod_interval = 0; 1612 } 1613 1614 /* 1615 * Workaround for STAR 9000961433 which affects only version 1616 * 3.00a of the DWC_usb3 core. This prevents the controller 1617 * interrupt from being masked while handling events. IMOD 1618 * allows us to work around this issue. Enable it for the 1619 * affected version. 1620 */ 1621 if (!dwc->imod_interval && 1622 DWC3_VER_IS(DWC3, 300A)) 1623 dwc->imod_interval = 1; 1624 1625 /* Check the maximum_speed parameter */ 1626 switch (dwc->maximum_speed) { 1627 case USB_SPEED_FULL: 1628 case USB_SPEED_HIGH: 1629 break; 1630 case USB_SPEED_SUPER: 1631 if (hwparam_gen == DWC3_GHWPARAMS3_SSPHY_IFC_DIS) 1632 dev_warn(dev, "UDC doesn't support Gen 1\n"); 1633 break; 1634 case USB_SPEED_SUPER_PLUS: 1635 if ((DWC3_IP_IS(DWC32) && 1636 hwparam_gen == DWC3_GHWPARAMS3_SSPHY_IFC_DIS) || 1637 (!DWC3_IP_IS(DWC32) && 1638 hwparam_gen != DWC3_GHWPARAMS3_SSPHY_IFC_GEN2)) 1639 dev_warn(dev, "UDC doesn't support SSP\n"); 1640 break; 1641 default: 1642 dev_err(dev, "invalid maximum_speed parameter %d\n", 1643 dwc->maximum_speed); 1644 fallthrough; 1645 case USB_SPEED_UNKNOWN: 1646 switch (hwparam_gen) { 1647 case DWC3_GHWPARAMS3_SSPHY_IFC_GEN2: 1648 dwc->maximum_speed = USB_SPEED_SUPER_PLUS; 1649 break; 1650 case DWC3_GHWPARAMS3_SSPHY_IFC_GEN1: 1651 if (DWC3_IP_IS(DWC32)) 1652 dwc->maximum_speed = USB_SPEED_SUPER_PLUS; 1653 else 1654 dwc->maximum_speed = USB_SPEED_SUPER; 1655 break; 1656 case DWC3_GHWPARAMS3_SSPHY_IFC_DIS: 1657 dwc->maximum_speed = USB_SPEED_HIGH; 1658 break; 1659 default: 1660 dwc->maximum_speed = USB_SPEED_SUPER; 1661 break; 1662 } 1663 break; 1664 } 1665 1666 /* 1667 * Currently the controller does not have visibility into the HW 1668 * parameter to determine the maximum number of lanes the HW supports. 1669 * If the number of lanes is not specified in the device property, then 1670 * set the default to support dual-lane for DWC_usb32 and single-lane 1671 * for DWC_usb31 for super-speed-plus. 1672 */ 1673 if (dwc->maximum_speed == USB_SPEED_SUPER_PLUS) { 1674 switch (dwc->max_ssp_rate) { 1675 case USB_SSP_GEN_2x1: 1676 if (hwparam_gen == DWC3_GHWPARAMS3_SSPHY_IFC_GEN1) 1677 dev_warn(dev, "UDC only supports Gen 1\n"); 1678 break; 1679 case USB_SSP_GEN_1x2: 1680 case USB_SSP_GEN_2x2: 1681 if (DWC3_IP_IS(DWC31)) 1682 dev_warn(dev, "UDC only supports single lane\n"); 1683 break; 1684 case USB_SSP_GEN_UNKNOWN: 1685 default: 1686 switch (hwparam_gen) { 1687 case DWC3_GHWPARAMS3_SSPHY_IFC_GEN2: 1688 if (DWC3_IP_IS(DWC32)) 1689 dwc->max_ssp_rate = USB_SSP_GEN_2x2; 1690 else 1691 dwc->max_ssp_rate = USB_SSP_GEN_2x1; 1692 break; 1693 case DWC3_GHWPARAMS3_SSPHY_IFC_GEN1: 1694 if (DWC3_IP_IS(DWC32)) 1695 dwc->max_ssp_rate = USB_SSP_GEN_1x2; 1696 break; 1697 } 1698 break; 1699 } 1700 } 1701 } 1702 1703 static struct extcon_dev *dwc3_get_extcon(struct dwc3 *dwc) 1704 { 1705 struct device *dev = dwc->dev; 1706 struct device_node *np_phy; 1707 struct extcon_dev *edev = NULL; 1708 const char *name; 1709 1710 if (device_property_read_bool(dev, "extcon")) 1711 return extcon_get_edev_by_phandle(dev, 0); 1712 1713 /* 1714 * Device tree platforms should get extcon via phandle. 1715 * On ACPI platforms, we get the name from a device property. 1716 * This device property is for kernel internal use only and 1717 * is expected to be set by the glue code. 1718 */ 1719 if (device_property_read_string(dev, "linux,extcon-name", &name) == 0) 1720 return extcon_get_extcon_dev(name); 1721 1722 /* 1723 * Check explicitly if "usb-role-switch" is used since 1724 * extcon_find_edev_by_node() can not be used to check the absence of 1725 * an extcon device. In the absence of an device it will always return 1726 * EPROBE_DEFER. 1727 */ 1728 if (IS_ENABLED(CONFIG_USB_ROLE_SWITCH) && 1729 device_property_read_bool(dev, "usb-role-switch")) 1730 return NULL; 1731 1732 /* 1733 * Try to get an extcon device from the USB PHY controller's "port" 1734 * node. Check if it has the "port" node first, to avoid printing the 1735 * error message from underlying code, as it's a valid case: extcon 1736 * device (and "port" node) may be missing in case of "usb-role-switch" 1737 * or OTG mode. 1738 */ 1739 np_phy = of_parse_phandle(dev->of_node, "phys", 0); 1740 if (of_graph_is_present(np_phy)) { 1741 struct device_node *np_conn; 1742 1743 np_conn = of_graph_get_remote_node(np_phy, -1, -1); 1744 if (np_conn) 1745 edev = extcon_find_edev_by_node(np_conn); 1746 of_node_put(np_conn); 1747 } 1748 of_node_put(np_phy); 1749 1750 return edev; 1751 } 1752 1753 static int dwc3_probe(struct platform_device *pdev) 1754 { 1755 struct device *dev = &pdev->dev; 1756 struct resource *res, dwc_res; 1757 struct dwc3 *dwc; 1758 1759 int ret; 1760 1761 void __iomem *regs; 1762 1763 dwc = devm_kzalloc(dev, sizeof(*dwc), GFP_KERNEL); 1764 if (!dwc) 1765 return -ENOMEM; 1766 1767 dwc->dev = dev; 1768 1769 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1770 if (!res) { 1771 dev_err(dev, "missing memory resource\n"); 1772 return -ENODEV; 1773 } 1774 1775 dwc->xhci_resources[0].start = res->start; 1776 dwc->xhci_resources[0].end = dwc->xhci_resources[0].start + 1777 DWC3_XHCI_REGS_END; 1778 dwc->xhci_resources[0].flags = res->flags; 1779 dwc->xhci_resources[0].name = res->name; 1780 1781 /* 1782 * Request memory region but exclude xHCI regs, 1783 * since it will be requested by the xhci-plat driver. 1784 */ 1785 dwc_res = *res; 1786 dwc_res.start += DWC3_GLOBALS_REGS_START; 1787 1788 regs = devm_ioremap_resource(dev, &dwc_res); 1789 if (IS_ERR(regs)) 1790 return PTR_ERR(regs); 1791 1792 dwc->regs = regs; 1793 dwc->regs_size = resource_size(&dwc_res); 1794 1795 dwc3_get_properties(dwc); 1796 1797 dwc->reset = devm_reset_control_array_get_optional_shared(dev); 1798 if (IS_ERR(dwc->reset)) { 1799 ret = PTR_ERR(dwc->reset); 1800 goto put_usb_psy; 1801 } 1802 1803 if (dev->of_node) { 1804 /* 1805 * Clocks are optional, but new DT platforms should support all 1806 * clocks as required by the DT-binding. 1807 * Some devices have different clock names in legacy device trees, 1808 * check for them to retain backwards compatibility. 1809 */ 1810 dwc->bus_clk = devm_clk_get_optional(dev, "bus_early"); 1811 if (IS_ERR(dwc->bus_clk)) { 1812 ret = dev_err_probe(dev, PTR_ERR(dwc->bus_clk), 1813 "could not get bus clock\n"); 1814 goto put_usb_psy; 1815 } 1816 1817 if (dwc->bus_clk == NULL) { 1818 dwc->bus_clk = devm_clk_get_optional(dev, "bus_clk"); 1819 if (IS_ERR(dwc->bus_clk)) { 1820 ret = dev_err_probe(dev, PTR_ERR(dwc->bus_clk), 1821 "could not get bus clock\n"); 1822 goto put_usb_psy; 1823 } 1824 } 1825 1826 dwc->ref_clk = devm_clk_get_optional(dev, "ref"); 1827 if (IS_ERR(dwc->ref_clk)) { 1828 ret = dev_err_probe(dev, PTR_ERR(dwc->ref_clk), 1829 "could not get ref clock\n"); 1830 goto put_usb_psy; 1831 } 1832 1833 if (dwc->ref_clk == NULL) { 1834 dwc->ref_clk = devm_clk_get_optional(dev, "ref_clk"); 1835 if (IS_ERR(dwc->ref_clk)) { 1836 ret = dev_err_probe(dev, PTR_ERR(dwc->ref_clk), 1837 "could not get ref clock\n"); 1838 goto put_usb_psy; 1839 } 1840 } 1841 1842 dwc->susp_clk = devm_clk_get_optional(dev, "suspend"); 1843 if (IS_ERR(dwc->susp_clk)) { 1844 ret = dev_err_probe(dev, PTR_ERR(dwc->susp_clk), 1845 "could not get suspend clock\n"); 1846 goto put_usb_psy; 1847 } 1848 1849 if (dwc->susp_clk == NULL) { 1850 dwc->susp_clk = devm_clk_get_optional(dev, "suspend_clk"); 1851 if (IS_ERR(dwc->susp_clk)) { 1852 ret = dev_err_probe(dev, PTR_ERR(dwc->susp_clk), 1853 "could not get suspend clock\n"); 1854 goto put_usb_psy; 1855 } 1856 } 1857 } 1858 1859 ret = reset_control_deassert(dwc->reset); 1860 if (ret) 1861 goto put_usb_psy; 1862 1863 ret = dwc3_clk_enable(dwc); 1864 if (ret) 1865 goto assert_reset; 1866 1867 if (!dwc3_core_is_valid(dwc)) { 1868 dev_err(dwc->dev, "this is not a DesignWare USB3 DRD Core\n"); 1869 ret = -ENODEV; 1870 goto disable_clks; 1871 } 1872 1873 platform_set_drvdata(pdev, dwc); 1874 dwc3_cache_hwparams(dwc); 1875 1876 if (!dwc->sysdev_is_parent && 1877 DWC3_GHWPARAMS0_AWIDTH(dwc->hwparams.hwparams0) == 64) { 1878 ret = dma_set_mask_and_coherent(dwc->sysdev, DMA_BIT_MASK(64)); 1879 if (ret) 1880 goto disable_clks; 1881 } 1882 1883 spin_lock_init(&dwc->lock); 1884 mutex_init(&dwc->mutex); 1885 1886 pm_runtime_set_active(dev); 1887 pm_runtime_use_autosuspend(dev); 1888 pm_runtime_set_autosuspend_delay(dev, DWC3_DEFAULT_AUTOSUSPEND_DELAY); 1889 pm_runtime_enable(dev); 1890 ret = pm_runtime_get_sync(dev); 1891 if (ret < 0) 1892 goto err1; 1893 1894 pm_runtime_forbid(dev); 1895 1896 ret = dwc3_alloc_event_buffers(dwc, DWC3_EVENT_BUFFERS_SIZE); 1897 if (ret) { 1898 dev_err(dwc->dev, "failed to allocate event buffers\n"); 1899 ret = -ENOMEM; 1900 goto err2; 1901 } 1902 1903 dwc->edev = dwc3_get_extcon(dwc); 1904 if (IS_ERR(dwc->edev)) { 1905 ret = dev_err_probe(dwc->dev, PTR_ERR(dwc->edev), "failed to get extcon\n"); 1906 goto err3; 1907 } 1908 1909 ret = dwc3_get_dr_mode(dwc); 1910 if (ret) 1911 goto err3; 1912 1913 ret = dwc3_alloc_scratch_buffers(dwc); 1914 if (ret) 1915 goto err3; 1916 1917 ret = dwc3_core_init(dwc); 1918 if (ret) { 1919 dev_err_probe(dev, ret, "failed to initialize core\n"); 1920 goto err4; 1921 } 1922 1923 dwc3_check_params(dwc); 1924 dwc3_debugfs_init(dwc); 1925 1926 ret = dwc3_core_init_mode(dwc); 1927 if (ret) 1928 goto err5; 1929 1930 pm_runtime_put(dev); 1931 1932 return 0; 1933 1934 err5: 1935 dwc3_debugfs_exit(dwc); 1936 dwc3_event_buffers_cleanup(dwc); 1937 1938 usb_phy_set_suspend(dwc->usb2_phy, 1); 1939 usb_phy_set_suspend(dwc->usb3_phy, 1); 1940 phy_power_off(dwc->usb2_generic_phy); 1941 phy_power_off(dwc->usb3_generic_phy); 1942 1943 usb_phy_shutdown(dwc->usb2_phy); 1944 usb_phy_shutdown(dwc->usb3_phy); 1945 phy_exit(dwc->usb2_generic_phy); 1946 phy_exit(dwc->usb3_generic_phy); 1947 1948 dwc3_ulpi_exit(dwc); 1949 1950 err4: 1951 dwc3_free_scratch_buffers(dwc); 1952 1953 err3: 1954 dwc3_free_event_buffers(dwc); 1955 1956 err2: 1957 pm_runtime_allow(&pdev->dev); 1958 1959 err1: 1960 pm_runtime_put_sync(&pdev->dev); 1961 pm_runtime_disable(&pdev->dev); 1962 1963 disable_clks: 1964 dwc3_clk_disable(dwc); 1965 assert_reset: 1966 reset_control_assert(dwc->reset); 1967 put_usb_psy: 1968 if (dwc->usb_psy) 1969 power_supply_put(dwc->usb_psy); 1970 1971 return ret; 1972 } 1973 1974 static int dwc3_remove(struct platform_device *pdev) 1975 { 1976 struct dwc3 *dwc = platform_get_drvdata(pdev); 1977 1978 pm_runtime_get_sync(&pdev->dev); 1979 1980 dwc3_core_exit_mode(dwc); 1981 dwc3_debugfs_exit(dwc); 1982 1983 dwc3_core_exit(dwc); 1984 dwc3_ulpi_exit(dwc); 1985 1986 pm_runtime_disable(&pdev->dev); 1987 pm_runtime_put_noidle(&pdev->dev); 1988 pm_runtime_set_suspended(&pdev->dev); 1989 1990 dwc3_free_event_buffers(dwc); 1991 dwc3_free_scratch_buffers(dwc); 1992 1993 if (dwc->usb_psy) 1994 power_supply_put(dwc->usb_psy); 1995 1996 return 0; 1997 } 1998 1999 #ifdef CONFIG_PM 2000 static int dwc3_core_init_for_resume(struct dwc3 *dwc) 2001 { 2002 int ret; 2003 2004 ret = reset_control_deassert(dwc->reset); 2005 if (ret) 2006 return ret; 2007 2008 ret = dwc3_clk_enable(dwc); 2009 if (ret) 2010 goto assert_reset; 2011 2012 ret = dwc3_core_init(dwc); 2013 if (ret) 2014 goto disable_clks; 2015 2016 return 0; 2017 2018 disable_clks: 2019 dwc3_clk_disable(dwc); 2020 assert_reset: 2021 reset_control_assert(dwc->reset); 2022 2023 return ret; 2024 } 2025 2026 static int dwc3_suspend_common(struct dwc3 *dwc, pm_message_t msg) 2027 { 2028 unsigned long flags; 2029 u32 reg; 2030 2031 switch (dwc->current_dr_role) { 2032 case DWC3_GCTL_PRTCAP_DEVICE: 2033 if (pm_runtime_suspended(dwc->dev)) 2034 break; 2035 dwc3_gadget_suspend(dwc); 2036 synchronize_irq(dwc->irq_gadget); 2037 dwc3_core_exit(dwc); 2038 break; 2039 case DWC3_GCTL_PRTCAP_HOST: 2040 if (!PMSG_IS_AUTO(msg) && !device_may_wakeup(dwc->dev)) { 2041 dwc3_core_exit(dwc); 2042 break; 2043 } 2044 2045 /* Let controller to suspend HSPHY before PHY driver suspends */ 2046 if (dwc->dis_u2_susphy_quirk || 2047 dwc->dis_enblslpm_quirk) { 2048 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0)); 2049 reg |= DWC3_GUSB2PHYCFG_ENBLSLPM | 2050 DWC3_GUSB2PHYCFG_SUSPHY; 2051 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg); 2052 2053 /* Give some time for USB2 PHY to suspend */ 2054 usleep_range(5000, 6000); 2055 } 2056 2057 phy_pm_runtime_put_sync(dwc->usb2_generic_phy); 2058 phy_pm_runtime_put_sync(dwc->usb3_generic_phy); 2059 break; 2060 case DWC3_GCTL_PRTCAP_OTG: 2061 /* do nothing during runtime_suspend */ 2062 if (PMSG_IS_AUTO(msg)) 2063 break; 2064 2065 if (dwc->current_otg_role == DWC3_OTG_ROLE_DEVICE) { 2066 spin_lock_irqsave(&dwc->lock, flags); 2067 dwc3_gadget_suspend(dwc); 2068 spin_unlock_irqrestore(&dwc->lock, flags); 2069 synchronize_irq(dwc->irq_gadget); 2070 } 2071 2072 dwc3_otg_exit(dwc); 2073 dwc3_core_exit(dwc); 2074 break; 2075 default: 2076 /* do nothing */ 2077 break; 2078 } 2079 2080 return 0; 2081 } 2082 2083 static int dwc3_resume_common(struct dwc3 *dwc, pm_message_t msg) 2084 { 2085 unsigned long flags; 2086 int ret; 2087 u32 reg; 2088 2089 switch (dwc->current_dr_role) { 2090 case DWC3_GCTL_PRTCAP_DEVICE: 2091 ret = dwc3_core_init_for_resume(dwc); 2092 if (ret) 2093 return ret; 2094 2095 dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_DEVICE); 2096 dwc3_gadget_resume(dwc); 2097 break; 2098 case DWC3_GCTL_PRTCAP_HOST: 2099 if (!PMSG_IS_AUTO(msg) && !device_may_wakeup(dwc->dev)) { 2100 ret = dwc3_core_init_for_resume(dwc); 2101 if (ret) 2102 return ret; 2103 dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_HOST); 2104 break; 2105 } 2106 /* Restore GUSB2PHYCFG bits that were modified in suspend */ 2107 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0)); 2108 if (dwc->dis_u2_susphy_quirk) 2109 reg &= ~DWC3_GUSB2PHYCFG_SUSPHY; 2110 2111 if (dwc->dis_enblslpm_quirk) 2112 reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM; 2113 2114 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg); 2115 2116 phy_pm_runtime_get_sync(dwc->usb2_generic_phy); 2117 phy_pm_runtime_get_sync(dwc->usb3_generic_phy); 2118 break; 2119 case DWC3_GCTL_PRTCAP_OTG: 2120 /* nothing to do on runtime_resume */ 2121 if (PMSG_IS_AUTO(msg)) 2122 break; 2123 2124 ret = dwc3_core_init_for_resume(dwc); 2125 if (ret) 2126 return ret; 2127 2128 dwc3_set_prtcap(dwc, dwc->current_dr_role); 2129 2130 dwc3_otg_init(dwc); 2131 if (dwc->current_otg_role == DWC3_OTG_ROLE_HOST) { 2132 dwc3_otg_host_init(dwc); 2133 } else if (dwc->current_otg_role == DWC3_OTG_ROLE_DEVICE) { 2134 spin_lock_irqsave(&dwc->lock, flags); 2135 dwc3_gadget_resume(dwc); 2136 spin_unlock_irqrestore(&dwc->lock, flags); 2137 } 2138 2139 break; 2140 default: 2141 /* do nothing */ 2142 break; 2143 } 2144 2145 return 0; 2146 } 2147 2148 static int dwc3_runtime_checks(struct dwc3 *dwc) 2149 { 2150 switch (dwc->current_dr_role) { 2151 case DWC3_GCTL_PRTCAP_DEVICE: 2152 if (dwc->connected) 2153 return -EBUSY; 2154 break; 2155 case DWC3_GCTL_PRTCAP_HOST: 2156 default: 2157 /* do nothing */ 2158 break; 2159 } 2160 2161 return 0; 2162 } 2163 2164 static int dwc3_runtime_suspend(struct device *dev) 2165 { 2166 struct dwc3 *dwc = dev_get_drvdata(dev); 2167 int ret; 2168 2169 if (dwc3_runtime_checks(dwc)) 2170 return -EBUSY; 2171 2172 ret = dwc3_suspend_common(dwc, PMSG_AUTO_SUSPEND); 2173 if (ret) 2174 return ret; 2175 2176 return 0; 2177 } 2178 2179 static int dwc3_runtime_resume(struct device *dev) 2180 { 2181 struct dwc3 *dwc = dev_get_drvdata(dev); 2182 int ret; 2183 2184 ret = dwc3_resume_common(dwc, PMSG_AUTO_RESUME); 2185 if (ret) 2186 return ret; 2187 2188 switch (dwc->current_dr_role) { 2189 case DWC3_GCTL_PRTCAP_DEVICE: 2190 dwc3_gadget_process_pending_events(dwc); 2191 break; 2192 case DWC3_GCTL_PRTCAP_HOST: 2193 default: 2194 /* do nothing */ 2195 break; 2196 } 2197 2198 pm_runtime_mark_last_busy(dev); 2199 2200 return 0; 2201 } 2202 2203 static int dwc3_runtime_idle(struct device *dev) 2204 { 2205 struct dwc3 *dwc = dev_get_drvdata(dev); 2206 2207 switch (dwc->current_dr_role) { 2208 case DWC3_GCTL_PRTCAP_DEVICE: 2209 if (dwc3_runtime_checks(dwc)) 2210 return -EBUSY; 2211 break; 2212 case DWC3_GCTL_PRTCAP_HOST: 2213 default: 2214 /* do nothing */ 2215 break; 2216 } 2217 2218 pm_runtime_mark_last_busy(dev); 2219 pm_runtime_autosuspend(dev); 2220 2221 return 0; 2222 } 2223 #endif /* CONFIG_PM */ 2224 2225 #ifdef CONFIG_PM_SLEEP 2226 static int dwc3_suspend(struct device *dev) 2227 { 2228 struct dwc3 *dwc = dev_get_drvdata(dev); 2229 int ret; 2230 2231 ret = dwc3_suspend_common(dwc, PMSG_SUSPEND); 2232 if (ret) 2233 return ret; 2234 2235 pinctrl_pm_select_sleep_state(dev); 2236 2237 return 0; 2238 } 2239 2240 static int dwc3_resume(struct device *dev) 2241 { 2242 struct dwc3 *dwc = dev_get_drvdata(dev); 2243 int ret; 2244 2245 pinctrl_pm_select_default_state(dev); 2246 2247 ret = dwc3_resume_common(dwc, PMSG_RESUME); 2248 if (ret) 2249 return ret; 2250 2251 pm_runtime_disable(dev); 2252 pm_runtime_set_active(dev); 2253 pm_runtime_enable(dev); 2254 2255 return 0; 2256 } 2257 2258 static void dwc3_complete(struct device *dev) 2259 { 2260 struct dwc3 *dwc = dev_get_drvdata(dev); 2261 u32 reg; 2262 2263 if (dwc->current_dr_role == DWC3_GCTL_PRTCAP_HOST && 2264 dwc->dis_split_quirk) { 2265 reg = dwc3_readl(dwc->regs, DWC3_GUCTL3); 2266 reg |= DWC3_GUCTL3_SPLITDISABLE; 2267 dwc3_writel(dwc->regs, DWC3_GUCTL3, reg); 2268 } 2269 } 2270 #else 2271 #define dwc3_complete NULL 2272 #endif /* CONFIG_PM_SLEEP */ 2273 2274 static const struct dev_pm_ops dwc3_dev_pm_ops = { 2275 SET_SYSTEM_SLEEP_PM_OPS(dwc3_suspend, dwc3_resume) 2276 .complete = dwc3_complete, 2277 SET_RUNTIME_PM_OPS(dwc3_runtime_suspend, dwc3_runtime_resume, 2278 dwc3_runtime_idle) 2279 }; 2280 2281 #ifdef CONFIG_OF 2282 static const struct of_device_id of_dwc3_match[] = { 2283 { 2284 .compatible = "snps,dwc3" 2285 }, 2286 { 2287 .compatible = "synopsys,dwc3" 2288 }, 2289 { }, 2290 }; 2291 MODULE_DEVICE_TABLE(of, of_dwc3_match); 2292 #endif 2293 2294 #ifdef CONFIG_ACPI 2295 2296 #define ACPI_ID_INTEL_BSW "808622B7" 2297 2298 static const struct acpi_device_id dwc3_acpi_match[] = { 2299 { ACPI_ID_INTEL_BSW, 0 }, 2300 { }, 2301 }; 2302 MODULE_DEVICE_TABLE(acpi, dwc3_acpi_match); 2303 #endif 2304 2305 static struct platform_driver dwc3_driver = { 2306 .probe = dwc3_probe, 2307 .remove = dwc3_remove, 2308 .driver = { 2309 .name = "dwc3", 2310 .of_match_table = of_match_ptr(of_dwc3_match), 2311 .acpi_match_table = ACPI_PTR(dwc3_acpi_match), 2312 .pm = &dwc3_dev_pm_ops, 2313 }, 2314 }; 2315 2316 module_platform_driver(dwc3_driver); 2317 2318 MODULE_ALIAS("platform:dwc3"); 2319 MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>"); 2320 MODULE_LICENSE("GPL v2"); 2321 MODULE_DESCRIPTION("DesignWare USB3 DRD Controller Driver"); 2322