1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * core.c - DesignWare USB3 DRD Controller Core file 4 * 5 * Copyright (C) 2010-2011 Texas Instruments Incorporated - https://www.ti.com 6 * 7 * Authors: Felipe Balbi <balbi@ti.com>, 8 * Sebastian Andrzej Siewior <bigeasy@linutronix.de> 9 */ 10 11 #include <linux/clk.h> 12 #include <linux/version.h> 13 #include <linux/module.h> 14 #include <linux/kernel.h> 15 #include <linux/slab.h> 16 #include <linux/spinlock.h> 17 #include <linux/platform_device.h> 18 #include <linux/pm_runtime.h> 19 #include <linux/interrupt.h> 20 #include <linux/ioport.h> 21 #include <linux/io.h> 22 #include <linux/list.h> 23 #include <linux/delay.h> 24 #include <linux/dma-mapping.h> 25 #include <linux/of.h> 26 #include <linux/of_graph.h> 27 #include <linux/acpi.h> 28 #include <linux/pinctrl/consumer.h> 29 #include <linux/reset.h> 30 #include <linux/bitfield.h> 31 32 #include <linux/usb/ch9.h> 33 #include <linux/usb/gadget.h> 34 #include <linux/usb/of.h> 35 #include <linux/usb/otg.h> 36 37 #include "core.h" 38 #include "gadget.h" 39 #include "io.h" 40 41 #include "debug.h" 42 43 #define DWC3_DEFAULT_AUTOSUSPEND_DELAY 5000 /* ms */ 44 45 /** 46 * dwc3_get_dr_mode - Validates and sets dr_mode 47 * @dwc: pointer to our context structure 48 */ 49 static int dwc3_get_dr_mode(struct dwc3 *dwc) 50 { 51 enum usb_dr_mode mode; 52 struct device *dev = dwc->dev; 53 unsigned int hw_mode; 54 55 if (dwc->dr_mode == USB_DR_MODE_UNKNOWN) 56 dwc->dr_mode = USB_DR_MODE_OTG; 57 58 mode = dwc->dr_mode; 59 hw_mode = DWC3_GHWPARAMS0_MODE(dwc->hwparams.hwparams0); 60 61 switch (hw_mode) { 62 case DWC3_GHWPARAMS0_MODE_GADGET: 63 if (IS_ENABLED(CONFIG_USB_DWC3_HOST)) { 64 dev_err(dev, 65 "Controller does not support host mode.\n"); 66 return -EINVAL; 67 } 68 mode = USB_DR_MODE_PERIPHERAL; 69 break; 70 case DWC3_GHWPARAMS0_MODE_HOST: 71 if (IS_ENABLED(CONFIG_USB_DWC3_GADGET)) { 72 dev_err(dev, 73 "Controller does not support device mode.\n"); 74 return -EINVAL; 75 } 76 mode = USB_DR_MODE_HOST; 77 break; 78 default: 79 if (IS_ENABLED(CONFIG_USB_DWC3_HOST)) 80 mode = USB_DR_MODE_HOST; 81 else if (IS_ENABLED(CONFIG_USB_DWC3_GADGET)) 82 mode = USB_DR_MODE_PERIPHERAL; 83 84 /* 85 * DWC_usb31 and DWC_usb3 v3.30a and higher do not support OTG 86 * mode. If the controller supports DRD but the dr_mode is not 87 * specified or set to OTG, then set the mode to peripheral. 88 */ 89 if (mode == USB_DR_MODE_OTG && !dwc->edev && 90 (!IS_ENABLED(CONFIG_USB_ROLE_SWITCH) || 91 !device_property_read_bool(dwc->dev, "usb-role-switch")) && 92 !DWC3_VER_IS_PRIOR(DWC3, 330A)) 93 mode = USB_DR_MODE_PERIPHERAL; 94 } 95 96 if (mode != dwc->dr_mode) { 97 dev_warn(dev, 98 "Configuration mismatch. dr_mode forced to %s\n", 99 mode == USB_DR_MODE_HOST ? "host" : "gadget"); 100 101 dwc->dr_mode = mode; 102 } 103 104 return 0; 105 } 106 107 void dwc3_enable_susphy(struct dwc3 *dwc, bool enable) 108 { 109 u32 reg; 110 111 reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0)); 112 if (enable && !dwc->dis_u3_susphy_quirk) 113 reg |= DWC3_GUSB3PIPECTL_SUSPHY; 114 else 115 reg &= ~DWC3_GUSB3PIPECTL_SUSPHY; 116 117 dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg); 118 119 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0)); 120 if (enable && !dwc->dis_u2_susphy_quirk) 121 reg |= DWC3_GUSB2PHYCFG_SUSPHY; 122 else 123 reg &= ~DWC3_GUSB2PHYCFG_SUSPHY; 124 125 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg); 126 } 127 128 void dwc3_set_prtcap(struct dwc3 *dwc, u32 mode) 129 { 130 u32 reg; 131 132 reg = dwc3_readl(dwc->regs, DWC3_GCTL); 133 reg &= ~(DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_OTG)); 134 reg |= DWC3_GCTL_PRTCAPDIR(mode); 135 dwc3_writel(dwc->regs, DWC3_GCTL, reg); 136 137 dwc->current_dr_role = mode; 138 } 139 140 static void __dwc3_set_mode(struct work_struct *work) 141 { 142 struct dwc3 *dwc = work_to_dwc(work); 143 unsigned long flags; 144 int ret; 145 u32 reg; 146 u32 desired_dr_role; 147 148 mutex_lock(&dwc->mutex); 149 spin_lock_irqsave(&dwc->lock, flags); 150 desired_dr_role = dwc->desired_dr_role; 151 spin_unlock_irqrestore(&dwc->lock, flags); 152 153 pm_runtime_get_sync(dwc->dev); 154 155 if (dwc->current_dr_role == DWC3_GCTL_PRTCAP_OTG) 156 dwc3_otg_update(dwc, 0); 157 158 if (!desired_dr_role) 159 goto out; 160 161 if (desired_dr_role == dwc->current_dr_role) 162 goto out; 163 164 if (desired_dr_role == DWC3_GCTL_PRTCAP_OTG && dwc->edev) 165 goto out; 166 167 switch (dwc->current_dr_role) { 168 case DWC3_GCTL_PRTCAP_HOST: 169 dwc3_host_exit(dwc); 170 break; 171 case DWC3_GCTL_PRTCAP_DEVICE: 172 dwc3_gadget_exit(dwc); 173 dwc3_event_buffers_cleanup(dwc); 174 break; 175 case DWC3_GCTL_PRTCAP_OTG: 176 dwc3_otg_exit(dwc); 177 spin_lock_irqsave(&dwc->lock, flags); 178 dwc->desired_otg_role = DWC3_OTG_ROLE_IDLE; 179 spin_unlock_irqrestore(&dwc->lock, flags); 180 dwc3_otg_update(dwc, 1); 181 break; 182 default: 183 break; 184 } 185 186 /* 187 * When current_dr_role is not set, there's no role switching. 188 * Only perform GCTL.CoreSoftReset when there's DRD role switching. 189 */ 190 if (dwc->current_dr_role && ((DWC3_IP_IS(DWC3) || 191 DWC3_VER_IS_PRIOR(DWC31, 190A)) && 192 desired_dr_role != DWC3_GCTL_PRTCAP_OTG)) { 193 reg = dwc3_readl(dwc->regs, DWC3_GCTL); 194 reg |= DWC3_GCTL_CORESOFTRESET; 195 dwc3_writel(dwc->regs, DWC3_GCTL, reg); 196 197 /* 198 * Wait for internal clocks to synchronized. DWC_usb31 and 199 * DWC_usb32 may need at least 50ms (less for DWC_usb3). To 200 * keep it consistent across different IPs, let's wait up to 201 * 100ms before clearing GCTL.CORESOFTRESET. 202 */ 203 msleep(100); 204 205 reg = dwc3_readl(dwc->regs, DWC3_GCTL); 206 reg &= ~DWC3_GCTL_CORESOFTRESET; 207 dwc3_writel(dwc->regs, DWC3_GCTL, reg); 208 } 209 210 spin_lock_irqsave(&dwc->lock, flags); 211 212 dwc3_set_prtcap(dwc, desired_dr_role); 213 214 spin_unlock_irqrestore(&dwc->lock, flags); 215 216 switch (desired_dr_role) { 217 case DWC3_GCTL_PRTCAP_HOST: 218 ret = dwc3_host_init(dwc); 219 if (ret) { 220 dev_err(dwc->dev, "failed to initialize host\n"); 221 } else { 222 if (dwc->usb2_phy) 223 otg_set_vbus(dwc->usb2_phy->otg, true); 224 phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_HOST); 225 phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_HOST); 226 if (dwc->dis_split_quirk) { 227 reg = dwc3_readl(dwc->regs, DWC3_GUCTL3); 228 reg |= DWC3_GUCTL3_SPLITDISABLE; 229 dwc3_writel(dwc->regs, DWC3_GUCTL3, reg); 230 } 231 } 232 break; 233 case DWC3_GCTL_PRTCAP_DEVICE: 234 dwc3_core_soft_reset(dwc); 235 236 dwc3_event_buffers_setup(dwc); 237 238 if (dwc->usb2_phy) 239 otg_set_vbus(dwc->usb2_phy->otg, false); 240 phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_DEVICE); 241 phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_DEVICE); 242 243 ret = dwc3_gadget_init(dwc); 244 if (ret) 245 dev_err(dwc->dev, "failed to initialize peripheral\n"); 246 break; 247 case DWC3_GCTL_PRTCAP_OTG: 248 dwc3_otg_init(dwc); 249 dwc3_otg_update(dwc, 0); 250 break; 251 default: 252 break; 253 } 254 255 out: 256 pm_runtime_mark_last_busy(dwc->dev); 257 pm_runtime_put_autosuspend(dwc->dev); 258 mutex_unlock(&dwc->mutex); 259 } 260 261 void dwc3_set_mode(struct dwc3 *dwc, u32 mode) 262 { 263 unsigned long flags; 264 265 if (dwc->dr_mode != USB_DR_MODE_OTG) 266 return; 267 268 spin_lock_irqsave(&dwc->lock, flags); 269 dwc->desired_dr_role = mode; 270 spin_unlock_irqrestore(&dwc->lock, flags); 271 272 queue_work(system_freezable_wq, &dwc->drd_work); 273 } 274 275 u32 dwc3_core_fifo_space(struct dwc3_ep *dep, u8 type) 276 { 277 struct dwc3 *dwc = dep->dwc; 278 u32 reg; 279 280 dwc3_writel(dwc->regs, DWC3_GDBGFIFOSPACE, 281 DWC3_GDBGFIFOSPACE_NUM(dep->number) | 282 DWC3_GDBGFIFOSPACE_TYPE(type)); 283 284 reg = dwc3_readl(dwc->regs, DWC3_GDBGFIFOSPACE); 285 286 return DWC3_GDBGFIFOSPACE_SPACE_AVAILABLE(reg); 287 } 288 289 /** 290 * dwc3_core_soft_reset - Issues core soft reset and PHY reset 291 * @dwc: pointer to our context structure 292 */ 293 int dwc3_core_soft_reset(struct dwc3 *dwc) 294 { 295 u32 reg; 296 int retries = 1000; 297 298 /* 299 * We're resetting only the device side because, if we're in host mode, 300 * XHCI driver will reset the host block. If dwc3 was configured for 301 * host-only mode, then we can return early. 302 */ 303 if (dwc->current_dr_role == DWC3_GCTL_PRTCAP_HOST) 304 return 0; 305 306 reg = dwc3_readl(dwc->regs, DWC3_DCTL); 307 reg |= DWC3_DCTL_CSFTRST; 308 reg &= ~DWC3_DCTL_RUN_STOP; 309 dwc3_gadget_dctl_write_safe(dwc, reg); 310 311 /* 312 * For DWC_usb31 controller 1.90a and later, the DCTL.CSFRST bit 313 * is cleared only after all the clocks are synchronized. This can 314 * take a little more than 50ms. Set the polling rate at 20ms 315 * for 10 times instead. 316 */ 317 if (DWC3_VER_IS_WITHIN(DWC31, 190A, ANY) || DWC3_IP_IS(DWC32)) 318 retries = 10; 319 320 do { 321 reg = dwc3_readl(dwc->regs, DWC3_DCTL); 322 if (!(reg & DWC3_DCTL_CSFTRST)) 323 goto done; 324 325 if (DWC3_VER_IS_WITHIN(DWC31, 190A, ANY) || DWC3_IP_IS(DWC32)) 326 msleep(20); 327 else 328 udelay(1); 329 } while (--retries); 330 331 dev_warn(dwc->dev, "DWC3 controller soft reset failed.\n"); 332 return -ETIMEDOUT; 333 334 done: 335 /* 336 * For DWC_usb31 controller 1.80a and prior, once DCTL.CSFRST bit 337 * is cleared, we must wait at least 50ms before accessing the PHY 338 * domain (synchronization delay). 339 */ 340 if (DWC3_VER_IS_WITHIN(DWC31, ANY, 180A)) 341 msleep(50); 342 343 return 0; 344 } 345 346 /* 347 * dwc3_frame_length_adjustment - Adjusts frame length if required 348 * @dwc3: Pointer to our controller context structure 349 */ 350 static void dwc3_frame_length_adjustment(struct dwc3 *dwc) 351 { 352 u32 reg; 353 u32 dft; 354 355 if (DWC3_VER_IS_PRIOR(DWC3, 250A)) 356 return; 357 358 if (dwc->fladj == 0) 359 return; 360 361 reg = dwc3_readl(dwc->regs, DWC3_GFLADJ); 362 dft = reg & DWC3_GFLADJ_30MHZ_MASK; 363 if (dft != dwc->fladj) { 364 reg &= ~DWC3_GFLADJ_30MHZ_MASK; 365 reg |= DWC3_GFLADJ_30MHZ_SDBND_SEL | dwc->fladj; 366 dwc3_writel(dwc->regs, DWC3_GFLADJ, reg); 367 } 368 } 369 370 /** 371 * dwc3_ref_clk_period - Reference clock period configuration 372 * Default reference clock period depends on hardware 373 * configuration. For systems with reference clock that differs 374 * from the default, this will set clock period in DWC3_GUCTL 375 * register. 376 * @dwc: Pointer to our controller context structure 377 */ 378 static void dwc3_ref_clk_period(struct dwc3 *dwc) 379 { 380 unsigned long period; 381 unsigned long fladj; 382 unsigned long decr; 383 unsigned long rate; 384 u32 reg; 385 386 if (dwc->ref_clk) { 387 rate = clk_get_rate(dwc->ref_clk); 388 if (!rate) 389 return; 390 period = NSEC_PER_SEC / rate; 391 } else if (dwc->ref_clk_per) { 392 period = dwc->ref_clk_per; 393 rate = NSEC_PER_SEC / period; 394 } else { 395 return; 396 } 397 398 reg = dwc3_readl(dwc->regs, DWC3_GUCTL); 399 reg &= ~DWC3_GUCTL_REFCLKPER_MASK; 400 reg |= FIELD_PREP(DWC3_GUCTL_REFCLKPER_MASK, period); 401 dwc3_writel(dwc->regs, DWC3_GUCTL, reg); 402 403 if (DWC3_VER_IS_PRIOR(DWC3, 250A)) 404 return; 405 406 /* 407 * The calculation below is 408 * 409 * 125000 * (NSEC_PER_SEC / (rate * period) - 1) 410 * 411 * but rearranged for fixed-point arithmetic. The division must be 412 * 64-bit because 125000 * NSEC_PER_SEC doesn't fit in 32 bits (and 413 * neither does rate * period). 414 * 415 * Note that rate * period ~= NSEC_PER_SECOND, minus the number of 416 * nanoseconds of error caused by the truncation which happened during 417 * the division when calculating rate or period (whichever one was 418 * derived from the other). We first calculate the relative error, then 419 * scale it to units of 8 ppm. 420 */ 421 fladj = div64_u64(125000ULL * NSEC_PER_SEC, (u64)rate * period); 422 fladj -= 125000; 423 424 /* 425 * The documented 240MHz constant is scaled by 2 to get PLS1 as well. 426 */ 427 decr = 480000000 / rate; 428 429 reg = dwc3_readl(dwc->regs, DWC3_GFLADJ); 430 reg &= ~DWC3_GFLADJ_REFCLK_FLADJ_MASK 431 & ~DWC3_GFLADJ_240MHZDECR 432 & ~DWC3_GFLADJ_240MHZDECR_PLS1; 433 reg |= FIELD_PREP(DWC3_GFLADJ_REFCLK_FLADJ_MASK, fladj) 434 | FIELD_PREP(DWC3_GFLADJ_240MHZDECR, decr >> 1) 435 | FIELD_PREP(DWC3_GFLADJ_240MHZDECR_PLS1, decr & 1); 436 437 if (dwc->gfladj_refclk_lpm_sel) 438 reg |= DWC3_GFLADJ_REFCLK_LPM_SEL; 439 440 dwc3_writel(dwc->regs, DWC3_GFLADJ, reg); 441 } 442 443 /** 444 * dwc3_free_one_event_buffer - Frees one event buffer 445 * @dwc: Pointer to our controller context structure 446 * @evt: Pointer to event buffer to be freed 447 */ 448 static void dwc3_free_one_event_buffer(struct dwc3 *dwc, 449 struct dwc3_event_buffer *evt) 450 { 451 dma_free_coherent(dwc->sysdev, evt->length, evt->buf, evt->dma); 452 } 453 454 /** 455 * dwc3_alloc_one_event_buffer - Allocates one event buffer structure 456 * @dwc: Pointer to our controller context structure 457 * @length: size of the event buffer 458 * 459 * Returns a pointer to the allocated event buffer structure on success 460 * otherwise ERR_PTR(errno). 461 */ 462 static struct dwc3_event_buffer *dwc3_alloc_one_event_buffer(struct dwc3 *dwc, 463 unsigned int length) 464 { 465 struct dwc3_event_buffer *evt; 466 467 evt = devm_kzalloc(dwc->dev, sizeof(*evt), GFP_KERNEL); 468 if (!evt) 469 return ERR_PTR(-ENOMEM); 470 471 evt->dwc = dwc; 472 evt->length = length; 473 evt->cache = devm_kzalloc(dwc->dev, length, GFP_KERNEL); 474 if (!evt->cache) 475 return ERR_PTR(-ENOMEM); 476 477 evt->buf = dma_alloc_coherent(dwc->sysdev, length, 478 &evt->dma, GFP_KERNEL); 479 if (!evt->buf) 480 return ERR_PTR(-ENOMEM); 481 482 return evt; 483 } 484 485 /** 486 * dwc3_free_event_buffers - frees all allocated event buffers 487 * @dwc: Pointer to our controller context structure 488 */ 489 static void dwc3_free_event_buffers(struct dwc3 *dwc) 490 { 491 struct dwc3_event_buffer *evt; 492 493 evt = dwc->ev_buf; 494 if (evt) 495 dwc3_free_one_event_buffer(dwc, evt); 496 } 497 498 /** 499 * dwc3_alloc_event_buffers - Allocates @num event buffers of size @length 500 * @dwc: pointer to our controller context structure 501 * @length: size of event buffer 502 * 503 * Returns 0 on success otherwise negative errno. In the error case, dwc 504 * may contain some buffers allocated but not all which were requested. 505 */ 506 static int dwc3_alloc_event_buffers(struct dwc3 *dwc, unsigned int length) 507 { 508 struct dwc3_event_buffer *evt; 509 510 evt = dwc3_alloc_one_event_buffer(dwc, length); 511 if (IS_ERR(evt)) { 512 dev_err(dwc->dev, "can't allocate event buffer\n"); 513 return PTR_ERR(evt); 514 } 515 dwc->ev_buf = evt; 516 517 return 0; 518 } 519 520 /** 521 * dwc3_event_buffers_setup - setup our allocated event buffers 522 * @dwc: pointer to our controller context structure 523 * 524 * Returns 0 on success otherwise negative errno. 525 */ 526 int dwc3_event_buffers_setup(struct dwc3 *dwc) 527 { 528 struct dwc3_event_buffer *evt; 529 530 evt = dwc->ev_buf; 531 evt->lpos = 0; 532 dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(0), 533 lower_32_bits(evt->dma)); 534 dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(0), 535 upper_32_bits(evt->dma)); 536 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0), 537 DWC3_GEVNTSIZ_SIZE(evt->length)); 538 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), 0); 539 540 return 0; 541 } 542 543 void dwc3_event_buffers_cleanup(struct dwc3 *dwc) 544 { 545 struct dwc3_event_buffer *evt; 546 547 evt = dwc->ev_buf; 548 549 evt->lpos = 0; 550 551 dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(0), 0); 552 dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(0), 0); 553 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0), DWC3_GEVNTSIZ_INTMASK 554 | DWC3_GEVNTSIZ_SIZE(0)); 555 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), 0); 556 } 557 558 static void dwc3_core_num_eps(struct dwc3 *dwc) 559 { 560 struct dwc3_hwparams *parms = &dwc->hwparams; 561 562 dwc->num_eps = DWC3_NUM_EPS(parms); 563 } 564 565 static void dwc3_cache_hwparams(struct dwc3 *dwc) 566 { 567 struct dwc3_hwparams *parms = &dwc->hwparams; 568 569 parms->hwparams0 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS0); 570 parms->hwparams1 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS1); 571 parms->hwparams2 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS2); 572 parms->hwparams3 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS3); 573 parms->hwparams4 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS4); 574 parms->hwparams5 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS5); 575 parms->hwparams6 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS6); 576 parms->hwparams7 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS7); 577 parms->hwparams8 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS8); 578 579 if (DWC3_IP_IS(DWC32)) 580 parms->hwparams9 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS9); 581 } 582 583 static int dwc3_core_ulpi_init(struct dwc3 *dwc) 584 { 585 int intf; 586 int ret = 0; 587 588 intf = DWC3_GHWPARAMS3_HSPHY_IFC(dwc->hwparams.hwparams3); 589 590 if (intf == DWC3_GHWPARAMS3_HSPHY_IFC_ULPI || 591 (intf == DWC3_GHWPARAMS3_HSPHY_IFC_UTMI_ULPI && 592 dwc->hsphy_interface && 593 !strncmp(dwc->hsphy_interface, "ulpi", 4))) 594 ret = dwc3_ulpi_init(dwc); 595 596 return ret; 597 } 598 599 /** 600 * dwc3_phy_setup - Configure USB PHY Interface of DWC3 Core 601 * @dwc: Pointer to our controller context structure 602 * 603 * Returns 0 on success. The USB PHY interfaces are configured but not 604 * initialized. The PHY interfaces and the PHYs get initialized together with 605 * the core in dwc3_core_init. 606 */ 607 static int dwc3_phy_setup(struct dwc3 *dwc) 608 { 609 u32 reg; 610 611 reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0)); 612 613 /* 614 * Make sure UX_EXIT_PX is cleared as that causes issues with some 615 * PHYs. Also, this bit is not supposed to be used in normal operation. 616 */ 617 reg &= ~DWC3_GUSB3PIPECTL_UX_EXIT_PX; 618 619 /* 620 * Above DWC_usb3.0 1.94a, it is recommended to set 621 * DWC3_GUSB3PIPECTL_SUSPHY to '0' during coreConsultant configuration. 622 * So default value will be '0' when the core is reset. Application 623 * needs to set it to '1' after the core initialization is completed. 624 * 625 * Similarly for DRD controllers, GUSB3PIPECTL.SUSPENDENABLE must be 626 * cleared after power-on reset, and it can be set after core 627 * initialization. 628 */ 629 reg &= ~DWC3_GUSB3PIPECTL_SUSPHY; 630 631 if (dwc->u2ss_inp3_quirk) 632 reg |= DWC3_GUSB3PIPECTL_U2SSINP3OK; 633 634 if (dwc->dis_rxdet_inp3_quirk) 635 reg |= DWC3_GUSB3PIPECTL_DISRXDETINP3; 636 637 if (dwc->req_p1p2p3_quirk) 638 reg |= DWC3_GUSB3PIPECTL_REQP1P2P3; 639 640 if (dwc->del_p1p2p3_quirk) 641 reg |= DWC3_GUSB3PIPECTL_DEP1P2P3_EN; 642 643 if (dwc->del_phy_power_chg_quirk) 644 reg |= DWC3_GUSB3PIPECTL_DEPOCHANGE; 645 646 if (dwc->lfps_filter_quirk) 647 reg |= DWC3_GUSB3PIPECTL_LFPSFILT; 648 649 if (dwc->rx_detect_poll_quirk) 650 reg |= DWC3_GUSB3PIPECTL_RX_DETOPOLL; 651 652 if (dwc->tx_de_emphasis_quirk) 653 reg |= DWC3_GUSB3PIPECTL_TX_DEEPH(dwc->tx_de_emphasis); 654 655 if (dwc->dis_del_phy_power_chg_quirk) 656 reg &= ~DWC3_GUSB3PIPECTL_DEPOCHANGE; 657 658 dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg); 659 660 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0)); 661 662 /* Select the HS PHY interface */ 663 switch (DWC3_GHWPARAMS3_HSPHY_IFC(dwc->hwparams.hwparams3)) { 664 case DWC3_GHWPARAMS3_HSPHY_IFC_UTMI_ULPI: 665 if (dwc->hsphy_interface && 666 !strncmp(dwc->hsphy_interface, "utmi", 4)) { 667 reg &= ~DWC3_GUSB2PHYCFG_ULPI_UTMI; 668 break; 669 } else if (dwc->hsphy_interface && 670 !strncmp(dwc->hsphy_interface, "ulpi", 4)) { 671 reg |= DWC3_GUSB2PHYCFG_ULPI_UTMI; 672 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg); 673 } else { 674 /* Relying on default value. */ 675 if (!(reg & DWC3_GUSB2PHYCFG_ULPI_UTMI)) 676 break; 677 } 678 fallthrough; 679 case DWC3_GHWPARAMS3_HSPHY_IFC_ULPI: 680 default: 681 break; 682 } 683 684 switch (dwc->hsphy_mode) { 685 case USBPHY_INTERFACE_MODE_UTMI: 686 reg &= ~(DWC3_GUSB2PHYCFG_PHYIF_MASK | 687 DWC3_GUSB2PHYCFG_USBTRDTIM_MASK); 688 reg |= DWC3_GUSB2PHYCFG_PHYIF(UTMI_PHYIF_8_BIT) | 689 DWC3_GUSB2PHYCFG_USBTRDTIM(USBTRDTIM_UTMI_8_BIT); 690 break; 691 case USBPHY_INTERFACE_MODE_UTMIW: 692 reg &= ~(DWC3_GUSB2PHYCFG_PHYIF_MASK | 693 DWC3_GUSB2PHYCFG_USBTRDTIM_MASK); 694 reg |= DWC3_GUSB2PHYCFG_PHYIF(UTMI_PHYIF_16_BIT) | 695 DWC3_GUSB2PHYCFG_USBTRDTIM(USBTRDTIM_UTMI_16_BIT); 696 break; 697 default: 698 break; 699 } 700 701 /* 702 * Above DWC_usb3.0 1.94a, it is recommended to set 703 * DWC3_GUSB2PHYCFG_SUSPHY to '0' during coreConsultant configuration. 704 * So default value will be '0' when the core is reset. Application 705 * needs to set it to '1' after the core initialization is completed. 706 * 707 * Similarly for DRD controllers, GUSB2PHYCFG.SUSPHY must be cleared 708 * after power-on reset, and it can be set after core initialization. 709 */ 710 reg &= ~DWC3_GUSB2PHYCFG_SUSPHY; 711 712 if (dwc->dis_enblslpm_quirk) 713 reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM; 714 else 715 reg |= DWC3_GUSB2PHYCFG_ENBLSLPM; 716 717 if (dwc->dis_u2_freeclk_exists_quirk || dwc->gfladj_refclk_lpm_sel) 718 reg &= ~DWC3_GUSB2PHYCFG_U2_FREECLK_EXISTS; 719 720 /* 721 * Some ULPI USB PHY does not support internal VBUS supply, to drive 722 * the CPEN pin requires the configuration of the ULPI DRVVBUSEXTERNAL 723 * bit of OTG_CTRL register. Controller configures the USB2 PHY 724 * ULPIEXTVBUSDRV bit[17] of the GUSB2PHYCFG register to drive vBus 725 * with an external supply. 726 */ 727 if (dwc->ulpi_ext_vbus_drv) 728 reg |= DWC3_GUSB2PHYCFG_ULPIEXTVBUSDRV; 729 730 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg); 731 732 return 0; 733 } 734 735 static int dwc3_phy_init(struct dwc3 *dwc) 736 { 737 int ret; 738 739 usb_phy_init(dwc->usb2_phy); 740 usb_phy_init(dwc->usb3_phy); 741 742 ret = phy_init(dwc->usb2_generic_phy); 743 if (ret < 0) 744 goto err_shutdown_usb3_phy; 745 746 ret = phy_init(dwc->usb3_generic_phy); 747 if (ret < 0) 748 goto err_exit_usb2_phy; 749 750 return 0; 751 752 err_exit_usb2_phy: 753 phy_exit(dwc->usb2_generic_phy); 754 err_shutdown_usb3_phy: 755 usb_phy_shutdown(dwc->usb3_phy); 756 usb_phy_shutdown(dwc->usb2_phy); 757 758 return ret; 759 } 760 761 static void dwc3_phy_exit(struct dwc3 *dwc) 762 { 763 phy_exit(dwc->usb3_generic_phy); 764 phy_exit(dwc->usb2_generic_phy); 765 766 usb_phy_shutdown(dwc->usb3_phy); 767 usb_phy_shutdown(dwc->usb2_phy); 768 } 769 770 static int dwc3_phy_power_on(struct dwc3 *dwc) 771 { 772 int ret; 773 774 usb_phy_set_suspend(dwc->usb2_phy, 0); 775 usb_phy_set_suspend(dwc->usb3_phy, 0); 776 777 ret = phy_power_on(dwc->usb2_generic_phy); 778 if (ret < 0) 779 goto err_suspend_usb3_phy; 780 781 ret = phy_power_on(dwc->usb3_generic_phy); 782 if (ret < 0) 783 goto err_power_off_usb2_phy; 784 785 return 0; 786 787 err_power_off_usb2_phy: 788 phy_power_off(dwc->usb2_generic_phy); 789 err_suspend_usb3_phy: 790 usb_phy_set_suspend(dwc->usb3_phy, 1); 791 usb_phy_set_suspend(dwc->usb2_phy, 1); 792 793 return ret; 794 } 795 796 static void dwc3_phy_power_off(struct dwc3 *dwc) 797 { 798 phy_power_off(dwc->usb3_generic_phy); 799 phy_power_off(dwc->usb2_generic_phy); 800 801 usb_phy_set_suspend(dwc->usb3_phy, 1); 802 usb_phy_set_suspend(dwc->usb2_phy, 1); 803 } 804 805 static int dwc3_clk_enable(struct dwc3 *dwc) 806 { 807 int ret; 808 809 ret = clk_prepare_enable(dwc->bus_clk); 810 if (ret) 811 return ret; 812 813 ret = clk_prepare_enable(dwc->ref_clk); 814 if (ret) 815 goto disable_bus_clk; 816 817 ret = clk_prepare_enable(dwc->susp_clk); 818 if (ret) 819 goto disable_ref_clk; 820 821 return 0; 822 823 disable_ref_clk: 824 clk_disable_unprepare(dwc->ref_clk); 825 disable_bus_clk: 826 clk_disable_unprepare(dwc->bus_clk); 827 return ret; 828 } 829 830 static void dwc3_clk_disable(struct dwc3 *dwc) 831 { 832 clk_disable_unprepare(dwc->susp_clk); 833 clk_disable_unprepare(dwc->ref_clk); 834 clk_disable_unprepare(dwc->bus_clk); 835 } 836 837 static void dwc3_core_exit(struct dwc3 *dwc) 838 { 839 dwc3_event_buffers_cleanup(dwc); 840 dwc3_phy_power_off(dwc); 841 dwc3_phy_exit(dwc); 842 dwc3_clk_disable(dwc); 843 reset_control_assert(dwc->reset); 844 } 845 846 static bool dwc3_core_is_valid(struct dwc3 *dwc) 847 { 848 u32 reg; 849 850 reg = dwc3_readl(dwc->regs, DWC3_GSNPSID); 851 dwc->ip = DWC3_GSNPS_ID(reg); 852 853 /* This should read as U3 followed by revision number */ 854 if (DWC3_IP_IS(DWC3)) { 855 dwc->revision = reg; 856 } else if (DWC3_IP_IS(DWC31) || DWC3_IP_IS(DWC32)) { 857 dwc->revision = dwc3_readl(dwc->regs, DWC3_VER_NUMBER); 858 dwc->version_type = dwc3_readl(dwc->regs, DWC3_VER_TYPE); 859 } else { 860 return false; 861 } 862 863 return true; 864 } 865 866 static void dwc3_core_setup_global_control(struct dwc3 *dwc) 867 { 868 unsigned int power_opt; 869 unsigned int hw_mode; 870 u32 reg; 871 872 reg = dwc3_readl(dwc->regs, DWC3_GCTL); 873 reg &= ~DWC3_GCTL_SCALEDOWN_MASK; 874 hw_mode = DWC3_GHWPARAMS0_MODE(dwc->hwparams.hwparams0); 875 power_opt = DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1); 876 877 switch (power_opt) { 878 case DWC3_GHWPARAMS1_EN_PWROPT_CLK: 879 /** 880 * WORKAROUND: DWC3 revisions between 2.10a and 2.50a have an 881 * issue which would cause xHCI compliance tests to fail. 882 * 883 * Because of that we cannot enable clock gating on such 884 * configurations. 885 * 886 * Refers to: 887 * 888 * STAR#9000588375: Clock Gating, SOF Issues when ref_clk-Based 889 * SOF/ITP Mode Used 890 */ 891 if ((dwc->dr_mode == USB_DR_MODE_HOST || 892 dwc->dr_mode == USB_DR_MODE_OTG) && 893 DWC3_VER_IS_WITHIN(DWC3, 210A, 250A)) 894 reg |= DWC3_GCTL_DSBLCLKGTNG | DWC3_GCTL_SOFITPSYNC; 895 else 896 reg &= ~DWC3_GCTL_DSBLCLKGTNG; 897 break; 898 case DWC3_GHWPARAMS1_EN_PWROPT_HIB: 899 /* 900 * REVISIT Enabling this bit so that host-mode hibernation 901 * will work. Device-mode hibernation is not yet implemented. 902 */ 903 reg |= DWC3_GCTL_GBLHIBERNATIONEN; 904 break; 905 default: 906 /* nothing */ 907 break; 908 } 909 910 /* 911 * This is a workaround for STAR#4846132, which only affects 912 * DWC_usb31 version2.00a operating in host mode. 913 * 914 * There is a problem in DWC_usb31 version 2.00a operating 915 * in host mode that would cause a CSR read timeout When CSR 916 * read coincides with RAM Clock Gating Entry. By disable 917 * Clock Gating, sacrificing power consumption for normal 918 * operation. 919 */ 920 if (power_opt != DWC3_GHWPARAMS1_EN_PWROPT_NO && 921 hw_mode != DWC3_GHWPARAMS0_MODE_GADGET && DWC3_VER_IS(DWC31, 200A)) 922 reg |= DWC3_GCTL_DSBLCLKGTNG; 923 924 /* check if current dwc3 is on simulation board */ 925 if (dwc->hwparams.hwparams6 & DWC3_GHWPARAMS6_EN_FPGA) { 926 dev_info(dwc->dev, "Running with FPGA optimizations\n"); 927 dwc->is_fpga = true; 928 } 929 930 WARN_ONCE(dwc->disable_scramble_quirk && !dwc->is_fpga, 931 "disable_scramble cannot be used on non-FPGA builds\n"); 932 933 if (dwc->disable_scramble_quirk && dwc->is_fpga) 934 reg |= DWC3_GCTL_DISSCRAMBLE; 935 else 936 reg &= ~DWC3_GCTL_DISSCRAMBLE; 937 938 if (dwc->u2exit_lfps_quirk) 939 reg |= DWC3_GCTL_U2EXIT_LFPS; 940 941 /* 942 * WORKAROUND: DWC3 revisions <1.90a have a bug 943 * where the device can fail to connect at SuperSpeed 944 * and falls back to high-speed mode which causes 945 * the device to enter a Connect/Disconnect loop 946 */ 947 if (DWC3_VER_IS_PRIOR(DWC3, 190A)) 948 reg |= DWC3_GCTL_U2RSTECN; 949 950 dwc3_writel(dwc->regs, DWC3_GCTL, reg); 951 } 952 953 static int dwc3_core_get_phy(struct dwc3 *dwc); 954 static int dwc3_core_ulpi_init(struct dwc3 *dwc); 955 956 /* set global incr burst type configuration registers */ 957 static void dwc3_set_incr_burst_type(struct dwc3 *dwc) 958 { 959 struct device *dev = dwc->dev; 960 /* incrx_mode : for INCR burst type. */ 961 bool incrx_mode; 962 /* incrx_size : for size of INCRX burst. */ 963 u32 incrx_size; 964 u32 *vals; 965 u32 cfg; 966 int ntype; 967 int ret; 968 int i; 969 970 cfg = dwc3_readl(dwc->regs, DWC3_GSBUSCFG0); 971 972 /* 973 * Handle property "snps,incr-burst-type-adjustment". 974 * Get the number of value from this property: 975 * result <= 0, means this property is not supported. 976 * result = 1, means INCRx burst mode supported. 977 * result > 1, means undefined length burst mode supported. 978 */ 979 ntype = device_property_count_u32(dev, "snps,incr-burst-type-adjustment"); 980 if (ntype <= 0) 981 return; 982 983 vals = kcalloc(ntype, sizeof(u32), GFP_KERNEL); 984 if (!vals) 985 return; 986 987 /* Get INCR burst type, and parse it */ 988 ret = device_property_read_u32_array(dev, 989 "snps,incr-burst-type-adjustment", vals, ntype); 990 if (ret) { 991 kfree(vals); 992 dev_err(dev, "Error to get property\n"); 993 return; 994 } 995 996 incrx_size = *vals; 997 998 if (ntype > 1) { 999 /* INCRX (undefined length) burst mode */ 1000 incrx_mode = INCRX_UNDEF_LENGTH_BURST_MODE; 1001 for (i = 1; i < ntype; i++) { 1002 if (vals[i] > incrx_size) 1003 incrx_size = vals[i]; 1004 } 1005 } else { 1006 /* INCRX burst mode */ 1007 incrx_mode = INCRX_BURST_MODE; 1008 } 1009 1010 kfree(vals); 1011 1012 /* Enable Undefined Length INCR Burst and Enable INCRx Burst */ 1013 cfg &= ~DWC3_GSBUSCFG0_INCRBRST_MASK; 1014 if (incrx_mode) 1015 cfg |= DWC3_GSBUSCFG0_INCRBRSTENA; 1016 switch (incrx_size) { 1017 case 256: 1018 cfg |= DWC3_GSBUSCFG0_INCR256BRSTENA; 1019 break; 1020 case 128: 1021 cfg |= DWC3_GSBUSCFG0_INCR128BRSTENA; 1022 break; 1023 case 64: 1024 cfg |= DWC3_GSBUSCFG0_INCR64BRSTENA; 1025 break; 1026 case 32: 1027 cfg |= DWC3_GSBUSCFG0_INCR32BRSTENA; 1028 break; 1029 case 16: 1030 cfg |= DWC3_GSBUSCFG0_INCR16BRSTENA; 1031 break; 1032 case 8: 1033 cfg |= DWC3_GSBUSCFG0_INCR8BRSTENA; 1034 break; 1035 case 4: 1036 cfg |= DWC3_GSBUSCFG0_INCR4BRSTENA; 1037 break; 1038 case 1: 1039 break; 1040 default: 1041 dev_err(dev, "Invalid property\n"); 1042 break; 1043 } 1044 1045 dwc3_writel(dwc->regs, DWC3_GSBUSCFG0, cfg); 1046 } 1047 1048 static void dwc3_set_power_down_clk_scale(struct dwc3 *dwc) 1049 { 1050 u32 scale; 1051 u32 reg; 1052 1053 if (!dwc->susp_clk) 1054 return; 1055 1056 /* 1057 * The power down scale field specifies how many suspend_clk 1058 * periods fit into a 16KHz clock period. When performing 1059 * the division, round up the remainder. 1060 * 1061 * The power down scale value is calculated using the fastest 1062 * frequency of the suspend_clk. If it isn't fixed (but within 1063 * the accuracy requirement), the driver may not know the max 1064 * rate of the suspend_clk, so only update the power down scale 1065 * if the default is less than the calculated value from 1066 * clk_get_rate() or if the default is questionably high 1067 * (3x or more) to be within the requirement. 1068 */ 1069 scale = DIV_ROUND_UP(clk_get_rate(dwc->susp_clk), 16000); 1070 reg = dwc3_readl(dwc->regs, DWC3_GCTL); 1071 if ((reg & DWC3_GCTL_PWRDNSCALE_MASK) < DWC3_GCTL_PWRDNSCALE(scale) || 1072 (reg & DWC3_GCTL_PWRDNSCALE_MASK) > DWC3_GCTL_PWRDNSCALE(scale*3)) { 1073 reg &= ~(DWC3_GCTL_PWRDNSCALE_MASK); 1074 reg |= DWC3_GCTL_PWRDNSCALE(scale); 1075 dwc3_writel(dwc->regs, DWC3_GCTL, reg); 1076 } 1077 } 1078 1079 static void dwc3_config_threshold(struct dwc3 *dwc) 1080 { 1081 u32 reg; 1082 u8 rx_thr_num; 1083 u8 rx_maxburst; 1084 u8 tx_thr_num; 1085 u8 tx_maxburst; 1086 1087 /* 1088 * Must config both number of packets and max burst settings to enable 1089 * RX and/or TX threshold. 1090 */ 1091 if (!DWC3_IP_IS(DWC3) && dwc->dr_mode == USB_DR_MODE_HOST) { 1092 rx_thr_num = dwc->rx_thr_num_pkt_prd; 1093 rx_maxburst = dwc->rx_max_burst_prd; 1094 tx_thr_num = dwc->tx_thr_num_pkt_prd; 1095 tx_maxburst = dwc->tx_max_burst_prd; 1096 1097 if (rx_thr_num && rx_maxburst) { 1098 reg = dwc3_readl(dwc->regs, DWC3_GRXTHRCFG); 1099 reg |= DWC31_RXTHRNUMPKTSEL_PRD; 1100 1101 reg &= ~DWC31_RXTHRNUMPKT_PRD(~0); 1102 reg |= DWC31_RXTHRNUMPKT_PRD(rx_thr_num); 1103 1104 reg &= ~DWC31_MAXRXBURSTSIZE_PRD(~0); 1105 reg |= DWC31_MAXRXBURSTSIZE_PRD(rx_maxburst); 1106 1107 dwc3_writel(dwc->regs, DWC3_GRXTHRCFG, reg); 1108 } 1109 1110 if (tx_thr_num && tx_maxburst) { 1111 reg = dwc3_readl(dwc->regs, DWC3_GTXTHRCFG); 1112 reg |= DWC31_TXTHRNUMPKTSEL_PRD; 1113 1114 reg &= ~DWC31_TXTHRNUMPKT_PRD(~0); 1115 reg |= DWC31_TXTHRNUMPKT_PRD(tx_thr_num); 1116 1117 reg &= ~DWC31_MAXTXBURSTSIZE_PRD(~0); 1118 reg |= DWC31_MAXTXBURSTSIZE_PRD(tx_maxburst); 1119 1120 dwc3_writel(dwc->regs, DWC3_GTXTHRCFG, reg); 1121 } 1122 } 1123 1124 rx_thr_num = dwc->rx_thr_num_pkt; 1125 rx_maxburst = dwc->rx_max_burst; 1126 tx_thr_num = dwc->tx_thr_num_pkt; 1127 tx_maxburst = dwc->tx_max_burst; 1128 1129 if (DWC3_IP_IS(DWC3)) { 1130 if (rx_thr_num && rx_maxburst) { 1131 reg = dwc3_readl(dwc->regs, DWC3_GRXTHRCFG); 1132 reg |= DWC3_GRXTHRCFG_PKTCNTSEL; 1133 1134 reg &= ~DWC3_GRXTHRCFG_RXPKTCNT(~0); 1135 reg |= DWC3_GRXTHRCFG_RXPKTCNT(rx_thr_num); 1136 1137 reg &= ~DWC3_GRXTHRCFG_MAXRXBURSTSIZE(~0); 1138 reg |= DWC3_GRXTHRCFG_MAXRXBURSTSIZE(rx_maxburst); 1139 1140 dwc3_writel(dwc->regs, DWC3_GRXTHRCFG, reg); 1141 } 1142 1143 if (tx_thr_num && tx_maxburst) { 1144 reg = dwc3_readl(dwc->regs, DWC3_GTXTHRCFG); 1145 reg |= DWC3_GTXTHRCFG_PKTCNTSEL; 1146 1147 reg &= ~DWC3_GTXTHRCFG_TXPKTCNT(~0); 1148 reg |= DWC3_GTXTHRCFG_TXPKTCNT(tx_thr_num); 1149 1150 reg &= ~DWC3_GTXTHRCFG_MAXTXBURSTSIZE(~0); 1151 reg |= DWC3_GTXTHRCFG_MAXTXBURSTSIZE(tx_maxburst); 1152 1153 dwc3_writel(dwc->regs, DWC3_GTXTHRCFG, reg); 1154 } 1155 } else { 1156 if (rx_thr_num && rx_maxburst) { 1157 reg = dwc3_readl(dwc->regs, DWC3_GRXTHRCFG); 1158 reg |= DWC31_GRXTHRCFG_PKTCNTSEL; 1159 1160 reg &= ~DWC31_GRXTHRCFG_RXPKTCNT(~0); 1161 reg |= DWC31_GRXTHRCFG_RXPKTCNT(rx_thr_num); 1162 1163 reg &= ~DWC31_GRXTHRCFG_MAXRXBURSTSIZE(~0); 1164 reg |= DWC31_GRXTHRCFG_MAXRXBURSTSIZE(rx_maxburst); 1165 1166 dwc3_writel(dwc->regs, DWC3_GRXTHRCFG, reg); 1167 } 1168 1169 if (tx_thr_num && tx_maxburst) { 1170 reg = dwc3_readl(dwc->regs, DWC3_GTXTHRCFG); 1171 reg |= DWC31_GTXTHRCFG_PKTCNTSEL; 1172 1173 reg &= ~DWC31_GTXTHRCFG_TXPKTCNT(~0); 1174 reg |= DWC31_GTXTHRCFG_TXPKTCNT(tx_thr_num); 1175 1176 reg &= ~DWC31_GTXTHRCFG_MAXTXBURSTSIZE(~0); 1177 reg |= DWC31_GTXTHRCFG_MAXTXBURSTSIZE(tx_maxburst); 1178 1179 dwc3_writel(dwc->regs, DWC3_GTXTHRCFG, reg); 1180 } 1181 } 1182 } 1183 1184 /** 1185 * dwc3_core_init - Low-level initialization of DWC3 Core 1186 * @dwc: Pointer to our controller context structure 1187 * 1188 * Returns 0 on success otherwise negative errno. 1189 */ 1190 static int dwc3_core_init(struct dwc3 *dwc) 1191 { 1192 unsigned int hw_mode; 1193 u32 reg; 1194 int ret; 1195 1196 hw_mode = DWC3_GHWPARAMS0_MODE(dwc->hwparams.hwparams0); 1197 1198 /* 1199 * Write Linux Version Code to our GUID register so it's easy to figure 1200 * out which kernel version a bug was found. 1201 */ 1202 dwc3_writel(dwc->regs, DWC3_GUID, LINUX_VERSION_CODE); 1203 1204 ret = dwc3_phy_setup(dwc); 1205 if (ret) 1206 return ret; 1207 1208 if (!dwc->ulpi_ready) { 1209 ret = dwc3_core_ulpi_init(dwc); 1210 if (ret) { 1211 if (ret == -ETIMEDOUT) { 1212 dwc3_core_soft_reset(dwc); 1213 ret = -EPROBE_DEFER; 1214 } 1215 return ret; 1216 } 1217 dwc->ulpi_ready = true; 1218 } 1219 1220 if (!dwc->phys_ready) { 1221 ret = dwc3_core_get_phy(dwc); 1222 if (ret) 1223 goto err_exit_ulpi; 1224 dwc->phys_ready = true; 1225 } 1226 1227 ret = dwc3_phy_init(dwc); 1228 if (ret) 1229 goto err_exit_ulpi; 1230 1231 ret = dwc3_core_soft_reset(dwc); 1232 if (ret) 1233 goto err_exit_phy; 1234 1235 dwc3_core_setup_global_control(dwc); 1236 dwc3_core_num_eps(dwc); 1237 1238 /* Set power down scale of suspend_clk */ 1239 dwc3_set_power_down_clk_scale(dwc); 1240 1241 /* Adjust Frame Length */ 1242 dwc3_frame_length_adjustment(dwc); 1243 1244 /* Adjust Reference Clock Period */ 1245 dwc3_ref_clk_period(dwc); 1246 1247 dwc3_set_incr_burst_type(dwc); 1248 1249 ret = dwc3_phy_power_on(dwc); 1250 if (ret) 1251 goto err_exit_phy; 1252 1253 ret = dwc3_event_buffers_setup(dwc); 1254 if (ret) { 1255 dev_err(dwc->dev, "failed to setup event buffers\n"); 1256 goto err_power_off_phy; 1257 } 1258 1259 /* 1260 * ENDXFER polling is available on version 3.10a and later of 1261 * the DWC_usb3 controller. It is NOT available in the 1262 * DWC_usb31 controller. 1263 */ 1264 if (DWC3_VER_IS_WITHIN(DWC3, 310A, ANY)) { 1265 reg = dwc3_readl(dwc->regs, DWC3_GUCTL2); 1266 reg |= DWC3_GUCTL2_RST_ACTBITLATER; 1267 dwc3_writel(dwc->regs, DWC3_GUCTL2, reg); 1268 } 1269 1270 /* 1271 * When configured in HOST mode, after issuing U3/L2 exit controller 1272 * fails to send proper CRC checksum in CRC5 feild. Because of this 1273 * behaviour Transaction Error is generated, resulting in reset and 1274 * re-enumeration of usb device attached. All the termsel, xcvrsel, 1275 * opmode becomes 0 during end of resume. Enabling bit 10 of GUCTL1 1276 * will correct this problem. This option is to support certain 1277 * legacy ULPI PHYs. 1278 */ 1279 if (dwc->resume_hs_terminations) { 1280 reg = dwc3_readl(dwc->regs, DWC3_GUCTL1); 1281 reg |= DWC3_GUCTL1_RESUME_OPMODE_HS_HOST; 1282 dwc3_writel(dwc->regs, DWC3_GUCTL1, reg); 1283 } 1284 1285 if (!DWC3_VER_IS_PRIOR(DWC3, 250A)) { 1286 reg = dwc3_readl(dwc->regs, DWC3_GUCTL1); 1287 1288 /* 1289 * Enable hardware control of sending remote wakeup 1290 * in HS when the device is in the L1 state. 1291 */ 1292 if (!DWC3_VER_IS_PRIOR(DWC3, 290A)) 1293 reg |= DWC3_GUCTL1_DEV_L1_EXIT_BY_HW; 1294 1295 /* 1296 * Decouple USB 2.0 L1 & L2 events which will allow for 1297 * gadget driver to only receive U3/L2 suspend & wakeup 1298 * events and prevent the more frequent L1 LPM transitions 1299 * from interrupting the driver. 1300 */ 1301 if (!DWC3_VER_IS_PRIOR(DWC3, 300A)) 1302 reg |= DWC3_GUCTL1_DEV_DECOUPLE_L1L2_EVT; 1303 1304 if (dwc->dis_tx_ipgap_linecheck_quirk) 1305 reg |= DWC3_GUCTL1_TX_IPGAP_LINECHECK_DIS; 1306 1307 if (dwc->parkmode_disable_ss_quirk) 1308 reg |= DWC3_GUCTL1_PARKMODE_DISABLE_SS; 1309 1310 if (dwc->parkmode_disable_hs_quirk) 1311 reg |= DWC3_GUCTL1_PARKMODE_DISABLE_HS; 1312 1313 if (DWC3_VER_IS_WITHIN(DWC3, 290A, ANY) && 1314 (dwc->maximum_speed == USB_SPEED_HIGH || 1315 dwc->maximum_speed == USB_SPEED_FULL)) 1316 reg |= DWC3_GUCTL1_DEV_FORCE_20_CLK_FOR_30_CLK; 1317 1318 dwc3_writel(dwc->regs, DWC3_GUCTL1, reg); 1319 } 1320 1321 dwc3_config_threshold(dwc); 1322 1323 return 0; 1324 1325 err_power_off_phy: 1326 dwc3_phy_power_off(dwc); 1327 err_exit_phy: 1328 dwc3_phy_exit(dwc); 1329 err_exit_ulpi: 1330 dwc3_ulpi_exit(dwc); 1331 1332 return ret; 1333 } 1334 1335 static int dwc3_core_get_phy(struct dwc3 *dwc) 1336 { 1337 struct device *dev = dwc->dev; 1338 struct device_node *node = dev->of_node; 1339 int ret; 1340 1341 if (node) { 1342 dwc->usb2_phy = devm_usb_get_phy_by_phandle(dev, "usb-phy", 0); 1343 dwc->usb3_phy = devm_usb_get_phy_by_phandle(dev, "usb-phy", 1); 1344 } else { 1345 dwc->usb2_phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB2); 1346 dwc->usb3_phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB3); 1347 } 1348 1349 if (IS_ERR(dwc->usb2_phy)) { 1350 ret = PTR_ERR(dwc->usb2_phy); 1351 if (ret == -ENXIO || ret == -ENODEV) 1352 dwc->usb2_phy = NULL; 1353 else 1354 return dev_err_probe(dev, ret, "no usb2 phy configured\n"); 1355 } 1356 1357 if (IS_ERR(dwc->usb3_phy)) { 1358 ret = PTR_ERR(dwc->usb3_phy); 1359 if (ret == -ENXIO || ret == -ENODEV) 1360 dwc->usb3_phy = NULL; 1361 else 1362 return dev_err_probe(dev, ret, "no usb3 phy configured\n"); 1363 } 1364 1365 dwc->usb2_generic_phy = devm_phy_get(dev, "usb2-phy"); 1366 if (IS_ERR(dwc->usb2_generic_phy)) { 1367 ret = PTR_ERR(dwc->usb2_generic_phy); 1368 if (ret == -ENOSYS || ret == -ENODEV) 1369 dwc->usb2_generic_phy = NULL; 1370 else 1371 return dev_err_probe(dev, ret, "no usb2 phy configured\n"); 1372 } 1373 1374 dwc->usb3_generic_phy = devm_phy_get(dev, "usb3-phy"); 1375 if (IS_ERR(dwc->usb3_generic_phy)) { 1376 ret = PTR_ERR(dwc->usb3_generic_phy); 1377 if (ret == -ENOSYS || ret == -ENODEV) 1378 dwc->usb3_generic_phy = NULL; 1379 else 1380 return dev_err_probe(dev, ret, "no usb3 phy configured\n"); 1381 } 1382 1383 return 0; 1384 } 1385 1386 static int dwc3_core_init_mode(struct dwc3 *dwc) 1387 { 1388 struct device *dev = dwc->dev; 1389 int ret; 1390 1391 switch (dwc->dr_mode) { 1392 case USB_DR_MODE_PERIPHERAL: 1393 dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_DEVICE); 1394 1395 if (dwc->usb2_phy) 1396 otg_set_vbus(dwc->usb2_phy->otg, false); 1397 phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_DEVICE); 1398 phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_DEVICE); 1399 1400 ret = dwc3_gadget_init(dwc); 1401 if (ret) 1402 return dev_err_probe(dev, ret, "failed to initialize gadget\n"); 1403 break; 1404 case USB_DR_MODE_HOST: 1405 dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_HOST); 1406 1407 if (dwc->usb2_phy) 1408 otg_set_vbus(dwc->usb2_phy->otg, true); 1409 phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_HOST); 1410 phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_HOST); 1411 1412 ret = dwc3_host_init(dwc); 1413 if (ret) 1414 return dev_err_probe(dev, ret, "failed to initialize host\n"); 1415 break; 1416 case USB_DR_MODE_OTG: 1417 INIT_WORK(&dwc->drd_work, __dwc3_set_mode); 1418 ret = dwc3_drd_init(dwc); 1419 if (ret) 1420 return dev_err_probe(dev, ret, "failed to initialize dual-role\n"); 1421 break; 1422 default: 1423 dev_err(dev, "Unsupported mode of operation %d\n", dwc->dr_mode); 1424 return -EINVAL; 1425 } 1426 1427 return 0; 1428 } 1429 1430 static void dwc3_core_exit_mode(struct dwc3 *dwc) 1431 { 1432 switch (dwc->dr_mode) { 1433 case USB_DR_MODE_PERIPHERAL: 1434 dwc3_gadget_exit(dwc); 1435 break; 1436 case USB_DR_MODE_HOST: 1437 dwc3_host_exit(dwc); 1438 break; 1439 case USB_DR_MODE_OTG: 1440 dwc3_drd_exit(dwc); 1441 break; 1442 default: 1443 /* do nothing */ 1444 break; 1445 } 1446 1447 /* de-assert DRVVBUS for HOST and OTG mode */ 1448 dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_DEVICE); 1449 } 1450 1451 static void dwc3_get_properties(struct dwc3 *dwc) 1452 { 1453 struct device *dev = dwc->dev; 1454 u8 lpm_nyet_threshold; 1455 u8 tx_de_emphasis; 1456 u8 hird_threshold; 1457 u8 rx_thr_num_pkt = 0; 1458 u8 rx_max_burst = 0; 1459 u8 tx_thr_num_pkt = 0; 1460 u8 tx_max_burst = 0; 1461 u8 rx_thr_num_pkt_prd = 0; 1462 u8 rx_max_burst_prd = 0; 1463 u8 tx_thr_num_pkt_prd = 0; 1464 u8 tx_max_burst_prd = 0; 1465 u8 tx_fifo_resize_max_num; 1466 const char *usb_psy_name; 1467 int ret; 1468 1469 /* default to highest possible threshold */ 1470 lpm_nyet_threshold = 0xf; 1471 1472 /* default to -3.5dB de-emphasis */ 1473 tx_de_emphasis = 1; 1474 1475 /* 1476 * default to assert utmi_sleep_n and use maximum allowed HIRD 1477 * threshold value of 0b1100 1478 */ 1479 hird_threshold = 12; 1480 1481 /* 1482 * default to a TXFIFO size large enough to fit 6 max packets. This 1483 * allows for systems with larger bus latencies to have some headroom 1484 * for endpoints that have a large bMaxBurst value. 1485 */ 1486 tx_fifo_resize_max_num = 6; 1487 1488 dwc->maximum_speed = usb_get_maximum_speed(dev); 1489 dwc->max_ssp_rate = usb_get_maximum_ssp_rate(dev); 1490 dwc->dr_mode = usb_get_dr_mode(dev); 1491 dwc->hsphy_mode = of_usb_get_phy_mode(dev->of_node); 1492 1493 dwc->sysdev_is_parent = device_property_read_bool(dev, 1494 "linux,sysdev_is_parent"); 1495 if (dwc->sysdev_is_parent) 1496 dwc->sysdev = dwc->dev->parent; 1497 else 1498 dwc->sysdev = dwc->dev; 1499 1500 dwc->sys_wakeup = device_may_wakeup(dwc->sysdev); 1501 1502 ret = device_property_read_string(dev, "usb-psy-name", &usb_psy_name); 1503 if (ret >= 0) { 1504 dwc->usb_psy = power_supply_get_by_name(usb_psy_name); 1505 if (!dwc->usb_psy) 1506 dev_err(dev, "couldn't get usb power supply\n"); 1507 } 1508 1509 dwc->has_lpm_erratum = device_property_read_bool(dev, 1510 "snps,has-lpm-erratum"); 1511 device_property_read_u8(dev, "snps,lpm-nyet-threshold", 1512 &lpm_nyet_threshold); 1513 dwc->is_utmi_l1_suspend = device_property_read_bool(dev, 1514 "snps,is-utmi-l1-suspend"); 1515 device_property_read_u8(dev, "snps,hird-threshold", 1516 &hird_threshold); 1517 dwc->dis_start_transfer_quirk = device_property_read_bool(dev, 1518 "snps,dis-start-transfer-quirk"); 1519 dwc->usb3_lpm_capable = device_property_read_bool(dev, 1520 "snps,usb3_lpm_capable"); 1521 dwc->usb2_lpm_disable = device_property_read_bool(dev, 1522 "snps,usb2-lpm-disable"); 1523 dwc->usb2_gadget_lpm_disable = device_property_read_bool(dev, 1524 "snps,usb2-gadget-lpm-disable"); 1525 device_property_read_u8(dev, "snps,rx-thr-num-pkt", 1526 &rx_thr_num_pkt); 1527 device_property_read_u8(dev, "snps,rx-max-burst", 1528 &rx_max_burst); 1529 device_property_read_u8(dev, "snps,tx-thr-num-pkt", 1530 &tx_thr_num_pkt); 1531 device_property_read_u8(dev, "snps,tx-max-burst", 1532 &tx_max_burst); 1533 device_property_read_u8(dev, "snps,rx-thr-num-pkt-prd", 1534 &rx_thr_num_pkt_prd); 1535 device_property_read_u8(dev, "snps,rx-max-burst-prd", 1536 &rx_max_burst_prd); 1537 device_property_read_u8(dev, "snps,tx-thr-num-pkt-prd", 1538 &tx_thr_num_pkt_prd); 1539 device_property_read_u8(dev, "snps,tx-max-burst-prd", 1540 &tx_max_burst_prd); 1541 dwc->do_fifo_resize = device_property_read_bool(dev, 1542 "tx-fifo-resize"); 1543 if (dwc->do_fifo_resize) 1544 device_property_read_u8(dev, "tx-fifo-max-num", 1545 &tx_fifo_resize_max_num); 1546 1547 dwc->disable_scramble_quirk = device_property_read_bool(dev, 1548 "snps,disable_scramble_quirk"); 1549 dwc->u2exit_lfps_quirk = device_property_read_bool(dev, 1550 "snps,u2exit_lfps_quirk"); 1551 dwc->u2ss_inp3_quirk = device_property_read_bool(dev, 1552 "snps,u2ss_inp3_quirk"); 1553 dwc->req_p1p2p3_quirk = device_property_read_bool(dev, 1554 "snps,req_p1p2p3_quirk"); 1555 dwc->del_p1p2p3_quirk = device_property_read_bool(dev, 1556 "snps,del_p1p2p3_quirk"); 1557 dwc->del_phy_power_chg_quirk = device_property_read_bool(dev, 1558 "snps,del_phy_power_chg_quirk"); 1559 dwc->lfps_filter_quirk = device_property_read_bool(dev, 1560 "snps,lfps_filter_quirk"); 1561 dwc->rx_detect_poll_quirk = device_property_read_bool(dev, 1562 "snps,rx_detect_poll_quirk"); 1563 dwc->dis_u3_susphy_quirk = device_property_read_bool(dev, 1564 "snps,dis_u3_susphy_quirk"); 1565 dwc->dis_u2_susphy_quirk = device_property_read_bool(dev, 1566 "snps,dis_u2_susphy_quirk"); 1567 dwc->dis_enblslpm_quirk = device_property_read_bool(dev, 1568 "snps,dis_enblslpm_quirk"); 1569 dwc->dis_u1_entry_quirk = device_property_read_bool(dev, 1570 "snps,dis-u1-entry-quirk"); 1571 dwc->dis_u2_entry_quirk = device_property_read_bool(dev, 1572 "snps,dis-u2-entry-quirk"); 1573 dwc->dis_rxdet_inp3_quirk = device_property_read_bool(dev, 1574 "snps,dis_rxdet_inp3_quirk"); 1575 dwc->dis_u2_freeclk_exists_quirk = device_property_read_bool(dev, 1576 "snps,dis-u2-freeclk-exists-quirk"); 1577 dwc->dis_del_phy_power_chg_quirk = device_property_read_bool(dev, 1578 "snps,dis-del-phy-power-chg-quirk"); 1579 dwc->dis_tx_ipgap_linecheck_quirk = device_property_read_bool(dev, 1580 "snps,dis-tx-ipgap-linecheck-quirk"); 1581 dwc->resume_hs_terminations = device_property_read_bool(dev, 1582 "snps,resume-hs-terminations"); 1583 dwc->ulpi_ext_vbus_drv = device_property_read_bool(dev, 1584 "snps,ulpi-ext-vbus-drv"); 1585 dwc->parkmode_disable_ss_quirk = device_property_read_bool(dev, 1586 "snps,parkmode-disable-ss-quirk"); 1587 dwc->parkmode_disable_hs_quirk = device_property_read_bool(dev, 1588 "snps,parkmode-disable-hs-quirk"); 1589 dwc->gfladj_refclk_lpm_sel = device_property_read_bool(dev, 1590 "snps,gfladj-refclk-lpm-sel-quirk"); 1591 1592 dwc->tx_de_emphasis_quirk = device_property_read_bool(dev, 1593 "snps,tx_de_emphasis_quirk"); 1594 device_property_read_u8(dev, "snps,tx_de_emphasis", 1595 &tx_de_emphasis); 1596 device_property_read_string(dev, "snps,hsphy_interface", 1597 &dwc->hsphy_interface); 1598 device_property_read_u32(dev, "snps,quirk-frame-length-adjustment", 1599 &dwc->fladj); 1600 device_property_read_u32(dev, "snps,ref-clock-period-ns", 1601 &dwc->ref_clk_per); 1602 1603 dwc->dis_metastability_quirk = device_property_read_bool(dev, 1604 "snps,dis_metastability_quirk"); 1605 1606 dwc->dis_split_quirk = device_property_read_bool(dev, 1607 "snps,dis-split-quirk"); 1608 1609 dwc->lpm_nyet_threshold = lpm_nyet_threshold; 1610 dwc->tx_de_emphasis = tx_de_emphasis; 1611 1612 dwc->hird_threshold = hird_threshold; 1613 1614 dwc->rx_thr_num_pkt = rx_thr_num_pkt; 1615 dwc->rx_max_burst = rx_max_burst; 1616 1617 dwc->tx_thr_num_pkt = tx_thr_num_pkt; 1618 dwc->tx_max_burst = tx_max_burst; 1619 1620 dwc->rx_thr_num_pkt_prd = rx_thr_num_pkt_prd; 1621 dwc->rx_max_burst_prd = rx_max_burst_prd; 1622 1623 dwc->tx_thr_num_pkt_prd = tx_thr_num_pkt_prd; 1624 dwc->tx_max_burst_prd = tx_max_burst_prd; 1625 1626 dwc->imod_interval = 0; 1627 1628 dwc->tx_fifo_resize_max_num = tx_fifo_resize_max_num; 1629 } 1630 1631 /* check whether the core supports IMOD */ 1632 bool dwc3_has_imod(struct dwc3 *dwc) 1633 { 1634 return DWC3_VER_IS_WITHIN(DWC3, 300A, ANY) || 1635 DWC3_VER_IS_WITHIN(DWC31, 120A, ANY) || 1636 DWC3_IP_IS(DWC32); 1637 } 1638 1639 static void dwc3_check_params(struct dwc3 *dwc) 1640 { 1641 struct device *dev = dwc->dev; 1642 unsigned int hwparam_gen = 1643 DWC3_GHWPARAMS3_SSPHY_IFC(dwc->hwparams.hwparams3); 1644 1645 /* Check for proper value of imod_interval */ 1646 if (dwc->imod_interval && !dwc3_has_imod(dwc)) { 1647 dev_warn(dwc->dev, "Interrupt moderation not supported\n"); 1648 dwc->imod_interval = 0; 1649 } 1650 1651 /* 1652 * Workaround for STAR 9000961433 which affects only version 1653 * 3.00a of the DWC_usb3 core. This prevents the controller 1654 * interrupt from being masked while handling events. IMOD 1655 * allows us to work around this issue. Enable it for the 1656 * affected version. 1657 */ 1658 if (!dwc->imod_interval && 1659 DWC3_VER_IS(DWC3, 300A)) 1660 dwc->imod_interval = 1; 1661 1662 /* Check the maximum_speed parameter */ 1663 switch (dwc->maximum_speed) { 1664 case USB_SPEED_FULL: 1665 case USB_SPEED_HIGH: 1666 break; 1667 case USB_SPEED_SUPER: 1668 if (hwparam_gen == DWC3_GHWPARAMS3_SSPHY_IFC_DIS) 1669 dev_warn(dev, "UDC doesn't support Gen 1\n"); 1670 break; 1671 case USB_SPEED_SUPER_PLUS: 1672 if ((DWC3_IP_IS(DWC32) && 1673 hwparam_gen == DWC3_GHWPARAMS3_SSPHY_IFC_DIS) || 1674 (!DWC3_IP_IS(DWC32) && 1675 hwparam_gen != DWC3_GHWPARAMS3_SSPHY_IFC_GEN2)) 1676 dev_warn(dev, "UDC doesn't support SSP\n"); 1677 break; 1678 default: 1679 dev_err(dev, "invalid maximum_speed parameter %d\n", 1680 dwc->maximum_speed); 1681 fallthrough; 1682 case USB_SPEED_UNKNOWN: 1683 switch (hwparam_gen) { 1684 case DWC3_GHWPARAMS3_SSPHY_IFC_GEN2: 1685 dwc->maximum_speed = USB_SPEED_SUPER_PLUS; 1686 break; 1687 case DWC3_GHWPARAMS3_SSPHY_IFC_GEN1: 1688 if (DWC3_IP_IS(DWC32)) 1689 dwc->maximum_speed = USB_SPEED_SUPER_PLUS; 1690 else 1691 dwc->maximum_speed = USB_SPEED_SUPER; 1692 break; 1693 case DWC3_GHWPARAMS3_SSPHY_IFC_DIS: 1694 dwc->maximum_speed = USB_SPEED_HIGH; 1695 break; 1696 default: 1697 dwc->maximum_speed = USB_SPEED_SUPER; 1698 break; 1699 } 1700 break; 1701 } 1702 1703 /* 1704 * Currently the controller does not have visibility into the HW 1705 * parameter to determine the maximum number of lanes the HW supports. 1706 * If the number of lanes is not specified in the device property, then 1707 * set the default to support dual-lane for DWC_usb32 and single-lane 1708 * for DWC_usb31 for super-speed-plus. 1709 */ 1710 if (dwc->maximum_speed == USB_SPEED_SUPER_PLUS) { 1711 switch (dwc->max_ssp_rate) { 1712 case USB_SSP_GEN_2x1: 1713 if (hwparam_gen == DWC3_GHWPARAMS3_SSPHY_IFC_GEN1) 1714 dev_warn(dev, "UDC only supports Gen 1\n"); 1715 break; 1716 case USB_SSP_GEN_1x2: 1717 case USB_SSP_GEN_2x2: 1718 if (DWC3_IP_IS(DWC31)) 1719 dev_warn(dev, "UDC only supports single lane\n"); 1720 break; 1721 case USB_SSP_GEN_UNKNOWN: 1722 default: 1723 switch (hwparam_gen) { 1724 case DWC3_GHWPARAMS3_SSPHY_IFC_GEN2: 1725 if (DWC3_IP_IS(DWC32)) 1726 dwc->max_ssp_rate = USB_SSP_GEN_2x2; 1727 else 1728 dwc->max_ssp_rate = USB_SSP_GEN_2x1; 1729 break; 1730 case DWC3_GHWPARAMS3_SSPHY_IFC_GEN1: 1731 if (DWC3_IP_IS(DWC32)) 1732 dwc->max_ssp_rate = USB_SSP_GEN_1x2; 1733 break; 1734 } 1735 break; 1736 } 1737 } 1738 } 1739 1740 static struct extcon_dev *dwc3_get_extcon(struct dwc3 *dwc) 1741 { 1742 struct device *dev = dwc->dev; 1743 struct device_node *np_phy; 1744 struct extcon_dev *edev = NULL; 1745 const char *name; 1746 1747 if (device_property_read_bool(dev, "extcon")) 1748 return extcon_get_edev_by_phandle(dev, 0); 1749 1750 /* 1751 * Device tree platforms should get extcon via phandle. 1752 * On ACPI platforms, we get the name from a device property. 1753 * This device property is for kernel internal use only and 1754 * is expected to be set by the glue code. 1755 */ 1756 if (device_property_read_string(dev, "linux,extcon-name", &name) == 0) 1757 return extcon_get_extcon_dev(name); 1758 1759 /* 1760 * Check explicitly if "usb-role-switch" is used since 1761 * extcon_find_edev_by_node() can not be used to check the absence of 1762 * an extcon device. In the absence of an device it will always return 1763 * EPROBE_DEFER. 1764 */ 1765 if (IS_ENABLED(CONFIG_USB_ROLE_SWITCH) && 1766 device_property_read_bool(dev, "usb-role-switch")) 1767 return NULL; 1768 1769 /* 1770 * Try to get an extcon device from the USB PHY controller's "port" 1771 * node. Check if it has the "port" node first, to avoid printing the 1772 * error message from underlying code, as it's a valid case: extcon 1773 * device (and "port" node) may be missing in case of "usb-role-switch" 1774 * or OTG mode. 1775 */ 1776 np_phy = of_parse_phandle(dev->of_node, "phys", 0); 1777 if (of_graph_is_present(np_phy)) { 1778 struct device_node *np_conn; 1779 1780 np_conn = of_graph_get_remote_node(np_phy, -1, -1); 1781 if (np_conn) 1782 edev = extcon_find_edev_by_node(np_conn); 1783 of_node_put(np_conn); 1784 } 1785 of_node_put(np_phy); 1786 1787 return edev; 1788 } 1789 1790 static int dwc3_get_clocks(struct dwc3 *dwc) 1791 { 1792 struct device *dev = dwc->dev; 1793 1794 if (!dev->of_node) 1795 return 0; 1796 1797 /* 1798 * Clocks are optional, but new DT platforms should support all clocks 1799 * as required by the DT-binding. 1800 * Some devices have different clock names in legacy device trees, 1801 * check for them to retain backwards compatibility. 1802 */ 1803 dwc->bus_clk = devm_clk_get_optional(dev, "bus_early"); 1804 if (IS_ERR(dwc->bus_clk)) { 1805 return dev_err_probe(dev, PTR_ERR(dwc->bus_clk), 1806 "could not get bus clock\n"); 1807 } 1808 1809 if (dwc->bus_clk == NULL) { 1810 dwc->bus_clk = devm_clk_get_optional(dev, "bus_clk"); 1811 if (IS_ERR(dwc->bus_clk)) { 1812 return dev_err_probe(dev, PTR_ERR(dwc->bus_clk), 1813 "could not get bus clock\n"); 1814 } 1815 } 1816 1817 dwc->ref_clk = devm_clk_get_optional(dev, "ref"); 1818 if (IS_ERR(dwc->ref_clk)) { 1819 return dev_err_probe(dev, PTR_ERR(dwc->ref_clk), 1820 "could not get ref clock\n"); 1821 } 1822 1823 if (dwc->ref_clk == NULL) { 1824 dwc->ref_clk = devm_clk_get_optional(dev, "ref_clk"); 1825 if (IS_ERR(dwc->ref_clk)) { 1826 return dev_err_probe(dev, PTR_ERR(dwc->ref_clk), 1827 "could not get ref clock\n"); 1828 } 1829 } 1830 1831 dwc->susp_clk = devm_clk_get_optional(dev, "suspend"); 1832 if (IS_ERR(dwc->susp_clk)) { 1833 return dev_err_probe(dev, PTR_ERR(dwc->susp_clk), 1834 "could not get suspend clock\n"); 1835 } 1836 1837 if (dwc->susp_clk == NULL) { 1838 dwc->susp_clk = devm_clk_get_optional(dev, "suspend_clk"); 1839 if (IS_ERR(dwc->susp_clk)) { 1840 return dev_err_probe(dev, PTR_ERR(dwc->susp_clk), 1841 "could not get suspend clock\n"); 1842 } 1843 } 1844 1845 return 0; 1846 } 1847 1848 static int dwc3_probe(struct platform_device *pdev) 1849 { 1850 struct device *dev = &pdev->dev; 1851 struct resource *res, dwc_res; 1852 void __iomem *regs; 1853 struct dwc3 *dwc; 1854 int ret; 1855 1856 dwc = devm_kzalloc(dev, sizeof(*dwc), GFP_KERNEL); 1857 if (!dwc) 1858 return -ENOMEM; 1859 1860 dwc->dev = dev; 1861 1862 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1863 if (!res) { 1864 dev_err(dev, "missing memory resource\n"); 1865 return -ENODEV; 1866 } 1867 1868 dwc->xhci_resources[0].start = res->start; 1869 dwc->xhci_resources[0].end = dwc->xhci_resources[0].start + 1870 DWC3_XHCI_REGS_END; 1871 dwc->xhci_resources[0].flags = res->flags; 1872 dwc->xhci_resources[0].name = res->name; 1873 1874 /* 1875 * Request memory region but exclude xHCI regs, 1876 * since it will be requested by the xhci-plat driver. 1877 */ 1878 dwc_res = *res; 1879 dwc_res.start += DWC3_GLOBALS_REGS_START; 1880 1881 if (dev->of_node) { 1882 struct device_node *parent = of_get_parent(dev->of_node); 1883 1884 if (of_device_is_compatible(parent, "realtek,rtd-dwc3")) { 1885 dwc_res.start -= DWC3_GLOBALS_REGS_START; 1886 dwc_res.start += DWC3_RTK_RTD_GLOBALS_REGS_START; 1887 } 1888 1889 of_node_put(parent); 1890 } 1891 1892 regs = devm_ioremap_resource(dev, &dwc_res); 1893 if (IS_ERR(regs)) 1894 return PTR_ERR(regs); 1895 1896 dwc->regs = regs; 1897 dwc->regs_size = resource_size(&dwc_res); 1898 1899 dwc3_get_properties(dwc); 1900 1901 dwc->reset = devm_reset_control_array_get_optional_shared(dev); 1902 if (IS_ERR(dwc->reset)) { 1903 ret = PTR_ERR(dwc->reset); 1904 goto err_put_psy; 1905 } 1906 1907 ret = dwc3_get_clocks(dwc); 1908 if (ret) 1909 goto err_put_psy; 1910 1911 ret = reset_control_deassert(dwc->reset); 1912 if (ret) 1913 goto err_put_psy; 1914 1915 ret = dwc3_clk_enable(dwc); 1916 if (ret) 1917 goto err_assert_reset; 1918 1919 if (!dwc3_core_is_valid(dwc)) { 1920 dev_err(dwc->dev, "this is not a DesignWare USB3 DRD Core\n"); 1921 ret = -ENODEV; 1922 goto err_disable_clks; 1923 } 1924 1925 platform_set_drvdata(pdev, dwc); 1926 dwc3_cache_hwparams(dwc); 1927 1928 if (!dwc->sysdev_is_parent && 1929 DWC3_GHWPARAMS0_AWIDTH(dwc->hwparams.hwparams0) == 64) { 1930 ret = dma_set_mask_and_coherent(dwc->sysdev, DMA_BIT_MASK(64)); 1931 if (ret) 1932 goto err_disable_clks; 1933 } 1934 1935 spin_lock_init(&dwc->lock); 1936 mutex_init(&dwc->mutex); 1937 1938 pm_runtime_get_noresume(dev); 1939 pm_runtime_set_active(dev); 1940 pm_runtime_use_autosuspend(dev); 1941 pm_runtime_set_autosuspend_delay(dev, DWC3_DEFAULT_AUTOSUSPEND_DELAY); 1942 pm_runtime_enable(dev); 1943 1944 pm_runtime_forbid(dev); 1945 1946 ret = dwc3_alloc_event_buffers(dwc, DWC3_EVENT_BUFFERS_SIZE); 1947 if (ret) { 1948 dev_err(dwc->dev, "failed to allocate event buffers\n"); 1949 ret = -ENOMEM; 1950 goto err_allow_rpm; 1951 } 1952 1953 dwc->edev = dwc3_get_extcon(dwc); 1954 if (IS_ERR(dwc->edev)) { 1955 ret = dev_err_probe(dwc->dev, PTR_ERR(dwc->edev), "failed to get extcon\n"); 1956 goto err_free_event_buffers; 1957 } 1958 1959 ret = dwc3_get_dr_mode(dwc); 1960 if (ret) 1961 goto err_free_event_buffers; 1962 1963 ret = dwc3_core_init(dwc); 1964 if (ret) { 1965 dev_err_probe(dev, ret, "failed to initialize core\n"); 1966 goto err_free_event_buffers; 1967 } 1968 1969 dwc3_check_params(dwc); 1970 dwc3_debugfs_init(dwc); 1971 1972 ret = dwc3_core_init_mode(dwc); 1973 if (ret) 1974 goto err_exit_debugfs; 1975 1976 pm_runtime_put(dev); 1977 1978 dma_set_max_seg_size(dev, UINT_MAX); 1979 1980 return 0; 1981 1982 err_exit_debugfs: 1983 dwc3_debugfs_exit(dwc); 1984 dwc3_event_buffers_cleanup(dwc); 1985 dwc3_phy_power_off(dwc); 1986 dwc3_phy_exit(dwc); 1987 dwc3_ulpi_exit(dwc); 1988 err_free_event_buffers: 1989 dwc3_free_event_buffers(dwc); 1990 err_allow_rpm: 1991 pm_runtime_allow(dev); 1992 pm_runtime_disable(dev); 1993 pm_runtime_dont_use_autosuspend(dev); 1994 pm_runtime_set_suspended(dev); 1995 pm_runtime_put_noidle(dev); 1996 err_disable_clks: 1997 dwc3_clk_disable(dwc); 1998 err_assert_reset: 1999 reset_control_assert(dwc->reset); 2000 err_put_psy: 2001 if (dwc->usb_psy) 2002 power_supply_put(dwc->usb_psy); 2003 2004 return ret; 2005 } 2006 2007 static void dwc3_remove(struct platform_device *pdev) 2008 { 2009 struct dwc3 *dwc = platform_get_drvdata(pdev); 2010 2011 pm_runtime_get_sync(&pdev->dev); 2012 2013 dwc3_core_exit_mode(dwc); 2014 dwc3_debugfs_exit(dwc); 2015 2016 dwc3_core_exit(dwc); 2017 dwc3_ulpi_exit(dwc); 2018 2019 pm_runtime_allow(&pdev->dev); 2020 pm_runtime_disable(&pdev->dev); 2021 pm_runtime_dont_use_autosuspend(&pdev->dev); 2022 pm_runtime_put_noidle(&pdev->dev); 2023 /* 2024 * HACK: Clear the driver data, which is currently accessed by parent 2025 * glue drivers, before allowing the parent to suspend. 2026 */ 2027 platform_set_drvdata(pdev, NULL); 2028 pm_runtime_set_suspended(&pdev->dev); 2029 2030 dwc3_free_event_buffers(dwc); 2031 2032 if (dwc->usb_psy) 2033 power_supply_put(dwc->usb_psy); 2034 } 2035 2036 #ifdef CONFIG_PM 2037 static int dwc3_core_init_for_resume(struct dwc3 *dwc) 2038 { 2039 int ret; 2040 2041 ret = reset_control_deassert(dwc->reset); 2042 if (ret) 2043 return ret; 2044 2045 ret = dwc3_clk_enable(dwc); 2046 if (ret) 2047 goto assert_reset; 2048 2049 ret = dwc3_core_init(dwc); 2050 if (ret) 2051 goto disable_clks; 2052 2053 return 0; 2054 2055 disable_clks: 2056 dwc3_clk_disable(dwc); 2057 assert_reset: 2058 reset_control_assert(dwc->reset); 2059 2060 return ret; 2061 } 2062 2063 static int dwc3_suspend_common(struct dwc3 *dwc, pm_message_t msg) 2064 { 2065 u32 reg; 2066 2067 switch (dwc->current_dr_role) { 2068 case DWC3_GCTL_PRTCAP_DEVICE: 2069 if (pm_runtime_suspended(dwc->dev)) 2070 break; 2071 dwc3_gadget_suspend(dwc); 2072 synchronize_irq(dwc->irq_gadget); 2073 dwc3_core_exit(dwc); 2074 break; 2075 case DWC3_GCTL_PRTCAP_HOST: 2076 if (!PMSG_IS_AUTO(msg) && !device_may_wakeup(dwc->dev)) { 2077 dwc3_core_exit(dwc); 2078 break; 2079 } 2080 2081 /* Let controller to suspend HSPHY before PHY driver suspends */ 2082 if (dwc->dis_u2_susphy_quirk || 2083 dwc->dis_enblslpm_quirk) { 2084 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0)); 2085 reg |= DWC3_GUSB2PHYCFG_ENBLSLPM | 2086 DWC3_GUSB2PHYCFG_SUSPHY; 2087 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg); 2088 2089 /* Give some time for USB2 PHY to suspend */ 2090 usleep_range(5000, 6000); 2091 } 2092 2093 phy_pm_runtime_put_sync(dwc->usb2_generic_phy); 2094 phy_pm_runtime_put_sync(dwc->usb3_generic_phy); 2095 break; 2096 case DWC3_GCTL_PRTCAP_OTG: 2097 /* do nothing during runtime_suspend */ 2098 if (PMSG_IS_AUTO(msg)) 2099 break; 2100 2101 if (dwc->current_otg_role == DWC3_OTG_ROLE_DEVICE) { 2102 dwc3_gadget_suspend(dwc); 2103 synchronize_irq(dwc->irq_gadget); 2104 } 2105 2106 dwc3_otg_exit(dwc); 2107 dwc3_core_exit(dwc); 2108 break; 2109 default: 2110 /* do nothing */ 2111 break; 2112 } 2113 2114 return 0; 2115 } 2116 2117 static int dwc3_resume_common(struct dwc3 *dwc, pm_message_t msg) 2118 { 2119 int ret; 2120 u32 reg; 2121 2122 switch (dwc->current_dr_role) { 2123 case DWC3_GCTL_PRTCAP_DEVICE: 2124 ret = dwc3_core_init_for_resume(dwc); 2125 if (ret) 2126 return ret; 2127 2128 dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_DEVICE); 2129 dwc3_gadget_resume(dwc); 2130 break; 2131 case DWC3_GCTL_PRTCAP_HOST: 2132 if (!PMSG_IS_AUTO(msg) && !device_may_wakeup(dwc->dev)) { 2133 ret = dwc3_core_init_for_resume(dwc); 2134 if (ret) 2135 return ret; 2136 dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_HOST); 2137 break; 2138 } 2139 /* Restore GUSB2PHYCFG bits that were modified in suspend */ 2140 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0)); 2141 if (dwc->dis_u2_susphy_quirk) 2142 reg &= ~DWC3_GUSB2PHYCFG_SUSPHY; 2143 2144 if (dwc->dis_enblslpm_quirk) 2145 reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM; 2146 2147 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg); 2148 2149 phy_pm_runtime_get_sync(dwc->usb2_generic_phy); 2150 phy_pm_runtime_get_sync(dwc->usb3_generic_phy); 2151 break; 2152 case DWC3_GCTL_PRTCAP_OTG: 2153 /* nothing to do on runtime_resume */ 2154 if (PMSG_IS_AUTO(msg)) 2155 break; 2156 2157 ret = dwc3_core_init_for_resume(dwc); 2158 if (ret) 2159 return ret; 2160 2161 dwc3_set_prtcap(dwc, dwc->current_dr_role); 2162 2163 dwc3_otg_init(dwc); 2164 if (dwc->current_otg_role == DWC3_OTG_ROLE_HOST) { 2165 dwc3_otg_host_init(dwc); 2166 } else if (dwc->current_otg_role == DWC3_OTG_ROLE_DEVICE) { 2167 dwc3_gadget_resume(dwc); 2168 } 2169 2170 break; 2171 default: 2172 /* do nothing */ 2173 break; 2174 } 2175 2176 return 0; 2177 } 2178 2179 static int dwc3_runtime_checks(struct dwc3 *dwc) 2180 { 2181 switch (dwc->current_dr_role) { 2182 case DWC3_GCTL_PRTCAP_DEVICE: 2183 if (dwc->connected) 2184 return -EBUSY; 2185 break; 2186 case DWC3_GCTL_PRTCAP_HOST: 2187 default: 2188 /* do nothing */ 2189 break; 2190 } 2191 2192 return 0; 2193 } 2194 2195 static int dwc3_runtime_suspend(struct device *dev) 2196 { 2197 struct dwc3 *dwc = dev_get_drvdata(dev); 2198 int ret; 2199 2200 if (dwc3_runtime_checks(dwc)) 2201 return -EBUSY; 2202 2203 ret = dwc3_suspend_common(dwc, PMSG_AUTO_SUSPEND); 2204 if (ret) 2205 return ret; 2206 2207 return 0; 2208 } 2209 2210 static int dwc3_runtime_resume(struct device *dev) 2211 { 2212 struct dwc3 *dwc = dev_get_drvdata(dev); 2213 int ret; 2214 2215 ret = dwc3_resume_common(dwc, PMSG_AUTO_RESUME); 2216 if (ret) 2217 return ret; 2218 2219 switch (dwc->current_dr_role) { 2220 case DWC3_GCTL_PRTCAP_DEVICE: 2221 dwc3_gadget_process_pending_events(dwc); 2222 break; 2223 case DWC3_GCTL_PRTCAP_HOST: 2224 default: 2225 /* do nothing */ 2226 break; 2227 } 2228 2229 pm_runtime_mark_last_busy(dev); 2230 2231 return 0; 2232 } 2233 2234 static int dwc3_runtime_idle(struct device *dev) 2235 { 2236 struct dwc3 *dwc = dev_get_drvdata(dev); 2237 2238 switch (dwc->current_dr_role) { 2239 case DWC3_GCTL_PRTCAP_DEVICE: 2240 if (dwc3_runtime_checks(dwc)) 2241 return -EBUSY; 2242 break; 2243 case DWC3_GCTL_PRTCAP_HOST: 2244 default: 2245 /* do nothing */ 2246 break; 2247 } 2248 2249 pm_runtime_mark_last_busy(dev); 2250 pm_runtime_autosuspend(dev); 2251 2252 return 0; 2253 } 2254 #endif /* CONFIG_PM */ 2255 2256 #ifdef CONFIG_PM_SLEEP 2257 static int dwc3_suspend(struct device *dev) 2258 { 2259 struct dwc3 *dwc = dev_get_drvdata(dev); 2260 int ret; 2261 2262 ret = dwc3_suspend_common(dwc, PMSG_SUSPEND); 2263 if (ret) 2264 return ret; 2265 2266 pinctrl_pm_select_sleep_state(dev); 2267 2268 return 0; 2269 } 2270 2271 static int dwc3_resume(struct device *dev) 2272 { 2273 struct dwc3 *dwc = dev_get_drvdata(dev); 2274 int ret; 2275 2276 pinctrl_pm_select_default_state(dev); 2277 2278 ret = dwc3_resume_common(dwc, PMSG_RESUME); 2279 if (ret) 2280 return ret; 2281 2282 pm_runtime_disable(dev); 2283 pm_runtime_set_active(dev); 2284 pm_runtime_enable(dev); 2285 2286 return 0; 2287 } 2288 2289 static void dwc3_complete(struct device *dev) 2290 { 2291 struct dwc3 *dwc = dev_get_drvdata(dev); 2292 u32 reg; 2293 2294 if (dwc->current_dr_role == DWC3_GCTL_PRTCAP_HOST && 2295 dwc->dis_split_quirk) { 2296 reg = dwc3_readl(dwc->regs, DWC3_GUCTL3); 2297 reg |= DWC3_GUCTL3_SPLITDISABLE; 2298 dwc3_writel(dwc->regs, DWC3_GUCTL3, reg); 2299 } 2300 } 2301 #else 2302 #define dwc3_complete NULL 2303 #endif /* CONFIG_PM_SLEEP */ 2304 2305 static const struct dev_pm_ops dwc3_dev_pm_ops = { 2306 SET_SYSTEM_SLEEP_PM_OPS(dwc3_suspend, dwc3_resume) 2307 .complete = dwc3_complete, 2308 SET_RUNTIME_PM_OPS(dwc3_runtime_suspend, dwc3_runtime_resume, 2309 dwc3_runtime_idle) 2310 }; 2311 2312 #ifdef CONFIG_OF 2313 static const struct of_device_id of_dwc3_match[] = { 2314 { 2315 .compatible = "snps,dwc3" 2316 }, 2317 { 2318 .compatible = "synopsys,dwc3" 2319 }, 2320 { }, 2321 }; 2322 MODULE_DEVICE_TABLE(of, of_dwc3_match); 2323 #endif 2324 2325 #ifdef CONFIG_ACPI 2326 2327 #define ACPI_ID_INTEL_BSW "808622B7" 2328 2329 static const struct acpi_device_id dwc3_acpi_match[] = { 2330 { ACPI_ID_INTEL_BSW, 0 }, 2331 { }, 2332 }; 2333 MODULE_DEVICE_TABLE(acpi, dwc3_acpi_match); 2334 #endif 2335 2336 static struct platform_driver dwc3_driver = { 2337 .probe = dwc3_probe, 2338 .remove_new = dwc3_remove, 2339 .driver = { 2340 .name = "dwc3", 2341 .of_match_table = of_match_ptr(of_dwc3_match), 2342 .acpi_match_table = ACPI_PTR(dwc3_acpi_match), 2343 .pm = &dwc3_dev_pm_ops, 2344 }, 2345 }; 2346 2347 module_platform_driver(dwc3_driver); 2348 2349 MODULE_ALIAS("platform:dwc3"); 2350 MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>"); 2351 MODULE_LICENSE("GPL v2"); 2352 MODULE_DESCRIPTION("DesignWare USB3 DRD Controller Driver"); 2353