1 // SPDX-License-Identifier: GPL-2.0 2 /** 3 * core.c - DesignWare USB3 DRD Controller Core file 4 * 5 * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com 6 * 7 * Authors: Felipe Balbi <balbi@ti.com>, 8 * Sebastian Andrzej Siewior <bigeasy@linutronix.de> 9 */ 10 11 #include <linux/version.h> 12 #include <linux/module.h> 13 #include <linux/kernel.h> 14 #include <linux/slab.h> 15 #include <linux/spinlock.h> 16 #include <linux/platform_device.h> 17 #include <linux/pm_runtime.h> 18 #include <linux/interrupt.h> 19 #include <linux/ioport.h> 20 #include <linux/io.h> 21 #include <linux/list.h> 22 #include <linux/delay.h> 23 #include <linux/dma-mapping.h> 24 #include <linux/of.h> 25 #include <linux/acpi.h> 26 #include <linux/pinctrl/consumer.h> 27 28 #include <linux/usb/ch9.h> 29 #include <linux/usb/gadget.h> 30 #include <linux/usb/of.h> 31 #include <linux/usb/otg.h> 32 33 #include "core.h" 34 #include "gadget.h" 35 #include "io.h" 36 37 #include "debug.h" 38 39 #define DWC3_DEFAULT_AUTOSUSPEND_DELAY 5000 /* ms */ 40 41 /** 42 * dwc3_get_dr_mode - Validates and sets dr_mode 43 * @dwc: pointer to our context structure 44 */ 45 static int dwc3_get_dr_mode(struct dwc3 *dwc) 46 { 47 enum usb_dr_mode mode; 48 struct device *dev = dwc->dev; 49 unsigned int hw_mode; 50 51 if (dwc->dr_mode == USB_DR_MODE_UNKNOWN) 52 dwc->dr_mode = USB_DR_MODE_OTG; 53 54 mode = dwc->dr_mode; 55 hw_mode = DWC3_GHWPARAMS0_MODE(dwc->hwparams.hwparams0); 56 57 switch (hw_mode) { 58 case DWC3_GHWPARAMS0_MODE_GADGET: 59 if (IS_ENABLED(CONFIG_USB_DWC3_HOST)) { 60 dev_err(dev, 61 "Controller does not support host mode.\n"); 62 return -EINVAL; 63 } 64 mode = USB_DR_MODE_PERIPHERAL; 65 break; 66 case DWC3_GHWPARAMS0_MODE_HOST: 67 if (IS_ENABLED(CONFIG_USB_DWC3_GADGET)) { 68 dev_err(dev, 69 "Controller does not support device mode.\n"); 70 return -EINVAL; 71 } 72 mode = USB_DR_MODE_HOST; 73 break; 74 default: 75 if (IS_ENABLED(CONFIG_USB_DWC3_HOST)) 76 mode = USB_DR_MODE_HOST; 77 else if (IS_ENABLED(CONFIG_USB_DWC3_GADGET)) 78 mode = USB_DR_MODE_PERIPHERAL; 79 } 80 81 if (mode != dwc->dr_mode) { 82 dev_warn(dev, 83 "Configuration mismatch. dr_mode forced to %s\n", 84 mode == USB_DR_MODE_HOST ? "host" : "gadget"); 85 86 dwc->dr_mode = mode; 87 } 88 89 return 0; 90 } 91 92 void dwc3_set_prtcap(struct dwc3 *dwc, u32 mode) 93 { 94 u32 reg; 95 96 reg = dwc3_readl(dwc->regs, DWC3_GCTL); 97 reg &= ~(DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_OTG)); 98 reg |= DWC3_GCTL_PRTCAPDIR(mode); 99 dwc3_writel(dwc->regs, DWC3_GCTL, reg); 100 101 dwc->current_dr_role = mode; 102 } 103 104 static void __dwc3_set_mode(struct work_struct *work) 105 { 106 struct dwc3 *dwc = work_to_dwc(work); 107 unsigned long flags; 108 int ret; 109 110 if (dwc->dr_mode != USB_DR_MODE_OTG) 111 return; 112 113 if (dwc->current_dr_role == DWC3_GCTL_PRTCAP_OTG) 114 dwc3_otg_update(dwc, 0); 115 116 if (!dwc->desired_dr_role) 117 return; 118 119 if (dwc->desired_dr_role == dwc->current_dr_role) 120 return; 121 122 if (dwc->desired_dr_role == DWC3_GCTL_PRTCAP_OTG && dwc->edev) 123 return; 124 125 switch (dwc->current_dr_role) { 126 case DWC3_GCTL_PRTCAP_HOST: 127 dwc3_host_exit(dwc); 128 break; 129 case DWC3_GCTL_PRTCAP_DEVICE: 130 dwc3_gadget_exit(dwc); 131 dwc3_event_buffers_cleanup(dwc); 132 break; 133 case DWC3_GCTL_PRTCAP_OTG: 134 dwc3_otg_exit(dwc); 135 spin_lock_irqsave(&dwc->lock, flags); 136 dwc->desired_otg_role = DWC3_OTG_ROLE_IDLE; 137 spin_unlock_irqrestore(&dwc->lock, flags); 138 dwc3_otg_update(dwc, 1); 139 break; 140 default: 141 break; 142 } 143 144 spin_lock_irqsave(&dwc->lock, flags); 145 146 dwc3_set_prtcap(dwc, dwc->desired_dr_role); 147 148 spin_unlock_irqrestore(&dwc->lock, flags); 149 150 switch (dwc->desired_dr_role) { 151 case DWC3_GCTL_PRTCAP_HOST: 152 ret = dwc3_host_init(dwc); 153 if (ret) { 154 dev_err(dwc->dev, "failed to initialize host\n"); 155 } else { 156 if (dwc->usb2_phy) 157 otg_set_vbus(dwc->usb2_phy->otg, true); 158 phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_HOST); 159 phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_HOST); 160 phy_calibrate(dwc->usb2_generic_phy); 161 } 162 break; 163 case DWC3_GCTL_PRTCAP_DEVICE: 164 dwc3_event_buffers_setup(dwc); 165 166 if (dwc->usb2_phy) 167 otg_set_vbus(dwc->usb2_phy->otg, false); 168 phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_DEVICE); 169 phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_DEVICE); 170 171 ret = dwc3_gadget_init(dwc); 172 if (ret) 173 dev_err(dwc->dev, "failed to initialize peripheral\n"); 174 break; 175 case DWC3_GCTL_PRTCAP_OTG: 176 dwc3_otg_init(dwc); 177 dwc3_otg_update(dwc, 0); 178 break; 179 default: 180 break; 181 } 182 183 } 184 185 void dwc3_set_mode(struct dwc3 *dwc, u32 mode) 186 { 187 unsigned long flags; 188 189 spin_lock_irqsave(&dwc->lock, flags); 190 dwc->desired_dr_role = mode; 191 spin_unlock_irqrestore(&dwc->lock, flags); 192 193 queue_work(system_freezable_wq, &dwc->drd_work); 194 } 195 196 u32 dwc3_core_fifo_space(struct dwc3_ep *dep, u8 type) 197 { 198 struct dwc3 *dwc = dep->dwc; 199 u32 reg; 200 201 dwc3_writel(dwc->regs, DWC3_GDBGFIFOSPACE, 202 DWC3_GDBGFIFOSPACE_NUM(dep->number) | 203 DWC3_GDBGFIFOSPACE_TYPE(type)); 204 205 reg = dwc3_readl(dwc->regs, DWC3_GDBGFIFOSPACE); 206 207 return DWC3_GDBGFIFOSPACE_SPACE_AVAILABLE(reg); 208 } 209 210 /** 211 * dwc3_core_soft_reset - Issues core soft reset and PHY reset 212 * @dwc: pointer to our context structure 213 */ 214 static int dwc3_core_soft_reset(struct dwc3 *dwc) 215 { 216 u32 reg; 217 int retries = 1000; 218 int ret; 219 220 usb_phy_init(dwc->usb2_phy); 221 usb_phy_init(dwc->usb3_phy); 222 ret = phy_init(dwc->usb2_generic_phy); 223 if (ret < 0) 224 return ret; 225 226 ret = phy_init(dwc->usb3_generic_phy); 227 if (ret < 0) { 228 phy_exit(dwc->usb2_generic_phy); 229 return ret; 230 } 231 232 /* 233 * We're resetting only the device side because, if we're in host mode, 234 * XHCI driver will reset the host block. If dwc3 was configured for 235 * host-only mode, then we can return early. 236 */ 237 if (dwc->current_dr_role == DWC3_GCTL_PRTCAP_HOST) 238 return 0; 239 240 reg = dwc3_readl(dwc->regs, DWC3_DCTL); 241 reg |= DWC3_DCTL_CSFTRST; 242 dwc3_writel(dwc->regs, DWC3_DCTL, reg); 243 244 do { 245 reg = dwc3_readl(dwc->regs, DWC3_DCTL); 246 if (!(reg & DWC3_DCTL_CSFTRST)) 247 goto done; 248 249 udelay(1); 250 } while (--retries); 251 252 phy_exit(dwc->usb3_generic_phy); 253 phy_exit(dwc->usb2_generic_phy); 254 255 return -ETIMEDOUT; 256 257 done: 258 /* 259 * For DWC_usb31 controller, once DWC3_DCTL_CSFTRST bit is cleared, 260 * we must wait at least 50ms before accessing the PHY domain 261 * (synchronization delay). DWC_usb31 programming guide section 1.3.2. 262 */ 263 if (dwc3_is_usb31(dwc)) 264 msleep(50); 265 266 return 0; 267 } 268 269 /* 270 * dwc3_frame_length_adjustment - Adjusts frame length if required 271 * @dwc3: Pointer to our controller context structure 272 */ 273 static void dwc3_frame_length_adjustment(struct dwc3 *dwc) 274 { 275 u32 reg; 276 u32 dft; 277 278 if (dwc->revision < DWC3_REVISION_250A) 279 return; 280 281 if (dwc->fladj == 0) 282 return; 283 284 reg = dwc3_readl(dwc->regs, DWC3_GFLADJ); 285 dft = reg & DWC3_GFLADJ_30MHZ_MASK; 286 if (!dev_WARN_ONCE(dwc->dev, dft == dwc->fladj, 287 "request value same as default, ignoring\n")) { 288 reg &= ~DWC3_GFLADJ_30MHZ_MASK; 289 reg |= DWC3_GFLADJ_30MHZ_SDBND_SEL | dwc->fladj; 290 dwc3_writel(dwc->regs, DWC3_GFLADJ, reg); 291 } 292 } 293 294 /** 295 * dwc3_free_one_event_buffer - Frees one event buffer 296 * @dwc: Pointer to our controller context structure 297 * @evt: Pointer to event buffer to be freed 298 */ 299 static void dwc3_free_one_event_buffer(struct dwc3 *dwc, 300 struct dwc3_event_buffer *evt) 301 { 302 dma_free_coherent(dwc->sysdev, evt->length, evt->buf, evt->dma); 303 } 304 305 /** 306 * dwc3_alloc_one_event_buffer - Allocates one event buffer structure 307 * @dwc: Pointer to our controller context structure 308 * @length: size of the event buffer 309 * 310 * Returns a pointer to the allocated event buffer structure on success 311 * otherwise ERR_PTR(errno). 312 */ 313 static struct dwc3_event_buffer *dwc3_alloc_one_event_buffer(struct dwc3 *dwc, 314 unsigned length) 315 { 316 struct dwc3_event_buffer *evt; 317 318 evt = devm_kzalloc(dwc->dev, sizeof(*evt), GFP_KERNEL); 319 if (!evt) 320 return ERR_PTR(-ENOMEM); 321 322 evt->dwc = dwc; 323 evt->length = length; 324 evt->cache = devm_kzalloc(dwc->dev, length, GFP_KERNEL); 325 if (!evt->cache) 326 return ERR_PTR(-ENOMEM); 327 328 evt->buf = dma_alloc_coherent(dwc->sysdev, length, 329 &evt->dma, GFP_KERNEL); 330 if (!evt->buf) 331 return ERR_PTR(-ENOMEM); 332 333 return evt; 334 } 335 336 /** 337 * dwc3_free_event_buffers - frees all allocated event buffers 338 * @dwc: Pointer to our controller context structure 339 */ 340 static void dwc3_free_event_buffers(struct dwc3 *dwc) 341 { 342 struct dwc3_event_buffer *evt; 343 344 evt = dwc->ev_buf; 345 if (evt) 346 dwc3_free_one_event_buffer(dwc, evt); 347 } 348 349 /** 350 * dwc3_alloc_event_buffers - Allocates @num event buffers of size @length 351 * @dwc: pointer to our controller context structure 352 * @length: size of event buffer 353 * 354 * Returns 0 on success otherwise negative errno. In the error case, dwc 355 * may contain some buffers allocated but not all which were requested. 356 */ 357 static int dwc3_alloc_event_buffers(struct dwc3 *dwc, unsigned length) 358 { 359 struct dwc3_event_buffer *evt; 360 361 evt = dwc3_alloc_one_event_buffer(dwc, length); 362 if (IS_ERR(evt)) { 363 dev_err(dwc->dev, "can't allocate event buffer\n"); 364 return PTR_ERR(evt); 365 } 366 dwc->ev_buf = evt; 367 368 return 0; 369 } 370 371 /** 372 * dwc3_event_buffers_setup - setup our allocated event buffers 373 * @dwc: pointer to our controller context structure 374 * 375 * Returns 0 on success otherwise negative errno. 376 */ 377 int dwc3_event_buffers_setup(struct dwc3 *dwc) 378 { 379 struct dwc3_event_buffer *evt; 380 381 evt = dwc->ev_buf; 382 evt->lpos = 0; 383 dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(0), 384 lower_32_bits(evt->dma)); 385 dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(0), 386 upper_32_bits(evt->dma)); 387 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0), 388 DWC3_GEVNTSIZ_SIZE(evt->length)); 389 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), 0); 390 391 return 0; 392 } 393 394 void dwc3_event_buffers_cleanup(struct dwc3 *dwc) 395 { 396 struct dwc3_event_buffer *evt; 397 398 evt = dwc->ev_buf; 399 400 evt->lpos = 0; 401 402 dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(0), 0); 403 dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(0), 0); 404 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0), DWC3_GEVNTSIZ_INTMASK 405 | DWC3_GEVNTSIZ_SIZE(0)); 406 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), 0); 407 } 408 409 static int dwc3_alloc_scratch_buffers(struct dwc3 *dwc) 410 { 411 if (!dwc->has_hibernation) 412 return 0; 413 414 if (!dwc->nr_scratch) 415 return 0; 416 417 dwc->scratchbuf = kmalloc_array(dwc->nr_scratch, 418 DWC3_SCRATCHBUF_SIZE, GFP_KERNEL); 419 if (!dwc->scratchbuf) 420 return -ENOMEM; 421 422 return 0; 423 } 424 425 static int dwc3_setup_scratch_buffers(struct dwc3 *dwc) 426 { 427 dma_addr_t scratch_addr; 428 u32 param; 429 int ret; 430 431 if (!dwc->has_hibernation) 432 return 0; 433 434 if (!dwc->nr_scratch) 435 return 0; 436 437 /* should never fall here */ 438 if (!WARN_ON(dwc->scratchbuf)) 439 return 0; 440 441 scratch_addr = dma_map_single(dwc->sysdev, dwc->scratchbuf, 442 dwc->nr_scratch * DWC3_SCRATCHBUF_SIZE, 443 DMA_BIDIRECTIONAL); 444 if (dma_mapping_error(dwc->sysdev, scratch_addr)) { 445 dev_err(dwc->sysdev, "failed to map scratch buffer\n"); 446 ret = -EFAULT; 447 goto err0; 448 } 449 450 dwc->scratch_addr = scratch_addr; 451 452 param = lower_32_bits(scratch_addr); 453 454 ret = dwc3_send_gadget_generic_command(dwc, 455 DWC3_DGCMD_SET_SCRATCHPAD_ADDR_LO, param); 456 if (ret < 0) 457 goto err1; 458 459 param = upper_32_bits(scratch_addr); 460 461 ret = dwc3_send_gadget_generic_command(dwc, 462 DWC3_DGCMD_SET_SCRATCHPAD_ADDR_HI, param); 463 if (ret < 0) 464 goto err1; 465 466 return 0; 467 468 err1: 469 dma_unmap_single(dwc->sysdev, dwc->scratch_addr, dwc->nr_scratch * 470 DWC3_SCRATCHBUF_SIZE, DMA_BIDIRECTIONAL); 471 472 err0: 473 return ret; 474 } 475 476 static void dwc3_free_scratch_buffers(struct dwc3 *dwc) 477 { 478 if (!dwc->has_hibernation) 479 return; 480 481 if (!dwc->nr_scratch) 482 return; 483 484 /* should never fall here */ 485 if (!WARN_ON(dwc->scratchbuf)) 486 return; 487 488 dma_unmap_single(dwc->sysdev, dwc->scratch_addr, dwc->nr_scratch * 489 DWC3_SCRATCHBUF_SIZE, DMA_BIDIRECTIONAL); 490 kfree(dwc->scratchbuf); 491 } 492 493 static void dwc3_core_num_eps(struct dwc3 *dwc) 494 { 495 struct dwc3_hwparams *parms = &dwc->hwparams; 496 497 dwc->num_eps = DWC3_NUM_EPS(parms); 498 } 499 500 static void dwc3_cache_hwparams(struct dwc3 *dwc) 501 { 502 struct dwc3_hwparams *parms = &dwc->hwparams; 503 504 parms->hwparams0 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS0); 505 parms->hwparams1 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS1); 506 parms->hwparams2 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS2); 507 parms->hwparams3 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS3); 508 parms->hwparams4 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS4); 509 parms->hwparams5 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS5); 510 parms->hwparams6 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS6); 511 parms->hwparams7 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS7); 512 parms->hwparams8 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS8); 513 } 514 515 static int dwc3_core_ulpi_init(struct dwc3 *dwc) 516 { 517 int intf; 518 int ret = 0; 519 520 intf = DWC3_GHWPARAMS3_HSPHY_IFC(dwc->hwparams.hwparams3); 521 522 if (intf == DWC3_GHWPARAMS3_HSPHY_IFC_ULPI || 523 (intf == DWC3_GHWPARAMS3_HSPHY_IFC_UTMI_ULPI && 524 dwc->hsphy_interface && 525 !strncmp(dwc->hsphy_interface, "ulpi", 4))) 526 ret = dwc3_ulpi_init(dwc); 527 528 return ret; 529 } 530 531 /** 532 * dwc3_phy_setup - Configure USB PHY Interface of DWC3 Core 533 * @dwc: Pointer to our controller context structure 534 * 535 * Returns 0 on success. The USB PHY interfaces are configured but not 536 * initialized. The PHY interfaces and the PHYs get initialized together with 537 * the core in dwc3_core_init. 538 */ 539 static int dwc3_phy_setup(struct dwc3 *dwc) 540 { 541 u32 reg; 542 543 reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0)); 544 545 /* 546 * Make sure UX_EXIT_PX is cleared as that causes issues with some 547 * PHYs. Also, this bit is not supposed to be used in normal operation. 548 */ 549 reg &= ~DWC3_GUSB3PIPECTL_UX_EXIT_PX; 550 551 /* 552 * Above 1.94a, it is recommended to set DWC3_GUSB3PIPECTL_SUSPHY 553 * to '0' during coreConsultant configuration. So default value 554 * will be '0' when the core is reset. Application needs to set it 555 * to '1' after the core initialization is completed. 556 */ 557 if (dwc->revision > DWC3_REVISION_194A) 558 reg |= DWC3_GUSB3PIPECTL_SUSPHY; 559 560 if (dwc->u2ss_inp3_quirk) 561 reg |= DWC3_GUSB3PIPECTL_U2SSINP3OK; 562 563 if (dwc->dis_rxdet_inp3_quirk) 564 reg |= DWC3_GUSB3PIPECTL_DISRXDETINP3; 565 566 if (dwc->req_p1p2p3_quirk) 567 reg |= DWC3_GUSB3PIPECTL_REQP1P2P3; 568 569 if (dwc->del_p1p2p3_quirk) 570 reg |= DWC3_GUSB3PIPECTL_DEP1P2P3_EN; 571 572 if (dwc->del_phy_power_chg_quirk) 573 reg |= DWC3_GUSB3PIPECTL_DEPOCHANGE; 574 575 if (dwc->lfps_filter_quirk) 576 reg |= DWC3_GUSB3PIPECTL_LFPSFILT; 577 578 if (dwc->rx_detect_poll_quirk) 579 reg |= DWC3_GUSB3PIPECTL_RX_DETOPOLL; 580 581 if (dwc->tx_de_emphasis_quirk) 582 reg |= DWC3_GUSB3PIPECTL_TX_DEEPH(dwc->tx_de_emphasis); 583 584 if (dwc->dis_u3_susphy_quirk) 585 reg &= ~DWC3_GUSB3PIPECTL_SUSPHY; 586 587 if (dwc->dis_del_phy_power_chg_quirk) 588 reg &= ~DWC3_GUSB3PIPECTL_DEPOCHANGE; 589 590 dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg); 591 592 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0)); 593 594 /* Select the HS PHY interface */ 595 switch (DWC3_GHWPARAMS3_HSPHY_IFC(dwc->hwparams.hwparams3)) { 596 case DWC3_GHWPARAMS3_HSPHY_IFC_UTMI_ULPI: 597 if (dwc->hsphy_interface && 598 !strncmp(dwc->hsphy_interface, "utmi", 4)) { 599 reg &= ~DWC3_GUSB2PHYCFG_ULPI_UTMI; 600 break; 601 } else if (dwc->hsphy_interface && 602 !strncmp(dwc->hsphy_interface, "ulpi", 4)) { 603 reg |= DWC3_GUSB2PHYCFG_ULPI_UTMI; 604 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg); 605 } else { 606 /* Relying on default value. */ 607 if (!(reg & DWC3_GUSB2PHYCFG_ULPI_UTMI)) 608 break; 609 } 610 /* FALLTHROUGH */ 611 case DWC3_GHWPARAMS3_HSPHY_IFC_ULPI: 612 /* FALLTHROUGH */ 613 default: 614 break; 615 } 616 617 switch (dwc->hsphy_mode) { 618 case USBPHY_INTERFACE_MODE_UTMI: 619 reg &= ~(DWC3_GUSB2PHYCFG_PHYIF_MASK | 620 DWC3_GUSB2PHYCFG_USBTRDTIM_MASK); 621 reg |= DWC3_GUSB2PHYCFG_PHYIF(UTMI_PHYIF_8_BIT) | 622 DWC3_GUSB2PHYCFG_USBTRDTIM(USBTRDTIM_UTMI_8_BIT); 623 break; 624 case USBPHY_INTERFACE_MODE_UTMIW: 625 reg &= ~(DWC3_GUSB2PHYCFG_PHYIF_MASK | 626 DWC3_GUSB2PHYCFG_USBTRDTIM_MASK); 627 reg |= DWC3_GUSB2PHYCFG_PHYIF(UTMI_PHYIF_16_BIT) | 628 DWC3_GUSB2PHYCFG_USBTRDTIM(USBTRDTIM_UTMI_16_BIT); 629 break; 630 default: 631 break; 632 } 633 634 /* 635 * Above 1.94a, it is recommended to set DWC3_GUSB2PHYCFG_SUSPHY to 636 * '0' during coreConsultant configuration. So default value will 637 * be '0' when the core is reset. Application needs to set it to 638 * '1' after the core initialization is completed. 639 */ 640 if (dwc->revision > DWC3_REVISION_194A) 641 reg |= DWC3_GUSB2PHYCFG_SUSPHY; 642 643 if (dwc->dis_u2_susphy_quirk) 644 reg &= ~DWC3_GUSB2PHYCFG_SUSPHY; 645 646 if (dwc->dis_enblslpm_quirk) 647 reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM; 648 649 if (dwc->dis_u2_freeclk_exists_quirk) 650 reg &= ~DWC3_GUSB2PHYCFG_U2_FREECLK_EXISTS; 651 652 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg); 653 654 return 0; 655 } 656 657 static void dwc3_core_exit(struct dwc3 *dwc) 658 { 659 dwc3_event_buffers_cleanup(dwc); 660 661 usb_phy_shutdown(dwc->usb2_phy); 662 usb_phy_shutdown(dwc->usb3_phy); 663 phy_exit(dwc->usb2_generic_phy); 664 phy_exit(dwc->usb3_generic_phy); 665 666 usb_phy_set_suspend(dwc->usb2_phy, 1); 667 usb_phy_set_suspend(dwc->usb3_phy, 1); 668 phy_power_off(dwc->usb2_generic_phy); 669 phy_power_off(dwc->usb3_generic_phy); 670 } 671 672 static bool dwc3_core_is_valid(struct dwc3 *dwc) 673 { 674 u32 reg; 675 676 reg = dwc3_readl(dwc->regs, DWC3_GSNPSID); 677 678 /* This should read as U3 followed by revision number */ 679 if ((reg & DWC3_GSNPSID_MASK) == 0x55330000) { 680 /* Detected DWC_usb3 IP */ 681 dwc->revision = reg; 682 } else if ((reg & DWC3_GSNPSID_MASK) == 0x33310000) { 683 /* Detected DWC_usb31 IP */ 684 dwc->revision = dwc3_readl(dwc->regs, DWC3_VER_NUMBER); 685 dwc->revision |= DWC3_REVISION_IS_DWC31; 686 } else { 687 return false; 688 } 689 690 return true; 691 } 692 693 static void dwc3_core_setup_global_control(struct dwc3 *dwc) 694 { 695 u32 hwparams4 = dwc->hwparams.hwparams4; 696 u32 reg; 697 698 reg = dwc3_readl(dwc->regs, DWC3_GCTL); 699 reg &= ~DWC3_GCTL_SCALEDOWN_MASK; 700 701 switch (DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1)) { 702 case DWC3_GHWPARAMS1_EN_PWROPT_CLK: 703 /** 704 * WORKAROUND: DWC3 revisions between 2.10a and 2.50a have an 705 * issue which would cause xHCI compliance tests to fail. 706 * 707 * Because of that we cannot enable clock gating on such 708 * configurations. 709 * 710 * Refers to: 711 * 712 * STAR#9000588375: Clock Gating, SOF Issues when ref_clk-Based 713 * SOF/ITP Mode Used 714 */ 715 if ((dwc->dr_mode == USB_DR_MODE_HOST || 716 dwc->dr_mode == USB_DR_MODE_OTG) && 717 (dwc->revision >= DWC3_REVISION_210A && 718 dwc->revision <= DWC3_REVISION_250A)) 719 reg |= DWC3_GCTL_DSBLCLKGTNG | DWC3_GCTL_SOFITPSYNC; 720 else 721 reg &= ~DWC3_GCTL_DSBLCLKGTNG; 722 break; 723 case DWC3_GHWPARAMS1_EN_PWROPT_HIB: 724 /* enable hibernation here */ 725 dwc->nr_scratch = DWC3_GHWPARAMS4_HIBER_SCRATCHBUFS(hwparams4); 726 727 /* 728 * REVISIT Enabling this bit so that host-mode hibernation 729 * will work. Device-mode hibernation is not yet implemented. 730 */ 731 reg |= DWC3_GCTL_GBLHIBERNATIONEN; 732 break; 733 default: 734 /* nothing */ 735 break; 736 } 737 738 /* check if current dwc3 is on simulation board */ 739 if (dwc->hwparams.hwparams6 & DWC3_GHWPARAMS6_EN_FPGA) { 740 dev_info(dwc->dev, "Running with FPGA optmizations\n"); 741 dwc->is_fpga = true; 742 } 743 744 WARN_ONCE(dwc->disable_scramble_quirk && !dwc->is_fpga, 745 "disable_scramble cannot be used on non-FPGA builds\n"); 746 747 if (dwc->disable_scramble_quirk && dwc->is_fpga) 748 reg |= DWC3_GCTL_DISSCRAMBLE; 749 else 750 reg &= ~DWC3_GCTL_DISSCRAMBLE; 751 752 if (dwc->u2exit_lfps_quirk) 753 reg |= DWC3_GCTL_U2EXIT_LFPS; 754 755 /* 756 * WORKAROUND: DWC3 revisions <1.90a have a bug 757 * where the device can fail to connect at SuperSpeed 758 * and falls back to high-speed mode which causes 759 * the device to enter a Connect/Disconnect loop 760 */ 761 if (dwc->revision < DWC3_REVISION_190A) 762 reg |= DWC3_GCTL_U2RSTECN; 763 764 dwc3_writel(dwc->regs, DWC3_GCTL, reg); 765 } 766 767 static int dwc3_core_get_phy(struct dwc3 *dwc); 768 static int dwc3_core_ulpi_init(struct dwc3 *dwc); 769 770 /** 771 * dwc3_core_init - Low-level initialization of DWC3 Core 772 * @dwc: Pointer to our controller context structure 773 * 774 * Returns 0 on success otherwise negative errno. 775 */ 776 static int dwc3_core_init(struct dwc3 *dwc) 777 { 778 u32 reg; 779 int ret; 780 781 if (!dwc3_core_is_valid(dwc)) { 782 dev_err(dwc->dev, "this is not a DesignWare USB3 DRD Core\n"); 783 ret = -ENODEV; 784 goto err0; 785 } 786 787 /* 788 * Write Linux Version Code to our GUID register so it's easy to figure 789 * out which kernel version a bug was found. 790 */ 791 dwc3_writel(dwc->regs, DWC3_GUID, LINUX_VERSION_CODE); 792 793 /* Handle USB2.0-only core configuration */ 794 if (DWC3_GHWPARAMS3_SSPHY_IFC(dwc->hwparams.hwparams3) == 795 DWC3_GHWPARAMS3_SSPHY_IFC_DIS) { 796 if (dwc->maximum_speed == USB_SPEED_SUPER) 797 dwc->maximum_speed = USB_SPEED_HIGH; 798 } 799 800 ret = dwc3_phy_setup(dwc); 801 if (ret) 802 goto err0; 803 804 if (!dwc->ulpi_ready) { 805 ret = dwc3_core_ulpi_init(dwc); 806 if (ret) 807 goto err0; 808 dwc->ulpi_ready = true; 809 } 810 811 if (!dwc->phys_ready) { 812 ret = dwc3_core_get_phy(dwc); 813 if (ret) 814 goto err0a; 815 dwc->phys_ready = true; 816 } 817 818 ret = dwc3_core_soft_reset(dwc); 819 if (ret) 820 goto err0a; 821 822 dwc3_core_setup_global_control(dwc); 823 dwc3_core_num_eps(dwc); 824 825 ret = dwc3_setup_scratch_buffers(dwc); 826 if (ret) 827 goto err1; 828 829 /* Adjust Frame Length */ 830 dwc3_frame_length_adjustment(dwc); 831 832 usb_phy_set_suspend(dwc->usb2_phy, 0); 833 usb_phy_set_suspend(dwc->usb3_phy, 0); 834 ret = phy_power_on(dwc->usb2_generic_phy); 835 if (ret < 0) 836 goto err2; 837 838 ret = phy_power_on(dwc->usb3_generic_phy); 839 if (ret < 0) 840 goto err3; 841 842 ret = dwc3_event_buffers_setup(dwc); 843 if (ret) { 844 dev_err(dwc->dev, "failed to setup event buffers\n"); 845 goto err4; 846 } 847 848 /* 849 * ENDXFER polling is available on version 3.10a and later of 850 * the DWC_usb3 controller. It is NOT available in the 851 * DWC_usb31 controller. 852 */ 853 if (!dwc3_is_usb31(dwc) && dwc->revision >= DWC3_REVISION_310A) { 854 reg = dwc3_readl(dwc->regs, DWC3_GUCTL2); 855 reg |= DWC3_GUCTL2_RST_ACTBITLATER; 856 dwc3_writel(dwc->regs, DWC3_GUCTL2, reg); 857 } 858 859 if (dwc->revision >= DWC3_REVISION_250A) { 860 reg = dwc3_readl(dwc->regs, DWC3_GUCTL1); 861 862 /* 863 * Enable hardware control of sending remote wakeup 864 * in HS when the device is in the L1 state. 865 */ 866 if (dwc->revision >= DWC3_REVISION_290A) 867 reg |= DWC3_GUCTL1_DEV_L1_EXIT_BY_HW; 868 869 if (dwc->dis_tx_ipgap_linecheck_quirk) 870 reg |= DWC3_GUCTL1_TX_IPGAP_LINECHECK_DIS; 871 872 dwc3_writel(dwc->regs, DWC3_GUCTL1, reg); 873 } 874 875 /* 876 * Must config both number of packets and max burst settings to enable 877 * RX and/or TX threshold. 878 */ 879 if (dwc3_is_usb31(dwc) && dwc->dr_mode == USB_DR_MODE_HOST) { 880 u8 rx_thr_num = dwc->rx_thr_num_pkt_prd; 881 u8 rx_maxburst = dwc->rx_max_burst_prd; 882 u8 tx_thr_num = dwc->tx_thr_num_pkt_prd; 883 u8 tx_maxburst = dwc->tx_max_burst_prd; 884 885 if (rx_thr_num && rx_maxburst) { 886 reg = dwc3_readl(dwc->regs, DWC3_GRXTHRCFG); 887 reg |= DWC31_RXTHRNUMPKTSEL_PRD; 888 889 reg &= ~DWC31_RXTHRNUMPKT_PRD(~0); 890 reg |= DWC31_RXTHRNUMPKT_PRD(rx_thr_num); 891 892 reg &= ~DWC31_MAXRXBURSTSIZE_PRD(~0); 893 reg |= DWC31_MAXRXBURSTSIZE_PRD(rx_maxburst); 894 895 dwc3_writel(dwc->regs, DWC3_GRXTHRCFG, reg); 896 } 897 898 if (tx_thr_num && tx_maxburst) { 899 reg = dwc3_readl(dwc->regs, DWC3_GTXTHRCFG); 900 reg |= DWC31_TXTHRNUMPKTSEL_PRD; 901 902 reg &= ~DWC31_TXTHRNUMPKT_PRD(~0); 903 reg |= DWC31_TXTHRNUMPKT_PRD(tx_thr_num); 904 905 reg &= ~DWC31_MAXTXBURSTSIZE_PRD(~0); 906 reg |= DWC31_MAXTXBURSTSIZE_PRD(tx_maxburst); 907 908 dwc3_writel(dwc->regs, DWC3_GTXTHRCFG, reg); 909 } 910 } 911 912 return 0; 913 914 err4: 915 phy_power_off(dwc->usb3_generic_phy); 916 917 err3: 918 phy_power_off(dwc->usb2_generic_phy); 919 920 err2: 921 usb_phy_set_suspend(dwc->usb2_phy, 1); 922 usb_phy_set_suspend(dwc->usb3_phy, 1); 923 924 err1: 925 usb_phy_shutdown(dwc->usb2_phy); 926 usb_phy_shutdown(dwc->usb3_phy); 927 phy_exit(dwc->usb2_generic_phy); 928 phy_exit(dwc->usb3_generic_phy); 929 930 err0a: 931 dwc3_ulpi_exit(dwc); 932 933 err0: 934 return ret; 935 } 936 937 static int dwc3_core_get_phy(struct dwc3 *dwc) 938 { 939 struct device *dev = dwc->dev; 940 struct device_node *node = dev->of_node; 941 int ret; 942 943 if (node) { 944 dwc->usb2_phy = devm_usb_get_phy_by_phandle(dev, "usb-phy", 0); 945 dwc->usb3_phy = devm_usb_get_phy_by_phandle(dev, "usb-phy", 1); 946 } else { 947 dwc->usb2_phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB2); 948 dwc->usb3_phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB3); 949 } 950 951 if (IS_ERR(dwc->usb2_phy)) { 952 ret = PTR_ERR(dwc->usb2_phy); 953 if (ret == -ENXIO || ret == -ENODEV) { 954 dwc->usb2_phy = NULL; 955 } else if (ret == -EPROBE_DEFER) { 956 return ret; 957 } else { 958 dev_err(dev, "no usb2 phy configured\n"); 959 return ret; 960 } 961 } 962 963 if (IS_ERR(dwc->usb3_phy)) { 964 ret = PTR_ERR(dwc->usb3_phy); 965 if (ret == -ENXIO || ret == -ENODEV) { 966 dwc->usb3_phy = NULL; 967 } else if (ret == -EPROBE_DEFER) { 968 return ret; 969 } else { 970 dev_err(dev, "no usb3 phy configured\n"); 971 return ret; 972 } 973 } 974 975 dwc->usb2_generic_phy = devm_phy_get(dev, "usb2-phy"); 976 if (IS_ERR(dwc->usb2_generic_phy)) { 977 ret = PTR_ERR(dwc->usb2_generic_phy); 978 if (ret == -ENOSYS || ret == -ENODEV) { 979 dwc->usb2_generic_phy = NULL; 980 } else if (ret == -EPROBE_DEFER) { 981 return ret; 982 } else { 983 dev_err(dev, "no usb2 phy configured\n"); 984 return ret; 985 } 986 } 987 988 dwc->usb3_generic_phy = devm_phy_get(dev, "usb3-phy"); 989 if (IS_ERR(dwc->usb3_generic_phy)) { 990 ret = PTR_ERR(dwc->usb3_generic_phy); 991 if (ret == -ENOSYS || ret == -ENODEV) { 992 dwc->usb3_generic_phy = NULL; 993 } else if (ret == -EPROBE_DEFER) { 994 return ret; 995 } else { 996 dev_err(dev, "no usb3 phy configured\n"); 997 return ret; 998 } 999 } 1000 1001 return 0; 1002 } 1003 1004 static int dwc3_core_init_mode(struct dwc3 *dwc) 1005 { 1006 struct device *dev = dwc->dev; 1007 int ret; 1008 1009 switch (dwc->dr_mode) { 1010 case USB_DR_MODE_PERIPHERAL: 1011 dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_DEVICE); 1012 1013 if (dwc->usb2_phy) 1014 otg_set_vbus(dwc->usb2_phy->otg, false); 1015 phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_DEVICE); 1016 phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_DEVICE); 1017 1018 ret = dwc3_gadget_init(dwc); 1019 if (ret) { 1020 if (ret != -EPROBE_DEFER) 1021 dev_err(dev, "failed to initialize gadget\n"); 1022 return ret; 1023 } 1024 break; 1025 case USB_DR_MODE_HOST: 1026 dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_HOST); 1027 1028 if (dwc->usb2_phy) 1029 otg_set_vbus(dwc->usb2_phy->otg, true); 1030 phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_HOST); 1031 phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_HOST); 1032 1033 ret = dwc3_host_init(dwc); 1034 if (ret) { 1035 if (ret != -EPROBE_DEFER) 1036 dev_err(dev, "failed to initialize host\n"); 1037 return ret; 1038 } 1039 phy_calibrate(dwc->usb2_generic_phy); 1040 break; 1041 case USB_DR_MODE_OTG: 1042 INIT_WORK(&dwc->drd_work, __dwc3_set_mode); 1043 ret = dwc3_drd_init(dwc); 1044 if (ret) { 1045 if (ret != -EPROBE_DEFER) 1046 dev_err(dev, "failed to initialize dual-role\n"); 1047 return ret; 1048 } 1049 break; 1050 default: 1051 dev_err(dev, "Unsupported mode of operation %d\n", dwc->dr_mode); 1052 return -EINVAL; 1053 } 1054 1055 return 0; 1056 } 1057 1058 static void dwc3_core_exit_mode(struct dwc3 *dwc) 1059 { 1060 switch (dwc->dr_mode) { 1061 case USB_DR_MODE_PERIPHERAL: 1062 dwc3_gadget_exit(dwc); 1063 break; 1064 case USB_DR_MODE_HOST: 1065 dwc3_host_exit(dwc); 1066 break; 1067 case USB_DR_MODE_OTG: 1068 dwc3_drd_exit(dwc); 1069 break; 1070 default: 1071 /* do nothing */ 1072 break; 1073 } 1074 } 1075 1076 static void dwc3_get_properties(struct dwc3 *dwc) 1077 { 1078 struct device *dev = dwc->dev; 1079 u8 lpm_nyet_threshold; 1080 u8 tx_de_emphasis; 1081 u8 hird_threshold; 1082 u8 rx_thr_num_pkt_prd; 1083 u8 rx_max_burst_prd; 1084 u8 tx_thr_num_pkt_prd; 1085 u8 tx_max_burst_prd; 1086 1087 /* default to highest possible threshold */ 1088 lpm_nyet_threshold = 0xff; 1089 1090 /* default to -3.5dB de-emphasis */ 1091 tx_de_emphasis = 1; 1092 1093 /* 1094 * default to assert utmi_sleep_n and use maximum allowed HIRD 1095 * threshold value of 0b1100 1096 */ 1097 hird_threshold = 12; 1098 1099 dwc->maximum_speed = usb_get_maximum_speed(dev); 1100 dwc->dr_mode = usb_get_dr_mode(dev); 1101 dwc->hsphy_mode = of_usb_get_phy_mode(dev->of_node); 1102 1103 dwc->sysdev_is_parent = device_property_read_bool(dev, 1104 "linux,sysdev_is_parent"); 1105 if (dwc->sysdev_is_parent) 1106 dwc->sysdev = dwc->dev->parent; 1107 else 1108 dwc->sysdev = dwc->dev; 1109 1110 dwc->has_lpm_erratum = device_property_read_bool(dev, 1111 "snps,has-lpm-erratum"); 1112 device_property_read_u8(dev, "snps,lpm-nyet-threshold", 1113 &lpm_nyet_threshold); 1114 dwc->is_utmi_l1_suspend = device_property_read_bool(dev, 1115 "snps,is-utmi-l1-suspend"); 1116 device_property_read_u8(dev, "snps,hird-threshold", 1117 &hird_threshold); 1118 dwc->usb3_lpm_capable = device_property_read_bool(dev, 1119 "snps,usb3_lpm_capable"); 1120 device_property_read_u8(dev, "snps,rx-thr-num-pkt-prd", 1121 &rx_thr_num_pkt_prd); 1122 device_property_read_u8(dev, "snps,rx-max-burst-prd", 1123 &rx_max_burst_prd); 1124 device_property_read_u8(dev, "snps,tx-thr-num-pkt-prd", 1125 &tx_thr_num_pkt_prd); 1126 device_property_read_u8(dev, "snps,tx-max-burst-prd", 1127 &tx_max_burst_prd); 1128 1129 dwc->disable_scramble_quirk = device_property_read_bool(dev, 1130 "snps,disable_scramble_quirk"); 1131 dwc->u2exit_lfps_quirk = device_property_read_bool(dev, 1132 "snps,u2exit_lfps_quirk"); 1133 dwc->u2ss_inp3_quirk = device_property_read_bool(dev, 1134 "snps,u2ss_inp3_quirk"); 1135 dwc->req_p1p2p3_quirk = device_property_read_bool(dev, 1136 "snps,req_p1p2p3_quirk"); 1137 dwc->del_p1p2p3_quirk = device_property_read_bool(dev, 1138 "snps,del_p1p2p3_quirk"); 1139 dwc->del_phy_power_chg_quirk = device_property_read_bool(dev, 1140 "snps,del_phy_power_chg_quirk"); 1141 dwc->lfps_filter_quirk = device_property_read_bool(dev, 1142 "snps,lfps_filter_quirk"); 1143 dwc->rx_detect_poll_quirk = device_property_read_bool(dev, 1144 "snps,rx_detect_poll_quirk"); 1145 dwc->dis_u3_susphy_quirk = device_property_read_bool(dev, 1146 "snps,dis_u3_susphy_quirk"); 1147 dwc->dis_u2_susphy_quirk = device_property_read_bool(dev, 1148 "snps,dis_u2_susphy_quirk"); 1149 dwc->dis_enblslpm_quirk = device_property_read_bool(dev, 1150 "snps,dis_enblslpm_quirk"); 1151 dwc->dis_rxdet_inp3_quirk = device_property_read_bool(dev, 1152 "snps,dis_rxdet_inp3_quirk"); 1153 dwc->dis_u2_freeclk_exists_quirk = device_property_read_bool(dev, 1154 "snps,dis-u2-freeclk-exists-quirk"); 1155 dwc->dis_del_phy_power_chg_quirk = device_property_read_bool(dev, 1156 "snps,dis-del-phy-power-chg-quirk"); 1157 dwc->dis_tx_ipgap_linecheck_quirk = device_property_read_bool(dev, 1158 "snps,dis-tx-ipgap-linecheck-quirk"); 1159 1160 dwc->tx_de_emphasis_quirk = device_property_read_bool(dev, 1161 "snps,tx_de_emphasis_quirk"); 1162 device_property_read_u8(dev, "snps,tx_de_emphasis", 1163 &tx_de_emphasis); 1164 device_property_read_string(dev, "snps,hsphy_interface", 1165 &dwc->hsphy_interface); 1166 device_property_read_u32(dev, "snps,quirk-frame-length-adjustment", 1167 &dwc->fladj); 1168 1169 dwc->dis_metastability_quirk = device_property_read_bool(dev, 1170 "snps,dis_metastability_quirk"); 1171 1172 dwc->lpm_nyet_threshold = lpm_nyet_threshold; 1173 dwc->tx_de_emphasis = tx_de_emphasis; 1174 1175 dwc->hird_threshold = hird_threshold 1176 | (dwc->is_utmi_l1_suspend << 4); 1177 1178 dwc->rx_thr_num_pkt_prd = rx_thr_num_pkt_prd; 1179 dwc->rx_max_burst_prd = rx_max_burst_prd; 1180 1181 dwc->tx_thr_num_pkt_prd = tx_thr_num_pkt_prd; 1182 dwc->tx_max_burst_prd = tx_max_burst_prd; 1183 1184 dwc->imod_interval = 0; 1185 } 1186 1187 /* check whether the core supports IMOD */ 1188 bool dwc3_has_imod(struct dwc3 *dwc) 1189 { 1190 return ((dwc3_is_usb3(dwc) && 1191 dwc->revision >= DWC3_REVISION_300A) || 1192 (dwc3_is_usb31(dwc) && 1193 dwc->revision >= DWC3_USB31_REVISION_120A)); 1194 } 1195 1196 static void dwc3_check_params(struct dwc3 *dwc) 1197 { 1198 struct device *dev = dwc->dev; 1199 1200 /* Check for proper value of imod_interval */ 1201 if (dwc->imod_interval && !dwc3_has_imod(dwc)) { 1202 dev_warn(dwc->dev, "Interrupt moderation not supported\n"); 1203 dwc->imod_interval = 0; 1204 } 1205 1206 /* 1207 * Workaround for STAR 9000961433 which affects only version 1208 * 3.00a of the DWC_usb3 core. This prevents the controller 1209 * interrupt from being masked while handling events. IMOD 1210 * allows us to work around this issue. Enable it for the 1211 * affected version. 1212 */ 1213 if (!dwc->imod_interval && 1214 (dwc->revision == DWC3_REVISION_300A)) 1215 dwc->imod_interval = 1; 1216 1217 /* Check the maximum_speed parameter */ 1218 switch (dwc->maximum_speed) { 1219 case USB_SPEED_LOW: 1220 case USB_SPEED_FULL: 1221 case USB_SPEED_HIGH: 1222 case USB_SPEED_SUPER: 1223 case USB_SPEED_SUPER_PLUS: 1224 break; 1225 default: 1226 dev_err(dev, "invalid maximum_speed parameter %d\n", 1227 dwc->maximum_speed); 1228 /* fall through */ 1229 case USB_SPEED_UNKNOWN: 1230 /* default to superspeed */ 1231 dwc->maximum_speed = USB_SPEED_SUPER; 1232 1233 /* 1234 * default to superspeed plus if we are capable. 1235 */ 1236 if (dwc3_is_usb31(dwc) && 1237 (DWC3_GHWPARAMS3_SSPHY_IFC(dwc->hwparams.hwparams3) == 1238 DWC3_GHWPARAMS3_SSPHY_IFC_GEN2)) 1239 dwc->maximum_speed = USB_SPEED_SUPER_PLUS; 1240 1241 break; 1242 } 1243 } 1244 1245 static int dwc3_probe(struct platform_device *pdev) 1246 { 1247 struct device *dev = &pdev->dev; 1248 struct resource *res; 1249 struct dwc3 *dwc; 1250 1251 int ret; 1252 1253 void __iomem *regs; 1254 1255 dwc = devm_kzalloc(dev, sizeof(*dwc), GFP_KERNEL); 1256 if (!dwc) 1257 return -ENOMEM; 1258 1259 dwc->dev = dev; 1260 1261 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1262 if (!res) { 1263 dev_err(dev, "missing memory resource\n"); 1264 return -ENODEV; 1265 } 1266 1267 dwc->xhci_resources[0].start = res->start; 1268 dwc->xhci_resources[0].end = dwc->xhci_resources[0].start + 1269 DWC3_XHCI_REGS_END; 1270 dwc->xhci_resources[0].flags = res->flags; 1271 dwc->xhci_resources[0].name = res->name; 1272 1273 res->start += DWC3_GLOBALS_REGS_START; 1274 1275 /* 1276 * Request memory region but exclude xHCI regs, 1277 * since it will be requested by the xhci-plat driver. 1278 */ 1279 regs = devm_ioremap_resource(dev, res); 1280 if (IS_ERR(regs)) { 1281 ret = PTR_ERR(regs); 1282 goto err0; 1283 } 1284 1285 dwc->regs = regs; 1286 dwc->regs_size = resource_size(res); 1287 1288 dwc3_get_properties(dwc); 1289 1290 platform_set_drvdata(pdev, dwc); 1291 dwc3_cache_hwparams(dwc); 1292 1293 spin_lock_init(&dwc->lock); 1294 1295 pm_runtime_set_active(dev); 1296 pm_runtime_use_autosuspend(dev); 1297 pm_runtime_set_autosuspend_delay(dev, DWC3_DEFAULT_AUTOSUSPEND_DELAY); 1298 pm_runtime_enable(dev); 1299 ret = pm_runtime_get_sync(dev); 1300 if (ret < 0) 1301 goto err1; 1302 1303 pm_runtime_forbid(dev); 1304 1305 ret = dwc3_alloc_event_buffers(dwc, DWC3_EVENT_BUFFERS_SIZE); 1306 if (ret) { 1307 dev_err(dwc->dev, "failed to allocate event buffers\n"); 1308 ret = -ENOMEM; 1309 goto err2; 1310 } 1311 1312 ret = dwc3_get_dr_mode(dwc); 1313 if (ret) 1314 goto err3; 1315 1316 ret = dwc3_alloc_scratch_buffers(dwc); 1317 if (ret) 1318 goto err3; 1319 1320 ret = dwc3_core_init(dwc); 1321 if (ret) { 1322 dev_err(dev, "failed to initialize core\n"); 1323 goto err4; 1324 } 1325 1326 dwc3_check_params(dwc); 1327 1328 ret = dwc3_core_init_mode(dwc); 1329 if (ret) 1330 goto err5; 1331 1332 dwc3_debugfs_init(dwc); 1333 pm_runtime_put(dev); 1334 1335 return 0; 1336 1337 err5: 1338 dwc3_event_buffers_cleanup(dwc); 1339 1340 err4: 1341 dwc3_free_scratch_buffers(dwc); 1342 1343 err3: 1344 dwc3_free_event_buffers(dwc); 1345 1346 err2: 1347 pm_runtime_allow(&pdev->dev); 1348 1349 err1: 1350 pm_runtime_put_sync(&pdev->dev); 1351 pm_runtime_disable(&pdev->dev); 1352 1353 err0: 1354 /* 1355 * restore res->start back to its original value so that, in case the 1356 * probe is deferred, we don't end up getting error in request the 1357 * memory region the next time probe is called. 1358 */ 1359 res->start -= DWC3_GLOBALS_REGS_START; 1360 1361 return ret; 1362 } 1363 1364 static int dwc3_remove(struct platform_device *pdev) 1365 { 1366 struct dwc3 *dwc = platform_get_drvdata(pdev); 1367 struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1368 1369 pm_runtime_get_sync(&pdev->dev); 1370 /* 1371 * restore res->start back to its original value so that, in case the 1372 * probe is deferred, we don't end up getting error in request the 1373 * memory region the next time probe is called. 1374 */ 1375 res->start -= DWC3_GLOBALS_REGS_START; 1376 1377 dwc3_debugfs_exit(dwc); 1378 dwc3_core_exit_mode(dwc); 1379 1380 dwc3_core_exit(dwc); 1381 dwc3_ulpi_exit(dwc); 1382 1383 pm_runtime_put_sync(&pdev->dev); 1384 pm_runtime_allow(&pdev->dev); 1385 pm_runtime_disable(&pdev->dev); 1386 1387 dwc3_free_event_buffers(dwc); 1388 dwc3_free_scratch_buffers(dwc); 1389 1390 return 0; 1391 } 1392 1393 #ifdef CONFIG_PM 1394 static int dwc3_suspend_common(struct dwc3 *dwc, pm_message_t msg) 1395 { 1396 unsigned long flags; 1397 1398 switch (dwc->current_dr_role) { 1399 case DWC3_GCTL_PRTCAP_DEVICE: 1400 spin_lock_irqsave(&dwc->lock, flags); 1401 dwc3_gadget_suspend(dwc); 1402 spin_unlock_irqrestore(&dwc->lock, flags); 1403 dwc3_core_exit(dwc); 1404 break; 1405 case DWC3_GCTL_PRTCAP_HOST: 1406 /* do nothing during host runtime_suspend */ 1407 if (!PMSG_IS_AUTO(msg)) 1408 dwc3_core_exit(dwc); 1409 break; 1410 case DWC3_GCTL_PRTCAP_OTG: 1411 /* do nothing during runtime_suspend */ 1412 if (PMSG_IS_AUTO(msg)) 1413 break; 1414 1415 if (dwc->current_otg_role == DWC3_OTG_ROLE_DEVICE) { 1416 spin_lock_irqsave(&dwc->lock, flags); 1417 dwc3_gadget_suspend(dwc); 1418 spin_unlock_irqrestore(&dwc->lock, flags); 1419 } 1420 1421 dwc3_otg_exit(dwc); 1422 dwc3_core_exit(dwc); 1423 break; 1424 default: 1425 /* do nothing */ 1426 break; 1427 } 1428 1429 return 0; 1430 } 1431 1432 static int dwc3_resume_common(struct dwc3 *dwc, pm_message_t msg) 1433 { 1434 unsigned long flags; 1435 int ret; 1436 1437 switch (dwc->current_dr_role) { 1438 case DWC3_GCTL_PRTCAP_DEVICE: 1439 ret = dwc3_core_init(dwc); 1440 if (ret) 1441 return ret; 1442 1443 dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_DEVICE); 1444 spin_lock_irqsave(&dwc->lock, flags); 1445 dwc3_gadget_resume(dwc); 1446 spin_unlock_irqrestore(&dwc->lock, flags); 1447 break; 1448 case DWC3_GCTL_PRTCAP_HOST: 1449 /* nothing to do on host runtime_resume */ 1450 if (!PMSG_IS_AUTO(msg)) { 1451 ret = dwc3_core_init(dwc); 1452 if (ret) 1453 return ret; 1454 dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_HOST); 1455 } 1456 break; 1457 case DWC3_GCTL_PRTCAP_OTG: 1458 /* nothing to do on runtime_resume */ 1459 if (PMSG_IS_AUTO(msg)) 1460 break; 1461 1462 ret = dwc3_core_init(dwc); 1463 if (ret) 1464 return ret; 1465 1466 dwc3_set_prtcap(dwc, dwc->current_dr_role); 1467 1468 dwc3_otg_init(dwc); 1469 if (dwc->current_otg_role == DWC3_OTG_ROLE_HOST) { 1470 dwc3_otg_host_init(dwc); 1471 } else if (dwc->current_otg_role == DWC3_OTG_ROLE_DEVICE) { 1472 spin_lock_irqsave(&dwc->lock, flags); 1473 dwc3_gadget_resume(dwc); 1474 spin_unlock_irqrestore(&dwc->lock, flags); 1475 } 1476 1477 break; 1478 default: 1479 /* do nothing */ 1480 break; 1481 } 1482 1483 return 0; 1484 } 1485 1486 static int dwc3_runtime_checks(struct dwc3 *dwc) 1487 { 1488 switch (dwc->current_dr_role) { 1489 case DWC3_GCTL_PRTCAP_DEVICE: 1490 if (dwc->connected) 1491 return -EBUSY; 1492 break; 1493 case DWC3_GCTL_PRTCAP_HOST: 1494 default: 1495 /* do nothing */ 1496 break; 1497 } 1498 1499 return 0; 1500 } 1501 1502 static int dwc3_runtime_suspend(struct device *dev) 1503 { 1504 struct dwc3 *dwc = dev_get_drvdata(dev); 1505 int ret; 1506 1507 if (dwc3_runtime_checks(dwc)) 1508 return -EBUSY; 1509 1510 ret = dwc3_suspend_common(dwc, PMSG_AUTO_SUSPEND); 1511 if (ret) 1512 return ret; 1513 1514 device_init_wakeup(dev, true); 1515 1516 return 0; 1517 } 1518 1519 static int dwc3_runtime_resume(struct device *dev) 1520 { 1521 struct dwc3 *dwc = dev_get_drvdata(dev); 1522 int ret; 1523 1524 device_init_wakeup(dev, false); 1525 1526 ret = dwc3_resume_common(dwc, PMSG_AUTO_RESUME); 1527 if (ret) 1528 return ret; 1529 1530 switch (dwc->current_dr_role) { 1531 case DWC3_GCTL_PRTCAP_DEVICE: 1532 dwc3_gadget_process_pending_events(dwc); 1533 break; 1534 case DWC3_GCTL_PRTCAP_HOST: 1535 default: 1536 /* do nothing */ 1537 break; 1538 } 1539 1540 pm_runtime_mark_last_busy(dev); 1541 1542 return 0; 1543 } 1544 1545 static int dwc3_runtime_idle(struct device *dev) 1546 { 1547 struct dwc3 *dwc = dev_get_drvdata(dev); 1548 1549 switch (dwc->current_dr_role) { 1550 case DWC3_GCTL_PRTCAP_DEVICE: 1551 if (dwc3_runtime_checks(dwc)) 1552 return -EBUSY; 1553 break; 1554 case DWC3_GCTL_PRTCAP_HOST: 1555 default: 1556 /* do nothing */ 1557 break; 1558 } 1559 1560 pm_runtime_mark_last_busy(dev); 1561 pm_runtime_autosuspend(dev); 1562 1563 return 0; 1564 } 1565 #endif /* CONFIG_PM */ 1566 1567 #ifdef CONFIG_PM_SLEEP 1568 static int dwc3_suspend(struct device *dev) 1569 { 1570 struct dwc3 *dwc = dev_get_drvdata(dev); 1571 int ret; 1572 1573 ret = dwc3_suspend_common(dwc, PMSG_SUSPEND); 1574 if (ret) 1575 return ret; 1576 1577 pinctrl_pm_select_sleep_state(dev); 1578 1579 return 0; 1580 } 1581 1582 static int dwc3_resume(struct device *dev) 1583 { 1584 struct dwc3 *dwc = dev_get_drvdata(dev); 1585 int ret; 1586 1587 pinctrl_pm_select_default_state(dev); 1588 1589 ret = dwc3_resume_common(dwc, PMSG_RESUME); 1590 if (ret) 1591 return ret; 1592 1593 pm_runtime_disable(dev); 1594 pm_runtime_set_active(dev); 1595 pm_runtime_enable(dev); 1596 1597 return 0; 1598 } 1599 #endif /* CONFIG_PM_SLEEP */ 1600 1601 static const struct dev_pm_ops dwc3_dev_pm_ops = { 1602 SET_SYSTEM_SLEEP_PM_OPS(dwc3_suspend, dwc3_resume) 1603 SET_RUNTIME_PM_OPS(dwc3_runtime_suspend, dwc3_runtime_resume, 1604 dwc3_runtime_idle) 1605 }; 1606 1607 #ifdef CONFIG_OF 1608 static const struct of_device_id of_dwc3_match[] = { 1609 { 1610 .compatible = "snps,dwc3" 1611 }, 1612 { 1613 .compatible = "synopsys,dwc3" 1614 }, 1615 { }, 1616 }; 1617 MODULE_DEVICE_TABLE(of, of_dwc3_match); 1618 #endif 1619 1620 #ifdef CONFIG_ACPI 1621 1622 #define ACPI_ID_INTEL_BSW "808622B7" 1623 1624 static const struct acpi_device_id dwc3_acpi_match[] = { 1625 { ACPI_ID_INTEL_BSW, 0 }, 1626 { }, 1627 }; 1628 MODULE_DEVICE_TABLE(acpi, dwc3_acpi_match); 1629 #endif 1630 1631 static struct platform_driver dwc3_driver = { 1632 .probe = dwc3_probe, 1633 .remove = dwc3_remove, 1634 .driver = { 1635 .name = "dwc3", 1636 .of_match_table = of_match_ptr(of_dwc3_match), 1637 .acpi_match_table = ACPI_PTR(dwc3_acpi_match), 1638 .pm = &dwc3_dev_pm_ops, 1639 }, 1640 }; 1641 1642 module_platform_driver(dwc3_driver); 1643 1644 MODULE_ALIAS("platform:dwc3"); 1645 MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>"); 1646 MODULE_LICENSE("GPL v2"); 1647 MODULE_DESCRIPTION("DesignWare USB3 DRD Controller Driver"); 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