1 /** 2 * core.c - DesignWare USB3 DRD Controller Core file 3 * 4 * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com 5 * 6 * Authors: Felipe Balbi <balbi@ti.com>, 7 * Sebastian Andrzej Siewior <bigeasy@linutronix.de> 8 * 9 * This program is free software: you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License version 2 of 11 * the License as published by the Free Software Foundation. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program. If not, see <http://www.gnu.org/licenses/>. 20 */ 21 22 #include <linux/version.h> 23 #include <linux/module.h> 24 #include <linux/kernel.h> 25 #include <linux/slab.h> 26 #include <linux/spinlock.h> 27 #include <linux/platform_device.h> 28 #include <linux/pm_runtime.h> 29 #include <linux/interrupt.h> 30 #include <linux/ioport.h> 31 #include <linux/io.h> 32 #include <linux/list.h> 33 #include <linux/delay.h> 34 #include <linux/dma-mapping.h> 35 #include <linux/of.h> 36 #include <linux/acpi.h> 37 #include <linux/pinctrl/consumer.h> 38 39 #include <linux/usb/ch9.h> 40 #include <linux/usb/gadget.h> 41 #include <linux/usb/of.h> 42 #include <linux/usb/otg.h> 43 44 #include "core.h" 45 #include "gadget.h" 46 #include "io.h" 47 48 #include "debug.h" 49 50 #define DWC3_DEFAULT_AUTOSUSPEND_DELAY 5000 /* ms */ 51 52 void dwc3_set_mode(struct dwc3 *dwc, u32 mode) 53 { 54 u32 reg; 55 56 reg = dwc3_readl(dwc->regs, DWC3_GCTL); 57 reg &= ~(DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_OTG)); 58 reg |= DWC3_GCTL_PRTCAPDIR(mode); 59 dwc3_writel(dwc->regs, DWC3_GCTL, reg); 60 } 61 62 u32 dwc3_core_fifo_space(struct dwc3_ep *dep, u8 type) 63 { 64 struct dwc3 *dwc = dep->dwc; 65 u32 reg; 66 67 dwc3_writel(dwc->regs, DWC3_GDBGFIFOSPACE, 68 DWC3_GDBGFIFOSPACE_NUM(dep->number) | 69 DWC3_GDBGFIFOSPACE_TYPE(type)); 70 71 reg = dwc3_readl(dwc->regs, DWC3_GDBGFIFOSPACE); 72 73 return DWC3_GDBGFIFOSPACE_SPACE_AVAILABLE(reg); 74 } 75 76 /** 77 * dwc3_core_soft_reset - Issues core soft reset and PHY reset 78 * @dwc: pointer to our context structure 79 */ 80 static int dwc3_core_soft_reset(struct dwc3 *dwc) 81 { 82 u32 reg; 83 int retries = 1000; 84 int ret; 85 86 usb_phy_init(dwc->usb2_phy); 87 usb_phy_init(dwc->usb3_phy); 88 ret = phy_init(dwc->usb2_generic_phy); 89 if (ret < 0) 90 return ret; 91 92 ret = phy_init(dwc->usb3_generic_phy); 93 if (ret < 0) { 94 phy_exit(dwc->usb2_generic_phy); 95 return ret; 96 } 97 98 /* 99 * We're resetting only the device side because, if we're in host mode, 100 * XHCI driver will reset the host block. If dwc3 was configured for 101 * host-only mode, then we can return early. 102 */ 103 if (dwc->dr_mode == USB_DR_MODE_HOST) 104 return 0; 105 106 reg = dwc3_readl(dwc->regs, DWC3_DCTL); 107 reg |= DWC3_DCTL_CSFTRST; 108 dwc3_writel(dwc->regs, DWC3_DCTL, reg); 109 110 do { 111 reg = dwc3_readl(dwc->regs, DWC3_DCTL); 112 if (!(reg & DWC3_DCTL_CSFTRST)) 113 return 0; 114 115 udelay(1); 116 } while (--retries); 117 118 return -ETIMEDOUT; 119 } 120 121 /** 122 * dwc3_soft_reset - Issue soft reset 123 * @dwc: Pointer to our controller context structure 124 */ 125 static int dwc3_soft_reset(struct dwc3 *dwc) 126 { 127 unsigned long timeout; 128 u32 reg; 129 130 timeout = jiffies + msecs_to_jiffies(500); 131 dwc3_writel(dwc->regs, DWC3_DCTL, DWC3_DCTL_CSFTRST); 132 do { 133 reg = dwc3_readl(dwc->regs, DWC3_DCTL); 134 if (!(reg & DWC3_DCTL_CSFTRST)) 135 break; 136 137 if (time_after(jiffies, timeout)) { 138 dev_err(dwc->dev, "Reset Timed Out\n"); 139 return -ETIMEDOUT; 140 } 141 142 cpu_relax(); 143 } while (true); 144 145 return 0; 146 } 147 148 /* 149 * dwc3_frame_length_adjustment - Adjusts frame length if required 150 * @dwc3: Pointer to our controller context structure 151 */ 152 static void dwc3_frame_length_adjustment(struct dwc3 *dwc) 153 { 154 u32 reg; 155 u32 dft; 156 157 if (dwc->revision < DWC3_REVISION_250A) 158 return; 159 160 if (dwc->fladj == 0) 161 return; 162 163 reg = dwc3_readl(dwc->regs, DWC3_GFLADJ); 164 dft = reg & DWC3_GFLADJ_30MHZ_MASK; 165 if (!dev_WARN_ONCE(dwc->dev, dft == dwc->fladj, 166 "request value same as default, ignoring\n")) { 167 reg &= ~DWC3_GFLADJ_30MHZ_MASK; 168 reg |= DWC3_GFLADJ_30MHZ_SDBND_SEL | dwc->fladj; 169 dwc3_writel(dwc->regs, DWC3_GFLADJ, reg); 170 } 171 } 172 173 /** 174 * dwc3_free_one_event_buffer - Frees one event buffer 175 * @dwc: Pointer to our controller context structure 176 * @evt: Pointer to event buffer to be freed 177 */ 178 static void dwc3_free_one_event_buffer(struct dwc3 *dwc, 179 struct dwc3_event_buffer *evt) 180 { 181 dma_free_coherent(dwc->dev, evt->length, evt->buf, evt->dma); 182 } 183 184 /** 185 * dwc3_alloc_one_event_buffer - Allocates one event buffer structure 186 * @dwc: Pointer to our controller context structure 187 * @length: size of the event buffer 188 * 189 * Returns a pointer to the allocated event buffer structure on success 190 * otherwise ERR_PTR(errno). 191 */ 192 static struct dwc3_event_buffer *dwc3_alloc_one_event_buffer(struct dwc3 *dwc, 193 unsigned length) 194 { 195 struct dwc3_event_buffer *evt; 196 197 evt = devm_kzalloc(dwc->dev, sizeof(*evt), GFP_KERNEL); 198 if (!evt) 199 return ERR_PTR(-ENOMEM); 200 201 evt->dwc = dwc; 202 evt->length = length; 203 evt->buf = dma_alloc_coherent(dwc->dev, length, 204 &evt->dma, GFP_KERNEL); 205 if (!evt->buf) 206 return ERR_PTR(-ENOMEM); 207 208 return evt; 209 } 210 211 /** 212 * dwc3_free_event_buffers - frees all allocated event buffers 213 * @dwc: Pointer to our controller context structure 214 */ 215 static void dwc3_free_event_buffers(struct dwc3 *dwc) 216 { 217 struct dwc3_event_buffer *evt; 218 219 evt = dwc->ev_buf; 220 if (evt) 221 dwc3_free_one_event_buffer(dwc, evt); 222 } 223 224 /** 225 * dwc3_alloc_event_buffers - Allocates @num event buffers of size @length 226 * @dwc: pointer to our controller context structure 227 * @length: size of event buffer 228 * 229 * Returns 0 on success otherwise negative errno. In the error case, dwc 230 * may contain some buffers allocated but not all which were requested. 231 */ 232 static int dwc3_alloc_event_buffers(struct dwc3 *dwc, unsigned length) 233 { 234 struct dwc3_event_buffer *evt; 235 236 evt = dwc3_alloc_one_event_buffer(dwc, length); 237 if (IS_ERR(evt)) { 238 dev_err(dwc->dev, "can't allocate event buffer\n"); 239 return PTR_ERR(evt); 240 } 241 dwc->ev_buf = evt; 242 243 return 0; 244 } 245 246 /** 247 * dwc3_event_buffers_setup - setup our allocated event buffers 248 * @dwc: pointer to our controller context structure 249 * 250 * Returns 0 on success otherwise negative errno. 251 */ 252 static int dwc3_event_buffers_setup(struct dwc3 *dwc) 253 { 254 struct dwc3_event_buffer *evt; 255 256 evt = dwc->ev_buf; 257 dwc3_trace(trace_dwc3_core, 258 "Event buf %p dma %08llx length %d\n", 259 evt->buf, (unsigned long long) evt->dma, 260 evt->length); 261 262 evt->lpos = 0; 263 264 dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(0), 265 lower_32_bits(evt->dma)); 266 dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(0), 267 upper_32_bits(evt->dma)); 268 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0), 269 DWC3_GEVNTSIZ_SIZE(evt->length)); 270 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), 0); 271 272 return 0; 273 } 274 275 static void dwc3_event_buffers_cleanup(struct dwc3 *dwc) 276 { 277 struct dwc3_event_buffer *evt; 278 279 evt = dwc->ev_buf; 280 281 evt->lpos = 0; 282 283 dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(0), 0); 284 dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(0), 0); 285 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0), DWC3_GEVNTSIZ_INTMASK 286 | DWC3_GEVNTSIZ_SIZE(0)); 287 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), 0); 288 } 289 290 static int dwc3_alloc_scratch_buffers(struct dwc3 *dwc) 291 { 292 if (!dwc->has_hibernation) 293 return 0; 294 295 if (!dwc->nr_scratch) 296 return 0; 297 298 dwc->scratchbuf = kmalloc_array(dwc->nr_scratch, 299 DWC3_SCRATCHBUF_SIZE, GFP_KERNEL); 300 if (!dwc->scratchbuf) 301 return -ENOMEM; 302 303 return 0; 304 } 305 306 static int dwc3_setup_scratch_buffers(struct dwc3 *dwc) 307 { 308 dma_addr_t scratch_addr; 309 u32 param; 310 int ret; 311 312 if (!dwc->has_hibernation) 313 return 0; 314 315 if (!dwc->nr_scratch) 316 return 0; 317 318 /* should never fall here */ 319 if (!WARN_ON(dwc->scratchbuf)) 320 return 0; 321 322 scratch_addr = dma_map_single(dwc->dev, dwc->scratchbuf, 323 dwc->nr_scratch * DWC3_SCRATCHBUF_SIZE, 324 DMA_BIDIRECTIONAL); 325 if (dma_mapping_error(dwc->dev, scratch_addr)) { 326 dev_err(dwc->dev, "failed to map scratch buffer\n"); 327 ret = -EFAULT; 328 goto err0; 329 } 330 331 dwc->scratch_addr = scratch_addr; 332 333 param = lower_32_bits(scratch_addr); 334 335 ret = dwc3_send_gadget_generic_command(dwc, 336 DWC3_DGCMD_SET_SCRATCHPAD_ADDR_LO, param); 337 if (ret < 0) 338 goto err1; 339 340 param = upper_32_bits(scratch_addr); 341 342 ret = dwc3_send_gadget_generic_command(dwc, 343 DWC3_DGCMD_SET_SCRATCHPAD_ADDR_HI, param); 344 if (ret < 0) 345 goto err1; 346 347 return 0; 348 349 err1: 350 dma_unmap_single(dwc->dev, dwc->scratch_addr, dwc->nr_scratch * 351 DWC3_SCRATCHBUF_SIZE, DMA_BIDIRECTIONAL); 352 353 err0: 354 return ret; 355 } 356 357 static void dwc3_free_scratch_buffers(struct dwc3 *dwc) 358 { 359 if (!dwc->has_hibernation) 360 return; 361 362 if (!dwc->nr_scratch) 363 return; 364 365 /* should never fall here */ 366 if (!WARN_ON(dwc->scratchbuf)) 367 return; 368 369 dma_unmap_single(dwc->dev, dwc->scratch_addr, dwc->nr_scratch * 370 DWC3_SCRATCHBUF_SIZE, DMA_BIDIRECTIONAL); 371 kfree(dwc->scratchbuf); 372 } 373 374 static void dwc3_core_num_eps(struct dwc3 *dwc) 375 { 376 struct dwc3_hwparams *parms = &dwc->hwparams; 377 378 dwc->num_in_eps = DWC3_NUM_IN_EPS(parms); 379 dwc->num_out_eps = DWC3_NUM_EPS(parms) - dwc->num_in_eps; 380 381 dwc3_trace(trace_dwc3_core, "found %d IN and %d OUT endpoints", 382 dwc->num_in_eps, dwc->num_out_eps); 383 } 384 385 static void dwc3_cache_hwparams(struct dwc3 *dwc) 386 { 387 struct dwc3_hwparams *parms = &dwc->hwparams; 388 389 parms->hwparams0 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS0); 390 parms->hwparams1 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS1); 391 parms->hwparams2 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS2); 392 parms->hwparams3 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS3); 393 parms->hwparams4 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS4); 394 parms->hwparams5 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS5); 395 parms->hwparams6 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS6); 396 parms->hwparams7 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS7); 397 parms->hwparams8 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS8); 398 } 399 400 /** 401 * dwc3_phy_setup - Configure USB PHY Interface of DWC3 Core 402 * @dwc: Pointer to our controller context structure 403 * 404 * Returns 0 on success. The USB PHY interfaces are configured but not 405 * initialized. The PHY interfaces and the PHYs get initialized together with 406 * the core in dwc3_core_init. 407 */ 408 static int dwc3_phy_setup(struct dwc3 *dwc) 409 { 410 u32 reg; 411 int ret; 412 413 reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0)); 414 415 /* 416 * Above 1.94a, it is recommended to set DWC3_GUSB3PIPECTL_SUSPHY 417 * to '0' during coreConsultant configuration. So default value 418 * will be '0' when the core is reset. Application needs to set it 419 * to '1' after the core initialization is completed. 420 */ 421 if (dwc->revision > DWC3_REVISION_194A) 422 reg |= DWC3_GUSB3PIPECTL_SUSPHY; 423 424 if (dwc->u2ss_inp3_quirk) 425 reg |= DWC3_GUSB3PIPECTL_U2SSINP3OK; 426 427 if (dwc->dis_rxdet_inp3_quirk) 428 reg |= DWC3_GUSB3PIPECTL_DISRXDETINP3; 429 430 if (dwc->req_p1p2p3_quirk) 431 reg |= DWC3_GUSB3PIPECTL_REQP1P2P3; 432 433 if (dwc->del_p1p2p3_quirk) 434 reg |= DWC3_GUSB3PIPECTL_DEP1P2P3_EN; 435 436 if (dwc->del_phy_power_chg_quirk) 437 reg |= DWC3_GUSB3PIPECTL_DEPOCHANGE; 438 439 if (dwc->lfps_filter_quirk) 440 reg |= DWC3_GUSB3PIPECTL_LFPSFILT; 441 442 if (dwc->rx_detect_poll_quirk) 443 reg |= DWC3_GUSB3PIPECTL_RX_DETOPOLL; 444 445 if (dwc->tx_de_emphasis_quirk) 446 reg |= DWC3_GUSB3PIPECTL_TX_DEEPH(dwc->tx_de_emphasis); 447 448 if (dwc->dis_u3_susphy_quirk) 449 reg &= ~DWC3_GUSB3PIPECTL_SUSPHY; 450 451 dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg); 452 453 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0)); 454 455 /* Select the HS PHY interface */ 456 switch (DWC3_GHWPARAMS3_HSPHY_IFC(dwc->hwparams.hwparams3)) { 457 case DWC3_GHWPARAMS3_HSPHY_IFC_UTMI_ULPI: 458 if (dwc->hsphy_interface && 459 !strncmp(dwc->hsphy_interface, "utmi", 4)) { 460 reg &= ~DWC3_GUSB2PHYCFG_ULPI_UTMI; 461 break; 462 } else if (dwc->hsphy_interface && 463 !strncmp(dwc->hsphy_interface, "ulpi", 4)) { 464 reg |= DWC3_GUSB2PHYCFG_ULPI_UTMI; 465 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg); 466 } else { 467 /* Relying on default value. */ 468 if (!(reg & DWC3_GUSB2PHYCFG_ULPI_UTMI)) 469 break; 470 } 471 /* FALLTHROUGH */ 472 case DWC3_GHWPARAMS3_HSPHY_IFC_ULPI: 473 /* Making sure the interface and PHY are operational */ 474 ret = dwc3_soft_reset(dwc); 475 if (ret) 476 return ret; 477 478 udelay(1); 479 480 ret = dwc3_ulpi_init(dwc); 481 if (ret) 482 return ret; 483 /* FALLTHROUGH */ 484 default: 485 break; 486 } 487 488 /* 489 * Above 1.94a, it is recommended to set DWC3_GUSB2PHYCFG_SUSPHY to 490 * '0' during coreConsultant configuration. So default value will 491 * be '0' when the core is reset. Application needs to set it to 492 * '1' after the core initialization is completed. 493 */ 494 if (dwc->revision > DWC3_REVISION_194A) 495 reg |= DWC3_GUSB2PHYCFG_SUSPHY; 496 497 if (dwc->dis_u2_susphy_quirk) 498 reg &= ~DWC3_GUSB2PHYCFG_SUSPHY; 499 500 if (dwc->dis_enblslpm_quirk) 501 reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM; 502 503 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg); 504 505 return 0; 506 } 507 508 static void dwc3_core_exit(struct dwc3 *dwc) 509 { 510 dwc3_event_buffers_cleanup(dwc); 511 512 usb_phy_shutdown(dwc->usb2_phy); 513 usb_phy_shutdown(dwc->usb3_phy); 514 phy_exit(dwc->usb2_generic_phy); 515 phy_exit(dwc->usb3_generic_phy); 516 517 usb_phy_set_suspend(dwc->usb2_phy, 1); 518 usb_phy_set_suspend(dwc->usb3_phy, 1); 519 phy_power_off(dwc->usb2_generic_phy); 520 phy_power_off(dwc->usb3_generic_phy); 521 } 522 523 /** 524 * dwc3_core_init - Low-level initialization of DWC3 Core 525 * @dwc: Pointer to our controller context structure 526 * 527 * Returns 0 on success otherwise negative errno. 528 */ 529 static int dwc3_core_init(struct dwc3 *dwc) 530 { 531 u32 hwparams4 = dwc->hwparams.hwparams4; 532 u32 reg; 533 int ret; 534 535 reg = dwc3_readl(dwc->regs, DWC3_GSNPSID); 536 /* This should read as U3 followed by revision number */ 537 if ((reg & DWC3_GSNPSID_MASK) == 0x55330000) { 538 /* Detected DWC_usb3 IP */ 539 dwc->revision = reg; 540 } else if ((reg & DWC3_GSNPSID_MASK) == 0x33310000) { 541 /* Detected DWC_usb31 IP */ 542 dwc->revision = dwc3_readl(dwc->regs, DWC3_VER_NUMBER); 543 dwc->revision |= DWC3_REVISION_IS_DWC31; 544 } else { 545 dev_err(dwc->dev, "this is not a DesignWare USB3 DRD Core\n"); 546 ret = -ENODEV; 547 goto err0; 548 } 549 550 /* 551 * Write Linux Version Code to our GUID register so it's easy to figure 552 * out which kernel version a bug was found. 553 */ 554 dwc3_writel(dwc->regs, DWC3_GUID, LINUX_VERSION_CODE); 555 556 /* Handle USB2.0-only core configuration */ 557 if (DWC3_GHWPARAMS3_SSPHY_IFC(dwc->hwparams.hwparams3) == 558 DWC3_GHWPARAMS3_SSPHY_IFC_DIS) { 559 if (dwc->maximum_speed == USB_SPEED_SUPER) 560 dwc->maximum_speed = USB_SPEED_HIGH; 561 } 562 563 /* issue device SoftReset too */ 564 ret = dwc3_soft_reset(dwc); 565 if (ret) 566 goto err0; 567 568 ret = dwc3_core_soft_reset(dwc); 569 if (ret) 570 goto err0; 571 572 ret = dwc3_phy_setup(dwc); 573 if (ret) 574 goto err0; 575 576 reg = dwc3_readl(dwc->regs, DWC3_GCTL); 577 reg &= ~DWC3_GCTL_SCALEDOWN_MASK; 578 579 switch (DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1)) { 580 case DWC3_GHWPARAMS1_EN_PWROPT_CLK: 581 /** 582 * WORKAROUND: DWC3 revisions between 2.10a and 2.50a have an 583 * issue which would cause xHCI compliance tests to fail. 584 * 585 * Because of that we cannot enable clock gating on such 586 * configurations. 587 * 588 * Refers to: 589 * 590 * STAR#9000588375: Clock Gating, SOF Issues when ref_clk-Based 591 * SOF/ITP Mode Used 592 */ 593 if ((dwc->dr_mode == USB_DR_MODE_HOST || 594 dwc->dr_mode == USB_DR_MODE_OTG) && 595 (dwc->revision >= DWC3_REVISION_210A && 596 dwc->revision <= DWC3_REVISION_250A)) 597 reg |= DWC3_GCTL_DSBLCLKGTNG | DWC3_GCTL_SOFITPSYNC; 598 else 599 reg &= ~DWC3_GCTL_DSBLCLKGTNG; 600 break; 601 case DWC3_GHWPARAMS1_EN_PWROPT_HIB: 602 /* enable hibernation here */ 603 dwc->nr_scratch = DWC3_GHWPARAMS4_HIBER_SCRATCHBUFS(hwparams4); 604 605 /* 606 * REVISIT Enabling this bit so that host-mode hibernation 607 * will work. Device-mode hibernation is not yet implemented. 608 */ 609 reg |= DWC3_GCTL_GBLHIBERNATIONEN; 610 break; 611 default: 612 dwc3_trace(trace_dwc3_core, "No power optimization available\n"); 613 } 614 615 /* check if current dwc3 is on simulation board */ 616 if (dwc->hwparams.hwparams6 & DWC3_GHWPARAMS6_EN_FPGA) { 617 dwc3_trace(trace_dwc3_core, 618 "running on FPGA platform\n"); 619 dwc->is_fpga = true; 620 } 621 622 WARN_ONCE(dwc->disable_scramble_quirk && !dwc->is_fpga, 623 "disable_scramble cannot be used on non-FPGA builds\n"); 624 625 if (dwc->disable_scramble_quirk && dwc->is_fpga) 626 reg |= DWC3_GCTL_DISSCRAMBLE; 627 else 628 reg &= ~DWC3_GCTL_DISSCRAMBLE; 629 630 if (dwc->u2exit_lfps_quirk) 631 reg |= DWC3_GCTL_U2EXIT_LFPS; 632 633 /* 634 * WORKAROUND: DWC3 revisions <1.90a have a bug 635 * where the device can fail to connect at SuperSpeed 636 * and falls back to high-speed mode which causes 637 * the device to enter a Connect/Disconnect loop 638 */ 639 if (dwc->revision < DWC3_REVISION_190A) 640 reg |= DWC3_GCTL_U2RSTECN; 641 642 dwc3_writel(dwc->regs, DWC3_GCTL, reg); 643 644 dwc3_core_num_eps(dwc); 645 646 ret = dwc3_setup_scratch_buffers(dwc); 647 if (ret) 648 goto err1; 649 650 /* Adjust Frame Length */ 651 dwc3_frame_length_adjustment(dwc); 652 653 usb_phy_set_suspend(dwc->usb2_phy, 0); 654 usb_phy_set_suspend(dwc->usb3_phy, 0); 655 ret = phy_power_on(dwc->usb2_generic_phy); 656 if (ret < 0) 657 goto err2; 658 659 ret = phy_power_on(dwc->usb3_generic_phy); 660 if (ret < 0) 661 goto err3; 662 663 ret = dwc3_event_buffers_setup(dwc); 664 if (ret) { 665 dev_err(dwc->dev, "failed to setup event buffers\n"); 666 goto err4; 667 } 668 669 return 0; 670 671 err4: 672 phy_power_off(dwc->usb2_generic_phy); 673 674 err3: 675 phy_power_off(dwc->usb3_generic_phy); 676 677 err2: 678 usb_phy_set_suspend(dwc->usb2_phy, 1); 679 usb_phy_set_suspend(dwc->usb3_phy, 1); 680 dwc3_core_exit(dwc); 681 682 err1: 683 usb_phy_shutdown(dwc->usb2_phy); 684 usb_phy_shutdown(dwc->usb3_phy); 685 phy_exit(dwc->usb2_generic_phy); 686 phy_exit(dwc->usb3_generic_phy); 687 688 err0: 689 return ret; 690 } 691 692 static int dwc3_core_get_phy(struct dwc3 *dwc) 693 { 694 struct device *dev = dwc->dev; 695 struct device_node *node = dev->of_node; 696 int ret; 697 698 if (node) { 699 dwc->usb2_phy = devm_usb_get_phy_by_phandle(dev, "usb-phy", 0); 700 dwc->usb3_phy = devm_usb_get_phy_by_phandle(dev, "usb-phy", 1); 701 } else { 702 dwc->usb2_phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB2); 703 dwc->usb3_phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB3); 704 } 705 706 if (IS_ERR(dwc->usb2_phy)) { 707 ret = PTR_ERR(dwc->usb2_phy); 708 if (ret == -ENXIO || ret == -ENODEV) { 709 dwc->usb2_phy = NULL; 710 } else if (ret == -EPROBE_DEFER) { 711 return ret; 712 } else { 713 dev_err(dev, "no usb2 phy configured\n"); 714 return ret; 715 } 716 } 717 718 if (IS_ERR(dwc->usb3_phy)) { 719 ret = PTR_ERR(dwc->usb3_phy); 720 if (ret == -ENXIO || ret == -ENODEV) { 721 dwc->usb3_phy = NULL; 722 } else if (ret == -EPROBE_DEFER) { 723 return ret; 724 } else { 725 dev_err(dev, "no usb3 phy configured\n"); 726 return ret; 727 } 728 } 729 730 dwc->usb2_generic_phy = devm_phy_get(dev, "usb2-phy"); 731 if (IS_ERR(dwc->usb2_generic_phy)) { 732 ret = PTR_ERR(dwc->usb2_generic_phy); 733 if (ret == -ENOSYS || ret == -ENODEV) { 734 dwc->usb2_generic_phy = NULL; 735 } else if (ret == -EPROBE_DEFER) { 736 return ret; 737 } else { 738 dev_err(dev, "no usb2 phy configured\n"); 739 return ret; 740 } 741 } 742 743 dwc->usb3_generic_phy = devm_phy_get(dev, "usb3-phy"); 744 if (IS_ERR(dwc->usb3_generic_phy)) { 745 ret = PTR_ERR(dwc->usb3_generic_phy); 746 if (ret == -ENOSYS || ret == -ENODEV) { 747 dwc->usb3_generic_phy = NULL; 748 } else if (ret == -EPROBE_DEFER) { 749 return ret; 750 } else { 751 dev_err(dev, "no usb3 phy configured\n"); 752 return ret; 753 } 754 } 755 756 return 0; 757 } 758 759 static int dwc3_core_init_mode(struct dwc3 *dwc) 760 { 761 struct device *dev = dwc->dev; 762 int ret; 763 764 switch (dwc->dr_mode) { 765 case USB_DR_MODE_PERIPHERAL: 766 dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_DEVICE); 767 ret = dwc3_gadget_init(dwc); 768 if (ret) { 769 if (ret != -EPROBE_DEFER) 770 dev_err(dev, "failed to initialize gadget\n"); 771 return ret; 772 } 773 break; 774 case USB_DR_MODE_HOST: 775 dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_HOST); 776 ret = dwc3_host_init(dwc); 777 if (ret) { 778 if (ret != -EPROBE_DEFER) 779 dev_err(dev, "failed to initialize host\n"); 780 return ret; 781 } 782 break; 783 case USB_DR_MODE_OTG: 784 dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_OTG); 785 ret = dwc3_host_init(dwc); 786 if (ret) { 787 if (ret != -EPROBE_DEFER) 788 dev_err(dev, "failed to initialize host\n"); 789 return ret; 790 } 791 792 ret = dwc3_gadget_init(dwc); 793 if (ret) { 794 if (ret != -EPROBE_DEFER) 795 dev_err(dev, "failed to initialize gadget\n"); 796 return ret; 797 } 798 break; 799 default: 800 dev_err(dev, "Unsupported mode of operation %d\n", dwc->dr_mode); 801 return -EINVAL; 802 } 803 804 return 0; 805 } 806 807 static void dwc3_core_exit_mode(struct dwc3 *dwc) 808 { 809 switch (dwc->dr_mode) { 810 case USB_DR_MODE_PERIPHERAL: 811 dwc3_gadget_exit(dwc); 812 break; 813 case USB_DR_MODE_HOST: 814 dwc3_host_exit(dwc); 815 break; 816 case USB_DR_MODE_OTG: 817 dwc3_host_exit(dwc); 818 dwc3_gadget_exit(dwc); 819 break; 820 default: 821 /* do nothing */ 822 break; 823 } 824 } 825 826 #define DWC3_ALIGN_MASK (16 - 1) 827 828 static int dwc3_probe(struct platform_device *pdev) 829 { 830 struct device *dev = &pdev->dev; 831 struct resource *res; 832 struct dwc3 *dwc; 833 u8 lpm_nyet_threshold; 834 u8 tx_de_emphasis; 835 u8 hird_threshold; 836 837 int ret; 838 839 void __iomem *regs; 840 void *mem; 841 842 mem = devm_kzalloc(dev, sizeof(*dwc) + DWC3_ALIGN_MASK, GFP_KERNEL); 843 if (!mem) 844 return -ENOMEM; 845 846 dwc = PTR_ALIGN(mem, DWC3_ALIGN_MASK + 1); 847 dwc->mem = mem; 848 dwc->dev = dev; 849 850 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 851 if (!res) { 852 dev_err(dev, "missing memory resource\n"); 853 return -ENODEV; 854 } 855 856 dwc->xhci_resources[0].start = res->start; 857 dwc->xhci_resources[0].end = dwc->xhci_resources[0].start + 858 DWC3_XHCI_REGS_END; 859 dwc->xhci_resources[0].flags = res->flags; 860 dwc->xhci_resources[0].name = res->name; 861 862 res->start += DWC3_GLOBALS_REGS_START; 863 864 /* 865 * Request memory region but exclude xHCI regs, 866 * since it will be requested by the xhci-plat driver. 867 */ 868 regs = devm_ioremap_resource(dev, res); 869 if (IS_ERR(regs)) { 870 ret = PTR_ERR(regs); 871 goto err0; 872 } 873 874 dwc->regs = regs; 875 dwc->regs_size = resource_size(res); 876 877 /* default to highest possible threshold */ 878 lpm_nyet_threshold = 0xff; 879 880 /* default to -3.5dB de-emphasis */ 881 tx_de_emphasis = 1; 882 883 /* 884 * default to assert utmi_sleep_n and use maximum allowed HIRD 885 * threshold value of 0b1100 886 */ 887 hird_threshold = 12; 888 889 dwc->maximum_speed = usb_get_maximum_speed(dev); 890 dwc->dr_mode = usb_get_dr_mode(dev); 891 892 dwc->has_lpm_erratum = device_property_read_bool(dev, 893 "snps,has-lpm-erratum"); 894 device_property_read_u8(dev, "snps,lpm-nyet-threshold", 895 &lpm_nyet_threshold); 896 dwc->is_utmi_l1_suspend = device_property_read_bool(dev, 897 "snps,is-utmi-l1-suspend"); 898 device_property_read_u8(dev, "snps,hird-threshold", 899 &hird_threshold); 900 dwc->usb3_lpm_capable = device_property_read_bool(dev, 901 "snps,usb3_lpm_capable"); 902 903 dwc->disable_scramble_quirk = device_property_read_bool(dev, 904 "snps,disable_scramble_quirk"); 905 dwc->u2exit_lfps_quirk = device_property_read_bool(dev, 906 "snps,u2exit_lfps_quirk"); 907 dwc->u2ss_inp3_quirk = device_property_read_bool(dev, 908 "snps,u2ss_inp3_quirk"); 909 dwc->req_p1p2p3_quirk = device_property_read_bool(dev, 910 "snps,req_p1p2p3_quirk"); 911 dwc->del_p1p2p3_quirk = device_property_read_bool(dev, 912 "snps,del_p1p2p3_quirk"); 913 dwc->del_phy_power_chg_quirk = device_property_read_bool(dev, 914 "snps,del_phy_power_chg_quirk"); 915 dwc->lfps_filter_quirk = device_property_read_bool(dev, 916 "snps,lfps_filter_quirk"); 917 dwc->rx_detect_poll_quirk = device_property_read_bool(dev, 918 "snps,rx_detect_poll_quirk"); 919 dwc->dis_u3_susphy_quirk = device_property_read_bool(dev, 920 "snps,dis_u3_susphy_quirk"); 921 dwc->dis_u2_susphy_quirk = device_property_read_bool(dev, 922 "snps,dis_u2_susphy_quirk"); 923 dwc->dis_enblslpm_quirk = device_property_read_bool(dev, 924 "snps,dis_enblslpm_quirk"); 925 dwc->dis_rxdet_inp3_quirk = device_property_read_bool(dev, 926 "snps,dis_rxdet_inp3_quirk"); 927 928 dwc->tx_de_emphasis_quirk = device_property_read_bool(dev, 929 "snps,tx_de_emphasis_quirk"); 930 device_property_read_u8(dev, "snps,tx_de_emphasis", 931 &tx_de_emphasis); 932 device_property_read_string(dev, "snps,hsphy_interface", 933 &dwc->hsphy_interface); 934 device_property_read_u32(dev, "snps,quirk-frame-length-adjustment", 935 &dwc->fladj); 936 937 dwc->lpm_nyet_threshold = lpm_nyet_threshold; 938 dwc->tx_de_emphasis = tx_de_emphasis; 939 940 dwc->hird_threshold = hird_threshold 941 | (dwc->is_utmi_l1_suspend << 4); 942 943 platform_set_drvdata(pdev, dwc); 944 dwc3_cache_hwparams(dwc); 945 946 ret = dwc3_core_get_phy(dwc); 947 if (ret) 948 goto err0; 949 950 spin_lock_init(&dwc->lock); 951 952 if (!dev->dma_mask) { 953 dev->dma_mask = dev->parent->dma_mask; 954 dev->dma_parms = dev->parent->dma_parms; 955 dma_set_coherent_mask(dev, dev->parent->coherent_dma_mask); 956 } 957 958 pm_runtime_set_active(dev); 959 pm_runtime_use_autosuspend(dev); 960 pm_runtime_set_autosuspend_delay(dev, DWC3_DEFAULT_AUTOSUSPEND_DELAY); 961 pm_runtime_enable(dev); 962 ret = pm_runtime_get_sync(dev); 963 if (ret < 0) 964 goto err1; 965 966 pm_runtime_forbid(dev); 967 968 ret = dwc3_alloc_event_buffers(dwc, DWC3_EVENT_BUFFERS_SIZE); 969 if (ret) { 970 dev_err(dwc->dev, "failed to allocate event buffers\n"); 971 ret = -ENOMEM; 972 goto err2; 973 } 974 975 if (IS_ENABLED(CONFIG_USB_DWC3_HOST) && 976 (dwc->dr_mode == USB_DR_MODE_OTG || 977 dwc->dr_mode == USB_DR_MODE_UNKNOWN)) 978 dwc->dr_mode = USB_DR_MODE_HOST; 979 else if (IS_ENABLED(CONFIG_USB_DWC3_GADGET) && 980 (dwc->dr_mode == USB_DR_MODE_OTG || 981 dwc->dr_mode == USB_DR_MODE_UNKNOWN)) 982 dwc->dr_mode = USB_DR_MODE_PERIPHERAL; 983 984 if (dwc->dr_mode == USB_DR_MODE_UNKNOWN) 985 dwc->dr_mode = USB_DR_MODE_OTG; 986 987 ret = dwc3_alloc_scratch_buffers(dwc); 988 if (ret) 989 goto err3; 990 991 ret = dwc3_core_init(dwc); 992 if (ret) { 993 dev_err(dev, "failed to initialize core\n"); 994 goto err4; 995 } 996 997 /* Check the maximum_speed parameter */ 998 switch (dwc->maximum_speed) { 999 case USB_SPEED_LOW: 1000 case USB_SPEED_FULL: 1001 case USB_SPEED_HIGH: 1002 case USB_SPEED_SUPER: 1003 case USB_SPEED_SUPER_PLUS: 1004 break; 1005 default: 1006 dev_err(dev, "invalid maximum_speed parameter %d\n", 1007 dwc->maximum_speed); 1008 /* fall through */ 1009 case USB_SPEED_UNKNOWN: 1010 /* default to superspeed */ 1011 dwc->maximum_speed = USB_SPEED_SUPER; 1012 1013 /* 1014 * default to superspeed plus if we are capable. 1015 */ 1016 if (dwc3_is_usb31(dwc) && 1017 (DWC3_GHWPARAMS3_SSPHY_IFC(dwc->hwparams.hwparams3) == 1018 DWC3_GHWPARAMS3_SSPHY_IFC_GEN2)) 1019 dwc->maximum_speed = USB_SPEED_SUPER_PLUS; 1020 1021 break; 1022 } 1023 1024 ret = dwc3_core_init_mode(dwc); 1025 if (ret) 1026 goto err5; 1027 1028 dwc3_debugfs_init(dwc); 1029 pm_runtime_put(dev); 1030 1031 return 0; 1032 1033 err5: 1034 dwc3_event_buffers_cleanup(dwc); 1035 1036 err4: 1037 dwc3_free_scratch_buffers(dwc); 1038 1039 err3: 1040 dwc3_free_event_buffers(dwc); 1041 dwc3_ulpi_exit(dwc); 1042 1043 err2: 1044 pm_runtime_allow(&pdev->dev); 1045 1046 err1: 1047 pm_runtime_put_sync(&pdev->dev); 1048 pm_runtime_disable(&pdev->dev); 1049 1050 err0: 1051 /* 1052 * restore res->start back to its original value so that, in case the 1053 * probe is deferred, we don't end up getting error in request the 1054 * memory region the next time probe is called. 1055 */ 1056 res->start -= DWC3_GLOBALS_REGS_START; 1057 1058 return ret; 1059 } 1060 1061 static int dwc3_remove(struct platform_device *pdev) 1062 { 1063 struct dwc3 *dwc = platform_get_drvdata(pdev); 1064 struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1065 1066 pm_runtime_get_sync(&pdev->dev); 1067 /* 1068 * restore res->start back to its original value so that, in case the 1069 * probe is deferred, we don't end up getting error in request the 1070 * memory region the next time probe is called. 1071 */ 1072 res->start -= DWC3_GLOBALS_REGS_START; 1073 1074 dwc3_debugfs_exit(dwc); 1075 dwc3_core_exit_mode(dwc); 1076 1077 dwc3_core_exit(dwc); 1078 dwc3_ulpi_exit(dwc); 1079 1080 pm_runtime_put_sync(&pdev->dev); 1081 pm_runtime_allow(&pdev->dev); 1082 pm_runtime_disable(&pdev->dev); 1083 1084 dwc3_free_event_buffers(dwc); 1085 dwc3_free_scratch_buffers(dwc); 1086 1087 return 0; 1088 } 1089 1090 #ifdef CONFIG_PM 1091 static int dwc3_suspend_common(struct dwc3 *dwc) 1092 { 1093 unsigned long flags; 1094 1095 switch (dwc->dr_mode) { 1096 case USB_DR_MODE_PERIPHERAL: 1097 case USB_DR_MODE_OTG: 1098 spin_lock_irqsave(&dwc->lock, flags); 1099 dwc3_gadget_suspend(dwc); 1100 spin_unlock_irqrestore(&dwc->lock, flags); 1101 break; 1102 case USB_DR_MODE_HOST: 1103 default: 1104 /* do nothing */ 1105 break; 1106 } 1107 1108 dwc3_core_exit(dwc); 1109 1110 return 0; 1111 } 1112 1113 static int dwc3_resume_common(struct dwc3 *dwc) 1114 { 1115 unsigned long flags; 1116 int ret; 1117 1118 ret = dwc3_core_init(dwc); 1119 if (ret) 1120 return ret; 1121 1122 switch (dwc->dr_mode) { 1123 case USB_DR_MODE_PERIPHERAL: 1124 case USB_DR_MODE_OTG: 1125 spin_lock_irqsave(&dwc->lock, flags); 1126 dwc3_gadget_resume(dwc); 1127 spin_unlock_irqrestore(&dwc->lock, flags); 1128 /* FALLTHROUGH */ 1129 case USB_DR_MODE_HOST: 1130 default: 1131 /* do nothing */ 1132 break; 1133 } 1134 1135 return 0; 1136 } 1137 1138 static int dwc3_runtime_checks(struct dwc3 *dwc) 1139 { 1140 switch (dwc->dr_mode) { 1141 case USB_DR_MODE_PERIPHERAL: 1142 case USB_DR_MODE_OTG: 1143 if (dwc->connected) 1144 return -EBUSY; 1145 break; 1146 case USB_DR_MODE_HOST: 1147 default: 1148 /* do nothing */ 1149 break; 1150 } 1151 1152 return 0; 1153 } 1154 1155 static int dwc3_runtime_suspend(struct device *dev) 1156 { 1157 struct dwc3 *dwc = dev_get_drvdata(dev); 1158 int ret; 1159 1160 if (dwc3_runtime_checks(dwc)) 1161 return -EBUSY; 1162 1163 ret = dwc3_suspend_common(dwc); 1164 if (ret) 1165 return ret; 1166 1167 device_init_wakeup(dev, true); 1168 1169 return 0; 1170 } 1171 1172 static int dwc3_runtime_resume(struct device *dev) 1173 { 1174 struct dwc3 *dwc = dev_get_drvdata(dev); 1175 int ret; 1176 1177 device_init_wakeup(dev, false); 1178 1179 ret = dwc3_resume_common(dwc); 1180 if (ret) 1181 return ret; 1182 1183 switch (dwc->dr_mode) { 1184 case USB_DR_MODE_PERIPHERAL: 1185 case USB_DR_MODE_OTG: 1186 dwc3_gadget_process_pending_events(dwc); 1187 break; 1188 case USB_DR_MODE_HOST: 1189 default: 1190 /* do nothing */ 1191 break; 1192 } 1193 1194 pm_runtime_mark_last_busy(dev); 1195 pm_runtime_put(dev); 1196 1197 return 0; 1198 } 1199 1200 static int dwc3_runtime_idle(struct device *dev) 1201 { 1202 struct dwc3 *dwc = dev_get_drvdata(dev); 1203 1204 switch (dwc->dr_mode) { 1205 case USB_DR_MODE_PERIPHERAL: 1206 case USB_DR_MODE_OTG: 1207 if (dwc3_runtime_checks(dwc)) 1208 return -EBUSY; 1209 break; 1210 case USB_DR_MODE_HOST: 1211 default: 1212 /* do nothing */ 1213 break; 1214 } 1215 1216 pm_runtime_mark_last_busy(dev); 1217 pm_runtime_autosuspend(dev); 1218 1219 return 0; 1220 } 1221 #endif /* CONFIG_PM */ 1222 1223 #ifdef CONFIG_PM_SLEEP 1224 static int dwc3_suspend(struct device *dev) 1225 { 1226 struct dwc3 *dwc = dev_get_drvdata(dev); 1227 int ret; 1228 1229 ret = dwc3_suspend_common(dwc); 1230 if (ret) 1231 return ret; 1232 1233 pinctrl_pm_select_sleep_state(dev); 1234 1235 return 0; 1236 } 1237 1238 static int dwc3_resume(struct device *dev) 1239 { 1240 struct dwc3 *dwc = dev_get_drvdata(dev); 1241 int ret; 1242 1243 pinctrl_pm_select_default_state(dev); 1244 1245 ret = dwc3_resume_common(dwc); 1246 if (ret) 1247 return ret; 1248 1249 pm_runtime_disable(dev); 1250 pm_runtime_set_active(dev); 1251 pm_runtime_enable(dev); 1252 1253 return 0; 1254 } 1255 #endif /* CONFIG_PM_SLEEP */ 1256 1257 static const struct dev_pm_ops dwc3_dev_pm_ops = { 1258 SET_SYSTEM_SLEEP_PM_OPS(dwc3_suspend, dwc3_resume) 1259 SET_RUNTIME_PM_OPS(dwc3_runtime_suspend, dwc3_runtime_resume, 1260 dwc3_runtime_idle) 1261 }; 1262 1263 #ifdef CONFIG_OF 1264 static const struct of_device_id of_dwc3_match[] = { 1265 { 1266 .compatible = "snps,dwc3" 1267 }, 1268 { 1269 .compatible = "synopsys,dwc3" 1270 }, 1271 { }, 1272 }; 1273 MODULE_DEVICE_TABLE(of, of_dwc3_match); 1274 #endif 1275 1276 #ifdef CONFIG_ACPI 1277 1278 #define ACPI_ID_INTEL_BSW "808622B7" 1279 1280 static const struct acpi_device_id dwc3_acpi_match[] = { 1281 { ACPI_ID_INTEL_BSW, 0 }, 1282 { }, 1283 }; 1284 MODULE_DEVICE_TABLE(acpi, dwc3_acpi_match); 1285 #endif 1286 1287 static struct platform_driver dwc3_driver = { 1288 .probe = dwc3_probe, 1289 .remove = dwc3_remove, 1290 .driver = { 1291 .name = "dwc3", 1292 .of_match_table = of_match_ptr(of_dwc3_match), 1293 .acpi_match_table = ACPI_PTR(dwc3_acpi_match), 1294 .pm = &dwc3_dev_pm_ops, 1295 }, 1296 }; 1297 1298 module_platform_driver(dwc3_driver); 1299 1300 MODULE_ALIAS("platform:dwc3"); 1301 MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>"); 1302 MODULE_LICENSE("GPL v2"); 1303 MODULE_DESCRIPTION("DesignWare USB3 DRD Controller Driver"); 1304