1 /** 2 * core.c - DesignWare USB3 DRD Controller Core file 3 * 4 * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com 5 * 6 * Authors: Felipe Balbi <balbi@ti.com>, 7 * Sebastian Andrzej Siewior <bigeasy@linutronix.de> 8 * 9 * This program is free software: you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License version 2 of 11 * the License as published by the Free Software Foundation. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program. If not, see <http://www.gnu.org/licenses/>. 20 */ 21 22 #include <linux/version.h> 23 #include <linux/module.h> 24 #include <linux/kernel.h> 25 #include <linux/slab.h> 26 #include <linux/spinlock.h> 27 #include <linux/platform_device.h> 28 #include <linux/pm_runtime.h> 29 #include <linux/interrupt.h> 30 #include <linux/ioport.h> 31 #include <linux/io.h> 32 #include <linux/list.h> 33 #include <linux/delay.h> 34 #include <linux/dma-mapping.h> 35 #include <linux/of.h> 36 #include <linux/acpi.h> 37 38 #include <linux/usb/ch9.h> 39 #include <linux/usb/gadget.h> 40 #include <linux/usb/of.h> 41 #include <linux/usb/otg.h> 42 43 #include "platform_data.h" 44 #include "core.h" 45 #include "gadget.h" 46 #include "io.h" 47 48 #include "debug.h" 49 50 /* -------------------------------------------------------------------------- */ 51 52 void dwc3_set_mode(struct dwc3 *dwc, u32 mode) 53 { 54 u32 reg; 55 56 reg = dwc3_readl(dwc->regs, DWC3_GCTL); 57 reg &= ~(DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_OTG)); 58 reg |= DWC3_GCTL_PRTCAPDIR(mode); 59 dwc3_writel(dwc->regs, DWC3_GCTL, reg); 60 } 61 62 /** 63 * dwc3_core_soft_reset - Issues core soft reset and PHY reset 64 * @dwc: pointer to our context structure 65 */ 66 static int dwc3_core_soft_reset(struct dwc3 *dwc) 67 { 68 u32 reg; 69 int ret; 70 71 /* Before Resetting PHY, put Core in Reset */ 72 reg = dwc3_readl(dwc->regs, DWC3_GCTL); 73 reg |= DWC3_GCTL_CORESOFTRESET; 74 dwc3_writel(dwc->regs, DWC3_GCTL, reg); 75 76 /* Assert USB3 PHY reset */ 77 reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0)); 78 reg |= DWC3_GUSB3PIPECTL_PHYSOFTRST; 79 dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg); 80 81 /* Assert USB2 PHY reset */ 82 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0)); 83 reg |= DWC3_GUSB2PHYCFG_PHYSOFTRST; 84 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg); 85 86 usb_phy_init(dwc->usb2_phy); 87 usb_phy_init(dwc->usb3_phy); 88 ret = phy_init(dwc->usb2_generic_phy); 89 if (ret < 0) 90 return ret; 91 92 ret = phy_init(dwc->usb3_generic_phy); 93 if (ret < 0) { 94 phy_exit(dwc->usb2_generic_phy); 95 return ret; 96 } 97 mdelay(100); 98 99 /* Clear USB3 PHY reset */ 100 reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0)); 101 reg &= ~DWC3_GUSB3PIPECTL_PHYSOFTRST; 102 dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg); 103 104 /* Clear USB2 PHY reset */ 105 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0)); 106 reg &= ~DWC3_GUSB2PHYCFG_PHYSOFTRST; 107 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg); 108 109 mdelay(100); 110 111 /* After PHYs are stable we can take Core out of reset state */ 112 reg = dwc3_readl(dwc->regs, DWC3_GCTL); 113 reg &= ~DWC3_GCTL_CORESOFTRESET; 114 dwc3_writel(dwc->regs, DWC3_GCTL, reg); 115 116 return 0; 117 } 118 119 /** 120 * dwc3_soft_reset - Issue soft reset 121 * @dwc: Pointer to our controller context structure 122 */ 123 static int dwc3_soft_reset(struct dwc3 *dwc) 124 { 125 unsigned long timeout; 126 u32 reg; 127 128 timeout = jiffies + msecs_to_jiffies(500); 129 dwc3_writel(dwc->regs, DWC3_DCTL, DWC3_DCTL_CSFTRST); 130 do { 131 reg = dwc3_readl(dwc->regs, DWC3_DCTL); 132 if (!(reg & DWC3_DCTL_CSFTRST)) 133 break; 134 135 if (time_after(jiffies, timeout)) { 136 dev_err(dwc->dev, "Reset Timed Out\n"); 137 return -ETIMEDOUT; 138 } 139 140 cpu_relax(); 141 } while (true); 142 143 return 0; 144 } 145 146 /** 147 * dwc3_free_one_event_buffer - Frees one event buffer 148 * @dwc: Pointer to our controller context structure 149 * @evt: Pointer to event buffer to be freed 150 */ 151 static void dwc3_free_one_event_buffer(struct dwc3 *dwc, 152 struct dwc3_event_buffer *evt) 153 { 154 dma_free_coherent(dwc->dev, evt->length, evt->buf, evt->dma); 155 } 156 157 /** 158 * dwc3_alloc_one_event_buffer - Allocates one event buffer structure 159 * @dwc: Pointer to our controller context structure 160 * @length: size of the event buffer 161 * 162 * Returns a pointer to the allocated event buffer structure on success 163 * otherwise ERR_PTR(errno). 164 */ 165 static struct dwc3_event_buffer *dwc3_alloc_one_event_buffer(struct dwc3 *dwc, 166 unsigned length) 167 { 168 struct dwc3_event_buffer *evt; 169 170 evt = devm_kzalloc(dwc->dev, sizeof(*evt), GFP_KERNEL); 171 if (!evt) 172 return ERR_PTR(-ENOMEM); 173 174 evt->dwc = dwc; 175 evt->length = length; 176 evt->buf = dma_alloc_coherent(dwc->dev, length, 177 &evt->dma, GFP_KERNEL); 178 if (!evt->buf) 179 return ERR_PTR(-ENOMEM); 180 181 return evt; 182 } 183 184 /** 185 * dwc3_free_event_buffers - frees all allocated event buffers 186 * @dwc: Pointer to our controller context structure 187 */ 188 static void dwc3_free_event_buffers(struct dwc3 *dwc) 189 { 190 struct dwc3_event_buffer *evt; 191 int i; 192 193 for (i = 0; i < dwc->num_event_buffers; i++) { 194 evt = dwc->ev_buffs[i]; 195 if (evt) 196 dwc3_free_one_event_buffer(dwc, evt); 197 } 198 } 199 200 /** 201 * dwc3_alloc_event_buffers - Allocates @num event buffers of size @length 202 * @dwc: pointer to our controller context structure 203 * @length: size of event buffer 204 * 205 * Returns 0 on success otherwise negative errno. In the error case, dwc 206 * may contain some buffers allocated but not all which were requested. 207 */ 208 static int dwc3_alloc_event_buffers(struct dwc3 *dwc, unsigned length) 209 { 210 int num; 211 int i; 212 213 num = DWC3_NUM_INT(dwc->hwparams.hwparams1); 214 dwc->num_event_buffers = num; 215 216 dwc->ev_buffs = devm_kzalloc(dwc->dev, sizeof(*dwc->ev_buffs) * num, 217 GFP_KERNEL); 218 if (!dwc->ev_buffs) 219 return -ENOMEM; 220 221 for (i = 0; i < num; i++) { 222 struct dwc3_event_buffer *evt; 223 224 evt = dwc3_alloc_one_event_buffer(dwc, length); 225 if (IS_ERR(evt)) { 226 dev_err(dwc->dev, "can't allocate event buffer\n"); 227 return PTR_ERR(evt); 228 } 229 dwc->ev_buffs[i] = evt; 230 } 231 232 return 0; 233 } 234 235 /** 236 * dwc3_event_buffers_setup - setup our allocated event buffers 237 * @dwc: pointer to our controller context structure 238 * 239 * Returns 0 on success otherwise negative errno. 240 */ 241 static int dwc3_event_buffers_setup(struct dwc3 *dwc) 242 { 243 struct dwc3_event_buffer *evt; 244 int n; 245 246 for (n = 0; n < dwc->num_event_buffers; n++) { 247 evt = dwc->ev_buffs[n]; 248 dev_dbg(dwc->dev, "Event buf %p dma %08llx length %d\n", 249 evt->buf, (unsigned long long) evt->dma, 250 evt->length); 251 252 evt->lpos = 0; 253 254 dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(n), 255 lower_32_bits(evt->dma)); 256 dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(n), 257 upper_32_bits(evt->dma)); 258 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(n), 259 DWC3_GEVNTSIZ_SIZE(evt->length)); 260 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(n), 0); 261 } 262 263 return 0; 264 } 265 266 static void dwc3_event_buffers_cleanup(struct dwc3 *dwc) 267 { 268 struct dwc3_event_buffer *evt; 269 int n; 270 271 for (n = 0; n < dwc->num_event_buffers; n++) { 272 evt = dwc->ev_buffs[n]; 273 274 evt->lpos = 0; 275 276 dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(n), 0); 277 dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(n), 0); 278 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(n), DWC3_GEVNTSIZ_INTMASK 279 | DWC3_GEVNTSIZ_SIZE(0)); 280 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(n), 0); 281 } 282 } 283 284 static int dwc3_alloc_scratch_buffers(struct dwc3 *dwc) 285 { 286 if (!dwc->has_hibernation) 287 return 0; 288 289 if (!dwc->nr_scratch) 290 return 0; 291 292 dwc->scratchbuf = kmalloc_array(dwc->nr_scratch, 293 DWC3_SCRATCHBUF_SIZE, GFP_KERNEL); 294 if (!dwc->scratchbuf) 295 return -ENOMEM; 296 297 return 0; 298 } 299 300 static int dwc3_setup_scratch_buffers(struct dwc3 *dwc) 301 { 302 dma_addr_t scratch_addr; 303 u32 param; 304 int ret; 305 306 if (!dwc->has_hibernation) 307 return 0; 308 309 if (!dwc->nr_scratch) 310 return 0; 311 312 /* should never fall here */ 313 if (!WARN_ON(dwc->scratchbuf)) 314 return 0; 315 316 scratch_addr = dma_map_single(dwc->dev, dwc->scratchbuf, 317 dwc->nr_scratch * DWC3_SCRATCHBUF_SIZE, 318 DMA_BIDIRECTIONAL); 319 if (dma_mapping_error(dwc->dev, scratch_addr)) { 320 dev_err(dwc->dev, "failed to map scratch buffer\n"); 321 ret = -EFAULT; 322 goto err0; 323 } 324 325 dwc->scratch_addr = scratch_addr; 326 327 param = lower_32_bits(scratch_addr); 328 329 ret = dwc3_send_gadget_generic_command(dwc, 330 DWC3_DGCMD_SET_SCRATCHPAD_ADDR_LO, param); 331 if (ret < 0) 332 goto err1; 333 334 param = upper_32_bits(scratch_addr); 335 336 ret = dwc3_send_gadget_generic_command(dwc, 337 DWC3_DGCMD_SET_SCRATCHPAD_ADDR_HI, param); 338 if (ret < 0) 339 goto err1; 340 341 return 0; 342 343 err1: 344 dma_unmap_single(dwc->dev, dwc->scratch_addr, dwc->nr_scratch * 345 DWC3_SCRATCHBUF_SIZE, DMA_BIDIRECTIONAL); 346 347 err0: 348 return ret; 349 } 350 351 static void dwc3_free_scratch_buffers(struct dwc3 *dwc) 352 { 353 if (!dwc->has_hibernation) 354 return; 355 356 if (!dwc->nr_scratch) 357 return; 358 359 /* should never fall here */ 360 if (!WARN_ON(dwc->scratchbuf)) 361 return; 362 363 dma_unmap_single(dwc->dev, dwc->scratch_addr, dwc->nr_scratch * 364 DWC3_SCRATCHBUF_SIZE, DMA_BIDIRECTIONAL); 365 kfree(dwc->scratchbuf); 366 } 367 368 static void dwc3_core_num_eps(struct dwc3 *dwc) 369 { 370 struct dwc3_hwparams *parms = &dwc->hwparams; 371 372 dwc->num_in_eps = DWC3_NUM_IN_EPS(parms); 373 dwc->num_out_eps = DWC3_NUM_EPS(parms) - dwc->num_in_eps; 374 375 dwc3_trace(trace_dwc3_core, "found %d IN and %d OUT endpoints", 376 dwc->num_in_eps, dwc->num_out_eps); 377 } 378 379 static void dwc3_cache_hwparams(struct dwc3 *dwc) 380 { 381 struct dwc3_hwparams *parms = &dwc->hwparams; 382 383 parms->hwparams0 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS0); 384 parms->hwparams1 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS1); 385 parms->hwparams2 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS2); 386 parms->hwparams3 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS3); 387 parms->hwparams4 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS4); 388 parms->hwparams5 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS5); 389 parms->hwparams6 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS6); 390 parms->hwparams7 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS7); 391 parms->hwparams8 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS8); 392 } 393 394 /** 395 * dwc3_phy_setup - Configure USB PHY Interface of DWC3 Core 396 * @dwc: Pointer to our controller context structure 397 * 398 * Returns 0 on success. The USB PHY interfaces are configured but not 399 * initialized. The PHY interfaces and the PHYs get initialized together with 400 * the core in dwc3_core_init. 401 */ 402 static int dwc3_phy_setup(struct dwc3 *dwc) 403 { 404 u32 reg; 405 int ret; 406 407 reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0)); 408 409 /* 410 * Above 1.94a, it is recommended to set DWC3_GUSB3PIPECTL_SUSPHY 411 * to '0' during coreConsultant configuration. So default value 412 * will be '0' when the core is reset. Application needs to set it 413 * to '1' after the core initialization is completed. 414 */ 415 if (dwc->revision > DWC3_REVISION_194A) 416 reg |= DWC3_GUSB3PIPECTL_SUSPHY; 417 418 if (dwc->u2ss_inp3_quirk) 419 reg |= DWC3_GUSB3PIPECTL_U2SSINP3OK; 420 421 if (dwc->req_p1p2p3_quirk) 422 reg |= DWC3_GUSB3PIPECTL_REQP1P2P3; 423 424 if (dwc->del_p1p2p3_quirk) 425 reg |= DWC3_GUSB3PIPECTL_DEP1P2P3_EN; 426 427 if (dwc->del_phy_power_chg_quirk) 428 reg |= DWC3_GUSB3PIPECTL_DEPOCHANGE; 429 430 if (dwc->lfps_filter_quirk) 431 reg |= DWC3_GUSB3PIPECTL_LFPSFILT; 432 433 if (dwc->rx_detect_poll_quirk) 434 reg |= DWC3_GUSB3PIPECTL_RX_DETOPOLL; 435 436 if (dwc->tx_de_emphasis_quirk) 437 reg |= DWC3_GUSB3PIPECTL_TX_DEEPH(dwc->tx_de_emphasis); 438 439 if (dwc->dis_u3_susphy_quirk) 440 reg &= ~DWC3_GUSB3PIPECTL_SUSPHY; 441 442 dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg); 443 444 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0)); 445 446 /* Select the HS PHY interface */ 447 switch (DWC3_GHWPARAMS3_HSPHY_IFC(dwc->hwparams.hwparams3)) { 448 case DWC3_GHWPARAMS3_HSPHY_IFC_UTMI_ULPI: 449 if (dwc->hsphy_interface && 450 !strncmp(dwc->hsphy_interface, "utmi", 4)) { 451 reg &= ~DWC3_GUSB2PHYCFG_ULPI_UTMI; 452 break; 453 } else if (dwc->hsphy_interface && 454 !strncmp(dwc->hsphy_interface, "ulpi", 4)) { 455 reg |= DWC3_GUSB2PHYCFG_ULPI_UTMI; 456 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg); 457 } else { 458 dev_warn(dwc->dev, "HSPHY Interface not defined\n"); 459 460 /* Relying on default value. */ 461 if (!(reg & DWC3_GUSB2PHYCFG_ULPI_UTMI)) 462 break; 463 } 464 /* FALLTHROUGH */ 465 case DWC3_GHWPARAMS3_HSPHY_IFC_ULPI: 466 /* Making sure the interface and PHY are operational */ 467 ret = dwc3_soft_reset(dwc); 468 if (ret) 469 return ret; 470 471 udelay(1); 472 473 ret = dwc3_ulpi_init(dwc); 474 if (ret) 475 return ret; 476 /* FALLTHROUGH */ 477 default: 478 break; 479 } 480 481 /* 482 * Above 1.94a, it is recommended to set DWC3_GUSB2PHYCFG_SUSPHY to 483 * '0' during coreConsultant configuration. So default value will 484 * be '0' when the core is reset. Application needs to set it to 485 * '1' after the core initialization is completed. 486 */ 487 if (dwc->revision > DWC3_REVISION_194A) 488 reg |= DWC3_GUSB2PHYCFG_SUSPHY; 489 490 if (dwc->dis_u2_susphy_quirk) 491 reg &= ~DWC3_GUSB2PHYCFG_SUSPHY; 492 493 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg); 494 495 return 0; 496 } 497 498 /** 499 * dwc3_core_init - Low-level initialization of DWC3 Core 500 * @dwc: Pointer to our controller context structure 501 * 502 * Returns 0 on success otherwise negative errno. 503 */ 504 static int dwc3_core_init(struct dwc3 *dwc) 505 { 506 u32 hwparams4 = dwc->hwparams.hwparams4; 507 u32 reg; 508 int ret; 509 510 reg = dwc3_readl(dwc->regs, DWC3_GSNPSID); 511 /* This should read as U3 followed by revision number */ 512 if ((reg & DWC3_GSNPSID_MASK) != 0x55330000) { 513 dev_err(dwc->dev, "this is not a DesignWare USB3 DRD Core\n"); 514 ret = -ENODEV; 515 goto err0; 516 } 517 dwc->revision = reg; 518 519 /* 520 * Write Linux Version Code to our GUID register so it's easy to figure 521 * out which kernel version a bug was found. 522 */ 523 dwc3_writel(dwc->regs, DWC3_GUID, LINUX_VERSION_CODE); 524 525 /* Handle USB2.0-only core configuration */ 526 if (DWC3_GHWPARAMS3_SSPHY_IFC(dwc->hwparams.hwparams3) == 527 DWC3_GHWPARAMS3_SSPHY_IFC_DIS) { 528 if (dwc->maximum_speed == USB_SPEED_SUPER) 529 dwc->maximum_speed = USB_SPEED_HIGH; 530 } 531 532 /* issue device SoftReset too */ 533 ret = dwc3_soft_reset(dwc); 534 if (ret) 535 goto err0; 536 537 ret = dwc3_core_soft_reset(dwc); 538 if (ret) 539 goto err0; 540 541 reg = dwc3_readl(dwc->regs, DWC3_GCTL); 542 reg &= ~DWC3_GCTL_SCALEDOWN_MASK; 543 544 switch (DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1)) { 545 case DWC3_GHWPARAMS1_EN_PWROPT_CLK: 546 /** 547 * WORKAROUND: DWC3 revisions between 2.10a and 2.50a have an 548 * issue which would cause xHCI compliance tests to fail. 549 * 550 * Because of that we cannot enable clock gating on such 551 * configurations. 552 * 553 * Refers to: 554 * 555 * STAR#9000588375: Clock Gating, SOF Issues when ref_clk-Based 556 * SOF/ITP Mode Used 557 */ 558 if ((dwc->dr_mode == USB_DR_MODE_HOST || 559 dwc->dr_mode == USB_DR_MODE_OTG) && 560 (dwc->revision >= DWC3_REVISION_210A && 561 dwc->revision <= DWC3_REVISION_250A)) 562 reg |= DWC3_GCTL_DSBLCLKGTNG | DWC3_GCTL_SOFITPSYNC; 563 else 564 reg &= ~DWC3_GCTL_DSBLCLKGTNG; 565 break; 566 case DWC3_GHWPARAMS1_EN_PWROPT_HIB: 567 /* enable hibernation here */ 568 dwc->nr_scratch = DWC3_GHWPARAMS4_HIBER_SCRATCHBUFS(hwparams4); 569 570 /* 571 * REVISIT Enabling this bit so that host-mode hibernation 572 * will work. Device-mode hibernation is not yet implemented. 573 */ 574 reg |= DWC3_GCTL_GBLHIBERNATIONEN; 575 break; 576 default: 577 dev_dbg(dwc->dev, "No power optimization available\n"); 578 } 579 580 /* check if current dwc3 is on simulation board */ 581 if (dwc->hwparams.hwparams6 & DWC3_GHWPARAMS6_EN_FPGA) { 582 dev_dbg(dwc->dev, "it is on FPGA board\n"); 583 dwc->is_fpga = true; 584 } 585 586 WARN_ONCE(dwc->disable_scramble_quirk && !dwc->is_fpga, 587 "disable_scramble cannot be used on non-FPGA builds\n"); 588 589 if (dwc->disable_scramble_quirk && dwc->is_fpga) 590 reg |= DWC3_GCTL_DISSCRAMBLE; 591 else 592 reg &= ~DWC3_GCTL_DISSCRAMBLE; 593 594 if (dwc->u2exit_lfps_quirk) 595 reg |= DWC3_GCTL_U2EXIT_LFPS; 596 597 /* 598 * WORKAROUND: DWC3 revisions <1.90a have a bug 599 * where the device can fail to connect at SuperSpeed 600 * and falls back to high-speed mode which causes 601 * the device to enter a Connect/Disconnect loop 602 */ 603 if (dwc->revision < DWC3_REVISION_190A) 604 reg |= DWC3_GCTL_U2RSTECN; 605 606 dwc3_core_num_eps(dwc); 607 608 dwc3_writel(dwc->regs, DWC3_GCTL, reg); 609 610 ret = dwc3_alloc_scratch_buffers(dwc); 611 if (ret) 612 goto err1; 613 614 ret = dwc3_setup_scratch_buffers(dwc); 615 if (ret) 616 goto err2; 617 618 return 0; 619 620 err2: 621 dwc3_free_scratch_buffers(dwc); 622 623 err1: 624 usb_phy_shutdown(dwc->usb2_phy); 625 usb_phy_shutdown(dwc->usb3_phy); 626 phy_exit(dwc->usb2_generic_phy); 627 phy_exit(dwc->usb3_generic_phy); 628 629 err0: 630 return ret; 631 } 632 633 static void dwc3_core_exit(struct dwc3 *dwc) 634 { 635 dwc3_free_scratch_buffers(dwc); 636 usb_phy_shutdown(dwc->usb2_phy); 637 usb_phy_shutdown(dwc->usb3_phy); 638 phy_exit(dwc->usb2_generic_phy); 639 phy_exit(dwc->usb3_generic_phy); 640 } 641 642 static int dwc3_core_get_phy(struct dwc3 *dwc) 643 { 644 struct device *dev = dwc->dev; 645 struct device_node *node = dev->of_node; 646 int ret; 647 648 if (node) { 649 dwc->usb2_phy = devm_usb_get_phy_by_phandle(dev, "usb-phy", 0); 650 dwc->usb3_phy = devm_usb_get_phy_by_phandle(dev, "usb-phy", 1); 651 } else { 652 dwc->usb2_phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB2); 653 dwc->usb3_phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB3); 654 } 655 656 if (IS_ERR(dwc->usb2_phy)) { 657 ret = PTR_ERR(dwc->usb2_phy); 658 if (ret == -ENXIO || ret == -ENODEV) { 659 dwc->usb2_phy = NULL; 660 } else if (ret == -EPROBE_DEFER) { 661 return ret; 662 } else { 663 dev_err(dev, "no usb2 phy configured\n"); 664 return ret; 665 } 666 } 667 668 if (IS_ERR(dwc->usb3_phy)) { 669 ret = PTR_ERR(dwc->usb3_phy); 670 if (ret == -ENXIO || ret == -ENODEV) { 671 dwc->usb3_phy = NULL; 672 } else if (ret == -EPROBE_DEFER) { 673 return ret; 674 } else { 675 dev_err(dev, "no usb3 phy configured\n"); 676 return ret; 677 } 678 } 679 680 dwc->usb2_generic_phy = devm_phy_get(dev, "usb2-phy"); 681 if (IS_ERR(dwc->usb2_generic_phy)) { 682 ret = PTR_ERR(dwc->usb2_generic_phy); 683 if (ret == -ENOSYS || ret == -ENODEV) { 684 dwc->usb2_generic_phy = NULL; 685 } else if (ret == -EPROBE_DEFER) { 686 return ret; 687 } else { 688 dev_err(dev, "no usb2 phy configured\n"); 689 return ret; 690 } 691 } 692 693 dwc->usb3_generic_phy = devm_phy_get(dev, "usb3-phy"); 694 if (IS_ERR(dwc->usb3_generic_phy)) { 695 ret = PTR_ERR(dwc->usb3_generic_phy); 696 if (ret == -ENOSYS || ret == -ENODEV) { 697 dwc->usb3_generic_phy = NULL; 698 } else if (ret == -EPROBE_DEFER) { 699 return ret; 700 } else { 701 dev_err(dev, "no usb3 phy configured\n"); 702 return ret; 703 } 704 } 705 706 return 0; 707 } 708 709 static int dwc3_core_init_mode(struct dwc3 *dwc) 710 { 711 struct device *dev = dwc->dev; 712 int ret; 713 714 switch (dwc->dr_mode) { 715 case USB_DR_MODE_PERIPHERAL: 716 dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_DEVICE); 717 ret = dwc3_gadget_init(dwc); 718 if (ret) { 719 dev_err(dev, "failed to initialize gadget\n"); 720 return ret; 721 } 722 break; 723 case USB_DR_MODE_HOST: 724 dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_HOST); 725 ret = dwc3_host_init(dwc); 726 if (ret) { 727 dev_err(dev, "failed to initialize host\n"); 728 return ret; 729 } 730 break; 731 case USB_DR_MODE_OTG: 732 dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_OTG); 733 ret = dwc3_host_init(dwc); 734 if (ret) { 735 dev_err(dev, "failed to initialize host\n"); 736 return ret; 737 } 738 739 ret = dwc3_gadget_init(dwc); 740 if (ret) { 741 dev_err(dev, "failed to initialize gadget\n"); 742 return ret; 743 } 744 break; 745 default: 746 dev_err(dev, "Unsupported mode of operation %d\n", dwc->dr_mode); 747 return -EINVAL; 748 } 749 750 return 0; 751 } 752 753 static void dwc3_core_exit_mode(struct dwc3 *dwc) 754 { 755 switch (dwc->dr_mode) { 756 case USB_DR_MODE_PERIPHERAL: 757 dwc3_gadget_exit(dwc); 758 break; 759 case USB_DR_MODE_HOST: 760 dwc3_host_exit(dwc); 761 break; 762 case USB_DR_MODE_OTG: 763 dwc3_host_exit(dwc); 764 dwc3_gadget_exit(dwc); 765 break; 766 default: 767 /* do nothing */ 768 break; 769 } 770 } 771 772 #define DWC3_ALIGN_MASK (16 - 1) 773 774 static int dwc3_probe(struct platform_device *pdev) 775 { 776 struct device *dev = &pdev->dev; 777 struct dwc3_platform_data *pdata = dev_get_platdata(dev); 778 struct device_node *node = dev->of_node; 779 struct resource *res; 780 struct dwc3 *dwc; 781 u8 lpm_nyet_threshold; 782 u8 tx_de_emphasis; 783 u8 hird_threshold; 784 785 int ret; 786 787 void __iomem *regs; 788 void *mem; 789 790 mem = devm_kzalloc(dev, sizeof(*dwc) + DWC3_ALIGN_MASK, GFP_KERNEL); 791 if (!mem) 792 return -ENOMEM; 793 794 dwc = PTR_ALIGN(mem, DWC3_ALIGN_MASK + 1); 795 dwc->mem = mem; 796 dwc->dev = dev; 797 798 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); 799 if (!res) { 800 dev_err(dev, "missing IRQ\n"); 801 return -ENODEV; 802 } 803 dwc->xhci_resources[1].start = res->start; 804 dwc->xhci_resources[1].end = res->end; 805 dwc->xhci_resources[1].flags = res->flags; 806 dwc->xhci_resources[1].name = res->name; 807 808 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 809 if (!res) { 810 dev_err(dev, "missing memory resource\n"); 811 return -ENODEV; 812 } 813 814 dwc->xhci_resources[0].start = res->start; 815 dwc->xhci_resources[0].end = dwc->xhci_resources[0].start + 816 DWC3_XHCI_REGS_END; 817 dwc->xhci_resources[0].flags = res->flags; 818 dwc->xhci_resources[0].name = res->name; 819 820 res->start += DWC3_GLOBALS_REGS_START; 821 822 /* 823 * Request memory region but exclude xHCI regs, 824 * since it will be requested by the xhci-plat driver. 825 */ 826 regs = devm_ioremap_resource(dev, res); 827 if (IS_ERR(regs)) { 828 ret = PTR_ERR(regs); 829 goto err0; 830 } 831 832 dwc->regs = regs; 833 dwc->regs_size = resource_size(res); 834 835 /* default to highest possible threshold */ 836 lpm_nyet_threshold = 0xff; 837 838 /* default to -3.5dB de-emphasis */ 839 tx_de_emphasis = 1; 840 841 /* 842 * default to assert utmi_sleep_n and use maximum allowed HIRD 843 * threshold value of 0b1100 844 */ 845 hird_threshold = 12; 846 847 if (node) { 848 dwc->maximum_speed = of_usb_get_maximum_speed(node); 849 dwc->has_lpm_erratum = of_property_read_bool(node, 850 "snps,has-lpm-erratum"); 851 of_property_read_u8(node, "snps,lpm-nyet-threshold", 852 &lpm_nyet_threshold); 853 dwc->is_utmi_l1_suspend = of_property_read_bool(node, 854 "snps,is-utmi-l1-suspend"); 855 of_property_read_u8(node, "snps,hird-threshold", 856 &hird_threshold); 857 dwc->usb3_lpm_capable = of_property_read_bool(node, 858 "snps,usb3_lpm_capable"); 859 860 dwc->needs_fifo_resize = of_property_read_bool(node, 861 "tx-fifo-resize"); 862 dwc->dr_mode = of_usb_get_dr_mode(node); 863 864 dwc->disable_scramble_quirk = of_property_read_bool(node, 865 "snps,disable_scramble_quirk"); 866 dwc->u2exit_lfps_quirk = of_property_read_bool(node, 867 "snps,u2exit_lfps_quirk"); 868 dwc->u2ss_inp3_quirk = of_property_read_bool(node, 869 "snps,u2ss_inp3_quirk"); 870 dwc->req_p1p2p3_quirk = of_property_read_bool(node, 871 "snps,req_p1p2p3_quirk"); 872 dwc->del_p1p2p3_quirk = of_property_read_bool(node, 873 "snps,del_p1p2p3_quirk"); 874 dwc->del_phy_power_chg_quirk = of_property_read_bool(node, 875 "snps,del_phy_power_chg_quirk"); 876 dwc->lfps_filter_quirk = of_property_read_bool(node, 877 "snps,lfps_filter_quirk"); 878 dwc->rx_detect_poll_quirk = of_property_read_bool(node, 879 "snps,rx_detect_poll_quirk"); 880 dwc->dis_u3_susphy_quirk = of_property_read_bool(node, 881 "snps,dis_u3_susphy_quirk"); 882 dwc->dis_u2_susphy_quirk = of_property_read_bool(node, 883 "snps,dis_u2_susphy_quirk"); 884 885 dwc->tx_de_emphasis_quirk = of_property_read_bool(node, 886 "snps,tx_de_emphasis_quirk"); 887 of_property_read_u8(node, "snps,tx_de_emphasis", 888 &tx_de_emphasis); 889 of_property_read_string(node, "snps,hsphy_interface", 890 &dwc->hsphy_interface); 891 } else if (pdata) { 892 dwc->maximum_speed = pdata->maximum_speed; 893 dwc->has_lpm_erratum = pdata->has_lpm_erratum; 894 if (pdata->lpm_nyet_threshold) 895 lpm_nyet_threshold = pdata->lpm_nyet_threshold; 896 dwc->is_utmi_l1_suspend = pdata->is_utmi_l1_suspend; 897 if (pdata->hird_threshold) 898 hird_threshold = pdata->hird_threshold; 899 900 dwc->needs_fifo_resize = pdata->tx_fifo_resize; 901 dwc->usb3_lpm_capable = pdata->usb3_lpm_capable; 902 dwc->dr_mode = pdata->dr_mode; 903 904 dwc->disable_scramble_quirk = pdata->disable_scramble_quirk; 905 dwc->u2exit_lfps_quirk = pdata->u2exit_lfps_quirk; 906 dwc->u2ss_inp3_quirk = pdata->u2ss_inp3_quirk; 907 dwc->req_p1p2p3_quirk = pdata->req_p1p2p3_quirk; 908 dwc->del_p1p2p3_quirk = pdata->del_p1p2p3_quirk; 909 dwc->del_phy_power_chg_quirk = pdata->del_phy_power_chg_quirk; 910 dwc->lfps_filter_quirk = pdata->lfps_filter_quirk; 911 dwc->rx_detect_poll_quirk = pdata->rx_detect_poll_quirk; 912 dwc->dis_u3_susphy_quirk = pdata->dis_u3_susphy_quirk; 913 dwc->dis_u2_susphy_quirk = pdata->dis_u2_susphy_quirk; 914 915 dwc->tx_de_emphasis_quirk = pdata->tx_de_emphasis_quirk; 916 if (pdata->tx_de_emphasis) 917 tx_de_emphasis = pdata->tx_de_emphasis; 918 919 dwc->hsphy_interface = pdata->hsphy_interface; 920 } 921 922 /* default to superspeed if no maximum_speed passed */ 923 if (dwc->maximum_speed == USB_SPEED_UNKNOWN) 924 dwc->maximum_speed = USB_SPEED_SUPER; 925 926 dwc->lpm_nyet_threshold = lpm_nyet_threshold; 927 dwc->tx_de_emphasis = tx_de_emphasis; 928 929 dwc->hird_threshold = hird_threshold 930 | (dwc->is_utmi_l1_suspend << 4); 931 932 platform_set_drvdata(pdev, dwc); 933 dwc3_cache_hwparams(dwc); 934 935 ret = dwc3_phy_setup(dwc); 936 if (ret) 937 goto err0; 938 939 ret = dwc3_core_get_phy(dwc); 940 if (ret) 941 goto err0; 942 943 spin_lock_init(&dwc->lock); 944 945 if (!dev->dma_mask) { 946 dev->dma_mask = dev->parent->dma_mask; 947 dev->dma_parms = dev->parent->dma_parms; 948 dma_set_coherent_mask(dev, dev->parent->coherent_dma_mask); 949 } 950 951 pm_runtime_enable(dev); 952 pm_runtime_get_sync(dev); 953 pm_runtime_forbid(dev); 954 955 ret = dwc3_alloc_event_buffers(dwc, DWC3_EVENT_BUFFERS_SIZE); 956 if (ret) { 957 dev_err(dwc->dev, "failed to allocate event buffers\n"); 958 ret = -ENOMEM; 959 goto err1; 960 } 961 962 if (IS_ENABLED(CONFIG_USB_DWC3_HOST)) 963 dwc->dr_mode = USB_DR_MODE_HOST; 964 else if (IS_ENABLED(CONFIG_USB_DWC3_GADGET)) 965 dwc->dr_mode = USB_DR_MODE_PERIPHERAL; 966 967 if (dwc->dr_mode == USB_DR_MODE_UNKNOWN) 968 dwc->dr_mode = USB_DR_MODE_OTG; 969 970 ret = dwc3_core_init(dwc); 971 if (ret) { 972 dev_err(dev, "failed to initialize core\n"); 973 goto err1; 974 } 975 976 usb_phy_set_suspend(dwc->usb2_phy, 0); 977 usb_phy_set_suspend(dwc->usb3_phy, 0); 978 ret = phy_power_on(dwc->usb2_generic_phy); 979 if (ret < 0) 980 goto err2; 981 982 ret = phy_power_on(dwc->usb3_generic_phy); 983 if (ret < 0) 984 goto err3; 985 986 ret = dwc3_event_buffers_setup(dwc); 987 if (ret) { 988 dev_err(dwc->dev, "failed to setup event buffers\n"); 989 goto err4; 990 } 991 992 ret = dwc3_core_init_mode(dwc); 993 if (ret) 994 goto err5; 995 996 ret = dwc3_debugfs_init(dwc); 997 if (ret) { 998 dev_err(dev, "failed to initialize debugfs\n"); 999 goto err6; 1000 } 1001 1002 pm_runtime_allow(dev); 1003 1004 return 0; 1005 1006 err6: 1007 dwc3_core_exit_mode(dwc); 1008 1009 err5: 1010 dwc3_event_buffers_cleanup(dwc); 1011 1012 err4: 1013 phy_power_off(dwc->usb3_generic_phy); 1014 1015 err3: 1016 phy_power_off(dwc->usb2_generic_phy); 1017 1018 err2: 1019 usb_phy_set_suspend(dwc->usb2_phy, 1); 1020 usb_phy_set_suspend(dwc->usb3_phy, 1); 1021 dwc3_core_exit(dwc); 1022 1023 err1: 1024 dwc3_free_event_buffers(dwc); 1025 dwc3_ulpi_exit(dwc); 1026 1027 err0: 1028 /* 1029 * restore res->start back to its original value so that, in case the 1030 * probe is deferred, we don't end up getting error in request the 1031 * memory region the next time probe is called. 1032 */ 1033 res->start -= DWC3_GLOBALS_REGS_START; 1034 1035 return ret; 1036 } 1037 1038 static int dwc3_remove(struct platform_device *pdev) 1039 { 1040 struct dwc3 *dwc = platform_get_drvdata(pdev); 1041 struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1042 1043 /* 1044 * restore res->start back to its original value so that, in case the 1045 * probe is deferred, we don't end up getting error in request the 1046 * memory region the next time probe is called. 1047 */ 1048 res->start -= DWC3_GLOBALS_REGS_START; 1049 1050 dwc3_debugfs_exit(dwc); 1051 dwc3_core_exit_mode(dwc); 1052 dwc3_event_buffers_cleanup(dwc); 1053 dwc3_free_event_buffers(dwc); 1054 1055 usb_phy_set_suspend(dwc->usb2_phy, 1); 1056 usb_phy_set_suspend(dwc->usb3_phy, 1); 1057 phy_power_off(dwc->usb2_generic_phy); 1058 phy_power_off(dwc->usb3_generic_phy); 1059 1060 dwc3_core_exit(dwc); 1061 dwc3_ulpi_exit(dwc); 1062 1063 pm_runtime_put_sync(&pdev->dev); 1064 pm_runtime_disable(&pdev->dev); 1065 1066 return 0; 1067 } 1068 1069 #ifdef CONFIG_PM_SLEEP 1070 static int dwc3_suspend(struct device *dev) 1071 { 1072 struct dwc3 *dwc = dev_get_drvdata(dev); 1073 unsigned long flags; 1074 1075 spin_lock_irqsave(&dwc->lock, flags); 1076 1077 switch (dwc->dr_mode) { 1078 case USB_DR_MODE_PERIPHERAL: 1079 case USB_DR_MODE_OTG: 1080 dwc3_gadget_suspend(dwc); 1081 /* FALLTHROUGH */ 1082 case USB_DR_MODE_HOST: 1083 default: 1084 dwc3_event_buffers_cleanup(dwc); 1085 break; 1086 } 1087 1088 dwc->gctl = dwc3_readl(dwc->regs, DWC3_GCTL); 1089 spin_unlock_irqrestore(&dwc->lock, flags); 1090 1091 usb_phy_shutdown(dwc->usb3_phy); 1092 usb_phy_shutdown(dwc->usb2_phy); 1093 phy_exit(dwc->usb2_generic_phy); 1094 phy_exit(dwc->usb3_generic_phy); 1095 1096 return 0; 1097 } 1098 1099 static int dwc3_resume(struct device *dev) 1100 { 1101 struct dwc3 *dwc = dev_get_drvdata(dev); 1102 unsigned long flags; 1103 int ret; 1104 1105 usb_phy_init(dwc->usb3_phy); 1106 usb_phy_init(dwc->usb2_phy); 1107 ret = phy_init(dwc->usb2_generic_phy); 1108 if (ret < 0) 1109 return ret; 1110 1111 ret = phy_init(dwc->usb3_generic_phy); 1112 if (ret < 0) 1113 goto err_usb2phy_init; 1114 1115 spin_lock_irqsave(&dwc->lock, flags); 1116 1117 dwc3_event_buffers_setup(dwc); 1118 dwc3_writel(dwc->regs, DWC3_GCTL, dwc->gctl); 1119 1120 switch (dwc->dr_mode) { 1121 case USB_DR_MODE_PERIPHERAL: 1122 case USB_DR_MODE_OTG: 1123 dwc3_gadget_resume(dwc); 1124 /* FALLTHROUGH */ 1125 case USB_DR_MODE_HOST: 1126 default: 1127 /* do nothing */ 1128 break; 1129 } 1130 1131 spin_unlock_irqrestore(&dwc->lock, flags); 1132 1133 pm_runtime_disable(dev); 1134 pm_runtime_set_active(dev); 1135 pm_runtime_enable(dev); 1136 1137 return 0; 1138 1139 err_usb2phy_init: 1140 phy_exit(dwc->usb2_generic_phy); 1141 1142 return ret; 1143 } 1144 1145 static const struct dev_pm_ops dwc3_dev_pm_ops = { 1146 SET_SYSTEM_SLEEP_PM_OPS(dwc3_suspend, dwc3_resume) 1147 }; 1148 1149 #define DWC3_PM_OPS &(dwc3_dev_pm_ops) 1150 #else 1151 #define DWC3_PM_OPS NULL 1152 #endif 1153 1154 #ifdef CONFIG_OF 1155 static const struct of_device_id of_dwc3_match[] = { 1156 { 1157 .compatible = "snps,dwc3" 1158 }, 1159 { 1160 .compatible = "synopsys,dwc3" 1161 }, 1162 { }, 1163 }; 1164 MODULE_DEVICE_TABLE(of, of_dwc3_match); 1165 #endif 1166 1167 #ifdef CONFIG_ACPI 1168 1169 #define ACPI_ID_INTEL_BSW "808622B7" 1170 1171 static const struct acpi_device_id dwc3_acpi_match[] = { 1172 { ACPI_ID_INTEL_BSW, 0 }, 1173 { }, 1174 }; 1175 MODULE_DEVICE_TABLE(acpi, dwc3_acpi_match); 1176 #endif 1177 1178 static struct platform_driver dwc3_driver = { 1179 .probe = dwc3_probe, 1180 .remove = dwc3_remove, 1181 .driver = { 1182 .name = "dwc3", 1183 .of_match_table = of_match_ptr(of_dwc3_match), 1184 .acpi_match_table = ACPI_PTR(dwc3_acpi_match), 1185 .pm = DWC3_PM_OPS, 1186 }, 1187 }; 1188 1189 module_platform_driver(dwc3_driver); 1190 1191 MODULE_ALIAS("platform:dwc3"); 1192 MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>"); 1193 MODULE_LICENSE("GPL v2"); 1194 MODULE_DESCRIPTION("DesignWare USB3 DRD Controller Driver"); 1195