xref: /openbmc/linux/drivers/usb/dwc3/core.c (revision 95e9fd10)
1 /**
2  * core.c - DesignWare USB3 DRD Controller Core file
3  *
4  * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
5  *
6  * Authors: Felipe Balbi <balbi@ti.com>,
7  *	    Sebastian Andrzej Siewior <bigeasy@linutronix.de>
8  *
9  * Redistribution and use in source and binary forms, with or without
10  * modification, are permitted provided that the following conditions
11  * are met:
12  * 1. Redistributions of source code must retain the above copyright
13  *    notice, this list of conditions, and the following disclaimer,
14  *    without modification.
15  * 2. Redistributions in binary form must reproduce the above copyright
16  *    notice, this list of conditions and the following disclaimer in the
17  *    documentation and/or other materials provided with the distribution.
18  * 3. The names of the above-listed copyright holders may not be used
19  *    to endorse or promote products derived from this software without
20  *    specific prior written permission.
21  *
22  * ALTERNATIVELY, this software may be distributed under the terms of the
23  * GNU General Public License ("GPL") version 2, as published by the Free
24  * Software Foundation.
25  *
26  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
27  * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
28  * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
29  * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
30  * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
31  * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
32  * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
33  * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
34  * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
35  * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
36  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
37  */
38 
39 #include <linux/module.h>
40 #include <linux/kernel.h>
41 #include <linux/slab.h>
42 #include <linux/spinlock.h>
43 #include <linux/platform_device.h>
44 #include <linux/pm_runtime.h>
45 #include <linux/interrupt.h>
46 #include <linux/ioport.h>
47 #include <linux/io.h>
48 #include <linux/list.h>
49 #include <linux/delay.h>
50 #include <linux/dma-mapping.h>
51 #include <linux/of.h>
52 
53 #include <linux/usb/ch9.h>
54 #include <linux/usb/gadget.h>
55 
56 #include "core.h"
57 #include "gadget.h"
58 #include "io.h"
59 
60 #include "debug.h"
61 
62 static char *maximum_speed = "super";
63 module_param(maximum_speed, charp, 0);
64 MODULE_PARM_DESC(maximum_speed, "Maximum supported speed.");
65 
66 /* -------------------------------------------------------------------------- */
67 
68 #define DWC3_DEVS_POSSIBLE	32
69 
70 static DECLARE_BITMAP(dwc3_devs, DWC3_DEVS_POSSIBLE);
71 
72 int dwc3_get_device_id(void)
73 {
74 	int		id;
75 
76 again:
77 	id = find_first_zero_bit(dwc3_devs, DWC3_DEVS_POSSIBLE);
78 	if (id < DWC3_DEVS_POSSIBLE) {
79 		int old;
80 
81 		old = test_and_set_bit(id, dwc3_devs);
82 		if (old)
83 			goto again;
84 	} else {
85 		pr_err("dwc3: no space for new device\n");
86 		id = -ENOMEM;
87 	}
88 
89 	return id;
90 }
91 EXPORT_SYMBOL_GPL(dwc3_get_device_id);
92 
93 void dwc3_put_device_id(int id)
94 {
95 	int			ret;
96 
97 	if (id < 0)
98 		return;
99 
100 	ret = test_bit(id, dwc3_devs);
101 	WARN(!ret, "dwc3: ID %d not in use\n", id);
102 	clear_bit(id, dwc3_devs);
103 }
104 EXPORT_SYMBOL_GPL(dwc3_put_device_id);
105 
106 void dwc3_set_mode(struct dwc3 *dwc, u32 mode)
107 {
108 	u32 reg;
109 
110 	reg = dwc3_readl(dwc->regs, DWC3_GCTL);
111 	reg &= ~(DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_OTG));
112 	reg |= DWC3_GCTL_PRTCAPDIR(mode);
113 	dwc3_writel(dwc->regs, DWC3_GCTL, reg);
114 }
115 
116 /**
117  * dwc3_core_soft_reset - Issues core soft reset and PHY reset
118  * @dwc: pointer to our context structure
119  */
120 static void dwc3_core_soft_reset(struct dwc3 *dwc)
121 {
122 	u32		reg;
123 
124 	/* Before Resetting PHY, put Core in Reset */
125 	reg = dwc3_readl(dwc->regs, DWC3_GCTL);
126 	reg |= DWC3_GCTL_CORESOFTRESET;
127 	dwc3_writel(dwc->regs, DWC3_GCTL, reg);
128 
129 	/* Assert USB3 PHY reset */
130 	reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
131 	reg |= DWC3_GUSB3PIPECTL_PHYSOFTRST;
132 	dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
133 
134 	/* Assert USB2 PHY reset */
135 	reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
136 	reg |= DWC3_GUSB2PHYCFG_PHYSOFTRST;
137 	dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
138 
139 	mdelay(100);
140 
141 	/* Clear USB3 PHY reset */
142 	reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
143 	reg &= ~DWC3_GUSB3PIPECTL_PHYSOFTRST;
144 	dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
145 
146 	/* Clear USB2 PHY reset */
147 	reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
148 	reg &= ~DWC3_GUSB2PHYCFG_PHYSOFTRST;
149 	dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
150 
151 	mdelay(100);
152 
153 	/* After PHYs are stable we can take Core out of reset state */
154 	reg = dwc3_readl(dwc->regs, DWC3_GCTL);
155 	reg &= ~DWC3_GCTL_CORESOFTRESET;
156 	dwc3_writel(dwc->regs, DWC3_GCTL, reg);
157 }
158 
159 /**
160  * dwc3_free_one_event_buffer - Frees one event buffer
161  * @dwc: Pointer to our controller context structure
162  * @evt: Pointer to event buffer to be freed
163  */
164 static void dwc3_free_one_event_buffer(struct dwc3 *dwc,
165 		struct dwc3_event_buffer *evt)
166 {
167 	dma_free_coherent(dwc->dev, evt->length, evt->buf, evt->dma);
168 	kfree(evt);
169 }
170 
171 /**
172  * dwc3_alloc_one_event_buffer - Allocates one event buffer structure
173  * @dwc: Pointer to our controller context structure
174  * @length: size of the event buffer
175  *
176  * Returns a pointer to the allocated event buffer structure on success
177  * otherwise ERR_PTR(errno).
178  */
179 static struct dwc3_event_buffer *__devinit
180 dwc3_alloc_one_event_buffer(struct dwc3 *dwc, unsigned length)
181 {
182 	struct dwc3_event_buffer	*evt;
183 
184 	evt = kzalloc(sizeof(*evt), GFP_KERNEL);
185 	if (!evt)
186 		return ERR_PTR(-ENOMEM);
187 
188 	evt->dwc	= dwc;
189 	evt->length	= length;
190 	evt->buf	= dma_alloc_coherent(dwc->dev, length,
191 			&evt->dma, GFP_KERNEL);
192 	if (!evt->buf) {
193 		kfree(evt);
194 		return ERR_PTR(-ENOMEM);
195 	}
196 
197 	return evt;
198 }
199 
200 /**
201  * dwc3_free_event_buffers - frees all allocated event buffers
202  * @dwc: Pointer to our controller context structure
203  */
204 static void dwc3_free_event_buffers(struct dwc3 *dwc)
205 {
206 	struct dwc3_event_buffer	*evt;
207 	int i;
208 
209 	for (i = 0; i < dwc->num_event_buffers; i++) {
210 		evt = dwc->ev_buffs[i];
211 		if (evt)
212 			dwc3_free_one_event_buffer(dwc, evt);
213 	}
214 
215 	kfree(dwc->ev_buffs);
216 }
217 
218 /**
219  * dwc3_alloc_event_buffers - Allocates @num event buffers of size @length
220  * @dwc: pointer to our controller context structure
221  * @length: size of event buffer
222  *
223  * Returns 0 on success otherwise negative errno. In the error case, dwc
224  * may contain some buffers allocated but not all which were requested.
225  */
226 static int __devinit dwc3_alloc_event_buffers(struct dwc3 *dwc, unsigned length)
227 {
228 	int			num;
229 	int			i;
230 
231 	num = DWC3_NUM_INT(dwc->hwparams.hwparams1);
232 	dwc->num_event_buffers = num;
233 
234 	dwc->ev_buffs = kzalloc(sizeof(*dwc->ev_buffs) * num, GFP_KERNEL);
235 	if (!dwc->ev_buffs) {
236 		dev_err(dwc->dev, "can't allocate event buffers array\n");
237 		return -ENOMEM;
238 	}
239 
240 	for (i = 0; i < num; i++) {
241 		struct dwc3_event_buffer	*evt;
242 
243 		evt = dwc3_alloc_one_event_buffer(dwc, length);
244 		if (IS_ERR(evt)) {
245 			dev_err(dwc->dev, "can't allocate event buffer\n");
246 			return PTR_ERR(evt);
247 		}
248 		dwc->ev_buffs[i] = evt;
249 	}
250 
251 	return 0;
252 }
253 
254 /**
255  * dwc3_event_buffers_setup - setup our allocated event buffers
256  * @dwc: pointer to our controller context structure
257  *
258  * Returns 0 on success otherwise negative errno.
259  */
260 static int dwc3_event_buffers_setup(struct dwc3 *dwc)
261 {
262 	struct dwc3_event_buffer	*evt;
263 	int				n;
264 
265 	for (n = 0; n < dwc->num_event_buffers; n++) {
266 		evt = dwc->ev_buffs[n];
267 		dev_dbg(dwc->dev, "Event buf %p dma %08llx length %d\n",
268 				evt->buf, (unsigned long long) evt->dma,
269 				evt->length);
270 
271 		evt->lpos = 0;
272 
273 		dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(n),
274 				lower_32_bits(evt->dma));
275 		dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(n),
276 				upper_32_bits(evt->dma));
277 		dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(n),
278 				evt->length & 0xffff);
279 		dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(n), 0);
280 	}
281 
282 	return 0;
283 }
284 
285 static void dwc3_event_buffers_cleanup(struct dwc3 *dwc)
286 {
287 	struct dwc3_event_buffer	*evt;
288 	int				n;
289 
290 	for (n = 0; n < dwc->num_event_buffers; n++) {
291 		evt = dwc->ev_buffs[n];
292 
293 		evt->lpos = 0;
294 
295 		dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(n), 0);
296 		dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(n), 0);
297 		dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(n), 0);
298 		dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(n), 0);
299 	}
300 }
301 
302 static void __devinit dwc3_cache_hwparams(struct dwc3 *dwc)
303 {
304 	struct dwc3_hwparams	*parms = &dwc->hwparams;
305 
306 	parms->hwparams0 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS0);
307 	parms->hwparams1 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS1);
308 	parms->hwparams2 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS2);
309 	parms->hwparams3 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS3);
310 	parms->hwparams4 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS4);
311 	parms->hwparams5 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS5);
312 	parms->hwparams6 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS6);
313 	parms->hwparams7 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS7);
314 	parms->hwparams8 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS8);
315 }
316 
317 /**
318  * dwc3_core_init - Low-level initialization of DWC3 Core
319  * @dwc: Pointer to our controller context structure
320  *
321  * Returns 0 on success otherwise negative errno.
322  */
323 static int __devinit dwc3_core_init(struct dwc3 *dwc)
324 {
325 	unsigned long		timeout;
326 	u32			reg;
327 	int			ret;
328 
329 	reg = dwc3_readl(dwc->regs, DWC3_GSNPSID);
330 	/* This should read as U3 followed by revision number */
331 	if ((reg & DWC3_GSNPSID_MASK) != 0x55330000) {
332 		dev_err(dwc->dev, "this is not a DesignWare USB3 DRD Core\n");
333 		ret = -ENODEV;
334 		goto err0;
335 	}
336 	dwc->revision = reg;
337 
338 	/* issue device SoftReset too */
339 	timeout = jiffies + msecs_to_jiffies(500);
340 	dwc3_writel(dwc->regs, DWC3_DCTL, DWC3_DCTL_CSFTRST);
341 	do {
342 		reg = dwc3_readl(dwc->regs, DWC3_DCTL);
343 		if (!(reg & DWC3_DCTL_CSFTRST))
344 			break;
345 
346 		if (time_after(jiffies, timeout)) {
347 			dev_err(dwc->dev, "Reset Timed Out\n");
348 			ret = -ETIMEDOUT;
349 			goto err0;
350 		}
351 
352 		cpu_relax();
353 	} while (true);
354 
355 	dwc3_core_soft_reset(dwc);
356 
357 	dwc3_cache_hwparams(dwc);
358 
359 	reg = dwc3_readl(dwc->regs, DWC3_GCTL);
360 	reg &= ~DWC3_GCTL_SCALEDOWN_MASK;
361 	reg &= ~DWC3_GCTL_DISSCRAMBLE;
362 
363 	switch (DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1)) {
364 	case DWC3_GHWPARAMS1_EN_PWROPT_CLK:
365 		reg &= ~DWC3_GCTL_DSBLCLKGTNG;
366 		break;
367 	default:
368 		dev_dbg(dwc->dev, "No power optimization available\n");
369 	}
370 
371 	/*
372 	 * WORKAROUND: DWC3 revisions <1.90a have a bug
373 	 * where the device can fail to connect at SuperSpeed
374 	 * and falls back to high-speed mode which causes
375 	 * the device to enter a Connect/Disconnect loop
376 	 */
377 	if (dwc->revision < DWC3_REVISION_190A)
378 		reg |= DWC3_GCTL_U2RSTECN;
379 
380 	dwc3_writel(dwc->regs, DWC3_GCTL, reg);
381 
382 	ret = dwc3_alloc_event_buffers(dwc, DWC3_EVENT_BUFFERS_SIZE);
383 	if (ret) {
384 		dev_err(dwc->dev, "failed to allocate event buffers\n");
385 		ret = -ENOMEM;
386 		goto err1;
387 	}
388 
389 	ret = dwc3_event_buffers_setup(dwc);
390 	if (ret) {
391 		dev_err(dwc->dev, "failed to setup event buffers\n");
392 		goto err1;
393 	}
394 
395 	return 0;
396 
397 err1:
398 	dwc3_free_event_buffers(dwc);
399 
400 err0:
401 	return ret;
402 }
403 
404 static void dwc3_core_exit(struct dwc3 *dwc)
405 {
406 	dwc3_event_buffers_cleanup(dwc);
407 	dwc3_free_event_buffers(dwc);
408 }
409 
410 #define DWC3_ALIGN_MASK		(16 - 1)
411 
412 static int __devinit dwc3_probe(struct platform_device *pdev)
413 {
414 	struct device_node	*node = pdev->dev.of_node;
415 	struct resource		*res;
416 	struct dwc3		*dwc;
417 	struct device		*dev = &pdev->dev;
418 
419 	int			ret = -ENOMEM;
420 
421 	void __iomem		*regs;
422 	void			*mem;
423 
424 	u8			mode;
425 
426 	mem = devm_kzalloc(dev, sizeof(*dwc) + DWC3_ALIGN_MASK, GFP_KERNEL);
427 	if (!mem) {
428 		dev_err(dev, "not enough memory\n");
429 		return -ENOMEM;
430 	}
431 	dwc = PTR_ALIGN(mem, DWC3_ALIGN_MASK + 1);
432 	dwc->mem = mem;
433 
434 	res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
435 	if (!res) {
436 		dev_err(dev, "missing IRQ\n");
437 		return -ENODEV;
438 	}
439 	dwc->xhci_resources[1] = *res;
440 
441 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
442 	if (!res) {
443 		dev_err(dev, "missing memory resource\n");
444 		return -ENODEV;
445 	}
446 	dwc->xhci_resources[0] = *res;
447 	dwc->xhci_resources[0].end = dwc->xhci_resources[0].start +
448 					DWC3_XHCI_REGS_END;
449 
450 	 /*
451 	  * Request memory region but exclude xHCI regs,
452 	  * since it will be requested by the xhci-plat driver.
453 	  */
454 	res = devm_request_mem_region(dev, res->start + DWC3_GLOBALS_REGS_START,
455 			resource_size(res) - DWC3_GLOBALS_REGS_START,
456 			dev_name(dev));
457 	if (!res) {
458 		dev_err(dev, "can't request mem region\n");
459 		return -ENOMEM;
460 	}
461 
462 	regs = devm_ioremap(dev, res->start, resource_size(res));
463 	if (!regs) {
464 		dev_err(dev, "ioremap failed\n");
465 		return -ENOMEM;
466 	}
467 
468 	spin_lock_init(&dwc->lock);
469 	platform_set_drvdata(pdev, dwc);
470 
471 	dwc->regs	= regs;
472 	dwc->regs_size	= resource_size(res);
473 	dwc->dev	= dev;
474 
475 	if (!strncmp("super", maximum_speed, 5))
476 		dwc->maximum_speed = DWC3_DCFG_SUPERSPEED;
477 	else if (!strncmp("high", maximum_speed, 4))
478 		dwc->maximum_speed = DWC3_DCFG_HIGHSPEED;
479 	else if (!strncmp("full", maximum_speed, 4))
480 		dwc->maximum_speed = DWC3_DCFG_FULLSPEED1;
481 	else if (!strncmp("low", maximum_speed, 3))
482 		dwc->maximum_speed = DWC3_DCFG_LOWSPEED;
483 	else
484 		dwc->maximum_speed = DWC3_DCFG_SUPERSPEED;
485 
486 	if (of_get_property(node, "tx-fifo-resize", NULL))
487 		dwc->needs_fifo_resize = true;
488 
489 	pm_runtime_enable(dev);
490 	pm_runtime_get_sync(dev);
491 	pm_runtime_forbid(dev);
492 
493 	ret = dwc3_core_init(dwc);
494 	if (ret) {
495 		dev_err(dev, "failed to initialize core\n");
496 		return ret;
497 	}
498 
499 	mode = DWC3_MODE(dwc->hwparams.hwparams0);
500 
501 	switch (mode) {
502 	case DWC3_MODE_DEVICE:
503 		dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_DEVICE);
504 		ret = dwc3_gadget_init(dwc);
505 		if (ret) {
506 			dev_err(dev, "failed to initialize gadget\n");
507 			goto err1;
508 		}
509 		break;
510 	case DWC3_MODE_HOST:
511 		dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_HOST);
512 		ret = dwc3_host_init(dwc);
513 		if (ret) {
514 			dev_err(dev, "failed to initialize host\n");
515 			goto err1;
516 		}
517 		break;
518 	case DWC3_MODE_DRD:
519 		dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_OTG);
520 		ret = dwc3_host_init(dwc);
521 		if (ret) {
522 			dev_err(dev, "failed to initialize host\n");
523 			goto err1;
524 		}
525 
526 		ret = dwc3_gadget_init(dwc);
527 		if (ret) {
528 			dev_err(dev, "failed to initialize gadget\n");
529 			goto err1;
530 		}
531 		break;
532 	default:
533 		dev_err(dev, "Unsupported mode of operation %d\n", mode);
534 		goto err1;
535 	}
536 	dwc->mode = mode;
537 
538 	ret = dwc3_debugfs_init(dwc);
539 	if (ret) {
540 		dev_err(dev, "failed to initialize debugfs\n");
541 		goto err2;
542 	}
543 
544 	pm_runtime_allow(dev);
545 
546 	return 0;
547 
548 err2:
549 	switch (mode) {
550 	case DWC3_MODE_DEVICE:
551 		dwc3_gadget_exit(dwc);
552 		break;
553 	case DWC3_MODE_HOST:
554 		dwc3_host_exit(dwc);
555 		break;
556 	case DWC3_MODE_DRD:
557 		dwc3_host_exit(dwc);
558 		dwc3_gadget_exit(dwc);
559 		break;
560 	default:
561 		/* do nothing */
562 		break;
563 	}
564 
565 err1:
566 	dwc3_core_exit(dwc);
567 
568 	return ret;
569 }
570 
571 static int __devexit dwc3_remove(struct platform_device *pdev)
572 {
573 	struct dwc3	*dwc = platform_get_drvdata(pdev);
574 	struct resource	*res;
575 
576 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
577 
578 	pm_runtime_put(&pdev->dev);
579 	pm_runtime_disable(&pdev->dev);
580 
581 	dwc3_debugfs_exit(dwc);
582 
583 	switch (dwc->mode) {
584 	case DWC3_MODE_DEVICE:
585 		dwc3_gadget_exit(dwc);
586 		break;
587 	case DWC3_MODE_HOST:
588 		dwc3_host_exit(dwc);
589 		break;
590 	case DWC3_MODE_DRD:
591 		dwc3_host_exit(dwc);
592 		dwc3_gadget_exit(dwc);
593 		break;
594 	default:
595 		/* do nothing */
596 		break;
597 	}
598 
599 	dwc3_core_exit(dwc);
600 
601 	return 0;
602 }
603 
604 static struct platform_driver dwc3_driver = {
605 	.probe		= dwc3_probe,
606 	.remove		= __devexit_p(dwc3_remove),
607 	.driver		= {
608 		.name	= "dwc3",
609 	},
610 };
611 
612 module_platform_driver(dwc3_driver);
613 
614 MODULE_ALIAS("platform:dwc3");
615 MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>");
616 MODULE_LICENSE("Dual BSD/GPL");
617 MODULE_DESCRIPTION("DesignWare USB3 DRD Controller Driver");
618