1 // SPDX-License-Identifier: GPL-2.0 2 /** 3 * core.c - DesignWare USB3 DRD Controller Core file 4 * 5 * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com 6 * 7 * Authors: Felipe Balbi <balbi@ti.com>, 8 * Sebastian Andrzej Siewior <bigeasy@linutronix.de> 9 */ 10 11 #include <linux/version.h> 12 #include <linux/module.h> 13 #include <linux/kernel.h> 14 #include <linux/slab.h> 15 #include <linux/spinlock.h> 16 #include <linux/platform_device.h> 17 #include <linux/pm_runtime.h> 18 #include <linux/interrupt.h> 19 #include <linux/ioport.h> 20 #include <linux/io.h> 21 #include <linux/list.h> 22 #include <linux/delay.h> 23 #include <linux/dma-mapping.h> 24 #include <linux/of.h> 25 #include <linux/acpi.h> 26 #include <linux/pinctrl/consumer.h> 27 28 #include <linux/usb/ch9.h> 29 #include <linux/usb/gadget.h> 30 #include <linux/usb/of.h> 31 #include <linux/usb/otg.h> 32 33 #include "core.h" 34 #include "gadget.h" 35 #include "io.h" 36 37 #include "debug.h" 38 39 #define DWC3_DEFAULT_AUTOSUSPEND_DELAY 5000 /* ms */ 40 41 /** 42 * dwc3_get_dr_mode - Validates and sets dr_mode 43 * @dwc: pointer to our context structure 44 */ 45 static int dwc3_get_dr_mode(struct dwc3 *dwc) 46 { 47 enum usb_dr_mode mode; 48 struct device *dev = dwc->dev; 49 unsigned int hw_mode; 50 51 if (dwc->dr_mode == USB_DR_MODE_UNKNOWN) 52 dwc->dr_mode = USB_DR_MODE_OTG; 53 54 mode = dwc->dr_mode; 55 hw_mode = DWC3_GHWPARAMS0_MODE(dwc->hwparams.hwparams0); 56 57 switch (hw_mode) { 58 case DWC3_GHWPARAMS0_MODE_GADGET: 59 if (IS_ENABLED(CONFIG_USB_DWC3_HOST)) { 60 dev_err(dev, 61 "Controller does not support host mode.\n"); 62 return -EINVAL; 63 } 64 mode = USB_DR_MODE_PERIPHERAL; 65 break; 66 case DWC3_GHWPARAMS0_MODE_HOST: 67 if (IS_ENABLED(CONFIG_USB_DWC3_GADGET)) { 68 dev_err(dev, 69 "Controller does not support device mode.\n"); 70 return -EINVAL; 71 } 72 mode = USB_DR_MODE_HOST; 73 break; 74 default: 75 if (IS_ENABLED(CONFIG_USB_DWC3_HOST)) 76 mode = USB_DR_MODE_HOST; 77 else if (IS_ENABLED(CONFIG_USB_DWC3_GADGET)) 78 mode = USB_DR_MODE_PERIPHERAL; 79 } 80 81 if (mode != dwc->dr_mode) { 82 dev_warn(dev, 83 "Configuration mismatch. dr_mode forced to %s\n", 84 mode == USB_DR_MODE_HOST ? "host" : "gadget"); 85 86 dwc->dr_mode = mode; 87 } 88 89 return 0; 90 } 91 92 static void dwc3_event_buffers_cleanup(struct dwc3 *dwc); 93 static int dwc3_event_buffers_setup(struct dwc3 *dwc); 94 95 static void dwc3_set_prtcap(struct dwc3 *dwc, u32 mode) 96 { 97 u32 reg; 98 99 reg = dwc3_readl(dwc->regs, DWC3_GCTL); 100 reg &= ~(DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_OTG)); 101 reg |= DWC3_GCTL_PRTCAPDIR(mode); 102 dwc3_writel(dwc->regs, DWC3_GCTL, reg); 103 104 dwc->current_dr_role = mode; 105 } 106 107 static void __dwc3_set_mode(struct work_struct *work) 108 { 109 struct dwc3 *dwc = work_to_dwc(work); 110 unsigned long flags; 111 int ret; 112 113 if (!dwc->desired_dr_role) 114 return; 115 116 if (dwc->desired_dr_role == dwc->current_dr_role) 117 return; 118 119 if (dwc->dr_mode != USB_DR_MODE_OTG) 120 return; 121 122 switch (dwc->current_dr_role) { 123 case DWC3_GCTL_PRTCAP_HOST: 124 dwc3_host_exit(dwc); 125 break; 126 case DWC3_GCTL_PRTCAP_DEVICE: 127 dwc3_gadget_exit(dwc); 128 dwc3_event_buffers_cleanup(dwc); 129 break; 130 default: 131 break; 132 } 133 134 spin_lock_irqsave(&dwc->lock, flags); 135 136 dwc3_set_prtcap(dwc, dwc->desired_dr_role); 137 138 spin_unlock_irqrestore(&dwc->lock, flags); 139 140 switch (dwc->desired_dr_role) { 141 case DWC3_GCTL_PRTCAP_HOST: 142 ret = dwc3_host_init(dwc); 143 if (ret) { 144 dev_err(dwc->dev, "failed to initialize host\n"); 145 } else { 146 if (dwc->usb2_phy) 147 otg_set_vbus(dwc->usb2_phy->otg, true); 148 phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_HOST); 149 phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_HOST); 150 phy_calibrate(dwc->usb2_generic_phy); 151 } 152 break; 153 case DWC3_GCTL_PRTCAP_DEVICE: 154 dwc3_event_buffers_setup(dwc); 155 156 if (dwc->usb2_phy) 157 otg_set_vbus(dwc->usb2_phy->otg, false); 158 phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_DEVICE); 159 phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_DEVICE); 160 161 ret = dwc3_gadget_init(dwc); 162 if (ret) 163 dev_err(dwc->dev, "failed to initialize peripheral\n"); 164 break; 165 default: 166 break; 167 } 168 } 169 170 void dwc3_set_mode(struct dwc3 *dwc, u32 mode) 171 { 172 unsigned long flags; 173 174 spin_lock_irqsave(&dwc->lock, flags); 175 dwc->desired_dr_role = mode; 176 spin_unlock_irqrestore(&dwc->lock, flags); 177 178 queue_work(system_power_efficient_wq, &dwc->drd_work); 179 } 180 181 u32 dwc3_core_fifo_space(struct dwc3_ep *dep, u8 type) 182 { 183 struct dwc3 *dwc = dep->dwc; 184 u32 reg; 185 186 dwc3_writel(dwc->regs, DWC3_GDBGFIFOSPACE, 187 DWC3_GDBGFIFOSPACE_NUM(dep->number) | 188 DWC3_GDBGFIFOSPACE_TYPE(type)); 189 190 reg = dwc3_readl(dwc->regs, DWC3_GDBGFIFOSPACE); 191 192 return DWC3_GDBGFIFOSPACE_SPACE_AVAILABLE(reg); 193 } 194 195 /** 196 * dwc3_core_soft_reset - Issues core soft reset and PHY reset 197 * @dwc: pointer to our context structure 198 */ 199 static int dwc3_core_soft_reset(struct dwc3 *dwc) 200 { 201 u32 reg; 202 int retries = 1000; 203 int ret; 204 205 usb_phy_init(dwc->usb2_phy); 206 usb_phy_init(dwc->usb3_phy); 207 ret = phy_init(dwc->usb2_generic_phy); 208 if (ret < 0) 209 return ret; 210 211 ret = phy_init(dwc->usb3_generic_phy); 212 if (ret < 0) { 213 phy_exit(dwc->usb2_generic_phy); 214 return ret; 215 } 216 217 /* 218 * We're resetting only the device side because, if we're in host mode, 219 * XHCI driver will reset the host block. If dwc3 was configured for 220 * host-only mode, then we can return early. 221 */ 222 if (dwc->current_dr_role == DWC3_GCTL_PRTCAP_HOST) 223 return 0; 224 225 reg = dwc3_readl(dwc->regs, DWC3_DCTL); 226 reg |= DWC3_DCTL_CSFTRST; 227 dwc3_writel(dwc->regs, DWC3_DCTL, reg); 228 229 do { 230 reg = dwc3_readl(dwc->regs, DWC3_DCTL); 231 if (!(reg & DWC3_DCTL_CSFTRST)) 232 return 0; 233 234 udelay(1); 235 } while (--retries); 236 237 phy_exit(dwc->usb3_generic_phy); 238 phy_exit(dwc->usb2_generic_phy); 239 240 return -ETIMEDOUT; 241 } 242 243 /* 244 * dwc3_frame_length_adjustment - Adjusts frame length if required 245 * @dwc3: Pointer to our controller context structure 246 */ 247 static void dwc3_frame_length_adjustment(struct dwc3 *dwc) 248 { 249 u32 reg; 250 u32 dft; 251 252 if (dwc->revision < DWC3_REVISION_250A) 253 return; 254 255 if (dwc->fladj == 0) 256 return; 257 258 reg = dwc3_readl(dwc->regs, DWC3_GFLADJ); 259 dft = reg & DWC3_GFLADJ_30MHZ_MASK; 260 if (!dev_WARN_ONCE(dwc->dev, dft == dwc->fladj, 261 "request value same as default, ignoring\n")) { 262 reg &= ~DWC3_GFLADJ_30MHZ_MASK; 263 reg |= DWC3_GFLADJ_30MHZ_SDBND_SEL | dwc->fladj; 264 dwc3_writel(dwc->regs, DWC3_GFLADJ, reg); 265 } 266 } 267 268 /** 269 * dwc3_free_one_event_buffer - Frees one event buffer 270 * @dwc: Pointer to our controller context structure 271 * @evt: Pointer to event buffer to be freed 272 */ 273 static void dwc3_free_one_event_buffer(struct dwc3 *dwc, 274 struct dwc3_event_buffer *evt) 275 { 276 dma_free_coherent(dwc->sysdev, evt->length, evt->buf, evt->dma); 277 } 278 279 /** 280 * dwc3_alloc_one_event_buffer - Allocates one event buffer structure 281 * @dwc: Pointer to our controller context structure 282 * @length: size of the event buffer 283 * 284 * Returns a pointer to the allocated event buffer structure on success 285 * otherwise ERR_PTR(errno). 286 */ 287 static struct dwc3_event_buffer *dwc3_alloc_one_event_buffer(struct dwc3 *dwc, 288 unsigned length) 289 { 290 struct dwc3_event_buffer *evt; 291 292 evt = devm_kzalloc(dwc->dev, sizeof(*evt), GFP_KERNEL); 293 if (!evt) 294 return ERR_PTR(-ENOMEM); 295 296 evt->dwc = dwc; 297 evt->length = length; 298 evt->cache = devm_kzalloc(dwc->dev, length, GFP_KERNEL); 299 if (!evt->cache) 300 return ERR_PTR(-ENOMEM); 301 302 evt->buf = dma_alloc_coherent(dwc->sysdev, length, 303 &evt->dma, GFP_KERNEL); 304 if (!evt->buf) 305 return ERR_PTR(-ENOMEM); 306 307 return evt; 308 } 309 310 /** 311 * dwc3_free_event_buffers - frees all allocated event buffers 312 * @dwc: Pointer to our controller context structure 313 */ 314 static void dwc3_free_event_buffers(struct dwc3 *dwc) 315 { 316 struct dwc3_event_buffer *evt; 317 318 evt = dwc->ev_buf; 319 if (evt) 320 dwc3_free_one_event_buffer(dwc, evt); 321 } 322 323 /** 324 * dwc3_alloc_event_buffers - Allocates @num event buffers of size @length 325 * @dwc: pointer to our controller context structure 326 * @length: size of event buffer 327 * 328 * Returns 0 on success otherwise negative errno. In the error case, dwc 329 * may contain some buffers allocated but not all which were requested. 330 */ 331 static int dwc3_alloc_event_buffers(struct dwc3 *dwc, unsigned length) 332 { 333 struct dwc3_event_buffer *evt; 334 335 evt = dwc3_alloc_one_event_buffer(dwc, length); 336 if (IS_ERR(evt)) { 337 dev_err(dwc->dev, "can't allocate event buffer\n"); 338 return PTR_ERR(evt); 339 } 340 dwc->ev_buf = evt; 341 342 return 0; 343 } 344 345 /** 346 * dwc3_event_buffers_setup - setup our allocated event buffers 347 * @dwc: pointer to our controller context structure 348 * 349 * Returns 0 on success otherwise negative errno. 350 */ 351 static int dwc3_event_buffers_setup(struct dwc3 *dwc) 352 { 353 struct dwc3_event_buffer *evt; 354 355 evt = dwc->ev_buf; 356 evt->lpos = 0; 357 dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(0), 358 lower_32_bits(evt->dma)); 359 dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(0), 360 upper_32_bits(evt->dma)); 361 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0), 362 DWC3_GEVNTSIZ_SIZE(evt->length)); 363 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), 0); 364 365 return 0; 366 } 367 368 static void dwc3_event_buffers_cleanup(struct dwc3 *dwc) 369 { 370 struct dwc3_event_buffer *evt; 371 372 evt = dwc->ev_buf; 373 374 evt->lpos = 0; 375 376 dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(0), 0); 377 dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(0), 0); 378 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0), DWC3_GEVNTSIZ_INTMASK 379 | DWC3_GEVNTSIZ_SIZE(0)); 380 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), 0); 381 } 382 383 static int dwc3_alloc_scratch_buffers(struct dwc3 *dwc) 384 { 385 if (!dwc->has_hibernation) 386 return 0; 387 388 if (!dwc->nr_scratch) 389 return 0; 390 391 dwc->scratchbuf = kmalloc_array(dwc->nr_scratch, 392 DWC3_SCRATCHBUF_SIZE, GFP_KERNEL); 393 if (!dwc->scratchbuf) 394 return -ENOMEM; 395 396 return 0; 397 } 398 399 static int dwc3_setup_scratch_buffers(struct dwc3 *dwc) 400 { 401 dma_addr_t scratch_addr; 402 u32 param; 403 int ret; 404 405 if (!dwc->has_hibernation) 406 return 0; 407 408 if (!dwc->nr_scratch) 409 return 0; 410 411 /* should never fall here */ 412 if (!WARN_ON(dwc->scratchbuf)) 413 return 0; 414 415 scratch_addr = dma_map_single(dwc->sysdev, dwc->scratchbuf, 416 dwc->nr_scratch * DWC3_SCRATCHBUF_SIZE, 417 DMA_BIDIRECTIONAL); 418 if (dma_mapping_error(dwc->sysdev, scratch_addr)) { 419 dev_err(dwc->sysdev, "failed to map scratch buffer\n"); 420 ret = -EFAULT; 421 goto err0; 422 } 423 424 dwc->scratch_addr = scratch_addr; 425 426 param = lower_32_bits(scratch_addr); 427 428 ret = dwc3_send_gadget_generic_command(dwc, 429 DWC3_DGCMD_SET_SCRATCHPAD_ADDR_LO, param); 430 if (ret < 0) 431 goto err1; 432 433 param = upper_32_bits(scratch_addr); 434 435 ret = dwc3_send_gadget_generic_command(dwc, 436 DWC3_DGCMD_SET_SCRATCHPAD_ADDR_HI, param); 437 if (ret < 0) 438 goto err1; 439 440 return 0; 441 442 err1: 443 dma_unmap_single(dwc->sysdev, dwc->scratch_addr, dwc->nr_scratch * 444 DWC3_SCRATCHBUF_SIZE, DMA_BIDIRECTIONAL); 445 446 err0: 447 return ret; 448 } 449 450 static void dwc3_free_scratch_buffers(struct dwc3 *dwc) 451 { 452 if (!dwc->has_hibernation) 453 return; 454 455 if (!dwc->nr_scratch) 456 return; 457 458 /* should never fall here */ 459 if (!WARN_ON(dwc->scratchbuf)) 460 return; 461 462 dma_unmap_single(dwc->sysdev, dwc->scratch_addr, dwc->nr_scratch * 463 DWC3_SCRATCHBUF_SIZE, DMA_BIDIRECTIONAL); 464 kfree(dwc->scratchbuf); 465 } 466 467 static void dwc3_core_num_eps(struct dwc3 *dwc) 468 { 469 struct dwc3_hwparams *parms = &dwc->hwparams; 470 471 dwc->num_eps = DWC3_NUM_EPS(parms); 472 } 473 474 static void dwc3_cache_hwparams(struct dwc3 *dwc) 475 { 476 struct dwc3_hwparams *parms = &dwc->hwparams; 477 478 parms->hwparams0 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS0); 479 parms->hwparams1 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS1); 480 parms->hwparams2 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS2); 481 parms->hwparams3 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS3); 482 parms->hwparams4 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS4); 483 parms->hwparams5 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS5); 484 parms->hwparams6 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS6); 485 parms->hwparams7 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS7); 486 parms->hwparams8 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS8); 487 } 488 489 static int dwc3_core_ulpi_init(struct dwc3 *dwc) 490 { 491 int intf; 492 int ret = 0; 493 494 intf = DWC3_GHWPARAMS3_HSPHY_IFC(dwc->hwparams.hwparams3); 495 496 if (intf == DWC3_GHWPARAMS3_HSPHY_IFC_ULPI || 497 (intf == DWC3_GHWPARAMS3_HSPHY_IFC_UTMI_ULPI && 498 dwc->hsphy_interface && 499 !strncmp(dwc->hsphy_interface, "ulpi", 4))) 500 ret = dwc3_ulpi_init(dwc); 501 502 return ret; 503 } 504 505 /** 506 * dwc3_phy_setup - Configure USB PHY Interface of DWC3 Core 507 * @dwc: Pointer to our controller context structure 508 * 509 * Returns 0 on success. The USB PHY interfaces are configured but not 510 * initialized. The PHY interfaces and the PHYs get initialized together with 511 * the core in dwc3_core_init. 512 */ 513 static int dwc3_phy_setup(struct dwc3 *dwc) 514 { 515 u32 reg; 516 517 reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0)); 518 519 /* 520 * Make sure UX_EXIT_PX is cleared as that causes issues with some 521 * PHYs. Also, this bit is not supposed to be used in normal operation. 522 */ 523 reg &= ~DWC3_GUSB3PIPECTL_UX_EXIT_PX; 524 525 /* 526 * Above 1.94a, it is recommended to set DWC3_GUSB3PIPECTL_SUSPHY 527 * to '0' during coreConsultant configuration. So default value 528 * will be '0' when the core is reset. Application needs to set it 529 * to '1' after the core initialization is completed. 530 */ 531 if (dwc->revision > DWC3_REVISION_194A) 532 reg |= DWC3_GUSB3PIPECTL_SUSPHY; 533 534 if (dwc->u2ss_inp3_quirk) 535 reg |= DWC3_GUSB3PIPECTL_U2SSINP3OK; 536 537 if (dwc->dis_rxdet_inp3_quirk) 538 reg |= DWC3_GUSB3PIPECTL_DISRXDETINP3; 539 540 if (dwc->req_p1p2p3_quirk) 541 reg |= DWC3_GUSB3PIPECTL_REQP1P2P3; 542 543 if (dwc->del_p1p2p3_quirk) 544 reg |= DWC3_GUSB3PIPECTL_DEP1P2P3_EN; 545 546 if (dwc->del_phy_power_chg_quirk) 547 reg |= DWC3_GUSB3PIPECTL_DEPOCHANGE; 548 549 if (dwc->lfps_filter_quirk) 550 reg |= DWC3_GUSB3PIPECTL_LFPSFILT; 551 552 if (dwc->rx_detect_poll_quirk) 553 reg |= DWC3_GUSB3PIPECTL_RX_DETOPOLL; 554 555 if (dwc->tx_de_emphasis_quirk) 556 reg |= DWC3_GUSB3PIPECTL_TX_DEEPH(dwc->tx_de_emphasis); 557 558 if (dwc->dis_u3_susphy_quirk) 559 reg &= ~DWC3_GUSB3PIPECTL_SUSPHY; 560 561 if (dwc->dis_del_phy_power_chg_quirk) 562 reg &= ~DWC3_GUSB3PIPECTL_DEPOCHANGE; 563 564 dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg); 565 566 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0)); 567 568 /* Select the HS PHY interface */ 569 switch (DWC3_GHWPARAMS3_HSPHY_IFC(dwc->hwparams.hwparams3)) { 570 case DWC3_GHWPARAMS3_HSPHY_IFC_UTMI_ULPI: 571 if (dwc->hsphy_interface && 572 !strncmp(dwc->hsphy_interface, "utmi", 4)) { 573 reg &= ~DWC3_GUSB2PHYCFG_ULPI_UTMI; 574 break; 575 } else if (dwc->hsphy_interface && 576 !strncmp(dwc->hsphy_interface, "ulpi", 4)) { 577 reg |= DWC3_GUSB2PHYCFG_ULPI_UTMI; 578 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg); 579 } else { 580 /* Relying on default value. */ 581 if (!(reg & DWC3_GUSB2PHYCFG_ULPI_UTMI)) 582 break; 583 } 584 /* FALLTHROUGH */ 585 case DWC3_GHWPARAMS3_HSPHY_IFC_ULPI: 586 /* FALLTHROUGH */ 587 default: 588 break; 589 } 590 591 switch (dwc->hsphy_mode) { 592 case USBPHY_INTERFACE_MODE_UTMI: 593 reg &= ~(DWC3_GUSB2PHYCFG_PHYIF_MASK | 594 DWC3_GUSB2PHYCFG_USBTRDTIM_MASK); 595 reg |= DWC3_GUSB2PHYCFG_PHYIF(UTMI_PHYIF_8_BIT) | 596 DWC3_GUSB2PHYCFG_USBTRDTIM(USBTRDTIM_UTMI_8_BIT); 597 break; 598 case USBPHY_INTERFACE_MODE_UTMIW: 599 reg &= ~(DWC3_GUSB2PHYCFG_PHYIF_MASK | 600 DWC3_GUSB2PHYCFG_USBTRDTIM_MASK); 601 reg |= DWC3_GUSB2PHYCFG_PHYIF(UTMI_PHYIF_16_BIT) | 602 DWC3_GUSB2PHYCFG_USBTRDTIM(USBTRDTIM_UTMI_16_BIT); 603 break; 604 default: 605 break; 606 } 607 608 /* 609 * Above 1.94a, it is recommended to set DWC3_GUSB2PHYCFG_SUSPHY to 610 * '0' during coreConsultant configuration. So default value will 611 * be '0' when the core is reset. Application needs to set it to 612 * '1' after the core initialization is completed. 613 */ 614 if (dwc->revision > DWC3_REVISION_194A) 615 reg |= DWC3_GUSB2PHYCFG_SUSPHY; 616 617 if (dwc->dis_u2_susphy_quirk) 618 reg &= ~DWC3_GUSB2PHYCFG_SUSPHY; 619 620 if (dwc->dis_enblslpm_quirk) 621 reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM; 622 623 if (dwc->dis_u2_freeclk_exists_quirk) 624 reg &= ~DWC3_GUSB2PHYCFG_U2_FREECLK_EXISTS; 625 626 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg); 627 628 return 0; 629 } 630 631 static void dwc3_core_exit(struct dwc3 *dwc) 632 { 633 dwc3_event_buffers_cleanup(dwc); 634 635 usb_phy_shutdown(dwc->usb2_phy); 636 usb_phy_shutdown(dwc->usb3_phy); 637 phy_exit(dwc->usb2_generic_phy); 638 phy_exit(dwc->usb3_generic_phy); 639 640 usb_phy_set_suspend(dwc->usb2_phy, 1); 641 usb_phy_set_suspend(dwc->usb3_phy, 1); 642 phy_power_off(dwc->usb2_generic_phy); 643 phy_power_off(dwc->usb3_generic_phy); 644 } 645 646 static bool dwc3_core_is_valid(struct dwc3 *dwc) 647 { 648 u32 reg; 649 650 reg = dwc3_readl(dwc->regs, DWC3_GSNPSID); 651 652 /* This should read as U3 followed by revision number */ 653 if ((reg & DWC3_GSNPSID_MASK) == 0x55330000) { 654 /* Detected DWC_usb3 IP */ 655 dwc->revision = reg; 656 } else if ((reg & DWC3_GSNPSID_MASK) == 0x33310000) { 657 /* Detected DWC_usb31 IP */ 658 dwc->revision = dwc3_readl(dwc->regs, DWC3_VER_NUMBER); 659 dwc->revision |= DWC3_REVISION_IS_DWC31; 660 } else { 661 return false; 662 } 663 664 return true; 665 } 666 667 static void dwc3_core_setup_global_control(struct dwc3 *dwc) 668 { 669 u32 hwparams4 = dwc->hwparams.hwparams4; 670 u32 reg; 671 672 reg = dwc3_readl(dwc->regs, DWC3_GCTL); 673 reg &= ~DWC3_GCTL_SCALEDOWN_MASK; 674 675 switch (DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1)) { 676 case DWC3_GHWPARAMS1_EN_PWROPT_CLK: 677 /** 678 * WORKAROUND: DWC3 revisions between 2.10a and 2.50a have an 679 * issue which would cause xHCI compliance tests to fail. 680 * 681 * Because of that we cannot enable clock gating on such 682 * configurations. 683 * 684 * Refers to: 685 * 686 * STAR#9000588375: Clock Gating, SOF Issues when ref_clk-Based 687 * SOF/ITP Mode Used 688 */ 689 if ((dwc->dr_mode == USB_DR_MODE_HOST || 690 dwc->dr_mode == USB_DR_MODE_OTG) && 691 (dwc->revision >= DWC3_REVISION_210A && 692 dwc->revision <= DWC3_REVISION_250A)) 693 reg |= DWC3_GCTL_DSBLCLKGTNG | DWC3_GCTL_SOFITPSYNC; 694 else 695 reg &= ~DWC3_GCTL_DSBLCLKGTNG; 696 break; 697 case DWC3_GHWPARAMS1_EN_PWROPT_HIB: 698 /* enable hibernation here */ 699 dwc->nr_scratch = DWC3_GHWPARAMS4_HIBER_SCRATCHBUFS(hwparams4); 700 701 /* 702 * REVISIT Enabling this bit so that host-mode hibernation 703 * will work. Device-mode hibernation is not yet implemented. 704 */ 705 reg |= DWC3_GCTL_GBLHIBERNATIONEN; 706 break; 707 default: 708 /* nothing */ 709 break; 710 } 711 712 /* check if current dwc3 is on simulation board */ 713 if (dwc->hwparams.hwparams6 & DWC3_GHWPARAMS6_EN_FPGA) { 714 dev_info(dwc->dev, "Running with FPGA optmizations\n"); 715 dwc->is_fpga = true; 716 } 717 718 WARN_ONCE(dwc->disable_scramble_quirk && !dwc->is_fpga, 719 "disable_scramble cannot be used on non-FPGA builds\n"); 720 721 if (dwc->disable_scramble_quirk && dwc->is_fpga) 722 reg |= DWC3_GCTL_DISSCRAMBLE; 723 else 724 reg &= ~DWC3_GCTL_DISSCRAMBLE; 725 726 if (dwc->u2exit_lfps_quirk) 727 reg |= DWC3_GCTL_U2EXIT_LFPS; 728 729 /* 730 * WORKAROUND: DWC3 revisions <1.90a have a bug 731 * where the device can fail to connect at SuperSpeed 732 * and falls back to high-speed mode which causes 733 * the device to enter a Connect/Disconnect loop 734 */ 735 if (dwc->revision < DWC3_REVISION_190A) 736 reg |= DWC3_GCTL_U2RSTECN; 737 738 dwc3_writel(dwc->regs, DWC3_GCTL, reg); 739 } 740 741 static int dwc3_core_get_phy(struct dwc3 *dwc); 742 static int dwc3_core_ulpi_init(struct dwc3 *dwc); 743 744 /** 745 * dwc3_core_init - Low-level initialization of DWC3 Core 746 * @dwc: Pointer to our controller context structure 747 * 748 * Returns 0 on success otherwise negative errno. 749 */ 750 static int dwc3_core_init(struct dwc3 *dwc) 751 { 752 u32 reg; 753 int ret; 754 755 if (!dwc3_core_is_valid(dwc)) { 756 dev_err(dwc->dev, "this is not a DesignWare USB3 DRD Core\n"); 757 ret = -ENODEV; 758 goto err0; 759 } 760 761 /* 762 * Write Linux Version Code to our GUID register so it's easy to figure 763 * out which kernel version a bug was found. 764 */ 765 dwc3_writel(dwc->regs, DWC3_GUID, LINUX_VERSION_CODE); 766 767 /* Handle USB2.0-only core configuration */ 768 if (DWC3_GHWPARAMS3_SSPHY_IFC(dwc->hwparams.hwparams3) == 769 DWC3_GHWPARAMS3_SSPHY_IFC_DIS) { 770 if (dwc->maximum_speed == USB_SPEED_SUPER) 771 dwc->maximum_speed = USB_SPEED_HIGH; 772 } 773 774 ret = dwc3_phy_setup(dwc); 775 if (ret) 776 goto err0; 777 778 if (!dwc->ulpi_ready) { 779 ret = dwc3_core_ulpi_init(dwc); 780 if (ret) 781 goto err0; 782 dwc->ulpi_ready = true; 783 } 784 785 if (!dwc->phys_ready) { 786 ret = dwc3_core_get_phy(dwc); 787 if (ret) 788 goto err0a; 789 dwc->phys_ready = true; 790 } 791 792 ret = dwc3_core_soft_reset(dwc); 793 if (ret) 794 goto err0a; 795 796 dwc3_core_setup_global_control(dwc); 797 dwc3_core_num_eps(dwc); 798 799 ret = dwc3_setup_scratch_buffers(dwc); 800 if (ret) 801 goto err1; 802 803 /* Adjust Frame Length */ 804 dwc3_frame_length_adjustment(dwc); 805 806 usb_phy_set_suspend(dwc->usb2_phy, 0); 807 usb_phy_set_suspend(dwc->usb3_phy, 0); 808 ret = phy_power_on(dwc->usb2_generic_phy); 809 if (ret < 0) 810 goto err2; 811 812 ret = phy_power_on(dwc->usb3_generic_phy); 813 if (ret < 0) 814 goto err3; 815 816 ret = dwc3_event_buffers_setup(dwc); 817 if (ret) { 818 dev_err(dwc->dev, "failed to setup event buffers\n"); 819 goto err4; 820 } 821 822 /* 823 * ENDXFER polling is available on version 3.10a and later of 824 * the DWC_usb3 controller. It is NOT available in the 825 * DWC_usb31 controller. 826 */ 827 if (!dwc3_is_usb31(dwc) && dwc->revision >= DWC3_REVISION_310A) { 828 reg = dwc3_readl(dwc->regs, DWC3_GUCTL2); 829 reg |= DWC3_GUCTL2_RST_ACTBITLATER; 830 dwc3_writel(dwc->regs, DWC3_GUCTL2, reg); 831 } 832 833 if (dwc->revision >= DWC3_REVISION_250A) { 834 reg = dwc3_readl(dwc->regs, DWC3_GUCTL1); 835 836 /* 837 * Enable hardware control of sending remote wakeup 838 * in HS when the device is in the L1 state. 839 */ 840 if (dwc->revision >= DWC3_REVISION_290A) 841 reg |= DWC3_GUCTL1_DEV_L1_EXIT_BY_HW; 842 843 if (dwc->dis_tx_ipgap_linecheck_quirk) 844 reg |= DWC3_GUCTL1_TX_IPGAP_LINECHECK_DIS; 845 846 dwc3_writel(dwc->regs, DWC3_GUCTL1, reg); 847 } 848 849 return 0; 850 851 err4: 852 phy_power_off(dwc->usb3_generic_phy); 853 854 err3: 855 phy_power_off(dwc->usb2_generic_phy); 856 857 err2: 858 usb_phy_set_suspend(dwc->usb2_phy, 1); 859 usb_phy_set_suspend(dwc->usb3_phy, 1); 860 861 err1: 862 usb_phy_shutdown(dwc->usb2_phy); 863 usb_phy_shutdown(dwc->usb3_phy); 864 phy_exit(dwc->usb2_generic_phy); 865 phy_exit(dwc->usb3_generic_phy); 866 867 err0a: 868 dwc3_ulpi_exit(dwc); 869 870 err0: 871 return ret; 872 } 873 874 static int dwc3_core_get_phy(struct dwc3 *dwc) 875 { 876 struct device *dev = dwc->dev; 877 struct device_node *node = dev->of_node; 878 int ret; 879 880 if (node) { 881 dwc->usb2_phy = devm_usb_get_phy_by_phandle(dev, "usb-phy", 0); 882 dwc->usb3_phy = devm_usb_get_phy_by_phandle(dev, "usb-phy", 1); 883 } else { 884 dwc->usb2_phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB2); 885 dwc->usb3_phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB3); 886 } 887 888 if (IS_ERR(dwc->usb2_phy)) { 889 ret = PTR_ERR(dwc->usb2_phy); 890 if (ret == -ENXIO || ret == -ENODEV) { 891 dwc->usb2_phy = NULL; 892 } else if (ret == -EPROBE_DEFER) { 893 return ret; 894 } else { 895 dev_err(dev, "no usb2 phy configured\n"); 896 return ret; 897 } 898 } 899 900 if (IS_ERR(dwc->usb3_phy)) { 901 ret = PTR_ERR(dwc->usb3_phy); 902 if (ret == -ENXIO || ret == -ENODEV) { 903 dwc->usb3_phy = NULL; 904 } else if (ret == -EPROBE_DEFER) { 905 return ret; 906 } else { 907 dev_err(dev, "no usb3 phy configured\n"); 908 return ret; 909 } 910 } 911 912 dwc->usb2_generic_phy = devm_phy_get(dev, "usb2-phy"); 913 if (IS_ERR(dwc->usb2_generic_phy)) { 914 ret = PTR_ERR(dwc->usb2_generic_phy); 915 if (ret == -ENOSYS || ret == -ENODEV) { 916 dwc->usb2_generic_phy = NULL; 917 } else if (ret == -EPROBE_DEFER) { 918 return ret; 919 } else { 920 dev_err(dev, "no usb2 phy configured\n"); 921 return ret; 922 } 923 } 924 925 dwc->usb3_generic_phy = devm_phy_get(dev, "usb3-phy"); 926 if (IS_ERR(dwc->usb3_generic_phy)) { 927 ret = PTR_ERR(dwc->usb3_generic_phy); 928 if (ret == -ENOSYS || ret == -ENODEV) { 929 dwc->usb3_generic_phy = NULL; 930 } else if (ret == -EPROBE_DEFER) { 931 return ret; 932 } else { 933 dev_err(dev, "no usb3 phy configured\n"); 934 return ret; 935 } 936 } 937 938 return 0; 939 } 940 941 static int dwc3_core_init_mode(struct dwc3 *dwc) 942 { 943 struct device *dev = dwc->dev; 944 int ret; 945 946 switch (dwc->dr_mode) { 947 case USB_DR_MODE_PERIPHERAL: 948 dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_DEVICE); 949 950 if (dwc->usb2_phy) 951 otg_set_vbus(dwc->usb2_phy->otg, false); 952 phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_DEVICE); 953 phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_DEVICE); 954 955 ret = dwc3_gadget_init(dwc); 956 if (ret) { 957 if (ret != -EPROBE_DEFER) 958 dev_err(dev, "failed to initialize gadget\n"); 959 return ret; 960 } 961 break; 962 case USB_DR_MODE_HOST: 963 dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_HOST); 964 965 if (dwc->usb2_phy) 966 otg_set_vbus(dwc->usb2_phy->otg, true); 967 phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_HOST); 968 phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_HOST); 969 970 ret = dwc3_host_init(dwc); 971 if (ret) { 972 if (ret != -EPROBE_DEFER) 973 dev_err(dev, "failed to initialize host\n"); 974 return ret; 975 } 976 phy_calibrate(dwc->usb2_generic_phy); 977 break; 978 case USB_DR_MODE_OTG: 979 INIT_WORK(&dwc->drd_work, __dwc3_set_mode); 980 ret = dwc3_drd_init(dwc); 981 if (ret) { 982 if (ret != -EPROBE_DEFER) 983 dev_err(dev, "failed to initialize dual-role\n"); 984 return ret; 985 } 986 break; 987 default: 988 dev_err(dev, "Unsupported mode of operation %d\n", dwc->dr_mode); 989 return -EINVAL; 990 } 991 992 return 0; 993 } 994 995 static void dwc3_core_exit_mode(struct dwc3 *dwc) 996 { 997 switch (dwc->dr_mode) { 998 case USB_DR_MODE_PERIPHERAL: 999 dwc3_gadget_exit(dwc); 1000 break; 1001 case USB_DR_MODE_HOST: 1002 dwc3_host_exit(dwc); 1003 break; 1004 case USB_DR_MODE_OTG: 1005 dwc3_drd_exit(dwc); 1006 break; 1007 default: 1008 /* do nothing */ 1009 break; 1010 } 1011 } 1012 1013 static void dwc3_get_properties(struct dwc3 *dwc) 1014 { 1015 struct device *dev = dwc->dev; 1016 u8 lpm_nyet_threshold; 1017 u8 tx_de_emphasis; 1018 u8 hird_threshold; 1019 1020 /* default to highest possible threshold */ 1021 lpm_nyet_threshold = 0xff; 1022 1023 /* default to -3.5dB de-emphasis */ 1024 tx_de_emphasis = 1; 1025 1026 /* 1027 * default to assert utmi_sleep_n and use maximum allowed HIRD 1028 * threshold value of 0b1100 1029 */ 1030 hird_threshold = 12; 1031 1032 dwc->maximum_speed = usb_get_maximum_speed(dev); 1033 dwc->dr_mode = usb_get_dr_mode(dev); 1034 dwc->hsphy_mode = of_usb_get_phy_mode(dev->of_node); 1035 1036 dwc->sysdev_is_parent = device_property_read_bool(dev, 1037 "linux,sysdev_is_parent"); 1038 if (dwc->sysdev_is_parent) 1039 dwc->sysdev = dwc->dev->parent; 1040 else 1041 dwc->sysdev = dwc->dev; 1042 1043 dwc->has_lpm_erratum = device_property_read_bool(dev, 1044 "snps,has-lpm-erratum"); 1045 device_property_read_u8(dev, "snps,lpm-nyet-threshold", 1046 &lpm_nyet_threshold); 1047 dwc->is_utmi_l1_suspend = device_property_read_bool(dev, 1048 "snps,is-utmi-l1-suspend"); 1049 device_property_read_u8(dev, "snps,hird-threshold", 1050 &hird_threshold); 1051 dwc->usb3_lpm_capable = device_property_read_bool(dev, 1052 "snps,usb3_lpm_capable"); 1053 1054 dwc->disable_scramble_quirk = device_property_read_bool(dev, 1055 "snps,disable_scramble_quirk"); 1056 dwc->u2exit_lfps_quirk = device_property_read_bool(dev, 1057 "snps,u2exit_lfps_quirk"); 1058 dwc->u2ss_inp3_quirk = device_property_read_bool(dev, 1059 "snps,u2ss_inp3_quirk"); 1060 dwc->req_p1p2p3_quirk = device_property_read_bool(dev, 1061 "snps,req_p1p2p3_quirk"); 1062 dwc->del_p1p2p3_quirk = device_property_read_bool(dev, 1063 "snps,del_p1p2p3_quirk"); 1064 dwc->del_phy_power_chg_quirk = device_property_read_bool(dev, 1065 "snps,del_phy_power_chg_quirk"); 1066 dwc->lfps_filter_quirk = device_property_read_bool(dev, 1067 "snps,lfps_filter_quirk"); 1068 dwc->rx_detect_poll_quirk = device_property_read_bool(dev, 1069 "snps,rx_detect_poll_quirk"); 1070 dwc->dis_u3_susphy_quirk = device_property_read_bool(dev, 1071 "snps,dis_u3_susphy_quirk"); 1072 dwc->dis_u2_susphy_quirk = device_property_read_bool(dev, 1073 "snps,dis_u2_susphy_quirk"); 1074 dwc->dis_enblslpm_quirk = device_property_read_bool(dev, 1075 "snps,dis_enblslpm_quirk"); 1076 dwc->dis_rxdet_inp3_quirk = device_property_read_bool(dev, 1077 "snps,dis_rxdet_inp3_quirk"); 1078 dwc->dis_u2_freeclk_exists_quirk = device_property_read_bool(dev, 1079 "snps,dis-u2-freeclk-exists-quirk"); 1080 dwc->dis_del_phy_power_chg_quirk = device_property_read_bool(dev, 1081 "snps,dis-del-phy-power-chg-quirk"); 1082 dwc->dis_tx_ipgap_linecheck_quirk = device_property_read_bool(dev, 1083 "snps,dis-tx-ipgap-linecheck-quirk"); 1084 1085 dwc->tx_de_emphasis_quirk = device_property_read_bool(dev, 1086 "snps,tx_de_emphasis_quirk"); 1087 device_property_read_u8(dev, "snps,tx_de_emphasis", 1088 &tx_de_emphasis); 1089 device_property_read_string(dev, "snps,hsphy_interface", 1090 &dwc->hsphy_interface); 1091 device_property_read_u32(dev, "snps,quirk-frame-length-adjustment", 1092 &dwc->fladj); 1093 1094 dwc->dis_metastability_quirk = device_property_read_bool(dev, 1095 "snps,dis_metastability_quirk"); 1096 1097 dwc->lpm_nyet_threshold = lpm_nyet_threshold; 1098 dwc->tx_de_emphasis = tx_de_emphasis; 1099 1100 dwc->hird_threshold = hird_threshold 1101 | (dwc->is_utmi_l1_suspend << 4); 1102 1103 dwc->imod_interval = 0; 1104 } 1105 1106 /* check whether the core supports IMOD */ 1107 bool dwc3_has_imod(struct dwc3 *dwc) 1108 { 1109 return ((dwc3_is_usb3(dwc) && 1110 dwc->revision >= DWC3_REVISION_300A) || 1111 (dwc3_is_usb31(dwc) && 1112 dwc->revision >= DWC3_USB31_REVISION_120A)); 1113 } 1114 1115 static void dwc3_check_params(struct dwc3 *dwc) 1116 { 1117 struct device *dev = dwc->dev; 1118 1119 /* Check for proper value of imod_interval */ 1120 if (dwc->imod_interval && !dwc3_has_imod(dwc)) { 1121 dev_warn(dwc->dev, "Interrupt moderation not supported\n"); 1122 dwc->imod_interval = 0; 1123 } 1124 1125 /* 1126 * Workaround for STAR 9000961433 which affects only version 1127 * 3.00a of the DWC_usb3 core. This prevents the controller 1128 * interrupt from being masked while handling events. IMOD 1129 * allows us to work around this issue. Enable it for the 1130 * affected version. 1131 */ 1132 if (!dwc->imod_interval && 1133 (dwc->revision == DWC3_REVISION_300A)) 1134 dwc->imod_interval = 1; 1135 1136 /* Check the maximum_speed parameter */ 1137 switch (dwc->maximum_speed) { 1138 case USB_SPEED_LOW: 1139 case USB_SPEED_FULL: 1140 case USB_SPEED_HIGH: 1141 case USB_SPEED_SUPER: 1142 case USB_SPEED_SUPER_PLUS: 1143 break; 1144 default: 1145 dev_err(dev, "invalid maximum_speed parameter %d\n", 1146 dwc->maximum_speed); 1147 /* fall through */ 1148 case USB_SPEED_UNKNOWN: 1149 /* default to superspeed */ 1150 dwc->maximum_speed = USB_SPEED_SUPER; 1151 1152 /* 1153 * default to superspeed plus if we are capable. 1154 */ 1155 if (dwc3_is_usb31(dwc) && 1156 (DWC3_GHWPARAMS3_SSPHY_IFC(dwc->hwparams.hwparams3) == 1157 DWC3_GHWPARAMS3_SSPHY_IFC_GEN2)) 1158 dwc->maximum_speed = USB_SPEED_SUPER_PLUS; 1159 1160 break; 1161 } 1162 } 1163 1164 static int dwc3_probe(struct platform_device *pdev) 1165 { 1166 struct device *dev = &pdev->dev; 1167 struct resource *res; 1168 struct dwc3 *dwc; 1169 1170 int ret; 1171 1172 void __iomem *regs; 1173 1174 dwc = devm_kzalloc(dev, sizeof(*dwc), GFP_KERNEL); 1175 if (!dwc) 1176 return -ENOMEM; 1177 1178 dwc->dev = dev; 1179 1180 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1181 if (!res) { 1182 dev_err(dev, "missing memory resource\n"); 1183 return -ENODEV; 1184 } 1185 1186 dwc->xhci_resources[0].start = res->start; 1187 dwc->xhci_resources[0].end = dwc->xhci_resources[0].start + 1188 DWC3_XHCI_REGS_END; 1189 dwc->xhci_resources[0].flags = res->flags; 1190 dwc->xhci_resources[0].name = res->name; 1191 1192 res->start += DWC3_GLOBALS_REGS_START; 1193 1194 /* 1195 * Request memory region but exclude xHCI regs, 1196 * since it will be requested by the xhci-plat driver. 1197 */ 1198 regs = devm_ioremap_resource(dev, res); 1199 if (IS_ERR(regs)) { 1200 ret = PTR_ERR(regs); 1201 goto err0; 1202 } 1203 1204 dwc->regs = regs; 1205 dwc->regs_size = resource_size(res); 1206 1207 dwc3_get_properties(dwc); 1208 1209 platform_set_drvdata(pdev, dwc); 1210 dwc3_cache_hwparams(dwc); 1211 1212 spin_lock_init(&dwc->lock); 1213 1214 pm_runtime_set_active(dev); 1215 pm_runtime_use_autosuspend(dev); 1216 pm_runtime_set_autosuspend_delay(dev, DWC3_DEFAULT_AUTOSUSPEND_DELAY); 1217 pm_runtime_enable(dev); 1218 ret = pm_runtime_get_sync(dev); 1219 if (ret < 0) 1220 goto err1; 1221 1222 pm_runtime_forbid(dev); 1223 1224 ret = dwc3_alloc_event_buffers(dwc, DWC3_EVENT_BUFFERS_SIZE); 1225 if (ret) { 1226 dev_err(dwc->dev, "failed to allocate event buffers\n"); 1227 ret = -ENOMEM; 1228 goto err2; 1229 } 1230 1231 ret = dwc3_get_dr_mode(dwc); 1232 if (ret) 1233 goto err3; 1234 1235 ret = dwc3_alloc_scratch_buffers(dwc); 1236 if (ret) 1237 goto err3; 1238 1239 ret = dwc3_core_init(dwc); 1240 if (ret) { 1241 dev_err(dev, "failed to initialize core\n"); 1242 goto err4; 1243 } 1244 1245 dwc3_check_params(dwc); 1246 1247 ret = dwc3_core_init_mode(dwc); 1248 if (ret) 1249 goto err5; 1250 1251 dwc3_debugfs_init(dwc); 1252 pm_runtime_put(dev); 1253 1254 return 0; 1255 1256 err5: 1257 dwc3_event_buffers_cleanup(dwc); 1258 1259 err4: 1260 dwc3_free_scratch_buffers(dwc); 1261 1262 err3: 1263 dwc3_free_event_buffers(dwc); 1264 1265 err2: 1266 pm_runtime_allow(&pdev->dev); 1267 1268 err1: 1269 pm_runtime_put_sync(&pdev->dev); 1270 pm_runtime_disable(&pdev->dev); 1271 1272 err0: 1273 /* 1274 * restore res->start back to its original value so that, in case the 1275 * probe is deferred, we don't end up getting error in request the 1276 * memory region the next time probe is called. 1277 */ 1278 res->start -= DWC3_GLOBALS_REGS_START; 1279 1280 return ret; 1281 } 1282 1283 static int dwc3_remove(struct platform_device *pdev) 1284 { 1285 struct dwc3 *dwc = platform_get_drvdata(pdev); 1286 struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1287 1288 pm_runtime_get_sync(&pdev->dev); 1289 /* 1290 * restore res->start back to its original value so that, in case the 1291 * probe is deferred, we don't end up getting error in request the 1292 * memory region the next time probe is called. 1293 */ 1294 res->start -= DWC3_GLOBALS_REGS_START; 1295 1296 dwc3_debugfs_exit(dwc); 1297 dwc3_core_exit_mode(dwc); 1298 1299 dwc3_core_exit(dwc); 1300 dwc3_ulpi_exit(dwc); 1301 1302 pm_runtime_put_sync(&pdev->dev); 1303 pm_runtime_allow(&pdev->dev); 1304 pm_runtime_disable(&pdev->dev); 1305 1306 dwc3_free_event_buffers(dwc); 1307 dwc3_free_scratch_buffers(dwc); 1308 1309 return 0; 1310 } 1311 1312 #ifdef CONFIG_PM 1313 static int dwc3_suspend_common(struct dwc3 *dwc, pm_message_t msg) 1314 { 1315 unsigned long flags; 1316 1317 switch (dwc->current_dr_role) { 1318 case DWC3_GCTL_PRTCAP_DEVICE: 1319 spin_lock_irqsave(&dwc->lock, flags); 1320 dwc3_gadget_suspend(dwc); 1321 spin_unlock_irqrestore(&dwc->lock, flags); 1322 dwc3_core_exit(dwc); 1323 break; 1324 case DWC3_GCTL_PRTCAP_HOST: 1325 /* do nothing during host runtime_suspend */ 1326 if (!PMSG_IS_AUTO(msg)) 1327 dwc3_core_exit(dwc); 1328 break; 1329 default: 1330 /* do nothing */ 1331 break; 1332 } 1333 1334 return 0; 1335 } 1336 1337 static int dwc3_resume_common(struct dwc3 *dwc, pm_message_t msg) 1338 { 1339 unsigned long flags; 1340 int ret; 1341 1342 switch (dwc->current_dr_role) { 1343 case DWC3_GCTL_PRTCAP_DEVICE: 1344 ret = dwc3_core_init(dwc); 1345 if (ret) 1346 return ret; 1347 1348 spin_lock_irqsave(&dwc->lock, flags); 1349 dwc3_gadget_resume(dwc); 1350 spin_unlock_irqrestore(&dwc->lock, flags); 1351 break; 1352 case DWC3_GCTL_PRTCAP_HOST: 1353 /* nothing to do on host runtime_resume */ 1354 if (!PMSG_IS_AUTO(msg)) { 1355 ret = dwc3_core_init(dwc); 1356 if (ret) 1357 return ret; 1358 } 1359 break; 1360 default: 1361 /* do nothing */ 1362 break; 1363 } 1364 1365 return 0; 1366 } 1367 1368 static int dwc3_runtime_checks(struct dwc3 *dwc) 1369 { 1370 switch (dwc->current_dr_role) { 1371 case DWC3_GCTL_PRTCAP_DEVICE: 1372 if (dwc->connected) 1373 return -EBUSY; 1374 break; 1375 case DWC3_GCTL_PRTCAP_HOST: 1376 default: 1377 /* do nothing */ 1378 break; 1379 } 1380 1381 return 0; 1382 } 1383 1384 static int dwc3_runtime_suspend(struct device *dev) 1385 { 1386 struct dwc3 *dwc = dev_get_drvdata(dev); 1387 int ret; 1388 1389 if (dwc3_runtime_checks(dwc)) 1390 return -EBUSY; 1391 1392 ret = dwc3_suspend_common(dwc, PMSG_AUTO_SUSPEND); 1393 if (ret) 1394 return ret; 1395 1396 device_init_wakeup(dev, true); 1397 1398 return 0; 1399 } 1400 1401 static int dwc3_runtime_resume(struct device *dev) 1402 { 1403 struct dwc3 *dwc = dev_get_drvdata(dev); 1404 int ret; 1405 1406 device_init_wakeup(dev, false); 1407 1408 ret = dwc3_resume_common(dwc, PMSG_AUTO_RESUME); 1409 if (ret) 1410 return ret; 1411 1412 switch (dwc->current_dr_role) { 1413 case DWC3_GCTL_PRTCAP_DEVICE: 1414 dwc3_gadget_process_pending_events(dwc); 1415 break; 1416 case DWC3_GCTL_PRTCAP_HOST: 1417 default: 1418 /* do nothing */ 1419 break; 1420 } 1421 1422 pm_runtime_mark_last_busy(dev); 1423 1424 return 0; 1425 } 1426 1427 static int dwc3_runtime_idle(struct device *dev) 1428 { 1429 struct dwc3 *dwc = dev_get_drvdata(dev); 1430 1431 switch (dwc->current_dr_role) { 1432 case DWC3_GCTL_PRTCAP_DEVICE: 1433 if (dwc3_runtime_checks(dwc)) 1434 return -EBUSY; 1435 break; 1436 case DWC3_GCTL_PRTCAP_HOST: 1437 default: 1438 /* do nothing */ 1439 break; 1440 } 1441 1442 pm_runtime_mark_last_busy(dev); 1443 pm_runtime_autosuspend(dev); 1444 1445 return 0; 1446 } 1447 #endif /* CONFIG_PM */ 1448 1449 #ifdef CONFIG_PM_SLEEP 1450 static int dwc3_suspend(struct device *dev) 1451 { 1452 struct dwc3 *dwc = dev_get_drvdata(dev); 1453 int ret; 1454 1455 ret = dwc3_suspend_common(dwc, PMSG_SUSPEND); 1456 if (ret) 1457 return ret; 1458 1459 pinctrl_pm_select_sleep_state(dev); 1460 1461 return 0; 1462 } 1463 1464 static int dwc3_resume(struct device *dev) 1465 { 1466 struct dwc3 *dwc = dev_get_drvdata(dev); 1467 int ret; 1468 1469 pinctrl_pm_select_default_state(dev); 1470 1471 ret = dwc3_resume_common(dwc, PMSG_RESUME); 1472 if (ret) 1473 return ret; 1474 1475 pm_runtime_disable(dev); 1476 pm_runtime_set_active(dev); 1477 pm_runtime_enable(dev); 1478 1479 return 0; 1480 } 1481 #endif /* CONFIG_PM_SLEEP */ 1482 1483 static const struct dev_pm_ops dwc3_dev_pm_ops = { 1484 SET_SYSTEM_SLEEP_PM_OPS(dwc3_suspend, dwc3_resume) 1485 SET_RUNTIME_PM_OPS(dwc3_runtime_suspend, dwc3_runtime_resume, 1486 dwc3_runtime_idle) 1487 }; 1488 1489 #ifdef CONFIG_OF 1490 static const struct of_device_id of_dwc3_match[] = { 1491 { 1492 .compatible = "snps,dwc3" 1493 }, 1494 { 1495 .compatible = "synopsys,dwc3" 1496 }, 1497 { }, 1498 }; 1499 MODULE_DEVICE_TABLE(of, of_dwc3_match); 1500 #endif 1501 1502 #ifdef CONFIG_ACPI 1503 1504 #define ACPI_ID_INTEL_BSW "808622B7" 1505 1506 static const struct acpi_device_id dwc3_acpi_match[] = { 1507 { ACPI_ID_INTEL_BSW, 0 }, 1508 { }, 1509 }; 1510 MODULE_DEVICE_TABLE(acpi, dwc3_acpi_match); 1511 #endif 1512 1513 static struct platform_driver dwc3_driver = { 1514 .probe = dwc3_probe, 1515 .remove = dwc3_remove, 1516 .driver = { 1517 .name = "dwc3", 1518 .of_match_table = of_match_ptr(of_dwc3_match), 1519 .acpi_match_table = ACPI_PTR(dwc3_acpi_match), 1520 .pm = &dwc3_dev_pm_ops, 1521 }, 1522 }; 1523 1524 module_platform_driver(dwc3_driver); 1525 1526 MODULE_ALIAS("platform:dwc3"); 1527 MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>"); 1528 MODULE_LICENSE("GPL v2"); 1529 MODULE_DESCRIPTION("DesignWare USB3 DRD Controller Driver"); 1530