1 // SPDX-License-Identifier: GPL-2.0 2 /** 3 * core.c - DesignWare USB3 DRD Controller Core file 4 * 5 * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com 6 * 7 * Authors: Felipe Balbi <balbi@ti.com>, 8 * Sebastian Andrzej Siewior <bigeasy@linutronix.de> 9 */ 10 11 #include <linux/clk.h> 12 #include <linux/version.h> 13 #include <linux/module.h> 14 #include <linux/kernel.h> 15 #include <linux/slab.h> 16 #include <linux/spinlock.h> 17 #include <linux/platform_device.h> 18 #include <linux/pm_runtime.h> 19 #include <linux/interrupt.h> 20 #include <linux/ioport.h> 21 #include <linux/io.h> 22 #include <linux/list.h> 23 #include <linux/delay.h> 24 #include <linux/dma-mapping.h> 25 #include <linux/of.h> 26 #include <linux/acpi.h> 27 #include <linux/pinctrl/consumer.h> 28 #include <linux/reset.h> 29 30 #include <linux/usb/ch9.h> 31 #include <linux/usb/gadget.h> 32 #include <linux/usb/of.h> 33 #include <linux/usb/otg.h> 34 35 #include "core.h" 36 #include "gadget.h" 37 #include "io.h" 38 39 #include "debug.h" 40 41 #define DWC3_DEFAULT_AUTOSUSPEND_DELAY 5000 /* ms */ 42 43 /** 44 * dwc3_get_dr_mode - Validates and sets dr_mode 45 * @dwc: pointer to our context structure 46 */ 47 static int dwc3_get_dr_mode(struct dwc3 *dwc) 48 { 49 enum usb_dr_mode mode; 50 struct device *dev = dwc->dev; 51 unsigned int hw_mode; 52 53 if (dwc->dr_mode == USB_DR_MODE_UNKNOWN) 54 dwc->dr_mode = USB_DR_MODE_OTG; 55 56 mode = dwc->dr_mode; 57 hw_mode = DWC3_GHWPARAMS0_MODE(dwc->hwparams.hwparams0); 58 59 switch (hw_mode) { 60 case DWC3_GHWPARAMS0_MODE_GADGET: 61 if (IS_ENABLED(CONFIG_USB_DWC3_HOST)) { 62 dev_err(dev, 63 "Controller does not support host mode.\n"); 64 return -EINVAL; 65 } 66 mode = USB_DR_MODE_PERIPHERAL; 67 break; 68 case DWC3_GHWPARAMS0_MODE_HOST: 69 if (IS_ENABLED(CONFIG_USB_DWC3_GADGET)) { 70 dev_err(dev, 71 "Controller does not support device mode.\n"); 72 return -EINVAL; 73 } 74 mode = USB_DR_MODE_HOST; 75 break; 76 default: 77 if (IS_ENABLED(CONFIG_USB_DWC3_HOST)) 78 mode = USB_DR_MODE_HOST; 79 else if (IS_ENABLED(CONFIG_USB_DWC3_GADGET)) 80 mode = USB_DR_MODE_PERIPHERAL; 81 82 /* 83 * DWC_usb31 and DWC_usb3 v3.30a and higher do not support OTG 84 * mode. If the controller supports DRD but the dr_mode is not 85 * specified or set to OTG, then set the mode to peripheral. 86 */ 87 if (mode == USB_DR_MODE_OTG && 88 dwc->revision >= DWC3_REVISION_330A) 89 mode = USB_DR_MODE_PERIPHERAL; 90 } 91 92 if (mode != dwc->dr_mode) { 93 dev_warn(dev, 94 "Configuration mismatch. dr_mode forced to %s\n", 95 mode == USB_DR_MODE_HOST ? "host" : "gadget"); 96 97 dwc->dr_mode = mode; 98 } 99 100 return 0; 101 } 102 103 void dwc3_set_prtcap(struct dwc3 *dwc, u32 mode) 104 { 105 u32 reg; 106 107 reg = dwc3_readl(dwc->regs, DWC3_GCTL); 108 reg &= ~(DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_OTG)); 109 reg |= DWC3_GCTL_PRTCAPDIR(mode); 110 dwc3_writel(dwc->regs, DWC3_GCTL, reg); 111 112 dwc->current_dr_role = mode; 113 } 114 115 static void __dwc3_set_mode(struct work_struct *work) 116 { 117 struct dwc3 *dwc = work_to_dwc(work); 118 unsigned long flags; 119 int ret; 120 121 if (dwc->dr_mode != USB_DR_MODE_OTG) 122 return; 123 124 if (dwc->current_dr_role == DWC3_GCTL_PRTCAP_OTG) 125 dwc3_otg_update(dwc, 0); 126 127 if (!dwc->desired_dr_role) 128 return; 129 130 if (dwc->desired_dr_role == dwc->current_dr_role) 131 return; 132 133 if (dwc->desired_dr_role == DWC3_GCTL_PRTCAP_OTG && dwc->edev) 134 return; 135 136 switch (dwc->current_dr_role) { 137 case DWC3_GCTL_PRTCAP_HOST: 138 dwc3_host_exit(dwc); 139 break; 140 case DWC3_GCTL_PRTCAP_DEVICE: 141 dwc3_gadget_exit(dwc); 142 dwc3_event_buffers_cleanup(dwc); 143 break; 144 case DWC3_GCTL_PRTCAP_OTG: 145 dwc3_otg_exit(dwc); 146 spin_lock_irqsave(&dwc->lock, flags); 147 dwc->desired_otg_role = DWC3_OTG_ROLE_IDLE; 148 spin_unlock_irqrestore(&dwc->lock, flags); 149 dwc3_otg_update(dwc, 1); 150 break; 151 default: 152 break; 153 } 154 155 spin_lock_irqsave(&dwc->lock, flags); 156 157 dwc3_set_prtcap(dwc, dwc->desired_dr_role); 158 159 spin_unlock_irqrestore(&dwc->lock, flags); 160 161 switch (dwc->desired_dr_role) { 162 case DWC3_GCTL_PRTCAP_HOST: 163 ret = dwc3_host_init(dwc); 164 if (ret) { 165 dev_err(dwc->dev, "failed to initialize host\n"); 166 } else { 167 if (dwc->usb2_phy) 168 otg_set_vbus(dwc->usb2_phy->otg, true); 169 phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_HOST); 170 phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_HOST); 171 phy_calibrate(dwc->usb2_generic_phy); 172 } 173 break; 174 case DWC3_GCTL_PRTCAP_DEVICE: 175 dwc3_event_buffers_setup(dwc); 176 177 if (dwc->usb2_phy) 178 otg_set_vbus(dwc->usb2_phy->otg, false); 179 phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_DEVICE); 180 phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_DEVICE); 181 182 ret = dwc3_gadget_init(dwc); 183 if (ret) 184 dev_err(dwc->dev, "failed to initialize peripheral\n"); 185 break; 186 case DWC3_GCTL_PRTCAP_OTG: 187 dwc3_otg_init(dwc); 188 dwc3_otg_update(dwc, 0); 189 break; 190 default: 191 break; 192 } 193 194 } 195 196 void dwc3_set_mode(struct dwc3 *dwc, u32 mode) 197 { 198 unsigned long flags; 199 200 spin_lock_irqsave(&dwc->lock, flags); 201 dwc->desired_dr_role = mode; 202 spin_unlock_irqrestore(&dwc->lock, flags); 203 204 queue_work(system_freezable_wq, &dwc->drd_work); 205 } 206 207 u32 dwc3_core_fifo_space(struct dwc3_ep *dep, u8 type) 208 { 209 struct dwc3 *dwc = dep->dwc; 210 u32 reg; 211 212 dwc3_writel(dwc->regs, DWC3_GDBGFIFOSPACE, 213 DWC3_GDBGFIFOSPACE_NUM(dep->number) | 214 DWC3_GDBGFIFOSPACE_TYPE(type)); 215 216 reg = dwc3_readl(dwc->regs, DWC3_GDBGFIFOSPACE); 217 218 return DWC3_GDBGFIFOSPACE_SPACE_AVAILABLE(reg); 219 } 220 221 /** 222 * dwc3_core_soft_reset - Issues core soft reset and PHY reset 223 * @dwc: pointer to our context structure 224 */ 225 static int dwc3_core_soft_reset(struct dwc3 *dwc) 226 { 227 u32 reg; 228 int retries = 1000; 229 int ret; 230 231 usb_phy_init(dwc->usb2_phy); 232 usb_phy_init(dwc->usb3_phy); 233 ret = phy_init(dwc->usb2_generic_phy); 234 if (ret < 0) 235 return ret; 236 237 ret = phy_init(dwc->usb3_generic_phy); 238 if (ret < 0) { 239 phy_exit(dwc->usb2_generic_phy); 240 return ret; 241 } 242 243 /* 244 * We're resetting only the device side because, if we're in host mode, 245 * XHCI driver will reset the host block. If dwc3 was configured for 246 * host-only mode, then we can return early. 247 */ 248 if (dwc->current_dr_role == DWC3_GCTL_PRTCAP_HOST) 249 return 0; 250 251 reg = dwc3_readl(dwc->regs, DWC3_DCTL); 252 reg |= DWC3_DCTL_CSFTRST; 253 dwc3_writel(dwc->regs, DWC3_DCTL, reg); 254 255 do { 256 reg = dwc3_readl(dwc->regs, DWC3_DCTL); 257 if (!(reg & DWC3_DCTL_CSFTRST)) 258 goto done; 259 260 udelay(1); 261 } while (--retries); 262 263 phy_exit(dwc->usb3_generic_phy); 264 phy_exit(dwc->usb2_generic_phy); 265 266 return -ETIMEDOUT; 267 268 done: 269 /* 270 * For DWC_usb31 controller, once DWC3_DCTL_CSFTRST bit is cleared, 271 * we must wait at least 50ms before accessing the PHY domain 272 * (synchronization delay). DWC_usb31 programming guide section 1.3.2. 273 */ 274 if (dwc3_is_usb31(dwc)) 275 msleep(50); 276 277 return 0; 278 } 279 280 static const struct clk_bulk_data dwc3_core_clks[] = { 281 { .id = "ref" }, 282 { .id = "bus_early" }, 283 { .id = "suspend" }, 284 }; 285 286 /* 287 * dwc3_frame_length_adjustment - Adjusts frame length if required 288 * @dwc3: Pointer to our controller context structure 289 */ 290 static void dwc3_frame_length_adjustment(struct dwc3 *dwc) 291 { 292 u32 reg; 293 u32 dft; 294 295 if (dwc->revision < DWC3_REVISION_250A) 296 return; 297 298 if (dwc->fladj == 0) 299 return; 300 301 reg = dwc3_readl(dwc->regs, DWC3_GFLADJ); 302 dft = reg & DWC3_GFLADJ_30MHZ_MASK; 303 if (!dev_WARN_ONCE(dwc->dev, dft == dwc->fladj, 304 "request value same as default, ignoring\n")) { 305 reg &= ~DWC3_GFLADJ_30MHZ_MASK; 306 reg |= DWC3_GFLADJ_30MHZ_SDBND_SEL | dwc->fladj; 307 dwc3_writel(dwc->regs, DWC3_GFLADJ, reg); 308 } 309 } 310 311 /** 312 * dwc3_free_one_event_buffer - Frees one event buffer 313 * @dwc: Pointer to our controller context structure 314 * @evt: Pointer to event buffer to be freed 315 */ 316 static void dwc3_free_one_event_buffer(struct dwc3 *dwc, 317 struct dwc3_event_buffer *evt) 318 { 319 dma_free_coherent(dwc->sysdev, evt->length, evt->buf, evt->dma); 320 } 321 322 /** 323 * dwc3_alloc_one_event_buffer - Allocates one event buffer structure 324 * @dwc: Pointer to our controller context structure 325 * @length: size of the event buffer 326 * 327 * Returns a pointer to the allocated event buffer structure on success 328 * otherwise ERR_PTR(errno). 329 */ 330 static struct dwc3_event_buffer *dwc3_alloc_one_event_buffer(struct dwc3 *dwc, 331 unsigned length) 332 { 333 struct dwc3_event_buffer *evt; 334 335 evt = devm_kzalloc(dwc->dev, sizeof(*evt), GFP_KERNEL); 336 if (!evt) 337 return ERR_PTR(-ENOMEM); 338 339 evt->dwc = dwc; 340 evt->length = length; 341 evt->cache = devm_kzalloc(dwc->dev, length, GFP_KERNEL); 342 if (!evt->cache) 343 return ERR_PTR(-ENOMEM); 344 345 evt->buf = dma_alloc_coherent(dwc->sysdev, length, 346 &evt->dma, GFP_KERNEL); 347 if (!evt->buf) 348 return ERR_PTR(-ENOMEM); 349 350 return evt; 351 } 352 353 /** 354 * dwc3_free_event_buffers - frees all allocated event buffers 355 * @dwc: Pointer to our controller context structure 356 */ 357 static void dwc3_free_event_buffers(struct dwc3 *dwc) 358 { 359 struct dwc3_event_buffer *evt; 360 361 evt = dwc->ev_buf; 362 if (evt) 363 dwc3_free_one_event_buffer(dwc, evt); 364 } 365 366 /** 367 * dwc3_alloc_event_buffers - Allocates @num event buffers of size @length 368 * @dwc: pointer to our controller context structure 369 * @length: size of event buffer 370 * 371 * Returns 0 on success otherwise negative errno. In the error case, dwc 372 * may contain some buffers allocated but not all which were requested. 373 */ 374 static int dwc3_alloc_event_buffers(struct dwc3 *dwc, unsigned length) 375 { 376 struct dwc3_event_buffer *evt; 377 378 evt = dwc3_alloc_one_event_buffer(dwc, length); 379 if (IS_ERR(evt)) { 380 dev_err(dwc->dev, "can't allocate event buffer\n"); 381 return PTR_ERR(evt); 382 } 383 dwc->ev_buf = evt; 384 385 return 0; 386 } 387 388 /** 389 * dwc3_event_buffers_setup - setup our allocated event buffers 390 * @dwc: pointer to our controller context structure 391 * 392 * Returns 0 on success otherwise negative errno. 393 */ 394 int dwc3_event_buffers_setup(struct dwc3 *dwc) 395 { 396 struct dwc3_event_buffer *evt; 397 398 evt = dwc->ev_buf; 399 evt->lpos = 0; 400 dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(0), 401 lower_32_bits(evt->dma)); 402 dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(0), 403 upper_32_bits(evt->dma)); 404 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0), 405 DWC3_GEVNTSIZ_SIZE(evt->length)); 406 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), 0); 407 408 return 0; 409 } 410 411 void dwc3_event_buffers_cleanup(struct dwc3 *dwc) 412 { 413 struct dwc3_event_buffer *evt; 414 415 evt = dwc->ev_buf; 416 417 evt->lpos = 0; 418 419 dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(0), 0); 420 dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(0), 0); 421 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0), DWC3_GEVNTSIZ_INTMASK 422 | DWC3_GEVNTSIZ_SIZE(0)); 423 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), 0); 424 } 425 426 static int dwc3_alloc_scratch_buffers(struct dwc3 *dwc) 427 { 428 if (!dwc->has_hibernation) 429 return 0; 430 431 if (!dwc->nr_scratch) 432 return 0; 433 434 dwc->scratchbuf = kmalloc_array(dwc->nr_scratch, 435 DWC3_SCRATCHBUF_SIZE, GFP_KERNEL); 436 if (!dwc->scratchbuf) 437 return -ENOMEM; 438 439 return 0; 440 } 441 442 static int dwc3_setup_scratch_buffers(struct dwc3 *dwc) 443 { 444 dma_addr_t scratch_addr; 445 u32 param; 446 int ret; 447 448 if (!dwc->has_hibernation) 449 return 0; 450 451 if (!dwc->nr_scratch) 452 return 0; 453 454 /* should never fall here */ 455 if (!WARN_ON(dwc->scratchbuf)) 456 return 0; 457 458 scratch_addr = dma_map_single(dwc->sysdev, dwc->scratchbuf, 459 dwc->nr_scratch * DWC3_SCRATCHBUF_SIZE, 460 DMA_BIDIRECTIONAL); 461 if (dma_mapping_error(dwc->sysdev, scratch_addr)) { 462 dev_err(dwc->sysdev, "failed to map scratch buffer\n"); 463 ret = -EFAULT; 464 goto err0; 465 } 466 467 dwc->scratch_addr = scratch_addr; 468 469 param = lower_32_bits(scratch_addr); 470 471 ret = dwc3_send_gadget_generic_command(dwc, 472 DWC3_DGCMD_SET_SCRATCHPAD_ADDR_LO, param); 473 if (ret < 0) 474 goto err1; 475 476 param = upper_32_bits(scratch_addr); 477 478 ret = dwc3_send_gadget_generic_command(dwc, 479 DWC3_DGCMD_SET_SCRATCHPAD_ADDR_HI, param); 480 if (ret < 0) 481 goto err1; 482 483 return 0; 484 485 err1: 486 dma_unmap_single(dwc->sysdev, dwc->scratch_addr, dwc->nr_scratch * 487 DWC3_SCRATCHBUF_SIZE, DMA_BIDIRECTIONAL); 488 489 err0: 490 return ret; 491 } 492 493 static void dwc3_free_scratch_buffers(struct dwc3 *dwc) 494 { 495 if (!dwc->has_hibernation) 496 return; 497 498 if (!dwc->nr_scratch) 499 return; 500 501 /* should never fall here */ 502 if (!WARN_ON(dwc->scratchbuf)) 503 return; 504 505 dma_unmap_single(dwc->sysdev, dwc->scratch_addr, dwc->nr_scratch * 506 DWC3_SCRATCHBUF_SIZE, DMA_BIDIRECTIONAL); 507 kfree(dwc->scratchbuf); 508 } 509 510 static void dwc3_core_num_eps(struct dwc3 *dwc) 511 { 512 struct dwc3_hwparams *parms = &dwc->hwparams; 513 514 dwc->num_eps = DWC3_NUM_EPS(parms); 515 } 516 517 static void dwc3_cache_hwparams(struct dwc3 *dwc) 518 { 519 struct dwc3_hwparams *parms = &dwc->hwparams; 520 521 parms->hwparams0 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS0); 522 parms->hwparams1 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS1); 523 parms->hwparams2 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS2); 524 parms->hwparams3 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS3); 525 parms->hwparams4 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS4); 526 parms->hwparams5 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS5); 527 parms->hwparams6 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS6); 528 parms->hwparams7 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS7); 529 parms->hwparams8 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS8); 530 } 531 532 static int dwc3_core_ulpi_init(struct dwc3 *dwc) 533 { 534 int intf; 535 int ret = 0; 536 537 intf = DWC3_GHWPARAMS3_HSPHY_IFC(dwc->hwparams.hwparams3); 538 539 if (intf == DWC3_GHWPARAMS3_HSPHY_IFC_ULPI || 540 (intf == DWC3_GHWPARAMS3_HSPHY_IFC_UTMI_ULPI && 541 dwc->hsphy_interface && 542 !strncmp(dwc->hsphy_interface, "ulpi", 4))) 543 ret = dwc3_ulpi_init(dwc); 544 545 return ret; 546 } 547 548 /** 549 * dwc3_phy_setup - Configure USB PHY Interface of DWC3 Core 550 * @dwc: Pointer to our controller context structure 551 * 552 * Returns 0 on success. The USB PHY interfaces are configured but not 553 * initialized. The PHY interfaces and the PHYs get initialized together with 554 * the core in dwc3_core_init. 555 */ 556 static int dwc3_phy_setup(struct dwc3 *dwc) 557 { 558 u32 reg; 559 560 reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0)); 561 562 /* 563 * Make sure UX_EXIT_PX is cleared as that causes issues with some 564 * PHYs. Also, this bit is not supposed to be used in normal operation. 565 */ 566 reg &= ~DWC3_GUSB3PIPECTL_UX_EXIT_PX; 567 568 /* 569 * Above 1.94a, it is recommended to set DWC3_GUSB3PIPECTL_SUSPHY 570 * to '0' during coreConsultant configuration. So default value 571 * will be '0' when the core is reset. Application needs to set it 572 * to '1' after the core initialization is completed. 573 */ 574 if (dwc->revision > DWC3_REVISION_194A) 575 reg |= DWC3_GUSB3PIPECTL_SUSPHY; 576 577 if (dwc->u2ss_inp3_quirk) 578 reg |= DWC3_GUSB3PIPECTL_U2SSINP3OK; 579 580 if (dwc->dis_rxdet_inp3_quirk) 581 reg |= DWC3_GUSB3PIPECTL_DISRXDETINP3; 582 583 if (dwc->req_p1p2p3_quirk) 584 reg |= DWC3_GUSB3PIPECTL_REQP1P2P3; 585 586 if (dwc->del_p1p2p3_quirk) 587 reg |= DWC3_GUSB3PIPECTL_DEP1P2P3_EN; 588 589 if (dwc->del_phy_power_chg_quirk) 590 reg |= DWC3_GUSB3PIPECTL_DEPOCHANGE; 591 592 if (dwc->lfps_filter_quirk) 593 reg |= DWC3_GUSB3PIPECTL_LFPSFILT; 594 595 if (dwc->rx_detect_poll_quirk) 596 reg |= DWC3_GUSB3PIPECTL_RX_DETOPOLL; 597 598 if (dwc->tx_de_emphasis_quirk) 599 reg |= DWC3_GUSB3PIPECTL_TX_DEEPH(dwc->tx_de_emphasis); 600 601 if (dwc->dis_u3_susphy_quirk) 602 reg &= ~DWC3_GUSB3PIPECTL_SUSPHY; 603 604 if (dwc->dis_del_phy_power_chg_quirk) 605 reg &= ~DWC3_GUSB3PIPECTL_DEPOCHANGE; 606 607 dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg); 608 609 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0)); 610 611 /* Select the HS PHY interface */ 612 switch (DWC3_GHWPARAMS3_HSPHY_IFC(dwc->hwparams.hwparams3)) { 613 case DWC3_GHWPARAMS3_HSPHY_IFC_UTMI_ULPI: 614 if (dwc->hsphy_interface && 615 !strncmp(dwc->hsphy_interface, "utmi", 4)) { 616 reg &= ~DWC3_GUSB2PHYCFG_ULPI_UTMI; 617 break; 618 } else if (dwc->hsphy_interface && 619 !strncmp(dwc->hsphy_interface, "ulpi", 4)) { 620 reg |= DWC3_GUSB2PHYCFG_ULPI_UTMI; 621 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg); 622 } else { 623 /* Relying on default value. */ 624 if (!(reg & DWC3_GUSB2PHYCFG_ULPI_UTMI)) 625 break; 626 } 627 /* FALLTHROUGH */ 628 case DWC3_GHWPARAMS3_HSPHY_IFC_ULPI: 629 /* FALLTHROUGH */ 630 default: 631 break; 632 } 633 634 switch (dwc->hsphy_mode) { 635 case USBPHY_INTERFACE_MODE_UTMI: 636 reg &= ~(DWC3_GUSB2PHYCFG_PHYIF_MASK | 637 DWC3_GUSB2PHYCFG_USBTRDTIM_MASK); 638 reg |= DWC3_GUSB2PHYCFG_PHYIF(UTMI_PHYIF_8_BIT) | 639 DWC3_GUSB2PHYCFG_USBTRDTIM(USBTRDTIM_UTMI_8_BIT); 640 break; 641 case USBPHY_INTERFACE_MODE_UTMIW: 642 reg &= ~(DWC3_GUSB2PHYCFG_PHYIF_MASK | 643 DWC3_GUSB2PHYCFG_USBTRDTIM_MASK); 644 reg |= DWC3_GUSB2PHYCFG_PHYIF(UTMI_PHYIF_16_BIT) | 645 DWC3_GUSB2PHYCFG_USBTRDTIM(USBTRDTIM_UTMI_16_BIT); 646 break; 647 default: 648 break; 649 } 650 651 /* 652 * Above 1.94a, it is recommended to set DWC3_GUSB2PHYCFG_SUSPHY to 653 * '0' during coreConsultant configuration. So default value will 654 * be '0' when the core is reset. Application needs to set it to 655 * '1' after the core initialization is completed. 656 */ 657 if (dwc->revision > DWC3_REVISION_194A) 658 reg |= DWC3_GUSB2PHYCFG_SUSPHY; 659 660 if (dwc->dis_u2_susphy_quirk) 661 reg &= ~DWC3_GUSB2PHYCFG_SUSPHY; 662 663 if (dwc->dis_enblslpm_quirk) 664 reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM; 665 else 666 reg |= DWC3_GUSB2PHYCFG_ENBLSLPM; 667 668 if (dwc->dis_u2_freeclk_exists_quirk) 669 reg &= ~DWC3_GUSB2PHYCFG_U2_FREECLK_EXISTS; 670 671 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg); 672 673 return 0; 674 } 675 676 static void dwc3_core_exit(struct dwc3 *dwc) 677 { 678 dwc3_event_buffers_cleanup(dwc); 679 680 usb_phy_shutdown(dwc->usb2_phy); 681 usb_phy_shutdown(dwc->usb3_phy); 682 phy_exit(dwc->usb2_generic_phy); 683 phy_exit(dwc->usb3_generic_phy); 684 685 usb_phy_set_suspend(dwc->usb2_phy, 1); 686 usb_phy_set_suspend(dwc->usb3_phy, 1); 687 phy_power_off(dwc->usb2_generic_phy); 688 phy_power_off(dwc->usb3_generic_phy); 689 clk_bulk_disable(dwc->num_clks, dwc->clks); 690 clk_bulk_unprepare(dwc->num_clks, dwc->clks); 691 reset_control_assert(dwc->reset); 692 } 693 694 static bool dwc3_core_is_valid(struct dwc3 *dwc) 695 { 696 u32 reg; 697 698 reg = dwc3_readl(dwc->regs, DWC3_GSNPSID); 699 700 /* This should read as U3 followed by revision number */ 701 if ((reg & DWC3_GSNPSID_MASK) == 0x55330000) { 702 /* Detected DWC_usb3 IP */ 703 dwc->revision = reg; 704 } else if ((reg & DWC3_GSNPSID_MASK) == 0x33310000) { 705 /* Detected DWC_usb31 IP */ 706 dwc->revision = dwc3_readl(dwc->regs, DWC3_VER_NUMBER); 707 dwc->revision |= DWC3_REVISION_IS_DWC31; 708 dwc->version_type = dwc3_readl(dwc->regs, DWC3_VER_TYPE); 709 } else { 710 return false; 711 } 712 713 return true; 714 } 715 716 static void dwc3_core_setup_global_control(struct dwc3 *dwc) 717 { 718 u32 hwparams4 = dwc->hwparams.hwparams4; 719 u32 reg; 720 721 reg = dwc3_readl(dwc->regs, DWC3_GCTL); 722 reg &= ~DWC3_GCTL_SCALEDOWN_MASK; 723 724 switch (DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1)) { 725 case DWC3_GHWPARAMS1_EN_PWROPT_CLK: 726 /** 727 * WORKAROUND: DWC3 revisions between 2.10a and 2.50a have an 728 * issue which would cause xHCI compliance tests to fail. 729 * 730 * Because of that we cannot enable clock gating on such 731 * configurations. 732 * 733 * Refers to: 734 * 735 * STAR#9000588375: Clock Gating, SOF Issues when ref_clk-Based 736 * SOF/ITP Mode Used 737 */ 738 if ((dwc->dr_mode == USB_DR_MODE_HOST || 739 dwc->dr_mode == USB_DR_MODE_OTG) && 740 (dwc->revision >= DWC3_REVISION_210A && 741 dwc->revision <= DWC3_REVISION_250A)) 742 reg |= DWC3_GCTL_DSBLCLKGTNG | DWC3_GCTL_SOFITPSYNC; 743 else 744 reg &= ~DWC3_GCTL_DSBLCLKGTNG; 745 break; 746 case DWC3_GHWPARAMS1_EN_PWROPT_HIB: 747 /* enable hibernation here */ 748 dwc->nr_scratch = DWC3_GHWPARAMS4_HIBER_SCRATCHBUFS(hwparams4); 749 750 /* 751 * REVISIT Enabling this bit so that host-mode hibernation 752 * will work. Device-mode hibernation is not yet implemented. 753 */ 754 reg |= DWC3_GCTL_GBLHIBERNATIONEN; 755 break; 756 default: 757 /* nothing */ 758 break; 759 } 760 761 /* check if current dwc3 is on simulation board */ 762 if (dwc->hwparams.hwparams6 & DWC3_GHWPARAMS6_EN_FPGA) { 763 dev_info(dwc->dev, "Running with FPGA optimizations\n"); 764 dwc->is_fpga = true; 765 } 766 767 WARN_ONCE(dwc->disable_scramble_quirk && !dwc->is_fpga, 768 "disable_scramble cannot be used on non-FPGA builds\n"); 769 770 if (dwc->disable_scramble_quirk && dwc->is_fpga) 771 reg |= DWC3_GCTL_DISSCRAMBLE; 772 else 773 reg &= ~DWC3_GCTL_DISSCRAMBLE; 774 775 if (dwc->u2exit_lfps_quirk) 776 reg |= DWC3_GCTL_U2EXIT_LFPS; 777 778 /* 779 * WORKAROUND: DWC3 revisions <1.90a have a bug 780 * where the device can fail to connect at SuperSpeed 781 * and falls back to high-speed mode which causes 782 * the device to enter a Connect/Disconnect loop 783 */ 784 if (dwc->revision < DWC3_REVISION_190A) 785 reg |= DWC3_GCTL_U2RSTECN; 786 787 dwc3_writel(dwc->regs, DWC3_GCTL, reg); 788 } 789 790 static int dwc3_core_get_phy(struct dwc3 *dwc); 791 static int dwc3_core_ulpi_init(struct dwc3 *dwc); 792 793 /* set global incr burst type configuration registers */ 794 static void dwc3_set_incr_burst_type(struct dwc3 *dwc) 795 { 796 struct device *dev = dwc->dev; 797 /* incrx_mode : for INCR burst type. */ 798 bool incrx_mode; 799 /* incrx_size : for size of INCRX burst. */ 800 u32 incrx_size; 801 u32 *vals; 802 u32 cfg; 803 int ntype; 804 int ret; 805 int i; 806 807 cfg = dwc3_readl(dwc->regs, DWC3_GSBUSCFG0); 808 809 /* 810 * Handle property "snps,incr-burst-type-adjustment". 811 * Get the number of value from this property: 812 * result <= 0, means this property is not supported. 813 * result = 1, means INCRx burst mode supported. 814 * result > 1, means undefined length burst mode supported. 815 */ 816 ntype = device_property_read_u32_array(dev, 817 "snps,incr-burst-type-adjustment", NULL, 0); 818 if (ntype <= 0) 819 return; 820 821 vals = kcalloc(ntype, sizeof(u32), GFP_KERNEL); 822 if (!vals) { 823 dev_err(dev, "Error to get memory\n"); 824 return; 825 } 826 827 /* Get INCR burst type, and parse it */ 828 ret = device_property_read_u32_array(dev, 829 "snps,incr-burst-type-adjustment", vals, ntype); 830 if (ret) { 831 dev_err(dev, "Error to get property\n"); 832 return; 833 } 834 835 incrx_size = *vals; 836 837 if (ntype > 1) { 838 /* INCRX (undefined length) burst mode */ 839 incrx_mode = INCRX_UNDEF_LENGTH_BURST_MODE; 840 for (i = 1; i < ntype; i++) { 841 if (vals[i] > incrx_size) 842 incrx_size = vals[i]; 843 } 844 } else { 845 /* INCRX burst mode */ 846 incrx_mode = INCRX_BURST_MODE; 847 } 848 849 /* Enable Undefined Length INCR Burst and Enable INCRx Burst */ 850 cfg &= ~DWC3_GSBUSCFG0_INCRBRST_MASK; 851 if (incrx_mode) 852 cfg |= DWC3_GSBUSCFG0_INCRBRSTENA; 853 switch (incrx_size) { 854 case 256: 855 cfg |= DWC3_GSBUSCFG0_INCR256BRSTENA; 856 break; 857 case 128: 858 cfg |= DWC3_GSBUSCFG0_INCR128BRSTENA; 859 break; 860 case 64: 861 cfg |= DWC3_GSBUSCFG0_INCR64BRSTENA; 862 break; 863 case 32: 864 cfg |= DWC3_GSBUSCFG0_INCR32BRSTENA; 865 break; 866 case 16: 867 cfg |= DWC3_GSBUSCFG0_INCR16BRSTENA; 868 break; 869 case 8: 870 cfg |= DWC3_GSBUSCFG0_INCR8BRSTENA; 871 break; 872 case 4: 873 cfg |= DWC3_GSBUSCFG0_INCR4BRSTENA; 874 break; 875 case 1: 876 break; 877 default: 878 dev_err(dev, "Invalid property\n"); 879 break; 880 } 881 882 dwc3_writel(dwc->regs, DWC3_GSBUSCFG0, cfg); 883 } 884 885 /** 886 * dwc3_core_init - Low-level initialization of DWC3 Core 887 * @dwc: Pointer to our controller context structure 888 * 889 * Returns 0 on success otherwise negative errno. 890 */ 891 static int dwc3_core_init(struct dwc3 *dwc) 892 { 893 u32 reg; 894 int ret; 895 896 if (!dwc3_core_is_valid(dwc)) { 897 dev_err(dwc->dev, "this is not a DesignWare USB3 DRD Core\n"); 898 ret = -ENODEV; 899 goto err0; 900 } 901 902 /* 903 * Write Linux Version Code to our GUID register so it's easy to figure 904 * out which kernel version a bug was found. 905 */ 906 dwc3_writel(dwc->regs, DWC3_GUID, LINUX_VERSION_CODE); 907 908 /* Handle USB2.0-only core configuration */ 909 if (DWC3_GHWPARAMS3_SSPHY_IFC(dwc->hwparams.hwparams3) == 910 DWC3_GHWPARAMS3_SSPHY_IFC_DIS) { 911 if (dwc->maximum_speed == USB_SPEED_SUPER) 912 dwc->maximum_speed = USB_SPEED_HIGH; 913 } 914 915 ret = dwc3_phy_setup(dwc); 916 if (ret) 917 goto err0; 918 919 if (!dwc->ulpi_ready) { 920 ret = dwc3_core_ulpi_init(dwc); 921 if (ret) 922 goto err0; 923 dwc->ulpi_ready = true; 924 } 925 926 if (!dwc->phys_ready) { 927 ret = dwc3_core_get_phy(dwc); 928 if (ret) 929 goto err0a; 930 dwc->phys_ready = true; 931 } 932 933 ret = dwc3_core_soft_reset(dwc); 934 if (ret) 935 goto err0a; 936 937 dwc3_core_setup_global_control(dwc); 938 dwc3_core_num_eps(dwc); 939 940 ret = dwc3_setup_scratch_buffers(dwc); 941 if (ret) 942 goto err1; 943 944 /* Adjust Frame Length */ 945 dwc3_frame_length_adjustment(dwc); 946 947 dwc3_set_incr_burst_type(dwc); 948 949 usb_phy_set_suspend(dwc->usb2_phy, 0); 950 usb_phy_set_suspend(dwc->usb3_phy, 0); 951 ret = phy_power_on(dwc->usb2_generic_phy); 952 if (ret < 0) 953 goto err2; 954 955 ret = phy_power_on(dwc->usb3_generic_phy); 956 if (ret < 0) 957 goto err3; 958 959 ret = dwc3_event_buffers_setup(dwc); 960 if (ret) { 961 dev_err(dwc->dev, "failed to setup event buffers\n"); 962 goto err4; 963 } 964 965 /* 966 * ENDXFER polling is available on version 3.10a and later of 967 * the DWC_usb3 controller. It is NOT available in the 968 * DWC_usb31 controller. 969 */ 970 if (!dwc3_is_usb31(dwc) && dwc->revision >= DWC3_REVISION_310A) { 971 reg = dwc3_readl(dwc->regs, DWC3_GUCTL2); 972 reg |= DWC3_GUCTL2_RST_ACTBITLATER; 973 dwc3_writel(dwc->regs, DWC3_GUCTL2, reg); 974 } 975 976 if (dwc->revision >= DWC3_REVISION_250A) { 977 reg = dwc3_readl(dwc->regs, DWC3_GUCTL1); 978 979 /* 980 * Enable hardware control of sending remote wakeup 981 * in HS when the device is in the L1 state. 982 */ 983 if (dwc->revision >= DWC3_REVISION_290A) 984 reg |= DWC3_GUCTL1_DEV_L1_EXIT_BY_HW; 985 986 if (dwc->dis_tx_ipgap_linecheck_quirk) 987 reg |= DWC3_GUCTL1_TX_IPGAP_LINECHECK_DIS; 988 989 dwc3_writel(dwc->regs, DWC3_GUCTL1, reg); 990 } 991 992 if (dwc->dr_mode == USB_DR_MODE_HOST || 993 dwc->dr_mode == USB_DR_MODE_OTG) { 994 reg = dwc3_readl(dwc->regs, DWC3_GUCTL); 995 996 /* 997 * Enable Auto retry Feature to make the controller operating in 998 * Host mode on seeing transaction errors(CRC errors or internal 999 * overrun scenerios) on IN transfers to reply to the device 1000 * with a non-terminating retry ACK (i.e, an ACK transcation 1001 * packet with Retry=1 & Nump != 0) 1002 */ 1003 reg |= DWC3_GUCTL_HSTINAUTORETRY; 1004 1005 dwc3_writel(dwc->regs, DWC3_GUCTL, reg); 1006 } 1007 1008 /* 1009 * Must config both number of packets and max burst settings to enable 1010 * RX and/or TX threshold. 1011 */ 1012 if (dwc3_is_usb31(dwc) && dwc->dr_mode == USB_DR_MODE_HOST) { 1013 u8 rx_thr_num = dwc->rx_thr_num_pkt_prd; 1014 u8 rx_maxburst = dwc->rx_max_burst_prd; 1015 u8 tx_thr_num = dwc->tx_thr_num_pkt_prd; 1016 u8 tx_maxburst = dwc->tx_max_burst_prd; 1017 1018 if (rx_thr_num && rx_maxburst) { 1019 reg = dwc3_readl(dwc->regs, DWC3_GRXTHRCFG); 1020 reg |= DWC31_RXTHRNUMPKTSEL_PRD; 1021 1022 reg &= ~DWC31_RXTHRNUMPKT_PRD(~0); 1023 reg |= DWC31_RXTHRNUMPKT_PRD(rx_thr_num); 1024 1025 reg &= ~DWC31_MAXRXBURSTSIZE_PRD(~0); 1026 reg |= DWC31_MAXRXBURSTSIZE_PRD(rx_maxburst); 1027 1028 dwc3_writel(dwc->regs, DWC3_GRXTHRCFG, reg); 1029 } 1030 1031 if (tx_thr_num && tx_maxburst) { 1032 reg = dwc3_readl(dwc->regs, DWC3_GTXTHRCFG); 1033 reg |= DWC31_TXTHRNUMPKTSEL_PRD; 1034 1035 reg &= ~DWC31_TXTHRNUMPKT_PRD(~0); 1036 reg |= DWC31_TXTHRNUMPKT_PRD(tx_thr_num); 1037 1038 reg &= ~DWC31_MAXTXBURSTSIZE_PRD(~0); 1039 reg |= DWC31_MAXTXBURSTSIZE_PRD(tx_maxburst); 1040 1041 dwc3_writel(dwc->regs, DWC3_GTXTHRCFG, reg); 1042 } 1043 } 1044 1045 return 0; 1046 1047 err4: 1048 phy_power_off(dwc->usb3_generic_phy); 1049 1050 err3: 1051 phy_power_off(dwc->usb2_generic_phy); 1052 1053 err2: 1054 usb_phy_set_suspend(dwc->usb2_phy, 1); 1055 usb_phy_set_suspend(dwc->usb3_phy, 1); 1056 1057 err1: 1058 usb_phy_shutdown(dwc->usb2_phy); 1059 usb_phy_shutdown(dwc->usb3_phy); 1060 phy_exit(dwc->usb2_generic_phy); 1061 phy_exit(dwc->usb3_generic_phy); 1062 1063 err0a: 1064 dwc3_ulpi_exit(dwc); 1065 1066 err0: 1067 return ret; 1068 } 1069 1070 static int dwc3_core_get_phy(struct dwc3 *dwc) 1071 { 1072 struct device *dev = dwc->dev; 1073 struct device_node *node = dev->of_node; 1074 int ret; 1075 1076 if (node) { 1077 dwc->usb2_phy = devm_usb_get_phy_by_phandle(dev, "usb-phy", 0); 1078 dwc->usb3_phy = devm_usb_get_phy_by_phandle(dev, "usb-phy", 1); 1079 } else { 1080 dwc->usb2_phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB2); 1081 dwc->usb3_phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB3); 1082 } 1083 1084 if (IS_ERR(dwc->usb2_phy)) { 1085 ret = PTR_ERR(dwc->usb2_phy); 1086 if (ret == -ENXIO || ret == -ENODEV) { 1087 dwc->usb2_phy = NULL; 1088 } else if (ret == -EPROBE_DEFER) { 1089 return ret; 1090 } else { 1091 dev_err(dev, "no usb2 phy configured\n"); 1092 return ret; 1093 } 1094 } 1095 1096 if (IS_ERR(dwc->usb3_phy)) { 1097 ret = PTR_ERR(dwc->usb3_phy); 1098 if (ret == -ENXIO || ret == -ENODEV) { 1099 dwc->usb3_phy = NULL; 1100 } else if (ret == -EPROBE_DEFER) { 1101 return ret; 1102 } else { 1103 dev_err(dev, "no usb3 phy configured\n"); 1104 return ret; 1105 } 1106 } 1107 1108 dwc->usb2_generic_phy = devm_phy_get(dev, "usb2-phy"); 1109 if (IS_ERR(dwc->usb2_generic_phy)) { 1110 ret = PTR_ERR(dwc->usb2_generic_phy); 1111 if (ret == -ENOSYS || ret == -ENODEV) { 1112 dwc->usb2_generic_phy = NULL; 1113 } else if (ret == -EPROBE_DEFER) { 1114 return ret; 1115 } else { 1116 dev_err(dev, "no usb2 phy configured\n"); 1117 return ret; 1118 } 1119 } 1120 1121 dwc->usb3_generic_phy = devm_phy_get(dev, "usb3-phy"); 1122 if (IS_ERR(dwc->usb3_generic_phy)) { 1123 ret = PTR_ERR(dwc->usb3_generic_phy); 1124 if (ret == -ENOSYS || ret == -ENODEV) { 1125 dwc->usb3_generic_phy = NULL; 1126 } else if (ret == -EPROBE_DEFER) { 1127 return ret; 1128 } else { 1129 dev_err(dev, "no usb3 phy configured\n"); 1130 return ret; 1131 } 1132 } 1133 1134 return 0; 1135 } 1136 1137 static int dwc3_core_init_mode(struct dwc3 *dwc) 1138 { 1139 struct device *dev = dwc->dev; 1140 int ret; 1141 1142 switch (dwc->dr_mode) { 1143 case USB_DR_MODE_PERIPHERAL: 1144 dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_DEVICE); 1145 1146 if (dwc->usb2_phy) 1147 otg_set_vbus(dwc->usb2_phy->otg, false); 1148 phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_DEVICE); 1149 phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_DEVICE); 1150 1151 ret = dwc3_gadget_init(dwc); 1152 if (ret) { 1153 if (ret != -EPROBE_DEFER) 1154 dev_err(dev, "failed to initialize gadget\n"); 1155 return ret; 1156 } 1157 break; 1158 case USB_DR_MODE_HOST: 1159 dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_HOST); 1160 1161 if (dwc->usb2_phy) 1162 otg_set_vbus(dwc->usb2_phy->otg, true); 1163 phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_HOST); 1164 phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_HOST); 1165 1166 ret = dwc3_host_init(dwc); 1167 if (ret) { 1168 if (ret != -EPROBE_DEFER) 1169 dev_err(dev, "failed to initialize host\n"); 1170 return ret; 1171 } 1172 phy_calibrate(dwc->usb2_generic_phy); 1173 break; 1174 case USB_DR_MODE_OTG: 1175 INIT_WORK(&dwc->drd_work, __dwc3_set_mode); 1176 ret = dwc3_drd_init(dwc); 1177 if (ret) { 1178 if (ret != -EPROBE_DEFER) 1179 dev_err(dev, "failed to initialize dual-role\n"); 1180 return ret; 1181 } 1182 break; 1183 default: 1184 dev_err(dev, "Unsupported mode of operation %d\n", dwc->dr_mode); 1185 return -EINVAL; 1186 } 1187 1188 return 0; 1189 } 1190 1191 static void dwc3_core_exit_mode(struct dwc3 *dwc) 1192 { 1193 switch (dwc->dr_mode) { 1194 case USB_DR_MODE_PERIPHERAL: 1195 dwc3_gadget_exit(dwc); 1196 break; 1197 case USB_DR_MODE_HOST: 1198 dwc3_host_exit(dwc); 1199 break; 1200 case USB_DR_MODE_OTG: 1201 dwc3_drd_exit(dwc); 1202 break; 1203 default: 1204 /* do nothing */ 1205 break; 1206 } 1207 } 1208 1209 static void dwc3_get_properties(struct dwc3 *dwc) 1210 { 1211 struct device *dev = dwc->dev; 1212 u8 lpm_nyet_threshold; 1213 u8 tx_de_emphasis; 1214 u8 hird_threshold; 1215 u8 rx_thr_num_pkt_prd; 1216 u8 rx_max_burst_prd; 1217 u8 tx_thr_num_pkt_prd; 1218 u8 tx_max_burst_prd; 1219 1220 /* default to highest possible threshold */ 1221 lpm_nyet_threshold = 0xff; 1222 1223 /* default to -3.5dB de-emphasis */ 1224 tx_de_emphasis = 1; 1225 1226 /* 1227 * default to assert utmi_sleep_n and use maximum allowed HIRD 1228 * threshold value of 0b1100 1229 */ 1230 hird_threshold = 12; 1231 1232 dwc->maximum_speed = usb_get_maximum_speed(dev); 1233 dwc->dr_mode = usb_get_dr_mode(dev); 1234 dwc->hsphy_mode = of_usb_get_phy_mode(dev->of_node); 1235 1236 dwc->sysdev_is_parent = device_property_read_bool(dev, 1237 "linux,sysdev_is_parent"); 1238 if (dwc->sysdev_is_parent) 1239 dwc->sysdev = dwc->dev->parent; 1240 else 1241 dwc->sysdev = dwc->dev; 1242 1243 dwc->has_lpm_erratum = device_property_read_bool(dev, 1244 "snps,has-lpm-erratum"); 1245 device_property_read_u8(dev, "snps,lpm-nyet-threshold", 1246 &lpm_nyet_threshold); 1247 dwc->is_utmi_l1_suspend = device_property_read_bool(dev, 1248 "snps,is-utmi-l1-suspend"); 1249 device_property_read_u8(dev, "snps,hird-threshold", 1250 &hird_threshold); 1251 dwc->dis_start_transfer_quirk = device_property_read_bool(dev, 1252 "snps,dis-start-transfer-quirk"); 1253 dwc->usb3_lpm_capable = device_property_read_bool(dev, 1254 "snps,usb3_lpm_capable"); 1255 dwc->usb2_lpm_disable = device_property_read_bool(dev, 1256 "snps,usb2-lpm-disable"); 1257 device_property_read_u8(dev, "snps,rx-thr-num-pkt-prd", 1258 &rx_thr_num_pkt_prd); 1259 device_property_read_u8(dev, "snps,rx-max-burst-prd", 1260 &rx_max_burst_prd); 1261 device_property_read_u8(dev, "snps,tx-thr-num-pkt-prd", 1262 &tx_thr_num_pkt_prd); 1263 device_property_read_u8(dev, "snps,tx-max-burst-prd", 1264 &tx_max_burst_prd); 1265 1266 dwc->disable_scramble_quirk = device_property_read_bool(dev, 1267 "snps,disable_scramble_quirk"); 1268 dwc->u2exit_lfps_quirk = device_property_read_bool(dev, 1269 "snps,u2exit_lfps_quirk"); 1270 dwc->u2ss_inp3_quirk = device_property_read_bool(dev, 1271 "snps,u2ss_inp3_quirk"); 1272 dwc->req_p1p2p3_quirk = device_property_read_bool(dev, 1273 "snps,req_p1p2p3_quirk"); 1274 dwc->del_p1p2p3_quirk = device_property_read_bool(dev, 1275 "snps,del_p1p2p3_quirk"); 1276 dwc->del_phy_power_chg_quirk = device_property_read_bool(dev, 1277 "snps,del_phy_power_chg_quirk"); 1278 dwc->lfps_filter_quirk = device_property_read_bool(dev, 1279 "snps,lfps_filter_quirk"); 1280 dwc->rx_detect_poll_quirk = device_property_read_bool(dev, 1281 "snps,rx_detect_poll_quirk"); 1282 dwc->dis_u3_susphy_quirk = device_property_read_bool(dev, 1283 "snps,dis_u3_susphy_quirk"); 1284 dwc->dis_u2_susphy_quirk = device_property_read_bool(dev, 1285 "snps,dis_u2_susphy_quirk"); 1286 dwc->dis_enblslpm_quirk = device_property_read_bool(dev, 1287 "snps,dis_enblslpm_quirk"); 1288 dwc->dis_rxdet_inp3_quirk = device_property_read_bool(dev, 1289 "snps,dis_rxdet_inp3_quirk"); 1290 dwc->dis_u2_freeclk_exists_quirk = device_property_read_bool(dev, 1291 "snps,dis-u2-freeclk-exists-quirk"); 1292 dwc->dis_del_phy_power_chg_quirk = device_property_read_bool(dev, 1293 "snps,dis-del-phy-power-chg-quirk"); 1294 dwc->dis_tx_ipgap_linecheck_quirk = device_property_read_bool(dev, 1295 "snps,dis-tx-ipgap-linecheck-quirk"); 1296 1297 dwc->tx_de_emphasis_quirk = device_property_read_bool(dev, 1298 "snps,tx_de_emphasis_quirk"); 1299 device_property_read_u8(dev, "snps,tx_de_emphasis", 1300 &tx_de_emphasis); 1301 device_property_read_string(dev, "snps,hsphy_interface", 1302 &dwc->hsphy_interface); 1303 device_property_read_u32(dev, "snps,quirk-frame-length-adjustment", 1304 &dwc->fladj); 1305 1306 dwc->dis_metastability_quirk = device_property_read_bool(dev, 1307 "snps,dis_metastability_quirk"); 1308 1309 dwc->lpm_nyet_threshold = lpm_nyet_threshold; 1310 dwc->tx_de_emphasis = tx_de_emphasis; 1311 1312 dwc->hird_threshold = hird_threshold 1313 | (dwc->is_utmi_l1_suspend << 4); 1314 1315 dwc->rx_thr_num_pkt_prd = rx_thr_num_pkt_prd; 1316 dwc->rx_max_burst_prd = rx_max_burst_prd; 1317 1318 dwc->tx_thr_num_pkt_prd = tx_thr_num_pkt_prd; 1319 dwc->tx_max_burst_prd = tx_max_burst_prd; 1320 1321 dwc->imod_interval = 0; 1322 } 1323 1324 /* check whether the core supports IMOD */ 1325 bool dwc3_has_imod(struct dwc3 *dwc) 1326 { 1327 return ((dwc3_is_usb3(dwc) && 1328 dwc->revision >= DWC3_REVISION_300A) || 1329 (dwc3_is_usb31(dwc) && 1330 dwc->revision >= DWC3_USB31_REVISION_120A)); 1331 } 1332 1333 static void dwc3_check_params(struct dwc3 *dwc) 1334 { 1335 struct device *dev = dwc->dev; 1336 1337 /* Check for proper value of imod_interval */ 1338 if (dwc->imod_interval && !dwc3_has_imod(dwc)) { 1339 dev_warn(dwc->dev, "Interrupt moderation not supported\n"); 1340 dwc->imod_interval = 0; 1341 } 1342 1343 /* 1344 * Workaround for STAR 9000961433 which affects only version 1345 * 3.00a of the DWC_usb3 core. This prevents the controller 1346 * interrupt from being masked while handling events. IMOD 1347 * allows us to work around this issue. Enable it for the 1348 * affected version. 1349 */ 1350 if (!dwc->imod_interval && 1351 (dwc->revision == DWC3_REVISION_300A)) 1352 dwc->imod_interval = 1; 1353 1354 /* Check the maximum_speed parameter */ 1355 switch (dwc->maximum_speed) { 1356 case USB_SPEED_LOW: 1357 case USB_SPEED_FULL: 1358 case USB_SPEED_HIGH: 1359 case USB_SPEED_SUPER: 1360 case USB_SPEED_SUPER_PLUS: 1361 break; 1362 default: 1363 dev_err(dev, "invalid maximum_speed parameter %d\n", 1364 dwc->maximum_speed); 1365 /* fall through */ 1366 case USB_SPEED_UNKNOWN: 1367 /* default to superspeed */ 1368 dwc->maximum_speed = USB_SPEED_SUPER; 1369 1370 /* 1371 * default to superspeed plus if we are capable. 1372 */ 1373 if (dwc3_is_usb31(dwc) && 1374 (DWC3_GHWPARAMS3_SSPHY_IFC(dwc->hwparams.hwparams3) == 1375 DWC3_GHWPARAMS3_SSPHY_IFC_GEN2)) 1376 dwc->maximum_speed = USB_SPEED_SUPER_PLUS; 1377 1378 break; 1379 } 1380 } 1381 1382 static int dwc3_probe(struct platform_device *pdev) 1383 { 1384 struct device *dev = &pdev->dev; 1385 struct resource *res, dwc_res; 1386 struct dwc3 *dwc; 1387 1388 int ret; 1389 1390 void __iomem *regs; 1391 1392 dwc = devm_kzalloc(dev, sizeof(*dwc), GFP_KERNEL); 1393 if (!dwc) 1394 return -ENOMEM; 1395 1396 dwc->clks = devm_kmemdup(dev, dwc3_core_clks, sizeof(dwc3_core_clks), 1397 GFP_KERNEL); 1398 if (!dwc->clks) 1399 return -ENOMEM; 1400 1401 dwc->dev = dev; 1402 1403 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1404 if (!res) { 1405 dev_err(dev, "missing memory resource\n"); 1406 return -ENODEV; 1407 } 1408 1409 dwc->xhci_resources[0].start = res->start; 1410 dwc->xhci_resources[0].end = dwc->xhci_resources[0].start + 1411 DWC3_XHCI_REGS_END; 1412 dwc->xhci_resources[0].flags = res->flags; 1413 dwc->xhci_resources[0].name = res->name; 1414 1415 /* 1416 * Request memory region but exclude xHCI regs, 1417 * since it will be requested by the xhci-plat driver. 1418 */ 1419 dwc_res = *res; 1420 dwc_res.start += DWC3_GLOBALS_REGS_START; 1421 1422 regs = devm_ioremap_resource(dev, &dwc_res); 1423 if (IS_ERR(regs)) 1424 return PTR_ERR(regs); 1425 1426 dwc->regs = regs; 1427 dwc->regs_size = resource_size(&dwc_res); 1428 1429 dwc3_get_properties(dwc); 1430 1431 dwc->reset = devm_reset_control_get_optional_shared(dev, NULL); 1432 if (IS_ERR(dwc->reset)) 1433 return PTR_ERR(dwc->reset); 1434 1435 if (dev->of_node) { 1436 dwc->num_clks = ARRAY_SIZE(dwc3_core_clks); 1437 1438 ret = clk_bulk_get(dev, dwc->num_clks, dwc->clks); 1439 if (ret == -EPROBE_DEFER) 1440 return ret; 1441 /* 1442 * Clocks are optional, but new DT platforms should support all 1443 * clocks as required by the DT-binding. 1444 */ 1445 if (ret) 1446 dwc->num_clks = 0; 1447 } 1448 1449 ret = reset_control_deassert(dwc->reset); 1450 if (ret) 1451 goto put_clks; 1452 1453 ret = clk_bulk_prepare(dwc->num_clks, dwc->clks); 1454 if (ret) 1455 goto assert_reset; 1456 1457 ret = clk_bulk_enable(dwc->num_clks, dwc->clks); 1458 if (ret) 1459 goto unprepare_clks; 1460 1461 platform_set_drvdata(pdev, dwc); 1462 dwc3_cache_hwparams(dwc); 1463 1464 spin_lock_init(&dwc->lock); 1465 1466 pm_runtime_set_active(dev); 1467 pm_runtime_use_autosuspend(dev); 1468 pm_runtime_set_autosuspend_delay(dev, DWC3_DEFAULT_AUTOSUSPEND_DELAY); 1469 pm_runtime_enable(dev); 1470 ret = pm_runtime_get_sync(dev); 1471 if (ret < 0) 1472 goto err1; 1473 1474 pm_runtime_forbid(dev); 1475 1476 ret = dwc3_alloc_event_buffers(dwc, DWC3_EVENT_BUFFERS_SIZE); 1477 if (ret) { 1478 dev_err(dwc->dev, "failed to allocate event buffers\n"); 1479 ret = -ENOMEM; 1480 goto err2; 1481 } 1482 1483 ret = dwc3_get_dr_mode(dwc); 1484 if (ret) 1485 goto err3; 1486 1487 ret = dwc3_alloc_scratch_buffers(dwc); 1488 if (ret) 1489 goto err3; 1490 1491 ret = dwc3_core_init(dwc); 1492 if (ret) { 1493 if (ret != -EPROBE_DEFER) 1494 dev_err(dev, "failed to initialize core: %d\n", ret); 1495 goto err4; 1496 } 1497 1498 dwc3_check_params(dwc); 1499 1500 ret = dwc3_core_init_mode(dwc); 1501 if (ret) 1502 goto err5; 1503 1504 dwc3_debugfs_init(dwc); 1505 pm_runtime_put(dev); 1506 1507 return 0; 1508 1509 err5: 1510 dwc3_event_buffers_cleanup(dwc); 1511 dwc3_ulpi_exit(dwc); 1512 1513 err4: 1514 dwc3_free_scratch_buffers(dwc); 1515 1516 err3: 1517 dwc3_free_event_buffers(dwc); 1518 1519 err2: 1520 pm_runtime_allow(&pdev->dev); 1521 1522 err1: 1523 pm_runtime_put_sync(&pdev->dev); 1524 pm_runtime_disable(&pdev->dev); 1525 1526 clk_bulk_disable(dwc->num_clks, dwc->clks); 1527 unprepare_clks: 1528 clk_bulk_unprepare(dwc->num_clks, dwc->clks); 1529 assert_reset: 1530 reset_control_assert(dwc->reset); 1531 put_clks: 1532 clk_bulk_put(dwc->num_clks, dwc->clks); 1533 1534 return ret; 1535 } 1536 1537 static int dwc3_remove(struct platform_device *pdev) 1538 { 1539 struct dwc3 *dwc = platform_get_drvdata(pdev); 1540 1541 pm_runtime_get_sync(&pdev->dev); 1542 1543 dwc3_debugfs_exit(dwc); 1544 dwc3_core_exit_mode(dwc); 1545 1546 dwc3_core_exit(dwc); 1547 dwc3_ulpi_exit(dwc); 1548 1549 pm_runtime_put_sync(&pdev->dev); 1550 pm_runtime_allow(&pdev->dev); 1551 pm_runtime_disable(&pdev->dev); 1552 1553 dwc3_free_event_buffers(dwc); 1554 dwc3_free_scratch_buffers(dwc); 1555 clk_bulk_put(dwc->num_clks, dwc->clks); 1556 1557 return 0; 1558 } 1559 1560 #ifdef CONFIG_PM 1561 static int dwc3_core_init_for_resume(struct dwc3 *dwc) 1562 { 1563 int ret; 1564 1565 ret = reset_control_deassert(dwc->reset); 1566 if (ret) 1567 return ret; 1568 1569 ret = clk_bulk_prepare(dwc->num_clks, dwc->clks); 1570 if (ret) 1571 goto assert_reset; 1572 1573 ret = clk_bulk_enable(dwc->num_clks, dwc->clks); 1574 if (ret) 1575 goto unprepare_clks; 1576 1577 ret = dwc3_core_init(dwc); 1578 if (ret) 1579 goto disable_clks; 1580 1581 return 0; 1582 1583 disable_clks: 1584 clk_bulk_disable(dwc->num_clks, dwc->clks); 1585 unprepare_clks: 1586 clk_bulk_unprepare(dwc->num_clks, dwc->clks); 1587 assert_reset: 1588 reset_control_assert(dwc->reset); 1589 1590 return ret; 1591 } 1592 1593 static int dwc3_suspend_common(struct dwc3 *dwc, pm_message_t msg) 1594 { 1595 unsigned long flags; 1596 u32 reg; 1597 1598 switch (dwc->current_dr_role) { 1599 case DWC3_GCTL_PRTCAP_DEVICE: 1600 spin_lock_irqsave(&dwc->lock, flags); 1601 dwc3_gadget_suspend(dwc); 1602 spin_unlock_irqrestore(&dwc->lock, flags); 1603 dwc3_core_exit(dwc); 1604 break; 1605 case DWC3_GCTL_PRTCAP_HOST: 1606 if (!PMSG_IS_AUTO(msg)) { 1607 dwc3_core_exit(dwc); 1608 break; 1609 } 1610 1611 /* Let controller to suspend HSPHY before PHY driver suspends */ 1612 if (dwc->dis_u2_susphy_quirk || 1613 dwc->dis_enblslpm_quirk) { 1614 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0)); 1615 reg |= DWC3_GUSB2PHYCFG_ENBLSLPM | 1616 DWC3_GUSB2PHYCFG_SUSPHY; 1617 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg); 1618 1619 /* Give some time for USB2 PHY to suspend */ 1620 usleep_range(5000, 6000); 1621 } 1622 1623 phy_pm_runtime_put_sync(dwc->usb2_generic_phy); 1624 phy_pm_runtime_put_sync(dwc->usb3_generic_phy); 1625 break; 1626 case DWC3_GCTL_PRTCAP_OTG: 1627 /* do nothing during runtime_suspend */ 1628 if (PMSG_IS_AUTO(msg)) 1629 break; 1630 1631 if (dwc->current_otg_role == DWC3_OTG_ROLE_DEVICE) { 1632 spin_lock_irqsave(&dwc->lock, flags); 1633 dwc3_gadget_suspend(dwc); 1634 spin_unlock_irqrestore(&dwc->lock, flags); 1635 } 1636 1637 dwc3_otg_exit(dwc); 1638 dwc3_core_exit(dwc); 1639 break; 1640 default: 1641 /* do nothing */ 1642 break; 1643 } 1644 1645 return 0; 1646 } 1647 1648 static int dwc3_resume_common(struct dwc3 *dwc, pm_message_t msg) 1649 { 1650 unsigned long flags; 1651 int ret; 1652 u32 reg; 1653 1654 switch (dwc->current_dr_role) { 1655 case DWC3_GCTL_PRTCAP_DEVICE: 1656 ret = dwc3_core_init_for_resume(dwc); 1657 if (ret) 1658 return ret; 1659 1660 dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_DEVICE); 1661 spin_lock_irqsave(&dwc->lock, flags); 1662 dwc3_gadget_resume(dwc); 1663 spin_unlock_irqrestore(&dwc->lock, flags); 1664 break; 1665 case DWC3_GCTL_PRTCAP_HOST: 1666 if (!PMSG_IS_AUTO(msg)) { 1667 ret = dwc3_core_init_for_resume(dwc); 1668 if (ret) 1669 return ret; 1670 dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_HOST); 1671 break; 1672 } 1673 /* Restore GUSB2PHYCFG bits that were modified in suspend */ 1674 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0)); 1675 if (dwc->dis_u2_susphy_quirk) 1676 reg &= ~DWC3_GUSB2PHYCFG_SUSPHY; 1677 1678 if (dwc->dis_enblslpm_quirk) 1679 reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM; 1680 1681 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg); 1682 1683 phy_pm_runtime_get_sync(dwc->usb2_generic_phy); 1684 phy_pm_runtime_get_sync(dwc->usb3_generic_phy); 1685 break; 1686 case DWC3_GCTL_PRTCAP_OTG: 1687 /* nothing to do on runtime_resume */ 1688 if (PMSG_IS_AUTO(msg)) 1689 break; 1690 1691 ret = dwc3_core_init(dwc); 1692 if (ret) 1693 return ret; 1694 1695 dwc3_set_prtcap(dwc, dwc->current_dr_role); 1696 1697 dwc3_otg_init(dwc); 1698 if (dwc->current_otg_role == DWC3_OTG_ROLE_HOST) { 1699 dwc3_otg_host_init(dwc); 1700 } else if (dwc->current_otg_role == DWC3_OTG_ROLE_DEVICE) { 1701 spin_lock_irqsave(&dwc->lock, flags); 1702 dwc3_gadget_resume(dwc); 1703 spin_unlock_irqrestore(&dwc->lock, flags); 1704 } 1705 1706 break; 1707 default: 1708 /* do nothing */ 1709 break; 1710 } 1711 1712 return 0; 1713 } 1714 1715 static int dwc3_runtime_checks(struct dwc3 *dwc) 1716 { 1717 switch (dwc->current_dr_role) { 1718 case DWC3_GCTL_PRTCAP_DEVICE: 1719 if (dwc->connected) 1720 return -EBUSY; 1721 break; 1722 case DWC3_GCTL_PRTCAP_HOST: 1723 default: 1724 /* do nothing */ 1725 break; 1726 } 1727 1728 return 0; 1729 } 1730 1731 static int dwc3_runtime_suspend(struct device *dev) 1732 { 1733 struct dwc3 *dwc = dev_get_drvdata(dev); 1734 int ret; 1735 1736 if (dwc3_runtime_checks(dwc)) 1737 return -EBUSY; 1738 1739 ret = dwc3_suspend_common(dwc, PMSG_AUTO_SUSPEND); 1740 if (ret) 1741 return ret; 1742 1743 device_init_wakeup(dev, true); 1744 1745 return 0; 1746 } 1747 1748 static int dwc3_runtime_resume(struct device *dev) 1749 { 1750 struct dwc3 *dwc = dev_get_drvdata(dev); 1751 int ret; 1752 1753 device_init_wakeup(dev, false); 1754 1755 ret = dwc3_resume_common(dwc, PMSG_AUTO_RESUME); 1756 if (ret) 1757 return ret; 1758 1759 switch (dwc->current_dr_role) { 1760 case DWC3_GCTL_PRTCAP_DEVICE: 1761 dwc3_gadget_process_pending_events(dwc); 1762 break; 1763 case DWC3_GCTL_PRTCAP_HOST: 1764 default: 1765 /* do nothing */ 1766 break; 1767 } 1768 1769 pm_runtime_mark_last_busy(dev); 1770 1771 return 0; 1772 } 1773 1774 static int dwc3_runtime_idle(struct device *dev) 1775 { 1776 struct dwc3 *dwc = dev_get_drvdata(dev); 1777 1778 switch (dwc->current_dr_role) { 1779 case DWC3_GCTL_PRTCAP_DEVICE: 1780 if (dwc3_runtime_checks(dwc)) 1781 return -EBUSY; 1782 break; 1783 case DWC3_GCTL_PRTCAP_HOST: 1784 default: 1785 /* do nothing */ 1786 break; 1787 } 1788 1789 pm_runtime_mark_last_busy(dev); 1790 pm_runtime_autosuspend(dev); 1791 1792 return 0; 1793 } 1794 #endif /* CONFIG_PM */ 1795 1796 #ifdef CONFIG_PM_SLEEP 1797 static int dwc3_suspend(struct device *dev) 1798 { 1799 struct dwc3 *dwc = dev_get_drvdata(dev); 1800 int ret; 1801 1802 ret = dwc3_suspend_common(dwc, PMSG_SUSPEND); 1803 if (ret) 1804 return ret; 1805 1806 pinctrl_pm_select_sleep_state(dev); 1807 1808 return 0; 1809 } 1810 1811 static int dwc3_resume(struct device *dev) 1812 { 1813 struct dwc3 *dwc = dev_get_drvdata(dev); 1814 int ret; 1815 1816 pinctrl_pm_select_default_state(dev); 1817 1818 ret = dwc3_resume_common(dwc, PMSG_RESUME); 1819 if (ret) 1820 return ret; 1821 1822 pm_runtime_disable(dev); 1823 pm_runtime_set_active(dev); 1824 pm_runtime_enable(dev); 1825 1826 return 0; 1827 } 1828 #endif /* CONFIG_PM_SLEEP */ 1829 1830 static const struct dev_pm_ops dwc3_dev_pm_ops = { 1831 SET_SYSTEM_SLEEP_PM_OPS(dwc3_suspend, dwc3_resume) 1832 SET_RUNTIME_PM_OPS(dwc3_runtime_suspend, dwc3_runtime_resume, 1833 dwc3_runtime_idle) 1834 }; 1835 1836 #ifdef CONFIG_OF 1837 static const struct of_device_id of_dwc3_match[] = { 1838 { 1839 .compatible = "snps,dwc3" 1840 }, 1841 { 1842 .compatible = "synopsys,dwc3" 1843 }, 1844 { }, 1845 }; 1846 MODULE_DEVICE_TABLE(of, of_dwc3_match); 1847 #endif 1848 1849 #ifdef CONFIG_ACPI 1850 1851 #define ACPI_ID_INTEL_BSW "808622B7" 1852 1853 static const struct acpi_device_id dwc3_acpi_match[] = { 1854 { ACPI_ID_INTEL_BSW, 0 }, 1855 { }, 1856 }; 1857 MODULE_DEVICE_TABLE(acpi, dwc3_acpi_match); 1858 #endif 1859 1860 static struct platform_driver dwc3_driver = { 1861 .probe = dwc3_probe, 1862 .remove = dwc3_remove, 1863 .driver = { 1864 .name = "dwc3", 1865 .of_match_table = of_match_ptr(of_dwc3_match), 1866 .acpi_match_table = ACPI_PTR(dwc3_acpi_match), 1867 .pm = &dwc3_dev_pm_ops, 1868 }, 1869 }; 1870 1871 module_platform_driver(dwc3_driver); 1872 1873 MODULE_ALIAS("platform:dwc3"); 1874 MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>"); 1875 MODULE_LICENSE("GPL v2"); 1876 MODULE_DESCRIPTION("DesignWare USB3 DRD Controller Driver"); 1877