1 // SPDX-License-Identifier: GPL-2.0 2 /** 3 * core.c - DesignWare USB3 DRD Controller Core file 4 * 5 * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com 6 * 7 * Authors: Felipe Balbi <balbi@ti.com>, 8 * Sebastian Andrzej Siewior <bigeasy@linutronix.de> 9 */ 10 11 #include <linux/version.h> 12 #include <linux/module.h> 13 #include <linux/kernel.h> 14 #include <linux/slab.h> 15 #include <linux/spinlock.h> 16 #include <linux/platform_device.h> 17 #include <linux/pm_runtime.h> 18 #include <linux/interrupt.h> 19 #include <linux/ioport.h> 20 #include <linux/io.h> 21 #include <linux/list.h> 22 #include <linux/delay.h> 23 #include <linux/dma-mapping.h> 24 #include <linux/of.h> 25 #include <linux/acpi.h> 26 #include <linux/pinctrl/consumer.h> 27 28 #include <linux/usb/ch9.h> 29 #include <linux/usb/gadget.h> 30 #include <linux/usb/of.h> 31 #include <linux/usb/otg.h> 32 33 #include "core.h" 34 #include "gadget.h" 35 #include "io.h" 36 37 #include "debug.h" 38 39 #define DWC3_DEFAULT_AUTOSUSPEND_DELAY 5000 /* ms */ 40 41 /** 42 * dwc3_get_dr_mode - Validates and sets dr_mode 43 * @dwc: pointer to our context structure 44 */ 45 static int dwc3_get_dr_mode(struct dwc3 *dwc) 46 { 47 enum usb_dr_mode mode; 48 struct device *dev = dwc->dev; 49 unsigned int hw_mode; 50 51 if (dwc->dr_mode == USB_DR_MODE_UNKNOWN) 52 dwc->dr_mode = USB_DR_MODE_OTG; 53 54 mode = dwc->dr_mode; 55 hw_mode = DWC3_GHWPARAMS0_MODE(dwc->hwparams.hwparams0); 56 57 switch (hw_mode) { 58 case DWC3_GHWPARAMS0_MODE_GADGET: 59 if (IS_ENABLED(CONFIG_USB_DWC3_HOST)) { 60 dev_err(dev, 61 "Controller does not support host mode.\n"); 62 return -EINVAL; 63 } 64 mode = USB_DR_MODE_PERIPHERAL; 65 break; 66 case DWC3_GHWPARAMS0_MODE_HOST: 67 if (IS_ENABLED(CONFIG_USB_DWC3_GADGET)) { 68 dev_err(dev, 69 "Controller does not support device mode.\n"); 70 return -EINVAL; 71 } 72 mode = USB_DR_MODE_HOST; 73 break; 74 default: 75 if (IS_ENABLED(CONFIG_USB_DWC3_HOST)) 76 mode = USB_DR_MODE_HOST; 77 else if (IS_ENABLED(CONFIG_USB_DWC3_GADGET)) 78 mode = USB_DR_MODE_PERIPHERAL; 79 } 80 81 if (mode != dwc->dr_mode) { 82 dev_warn(dev, 83 "Configuration mismatch. dr_mode forced to %s\n", 84 mode == USB_DR_MODE_HOST ? "host" : "gadget"); 85 86 dwc->dr_mode = mode; 87 } 88 89 return 0; 90 } 91 92 static void dwc3_event_buffers_cleanup(struct dwc3 *dwc); 93 static int dwc3_event_buffers_setup(struct dwc3 *dwc); 94 95 static void dwc3_set_prtcap(struct dwc3 *dwc, u32 mode) 96 { 97 u32 reg; 98 99 reg = dwc3_readl(dwc->regs, DWC3_GCTL); 100 reg &= ~(DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_OTG)); 101 reg |= DWC3_GCTL_PRTCAPDIR(mode); 102 dwc3_writel(dwc->regs, DWC3_GCTL, reg); 103 } 104 105 static void __dwc3_set_mode(struct work_struct *work) 106 { 107 struct dwc3 *dwc = work_to_dwc(work); 108 unsigned long flags; 109 int ret; 110 111 if (!dwc->desired_dr_role) 112 return; 113 114 if (dwc->desired_dr_role == dwc->current_dr_role) 115 return; 116 117 if (dwc->dr_mode != USB_DR_MODE_OTG) 118 return; 119 120 switch (dwc->current_dr_role) { 121 case DWC3_GCTL_PRTCAP_HOST: 122 dwc3_host_exit(dwc); 123 break; 124 case DWC3_GCTL_PRTCAP_DEVICE: 125 dwc3_gadget_exit(dwc); 126 dwc3_event_buffers_cleanup(dwc); 127 break; 128 default: 129 break; 130 } 131 132 spin_lock_irqsave(&dwc->lock, flags); 133 134 dwc3_set_prtcap(dwc, dwc->desired_dr_role); 135 136 dwc->current_dr_role = dwc->desired_dr_role; 137 138 spin_unlock_irqrestore(&dwc->lock, flags); 139 140 switch (dwc->desired_dr_role) { 141 case DWC3_GCTL_PRTCAP_HOST: 142 ret = dwc3_host_init(dwc); 143 if (ret) { 144 dev_err(dwc->dev, "failed to initialize host\n"); 145 } else { 146 if (dwc->usb2_phy) 147 otg_set_vbus(dwc->usb2_phy->otg, true); 148 phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_HOST); 149 phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_HOST); 150 } 151 break; 152 case DWC3_GCTL_PRTCAP_DEVICE: 153 dwc3_event_buffers_setup(dwc); 154 155 if (dwc->usb2_phy) 156 otg_set_vbus(dwc->usb2_phy->otg, false); 157 phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_DEVICE); 158 phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_DEVICE); 159 160 ret = dwc3_gadget_init(dwc); 161 if (ret) 162 dev_err(dwc->dev, "failed to initialize peripheral\n"); 163 break; 164 default: 165 break; 166 } 167 } 168 169 void dwc3_set_mode(struct dwc3 *dwc, u32 mode) 170 { 171 unsigned long flags; 172 173 spin_lock_irqsave(&dwc->lock, flags); 174 dwc->desired_dr_role = mode; 175 spin_unlock_irqrestore(&dwc->lock, flags); 176 177 queue_work(system_power_efficient_wq, &dwc->drd_work); 178 } 179 180 u32 dwc3_core_fifo_space(struct dwc3_ep *dep, u8 type) 181 { 182 struct dwc3 *dwc = dep->dwc; 183 u32 reg; 184 185 dwc3_writel(dwc->regs, DWC3_GDBGFIFOSPACE, 186 DWC3_GDBGFIFOSPACE_NUM(dep->number) | 187 DWC3_GDBGFIFOSPACE_TYPE(type)); 188 189 reg = dwc3_readl(dwc->regs, DWC3_GDBGFIFOSPACE); 190 191 return DWC3_GDBGFIFOSPACE_SPACE_AVAILABLE(reg); 192 } 193 194 /** 195 * dwc3_core_soft_reset - Issues core soft reset and PHY reset 196 * @dwc: pointer to our context structure 197 */ 198 static int dwc3_core_soft_reset(struct dwc3 *dwc) 199 { 200 u32 reg; 201 int retries = 1000; 202 int ret; 203 204 usb_phy_init(dwc->usb2_phy); 205 usb_phy_init(dwc->usb3_phy); 206 ret = phy_init(dwc->usb2_generic_phy); 207 if (ret < 0) 208 return ret; 209 210 ret = phy_init(dwc->usb3_generic_phy); 211 if (ret < 0) { 212 phy_exit(dwc->usb2_generic_phy); 213 return ret; 214 } 215 216 /* 217 * We're resetting only the device side because, if we're in host mode, 218 * XHCI driver will reset the host block. If dwc3 was configured for 219 * host-only mode, then we can return early. 220 */ 221 if (dwc->dr_mode == USB_DR_MODE_HOST) 222 return 0; 223 224 reg = dwc3_readl(dwc->regs, DWC3_DCTL); 225 reg |= DWC3_DCTL_CSFTRST; 226 dwc3_writel(dwc->regs, DWC3_DCTL, reg); 227 228 do { 229 reg = dwc3_readl(dwc->regs, DWC3_DCTL); 230 if (!(reg & DWC3_DCTL_CSFTRST)) 231 return 0; 232 233 udelay(1); 234 } while (--retries); 235 236 return -ETIMEDOUT; 237 } 238 239 /* 240 * dwc3_frame_length_adjustment - Adjusts frame length if required 241 * @dwc3: Pointer to our controller context structure 242 */ 243 static void dwc3_frame_length_adjustment(struct dwc3 *dwc) 244 { 245 u32 reg; 246 u32 dft; 247 248 if (dwc->revision < DWC3_REVISION_250A) 249 return; 250 251 if (dwc->fladj == 0) 252 return; 253 254 reg = dwc3_readl(dwc->regs, DWC3_GFLADJ); 255 dft = reg & DWC3_GFLADJ_30MHZ_MASK; 256 if (!dev_WARN_ONCE(dwc->dev, dft == dwc->fladj, 257 "request value same as default, ignoring\n")) { 258 reg &= ~DWC3_GFLADJ_30MHZ_MASK; 259 reg |= DWC3_GFLADJ_30MHZ_SDBND_SEL | dwc->fladj; 260 dwc3_writel(dwc->regs, DWC3_GFLADJ, reg); 261 } 262 } 263 264 /** 265 * dwc3_free_one_event_buffer - Frees one event buffer 266 * @dwc: Pointer to our controller context structure 267 * @evt: Pointer to event buffer to be freed 268 */ 269 static void dwc3_free_one_event_buffer(struct dwc3 *dwc, 270 struct dwc3_event_buffer *evt) 271 { 272 dma_free_coherent(dwc->sysdev, evt->length, evt->buf, evt->dma); 273 } 274 275 /** 276 * dwc3_alloc_one_event_buffer - Allocates one event buffer structure 277 * @dwc: Pointer to our controller context structure 278 * @length: size of the event buffer 279 * 280 * Returns a pointer to the allocated event buffer structure on success 281 * otherwise ERR_PTR(errno). 282 */ 283 static struct dwc3_event_buffer *dwc3_alloc_one_event_buffer(struct dwc3 *dwc, 284 unsigned length) 285 { 286 struct dwc3_event_buffer *evt; 287 288 evt = devm_kzalloc(dwc->dev, sizeof(*evt), GFP_KERNEL); 289 if (!evt) 290 return ERR_PTR(-ENOMEM); 291 292 evt->dwc = dwc; 293 evt->length = length; 294 evt->cache = devm_kzalloc(dwc->dev, length, GFP_KERNEL); 295 if (!evt->cache) 296 return ERR_PTR(-ENOMEM); 297 298 evt->buf = dma_alloc_coherent(dwc->sysdev, length, 299 &evt->dma, GFP_KERNEL); 300 if (!evt->buf) 301 return ERR_PTR(-ENOMEM); 302 303 return evt; 304 } 305 306 /** 307 * dwc3_free_event_buffers - frees all allocated event buffers 308 * @dwc: Pointer to our controller context structure 309 */ 310 static void dwc3_free_event_buffers(struct dwc3 *dwc) 311 { 312 struct dwc3_event_buffer *evt; 313 314 evt = dwc->ev_buf; 315 if (evt) 316 dwc3_free_one_event_buffer(dwc, evt); 317 } 318 319 /** 320 * dwc3_alloc_event_buffers - Allocates @num event buffers of size @length 321 * @dwc: pointer to our controller context structure 322 * @length: size of event buffer 323 * 324 * Returns 0 on success otherwise negative errno. In the error case, dwc 325 * may contain some buffers allocated but not all which were requested. 326 */ 327 static int dwc3_alloc_event_buffers(struct dwc3 *dwc, unsigned length) 328 { 329 struct dwc3_event_buffer *evt; 330 331 evt = dwc3_alloc_one_event_buffer(dwc, length); 332 if (IS_ERR(evt)) { 333 dev_err(dwc->dev, "can't allocate event buffer\n"); 334 return PTR_ERR(evt); 335 } 336 dwc->ev_buf = evt; 337 338 return 0; 339 } 340 341 /** 342 * dwc3_event_buffers_setup - setup our allocated event buffers 343 * @dwc: pointer to our controller context structure 344 * 345 * Returns 0 on success otherwise negative errno. 346 */ 347 static int dwc3_event_buffers_setup(struct dwc3 *dwc) 348 { 349 struct dwc3_event_buffer *evt; 350 351 evt = dwc->ev_buf; 352 evt->lpos = 0; 353 dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(0), 354 lower_32_bits(evt->dma)); 355 dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(0), 356 upper_32_bits(evt->dma)); 357 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0), 358 DWC3_GEVNTSIZ_SIZE(evt->length)); 359 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), 0); 360 361 return 0; 362 } 363 364 static void dwc3_event_buffers_cleanup(struct dwc3 *dwc) 365 { 366 struct dwc3_event_buffer *evt; 367 368 evt = dwc->ev_buf; 369 370 evt->lpos = 0; 371 372 dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(0), 0); 373 dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(0), 0); 374 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0), DWC3_GEVNTSIZ_INTMASK 375 | DWC3_GEVNTSIZ_SIZE(0)); 376 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), 0); 377 } 378 379 static int dwc3_alloc_scratch_buffers(struct dwc3 *dwc) 380 { 381 if (!dwc->has_hibernation) 382 return 0; 383 384 if (!dwc->nr_scratch) 385 return 0; 386 387 dwc->scratchbuf = kmalloc_array(dwc->nr_scratch, 388 DWC3_SCRATCHBUF_SIZE, GFP_KERNEL); 389 if (!dwc->scratchbuf) 390 return -ENOMEM; 391 392 return 0; 393 } 394 395 static int dwc3_setup_scratch_buffers(struct dwc3 *dwc) 396 { 397 dma_addr_t scratch_addr; 398 u32 param; 399 int ret; 400 401 if (!dwc->has_hibernation) 402 return 0; 403 404 if (!dwc->nr_scratch) 405 return 0; 406 407 /* should never fall here */ 408 if (!WARN_ON(dwc->scratchbuf)) 409 return 0; 410 411 scratch_addr = dma_map_single(dwc->sysdev, dwc->scratchbuf, 412 dwc->nr_scratch * DWC3_SCRATCHBUF_SIZE, 413 DMA_BIDIRECTIONAL); 414 if (dma_mapping_error(dwc->sysdev, scratch_addr)) { 415 dev_err(dwc->sysdev, "failed to map scratch buffer\n"); 416 ret = -EFAULT; 417 goto err0; 418 } 419 420 dwc->scratch_addr = scratch_addr; 421 422 param = lower_32_bits(scratch_addr); 423 424 ret = dwc3_send_gadget_generic_command(dwc, 425 DWC3_DGCMD_SET_SCRATCHPAD_ADDR_LO, param); 426 if (ret < 0) 427 goto err1; 428 429 param = upper_32_bits(scratch_addr); 430 431 ret = dwc3_send_gadget_generic_command(dwc, 432 DWC3_DGCMD_SET_SCRATCHPAD_ADDR_HI, param); 433 if (ret < 0) 434 goto err1; 435 436 return 0; 437 438 err1: 439 dma_unmap_single(dwc->sysdev, dwc->scratch_addr, dwc->nr_scratch * 440 DWC3_SCRATCHBUF_SIZE, DMA_BIDIRECTIONAL); 441 442 err0: 443 return ret; 444 } 445 446 static void dwc3_free_scratch_buffers(struct dwc3 *dwc) 447 { 448 if (!dwc->has_hibernation) 449 return; 450 451 if (!dwc->nr_scratch) 452 return; 453 454 /* should never fall here */ 455 if (!WARN_ON(dwc->scratchbuf)) 456 return; 457 458 dma_unmap_single(dwc->sysdev, dwc->scratch_addr, dwc->nr_scratch * 459 DWC3_SCRATCHBUF_SIZE, DMA_BIDIRECTIONAL); 460 kfree(dwc->scratchbuf); 461 } 462 463 static void dwc3_core_num_eps(struct dwc3 *dwc) 464 { 465 struct dwc3_hwparams *parms = &dwc->hwparams; 466 467 dwc->num_eps = DWC3_NUM_EPS(parms); 468 } 469 470 static void dwc3_cache_hwparams(struct dwc3 *dwc) 471 { 472 struct dwc3_hwparams *parms = &dwc->hwparams; 473 474 parms->hwparams0 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS0); 475 parms->hwparams1 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS1); 476 parms->hwparams2 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS2); 477 parms->hwparams3 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS3); 478 parms->hwparams4 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS4); 479 parms->hwparams5 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS5); 480 parms->hwparams6 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS6); 481 parms->hwparams7 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS7); 482 parms->hwparams8 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS8); 483 } 484 485 /** 486 * dwc3_phy_setup - Configure USB PHY Interface of DWC3 Core 487 * @dwc: Pointer to our controller context structure 488 * 489 * Returns 0 on success. The USB PHY interfaces are configured but not 490 * initialized. The PHY interfaces and the PHYs get initialized together with 491 * the core in dwc3_core_init. 492 */ 493 static int dwc3_phy_setup(struct dwc3 *dwc) 494 { 495 u32 reg; 496 int ret; 497 498 reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0)); 499 500 /* 501 * Make sure UX_EXIT_PX is cleared as that causes issues with some 502 * PHYs. Also, this bit is not supposed to be used in normal operation. 503 */ 504 reg &= ~DWC3_GUSB3PIPECTL_UX_EXIT_PX; 505 506 /* 507 * Above 1.94a, it is recommended to set DWC3_GUSB3PIPECTL_SUSPHY 508 * to '0' during coreConsultant configuration. So default value 509 * will be '0' when the core is reset. Application needs to set it 510 * to '1' after the core initialization is completed. 511 */ 512 if (dwc->revision > DWC3_REVISION_194A) 513 reg |= DWC3_GUSB3PIPECTL_SUSPHY; 514 515 if (dwc->u2ss_inp3_quirk) 516 reg |= DWC3_GUSB3PIPECTL_U2SSINP3OK; 517 518 if (dwc->dis_rxdet_inp3_quirk) 519 reg |= DWC3_GUSB3PIPECTL_DISRXDETINP3; 520 521 if (dwc->req_p1p2p3_quirk) 522 reg |= DWC3_GUSB3PIPECTL_REQP1P2P3; 523 524 if (dwc->del_p1p2p3_quirk) 525 reg |= DWC3_GUSB3PIPECTL_DEP1P2P3_EN; 526 527 if (dwc->del_phy_power_chg_quirk) 528 reg |= DWC3_GUSB3PIPECTL_DEPOCHANGE; 529 530 if (dwc->lfps_filter_quirk) 531 reg |= DWC3_GUSB3PIPECTL_LFPSFILT; 532 533 if (dwc->rx_detect_poll_quirk) 534 reg |= DWC3_GUSB3PIPECTL_RX_DETOPOLL; 535 536 if (dwc->tx_de_emphasis_quirk) 537 reg |= DWC3_GUSB3PIPECTL_TX_DEEPH(dwc->tx_de_emphasis); 538 539 if (dwc->dis_u3_susphy_quirk) 540 reg &= ~DWC3_GUSB3PIPECTL_SUSPHY; 541 542 if (dwc->dis_del_phy_power_chg_quirk) 543 reg &= ~DWC3_GUSB3PIPECTL_DEPOCHANGE; 544 545 dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg); 546 547 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0)); 548 549 /* Select the HS PHY interface */ 550 switch (DWC3_GHWPARAMS3_HSPHY_IFC(dwc->hwparams.hwparams3)) { 551 case DWC3_GHWPARAMS3_HSPHY_IFC_UTMI_ULPI: 552 if (dwc->hsphy_interface && 553 !strncmp(dwc->hsphy_interface, "utmi", 4)) { 554 reg &= ~DWC3_GUSB2PHYCFG_ULPI_UTMI; 555 break; 556 } else if (dwc->hsphy_interface && 557 !strncmp(dwc->hsphy_interface, "ulpi", 4)) { 558 reg |= DWC3_GUSB2PHYCFG_ULPI_UTMI; 559 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg); 560 } else { 561 /* Relying on default value. */ 562 if (!(reg & DWC3_GUSB2PHYCFG_ULPI_UTMI)) 563 break; 564 } 565 /* FALLTHROUGH */ 566 case DWC3_GHWPARAMS3_HSPHY_IFC_ULPI: 567 ret = dwc3_ulpi_init(dwc); 568 if (ret) 569 return ret; 570 /* FALLTHROUGH */ 571 default: 572 break; 573 } 574 575 switch (dwc->hsphy_mode) { 576 case USBPHY_INTERFACE_MODE_UTMI: 577 reg &= ~(DWC3_GUSB2PHYCFG_PHYIF_MASK | 578 DWC3_GUSB2PHYCFG_USBTRDTIM_MASK); 579 reg |= DWC3_GUSB2PHYCFG_PHYIF(UTMI_PHYIF_8_BIT) | 580 DWC3_GUSB2PHYCFG_USBTRDTIM(USBTRDTIM_UTMI_8_BIT); 581 break; 582 case USBPHY_INTERFACE_MODE_UTMIW: 583 reg &= ~(DWC3_GUSB2PHYCFG_PHYIF_MASK | 584 DWC3_GUSB2PHYCFG_USBTRDTIM_MASK); 585 reg |= DWC3_GUSB2PHYCFG_PHYIF(UTMI_PHYIF_16_BIT) | 586 DWC3_GUSB2PHYCFG_USBTRDTIM(USBTRDTIM_UTMI_16_BIT); 587 break; 588 default: 589 break; 590 } 591 592 /* 593 * Above 1.94a, it is recommended to set DWC3_GUSB2PHYCFG_SUSPHY to 594 * '0' during coreConsultant configuration. So default value will 595 * be '0' when the core is reset. Application needs to set it to 596 * '1' after the core initialization is completed. 597 */ 598 if (dwc->revision > DWC3_REVISION_194A) 599 reg |= DWC3_GUSB2PHYCFG_SUSPHY; 600 601 if (dwc->dis_u2_susphy_quirk) 602 reg &= ~DWC3_GUSB2PHYCFG_SUSPHY; 603 604 if (dwc->dis_enblslpm_quirk) 605 reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM; 606 607 if (dwc->dis_u2_freeclk_exists_quirk) 608 reg &= ~DWC3_GUSB2PHYCFG_U2_FREECLK_EXISTS; 609 610 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg); 611 612 return 0; 613 } 614 615 static void dwc3_core_exit(struct dwc3 *dwc) 616 { 617 dwc3_event_buffers_cleanup(dwc); 618 619 usb_phy_shutdown(dwc->usb2_phy); 620 usb_phy_shutdown(dwc->usb3_phy); 621 phy_exit(dwc->usb2_generic_phy); 622 phy_exit(dwc->usb3_generic_phy); 623 624 usb_phy_set_suspend(dwc->usb2_phy, 1); 625 usb_phy_set_suspend(dwc->usb3_phy, 1); 626 phy_power_off(dwc->usb2_generic_phy); 627 phy_power_off(dwc->usb3_generic_phy); 628 } 629 630 static bool dwc3_core_is_valid(struct dwc3 *dwc) 631 { 632 u32 reg; 633 634 reg = dwc3_readl(dwc->regs, DWC3_GSNPSID); 635 636 /* This should read as U3 followed by revision number */ 637 if ((reg & DWC3_GSNPSID_MASK) == 0x55330000) { 638 /* Detected DWC_usb3 IP */ 639 dwc->revision = reg; 640 } else if ((reg & DWC3_GSNPSID_MASK) == 0x33310000) { 641 /* Detected DWC_usb31 IP */ 642 dwc->revision = dwc3_readl(dwc->regs, DWC3_VER_NUMBER); 643 dwc->revision |= DWC3_REVISION_IS_DWC31; 644 } else { 645 return false; 646 } 647 648 return true; 649 } 650 651 static void dwc3_core_setup_global_control(struct dwc3 *dwc) 652 { 653 u32 hwparams4 = dwc->hwparams.hwparams4; 654 u32 reg; 655 656 reg = dwc3_readl(dwc->regs, DWC3_GCTL); 657 reg &= ~DWC3_GCTL_SCALEDOWN_MASK; 658 659 switch (DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1)) { 660 case DWC3_GHWPARAMS1_EN_PWROPT_CLK: 661 /** 662 * WORKAROUND: DWC3 revisions between 2.10a and 2.50a have an 663 * issue which would cause xHCI compliance tests to fail. 664 * 665 * Because of that we cannot enable clock gating on such 666 * configurations. 667 * 668 * Refers to: 669 * 670 * STAR#9000588375: Clock Gating, SOF Issues when ref_clk-Based 671 * SOF/ITP Mode Used 672 */ 673 if ((dwc->dr_mode == USB_DR_MODE_HOST || 674 dwc->dr_mode == USB_DR_MODE_OTG) && 675 (dwc->revision >= DWC3_REVISION_210A && 676 dwc->revision <= DWC3_REVISION_250A)) 677 reg |= DWC3_GCTL_DSBLCLKGTNG | DWC3_GCTL_SOFITPSYNC; 678 else 679 reg &= ~DWC3_GCTL_DSBLCLKGTNG; 680 break; 681 case DWC3_GHWPARAMS1_EN_PWROPT_HIB: 682 /* enable hibernation here */ 683 dwc->nr_scratch = DWC3_GHWPARAMS4_HIBER_SCRATCHBUFS(hwparams4); 684 685 /* 686 * REVISIT Enabling this bit so that host-mode hibernation 687 * will work. Device-mode hibernation is not yet implemented. 688 */ 689 reg |= DWC3_GCTL_GBLHIBERNATIONEN; 690 break; 691 default: 692 /* nothing */ 693 break; 694 } 695 696 /* check if current dwc3 is on simulation board */ 697 if (dwc->hwparams.hwparams6 & DWC3_GHWPARAMS6_EN_FPGA) { 698 dev_info(dwc->dev, "Running with FPGA optmizations\n"); 699 dwc->is_fpga = true; 700 } 701 702 WARN_ONCE(dwc->disable_scramble_quirk && !dwc->is_fpga, 703 "disable_scramble cannot be used on non-FPGA builds\n"); 704 705 if (dwc->disable_scramble_quirk && dwc->is_fpga) 706 reg |= DWC3_GCTL_DISSCRAMBLE; 707 else 708 reg &= ~DWC3_GCTL_DISSCRAMBLE; 709 710 if (dwc->u2exit_lfps_quirk) 711 reg |= DWC3_GCTL_U2EXIT_LFPS; 712 713 /* 714 * WORKAROUND: DWC3 revisions <1.90a have a bug 715 * where the device can fail to connect at SuperSpeed 716 * and falls back to high-speed mode which causes 717 * the device to enter a Connect/Disconnect loop 718 */ 719 if (dwc->revision < DWC3_REVISION_190A) 720 reg |= DWC3_GCTL_U2RSTECN; 721 722 dwc3_writel(dwc->regs, DWC3_GCTL, reg); 723 } 724 725 static int dwc3_core_get_phy(struct dwc3 *dwc); 726 727 /** 728 * dwc3_core_init - Low-level initialization of DWC3 Core 729 * @dwc: Pointer to our controller context structure 730 * 731 * Returns 0 on success otherwise negative errno. 732 */ 733 static int dwc3_core_init(struct dwc3 *dwc) 734 { 735 u32 reg; 736 int ret; 737 738 if (!dwc3_core_is_valid(dwc)) { 739 dev_err(dwc->dev, "this is not a DesignWare USB3 DRD Core\n"); 740 ret = -ENODEV; 741 goto err0; 742 } 743 744 /* 745 * Write Linux Version Code to our GUID register so it's easy to figure 746 * out which kernel version a bug was found. 747 */ 748 dwc3_writel(dwc->regs, DWC3_GUID, LINUX_VERSION_CODE); 749 750 /* Handle USB2.0-only core configuration */ 751 if (DWC3_GHWPARAMS3_SSPHY_IFC(dwc->hwparams.hwparams3) == 752 DWC3_GHWPARAMS3_SSPHY_IFC_DIS) { 753 if (dwc->maximum_speed == USB_SPEED_SUPER) 754 dwc->maximum_speed = USB_SPEED_HIGH; 755 } 756 757 ret = dwc3_core_get_phy(dwc); 758 if (ret) 759 goto err0; 760 761 ret = dwc3_core_soft_reset(dwc); 762 if (ret) 763 goto err0; 764 765 ret = dwc3_phy_setup(dwc); 766 if (ret) 767 goto err0; 768 769 dwc3_core_setup_global_control(dwc); 770 dwc3_core_num_eps(dwc); 771 772 ret = dwc3_setup_scratch_buffers(dwc); 773 if (ret) 774 goto err1; 775 776 /* Adjust Frame Length */ 777 dwc3_frame_length_adjustment(dwc); 778 779 usb_phy_set_suspend(dwc->usb2_phy, 0); 780 usb_phy_set_suspend(dwc->usb3_phy, 0); 781 ret = phy_power_on(dwc->usb2_generic_phy); 782 if (ret < 0) 783 goto err2; 784 785 ret = phy_power_on(dwc->usb3_generic_phy); 786 if (ret < 0) 787 goto err3; 788 789 ret = dwc3_event_buffers_setup(dwc); 790 if (ret) { 791 dev_err(dwc->dev, "failed to setup event buffers\n"); 792 goto err4; 793 } 794 795 /* 796 * ENDXFER polling is available on version 3.10a and later of 797 * the DWC_usb3 controller. It is NOT available in the 798 * DWC_usb31 controller. 799 */ 800 if (!dwc3_is_usb31(dwc) && dwc->revision >= DWC3_REVISION_310A) { 801 reg = dwc3_readl(dwc->regs, DWC3_GUCTL2); 802 reg |= DWC3_GUCTL2_RST_ACTBITLATER; 803 dwc3_writel(dwc->regs, DWC3_GUCTL2, reg); 804 } 805 806 if (dwc->revision >= DWC3_REVISION_250A) { 807 reg = dwc3_readl(dwc->regs, DWC3_GUCTL1); 808 809 /* 810 * Enable hardware control of sending remote wakeup 811 * in HS when the device is in the L1 state. 812 */ 813 if (dwc->revision >= DWC3_REVISION_290A) 814 reg |= DWC3_GUCTL1_DEV_L1_EXIT_BY_HW; 815 816 if (dwc->dis_tx_ipgap_linecheck_quirk) 817 reg |= DWC3_GUCTL1_TX_IPGAP_LINECHECK_DIS; 818 819 dwc3_writel(dwc->regs, DWC3_GUCTL1, reg); 820 } 821 822 return 0; 823 824 err4: 825 phy_power_off(dwc->usb3_generic_phy); 826 827 err3: 828 phy_power_off(dwc->usb2_generic_phy); 829 830 err2: 831 usb_phy_set_suspend(dwc->usb2_phy, 1); 832 usb_phy_set_suspend(dwc->usb3_phy, 1); 833 834 err1: 835 usb_phy_shutdown(dwc->usb2_phy); 836 usb_phy_shutdown(dwc->usb3_phy); 837 phy_exit(dwc->usb2_generic_phy); 838 phy_exit(dwc->usb3_generic_phy); 839 840 err0: 841 return ret; 842 } 843 844 static int dwc3_core_get_phy(struct dwc3 *dwc) 845 { 846 struct device *dev = dwc->dev; 847 struct device_node *node = dev->of_node; 848 int ret; 849 850 if (node) { 851 dwc->usb2_phy = devm_usb_get_phy_by_phandle(dev, "usb-phy", 0); 852 dwc->usb3_phy = devm_usb_get_phy_by_phandle(dev, "usb-phy", 1); 853 } else { 854 dwc->usb2_phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB2); 855 dwc->usb3_phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB3); 856 } 857 858 if (IS_ERR(dwc->usb2_phy)) { 859 ret = PTR_ERR(dwc->usb2_phy); 860 if (ret == -ENXIO || ret == -ENODEV) { 861 dwc->usb2_phy = NULL; 862 } else if (ret == -EPROBE_DEFER) { 863 return ret; 864 } else { 865 dev_err(dev, "no usb2 phy configured\n"); 866 return ret; 867 } 868 } 869 870 if (IS_ERR(dwc->usb3_phy)) { 871 ret = PTR_ERR(dwc->usb3_phy); 872 if (ret == -ENXIO || ret == -ENODEV) { 873 dwc->usb3_phy = NULL; 874 } else if (ret == -EPROBE_DEFER) { 875 return ret; 876 } else { 877 dev_err(dev, "no usb3 phy configured\n"); 878 return ret; 879 } 880 } 881 882 dwc->usb2_generic_phy = devm_phy_get(dev, "usb2-phy"); 883 if (IS_ERR(dwc->usb2_generic_phy)) { 884 ret = PTR_ERR(dwc->usb2_generic_phy); 885 if (ret == -ENOSYS || ret == -ENODEV) { 886 dwc->usb2_generic_phy = NULL; 887 } else if (ret == -EPROBE_DEFER) { 888 return ret; 889 } else { 890 dev_err(dev, "no usb2 phy configured\n"); 891 return ret; 892 } 893 } 894 895 dwc->usb3_generic_phy = devm_phy_get(dev, "usb3-phy"); 896 if (IS_ERR(dwc->usb3_generic_phy)) { 897 ret = PTR_ERR(dwc->usb3_generic_phy); 898 if (ret == -ENOSYS || ret == -ENODEV) { 899 dwc->usb3_generic_phy = NULL; 900 } else if (ret == -EPROBE_DEFER) { 901 return ret; 902 } else { 903 dev_err(dev, "no usb3 phy configured\n"); 904 return ret; 905 } 906 } 907 908 return 0; 909 } 910 911 static int dwc3_core_init_mode(struct dwc3 *dwc) 912 { 913 struct device *dev = dwc->dev; 914 int ret; 915 916 switch (dwc->dr_mode) { 917 case USB_DR_MODE_PERIPHERAL: 918 dwc->current_dr_role = DWC3_GCTL_PRTCAP_DEVICE; 919 dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_DEVICE); 920 921 if (dwc->usb2_phy) 922 otg_set_vbus(dwc->usb2_phy->otg, false); 923 phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_DEVICE); 924 phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_DEVICE); 925 926 ret = dwc3_gadget_init(dwc); 927 if (ret) { 928 if (ret != -EPROBE_DEFER) 929 dev_err(dev, "failed to initialize gadget\n"); 930 return ret; 931 } 932 break; 933 case USB_DR_MODE_HOST: 934 dwc->current_dr_role = DWC3_GCTL_PRTCAP_HOST; 935 dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_HOST); 936 937 if (dwc->usb2_phy) 938 otg_set_vbus(dwc->usb2_phy->otg, true); 939 phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_HOST); 940 phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_HOST); 941 942 ret = dwc3_host_init(dwc); 943 if (ret) { 944 if (ret != -EPROBE_DEFER) 945 dev_err(dev, "failed to initialize host\n"); 946 return ret; 947 } 948 break; 949 case USB_DR_MODE_OTG: 950 INIT_WORK(&dwc->drd_work, __dwc3_set_mode); 951 ret = dwc3_drd_init(dwc); 952 if (ret) { 953 if (ret != -EPROBE_DEFER) 954 dev_err(dev, "failed to initialize dual-role\n"); 955 return ret; 956 } 957 break; 958 default: 959 dev_err(dev, "Unsupported mode of operation %d\n", dwc->dr_mode); 960 return -EINVAL; 961 } 962 963 return 0; 964 } 965 966 static void dwc3_core_exit_mode(struct dwc3 *dwc) 967 { 968 switch (dwc->dr_mode) { 969 case USB_DR_MODE_PERIPHERAL: 970 dwc3_gadget_exit(dwc); 971 break; 972 case USB_DR_MODE_HOST: 973 dwc3_host_exit(dwc); 974 break; 975 case USB_DR_MODE_OTG: 976 dwc3_drd_exit(dwc); 977 break; 978 default: 979 /* do nothing */ 980 break; 981 } 982 } 983 984 static void dwc3_get_properties(struct dwc3 *dwc) 985 { 986 struct device *dev = dwc->dev; 987 u8 lpm_nyet_threshold; 988 u8 tx_de_emphasis; 989 u8 hird_threshold; 990 991 /* default to highest possible threshold */ 992 lpm_nyet_threshold = 0xff; 993 994 /* default to -3.5dB de-emphasis */ 995 tx_de_emphasis = 1; 996 997 /* 998 * default to assert utmi_sleep_n and use maximum allowed HIRD 999 * threshold value of 0b1100 1000 */ 1001 hird_threshold = 12; 1002 1003 dwc->maximum_speed = usb_get_maximum_speed(dev); 1004 dwc->dr_mode = usb_get_dr_mode(dev); 1005 dwc->hsphy_mode = of_usb_get_phy_mode(dev->of_node); 1006 1007 dwc->sysdev_is_parent = device_property_read_bool(dev, 1008 "linux,sysdev_is_parent"); 1009 if (dwc->sysdev_is_parent) 1010 dwc->sysdev = dwc->dev->parent; 1011 else 1012 dwc->sysdev = dwc->dev; 1013 1014 dwc->has_lpm_erratum = device_property_read_bool(dev, 1015 "snps,has-lpm-erratum"); 1016 device_property_read_u8(dev, "snps,lpm-nyet-threshold", 1017 &lpm_nyet_threshold); 1018 dwc->is_utmi_l1_suspend = device_property_read_bool(dev, 1019 "snps,is-utmi-l1-suspend"); 1020 device_property_read_u8(dev, "snps,hird-threshold", 1021 &hird_threshold); 1022 dwc->usb3_lpm_capable = device_property_read_bool(dev, 1023 "snps,usb3_lpm_capable"); 1024 1025 dwc->disable_scramble_quirk = device_property_read_bool(dev, 1026 "snps,disable_scramble_quirk"); 1027 dwc->u2exit_lfps_quirk = device_property_read_bool(dev, 1028 "snps,u2exit_lfps_quirk"); 1029 dwc->u2ss_inp3_quirk = device_property_read_bool(dev, 1030 "snps,u2ss_inp3_quirk"); 1031 dwc->req_p1p2p3_quirk = device_property_read_bool(dev, 1032 "snps,req_p1p2p3_quirk"); 1033 dwc->del_p1p2p3_quirk = device_property_read_bool(dev, 1034 "snps,del_p1p2p3_quirk"); 1035 dwc->del_phy_power_chg_quirk = device_property_read_bool(dev, 1036 "snps,del_phy_power_chg_quirk"); 1037 dwc->lfps_filter_quirk = device_property_read_bool(dev, 1038 "snps,lfps_filter_quirk"); 1039 dwc->rx_detect_poll_quirk = device_property_read_bool(dev, 1040 "snps,rx_detect_poll_quirk"); 1041 dwc->dis_u3_susphy_quirk = device_property_read_bool(dev, 1042 "snps,dis_u3_susphy_quirk"); 1043 dwc->dis_u2_susphy_quirk = device_property_read_bool(dev, 1044 "snps,dis_u2_susphy_quirk"); 1045 dwc->dis_enblslpm_quirk = device_property_read_bool(dev, 1046 "snps,dis_enblslpm_quirk"); 1047 dwc->dis_rxdet_inp3_quirk = device_property_read_bool(dev, 1048 "snps,dis_rxdet_inp3_quirk"); 1049 dwc->dis_u2_freeclk_exists_quirk = device_property_read_bool(dev, 1050 "snps,dis-u2-freeclk-exists-quirk"); 1051 dwc->dis_del_phy_power_chg_quirk = device_property_read_bool(dev, 1052 "snps,dis-del-phy-power-chg-quirk"); 1053 dwc->dis_tx_ipgap_linecheck_quirk = device_property_read_bool(dev, 1054 "snps,dis-tx-ipgap-linecheck-quirk"); 1055 1056 dwc->tx_de_emphasis_quirk = device_property_read_bool(dev, 1057 "snps,tx_de_emphasis_quirk"); 1058 device_property_read_u8(dev, "snps,tx_de_emphasis", 1059 &tx_de_emphasis); 1060 device_property_read_string(dev, "snps,hsphy_interface", 1061 &dwc->hsphy_interface); 1062 device_property_read_u32(dev, "snps,quirk-frame-length-adjustment", 1063 &dwc->fladj); 1064 1065 dwc->lpm_nyet_threshold = lpm_nyet_threshold; 1066 dwc->tx_de_emphasis = tx_de_emphasis; 1067 1068 dwc->hird_threshold = hird_threshold 1069 | (dwc->is_utmi_l1_suspend << 4); 1070 1071 dwc->imod_interval = 0; 1072 } 1073 1074 /* check whether the core supports IMOD */ 1075 bool dwc3_has_imod(struct dwc3 *dwc) 1076 { 1077 return ((dwc3_is_usb3(dwc) && 1078 dwc->revision >= DWC3_REVISION_300A) || 1079 (dwc3_is_usb31(dwc) && 1080 dwc->revision >= DWC3_USB31_REVISION_120A)); 1081 } 1082 1083 static void dwc3_check_params(struct dwc3 *dwc) 1084 { 1085 struct device *dev = dwc->dev; 1086 1087 /* Check for proper value of imod_interval */ 1088 if (dwc->imod_interval && !dwc3_has_imod(dwc)) { 1089 dev_warn(dwc->dev, "Interrupt moderation not supported\n"); 1090 dwc->imod_interval = 0; 1091 } 1092 1093 /* 1094 * Workaround for STAR 9000961433 which affects only version 1095 * 3.00a of the DWC_usb3 core. This prevents the controller 1096 * interrupt from being masked while handling events. IMOD 1097 * allows us to work around this issue. Enable it for the 1098 * affected version. 1099 */ 1100 if (!dwc->imod_interval && 1101 (dwc->revision == DWC3_REVISION_300A)) 1102 dwc->imod_interval = 1; 1103 1104 /* Check the maximum_speed parameter */ 1105 switch (dwc->maximum_speed) { 1106 case USB_SPEED_LOW: 1107 case USB_SPEED_FULL: 1108 case USB_SPEED_HIGH: 1109 case USB_SPEED_SUPER: 1110 case USB_SPEED_SUPER_PLUS: 1111 break; 1112 default: 1113 dev_err(dev, "invalid maximum_speed parameter %d\n", 1114 dwc->maximum_speed); 1115 /* fall through */ 1116 case USB_SPEED_UNKNOWN: 1117 /* default to superspeed */ 1118 dwc->maximum_speed = USB_SPEED_SUPER; 1119 1120 /* 1121 * default to superspeed plus if we are capable. 1122 */ 1123 if (dwc3_is_usb31(dwc) && 1124 (DWC3_GHWPARAMS3_SSPHY_IFC(dwc->hwparams.hwparams3) == 1125 DWC3_GHWPARAMS3_SSPHY_IFC_GEN2)) 1126 dwc->maximum_speed = USB_SPEED_SUPER_PLUS; 1127 1128 break; 1129 } 1130 } 1131 1132 static int dwc3_probe(struct platform_device *pdev) 1133 { 1134 struct device *dev = &pdev->dev; 1135 struct resource *res; 1136 struct dwc3 *dwc; 1137 1138 int ret; 1139 1140 void __iomem *regs; 1141 1142 dwc = devm_kzalloc(dev, sizeof(*dwc), GFP_KERNEL); 1143 if (!dwc) 1144 return -ENOMEM; 1145 1146 dwc->dev = dev; 1147 1148 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1149 if (!res) { 1150 dev_err(dev, "missing memory resource\n"); 1151 return -ENODEV; 1152 } 1153 1154 dwc->xhci_resources[0].start = res->start; 1155 dwc->xhci_resources[0].end = dwc->xhci_resources[0].start + 1156 DWC3_XHCI_REGS_END; 1157 dwc->xhci_resources[0].flags = res->flags; 1158 dwc->xhci_resources[0].name = res->name; 1159 1160 res->start += DWC3_GLOBALS_REGS_START; 1161 1162 /* 1163 * Request memory region but exclude xHCI regs, 1164 * since it will be requested by the xhci-plat driver. 1165 */ 1166 regs = devm_ioremap_resource(dev, res); 1167 if (IS_ERR(regs)) { 1168 ret = PTR_ERR(regs); 1169 goto err0; 1170 } 1171 1172 dwc->regs = regs; 1173 dwc->regs_size = resource_size(res); 1174 1175 dwc3_get_properties(dwc); 1176 1177 platform_set_drvdata(pdev, dwc); 1178 dwc3_cache_hwparams(dwc); 1179 1180 spin_lock_init(&dwc->lock); 1181 1182 pm_runtime_set_active(dev); 1183 pm_runtime_use_autosuspend(dev); 1184 pm_runtime_set_autosuspend_delay(dev, DWC3_DEFAULT_AUTOSUSPEND_DELAY); 1185 pm_runtime_enable(dev); 1186 ret = pm_runtime_get_sync(dev); 1187 if (ret < 0) 1188 goto err1; 1189 1190 pm_runtime_forbid(dev); 1191 1192 ret = dwc3_alloc_event_buffers(dwc, DWC3_EVENT_BUFFERS_SIZE); 1193 if (ret) { 1194 dev_err(dwc->dev, "failed to allocate event buffers\n"); 1195 ret = -ENOMEM; 1196 goto err2; 1197 } 1198 1199 ret = dwc3_get_dr_mode(dwc); 1200 if (ret) 1201 goto err3; 1202 1203 ret = dwc3_alloc_scratch_buffers(dwc); 1204 if (ret) 1205 goto err3; 1206 1207 ret = dwc3_core_init(dwc); 1208 if (ret) { 1209 dev_err(dev, "failed to initialize core\n"); 1210 goto err4; 1211 } 1212 1213 dwc3_check_params(dwc); 1214 1215 ret = dwc3_core_init_mode(dwc); 1216 if (ret) 1217 goto err5; 1218 1219 dwc3_debugfs_init(dwc); 1220 pm_runtime_put(dev); 1221 1222 return 0; 1223 1224 err5: 1225 dwc3_event_buffers_cleanup(dwc); 1226 1227 err4: 1228 dwc3_free_scratch_buffers(dwc); 1229 1230 err3: 1231 dwc3_free_event_buffers(dwc); 1232 dwc3_ulpi_exit(dwc); 1233 1234 err2: 1235 pm_runtime_allow(&pdev->dev); 1236 1237 err1: 1238 pm_runtime_put_sync(&pdev->dev); 1239 pm_runtime_disable(&pdev->dev); 1240 1241 err0: 1242 /* 1243 * restore res->start back to its original value so that, in case the 1244 * probe is deferred, we don't end up getting error in request the 1245 * memory region the next time probe is called. 1246 */ 1247 res->start -= DWC3_GLOBALS_REGS_START; 1248 1249 return ret; 1250 } 1251 1252 static int dwc3_remove(struct platform_device *pdev) 1253 { 1254 struct dwc3 *dwc = platform_get_drvdata(pdev); 1255 struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1256 1257 pm_runtime_get_sync(&pdev->dev); 1258 /* 1259 * restore res->start back to its original value so that, in case the 1260 * probe is deferred, we don't end up getting error in request the 1261 * memory region the next time probe is called. 1262 */ 1263 res->start -= DWC3_GLOBALS_REGS_START; 1264 1265 dwc3_debugfs_exit(dwc); 1266 dwc3_core_exit_mode(dwc); 1267 1268 dwc3_core_exit(dwc); 1269 dwc3_ulpi_exit(dwc); 1270 1271 pm_runtime_put_sync(&pdev->dev); 1272 pm_runtime_allow(&pdev->dev); 1273 pm_runtime_disable(&pdev->dev); 1274 1275 dwc3_free_event_buffers(dwc); 1276 dwc3_free_scratch_buffers(dwc); 1277 1278 return 0; 1279 } 1280 1281 #ifdef CONFIG_PM 1282 static int dwc3_suspend_common(struct dwc3 *dwc) 1283 { 1284 unsigned long flags; 1285 1286 switch (dwc->current_dr_role) { 1287 case DWC3_GCTL_PRTCAP_DEVICE: 1288 spin_lock_irqsave(&dwc->lock, flags); 1289 dwc3_gadget_suspend(dwc); 1290 spin_unlock_irqrestore(&dwc->lock, flags); 1291 dwc3_core_exit(dwc); 1292 break; 1293 case DWC3_GCTL_PRTCAP_HOST: 1294 default: 1295 /* do nothing */ 1296 break; 1297 } 1298 1299 return 0; 1300 } 1301 1302 static int dwc3_resume_common(struct dwc3 *dwc) 1303 { 1304 unsigned long flags; 1305 int ret; 1306 1307 switch (dwc->current_dr_role) { 1308 case DWC3_GCTL_PRTCAP_DEVICE: 1309 ret = dwc3_core_init(dwc); 1310 if (ret) 1311 return ret; 1312 1313 spin_lock_irqsave(&dwc->lock, flags); 1314 dwc3_gadget_resume(dwc); 1315 spin_unlock_irqrestore(&dwc->lock, flags); 1316 break; 1317 case DWC3_GCTL_PRTCAP_HOST: 1318 default: 1319 /* do nothing */ 1320 break; 1321 } 1322 1323 return 0; 1324 } 1325 1326 static int dwc3_runtime_checks(struct dwc3 *dwc) 1327 { 1328 switch (dwc->current_dr_role) { 1329 case USB_DR_MODE_PERIPHERAL: 1330 case USB_DR_MODE_OTG: 1331 if (dwc->connected) 1332 return -EBUSY; 1333 break; 1334 case USB_DR_MODE_HOST: 1335 default: 1336 /* do nothing */ 1337 break; 1338 } 1339 1340 return 0; 1341 } 1342 1343 static int dwc3_runtime_suspend(struct device *dev) 1344 { 1345 struct dwc3 *dwc = dev_get_drvdata(dev); 1346 int ret; 1347 1348 if (dwc3_runtime_checks(dwc)) 1349 return -EBUSY; 1350 1351 ret = dwc3_suspend_common(dwc); 1352 if (ret) 1353 return ret; 1354 1355 device_init_wakeup(dev, true); 1356 1357 return 0; 1358 } 1359 1360 static int dwc3_runtime_resume(struct device *dev) 1361 { 1362 struct dwc3 *dwc = dev_get_drvdata(dev); 1363 int ret; 1364 1365 device_init_wakeup(dev, false); 1366 1367 ret = dwc3_resume_common(dwc); 1368 if (ret) 1369 return ret; 1370 1371 switch (dwc->current_dr_role) { 1372 case DWC3_GCTL_PRTCAP_DEVICE: 1373 dwc3_gadget_process_pending_events(dwc); 1374 break; 1375 case DWC3_GCTL_PRTCAP_HOST: 1376 default: 1377 /* do nothing */ 1378 break; 1379 } 1380 1381 pm_runtime_mark_last_busy(dev); 1382 1383 return 0; 1384 } 1385 1386 static int dwc3_runtime_idle(struct device *dev) 1387 { 1388 struct dwc3 *dwc = dev_get_drvdata(dev); 1389 1390 switch (dwc->current_dr_role) { 1391 case DWC3_GCTL_PRTCAP_DEVICE: 1392 if (dwc3_runtime_checks(dwc)) 1393 return -EBUSY; 1394 break; 1395 case DWC3_GCTL_PRTCAP_HOST: 1396 default: 1397 /* do nothing */ 1398 break; 1399 } 1400 1401 pm_runtime_mark_last_busy(dev); 1402 pm_runtime_autosuspend(dev); 1403 1404 return 0; 1405 } 1406 #endif /* CONFIG_PM */ 1407 1408 #ifdef CONFIG_PM_SLEEP 1409 static int dwc3_suspend(struct device *dev) 1410 { 1411 struct dwc3 *dwc = dev_get_drvdata(dev); 1412 int ret; 1413 1414 ret = dwc3_suspend_common(dwc); 1415 if (ret) 1416 return ret; 1417 1418 pinctrl_pm_select_sleep_state(dev); 1419 1420 return 0; 1421 } 1422 1423 static int dwc3_resume(struct device *dev) 1424 { 1425 struct dwc3 *dwc = dev_get_drvdata(dev); 1426 int ret; 1427 1428 pinctrl_pm_select_default_state(dev); 1429 1430 ret = dwc3_resume_common(dwc); 1431 if (ret) 1432 return ret; 1433 1434 pm_runtime_disable(dev); 1435 pm_runtime_set_active(dev); 1436 pm_runtime_enable(dev); 1437 1438 return 0; 1439 } 1440 #endif /* CONFIG_PM_SLEEP */ 1441 1442 static const struct dev_pm_ops dwc3_dev_pm_ops = { 1443 SET_SYSTEM_SLEEP_PM_OPS(dwc3_suspend, dwc3_resume) 1444 SET_RUNTIME_PM_OPS(dwc3_runtime_suspend, dwc3_runtime_resume, 1445 dwc3_runtime_idle) 1446 }; 1447 1448 #ifdef CONFIG_OF 1449 static const struct of_device_id of_dwc3_match[] = { 1450 { 1451 .compatible = "snps,dwc3" 1452 }, 1453 { 1454 .compatible = "synopsys,dwc3" 1455 }, 1456 { }, 1457 }; 1458 MODULE_DEVICE_TABLE(of, of_dwc3_match); 1459 #endif 1460 1461 #ifdef CONFIG_ACPI 1462 1463 #define ACPI_ID_INTEL_BSW "808622B7" 1464 1465 static const struct acpi_device_id dwc3_acpi_match[] = { 1466 { ACPI_ID_INTEL_BSW, 0 }, 1467 { }, 1468 }; 1469 MODULE_DEVICE_TABLE(acpi, dwc3_acpi_match); 1470 #endif 1471 1472 static struct platform_driver dwc3_driver = { 1473 .probe = dwc3_probe, 1474 .remove = dwc3_remove, 1475 .driver = { 1476 .name = "dwc3", 1477 .of_match_table = of_match_ptr(of_dwc3_match), 1478 .acpi_match_table = ACPI_PTR(dwc3_acpi_match), 1479 .pm = &dwc3_dev_pm_ops, 1480 }, 1481 }; 1482 1483 module_platform_driver(dwc3_driver); 1484 1485 MODULE_ALIAS("platform:dwc3"); 1486 MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>"); 1487 MODULE_LICENSE("GPL v2"); 1488 MODULE_DESCRIPTION("DesignWare USB3 DRD Controller Driver"); 1489