1 /** 2 * core.c - DesignWare USB3 DRD Controller Core file 3 * 4 * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com 5 * 6 * Authors: Felipe Balbi <balbi@ti.com>, 7 * Sebastian Andrzej Siewior <bigeasy@linutronix.de> 8 * 9 * This program is free software: you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License version 2 of 11 * the License as published by the Free Software Foundation. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program. If not, see <http://www.gnu.org/licenses/>. 20 */ 21 22 #include <linux/version.h> 23 #include <linux/module.h> 24 #include <linux/kernel.h> 25 #include <linux/slab.h> 26 #include <linux/spinlock.h> 27 #include <linux/platform_device.h> 28 #include <linux/pm_runtime.h> 29 #include <linux/interrupt.h> 30 #include <linux/ioport.h> 31 #include <linux/io.h> 32 #include <linux/list.h> 33 #include <linux/delay.h> 34 #include <linux/dma-mapping.h> 35 #include <linux/of.h> 36 #include <linux/acpi.h> 37 38 #include <linux/usb/ch9.h> 39 #include <linux/usb/gadget.h> 40 #include <linux/usb/of.h> 41 #include <linux/usb/otg.h> 42 43 #include "platform_data.h" 44 #include "core.h" 45 #include "gadget.h" 46 #include "io.h" 47 48 #include "debug.h" 49 50 /* -------------------------------------------------------------------------- */ 51 52 void dwc3_set_mode(struct dwc3 *dwc, u32 mode) 53 { 54 u32 reg; 55 56 reg = dwc3_readl(dwc->regs, DWC3_GCTL); 57 reg &= ~(DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_OTG)); 58 reg |= DWC3_GCTL_PRTCAPDIR(mode); 59 dwc3_writel(dwc->regs, DWC3_GCTL, reg); 60 } 61 62 /** 63 * dwc3_core_soft_reset - Issues core soft reset and PHY reset 64 * @dwc: pointer to our context structure 65 */ 66 static int dwc3_core_soft_reset(struct dwc3 *dwc) 67 { 68 u32 reg; 69 int ret; 70 71 /* Before Resetting PHY, put Core in Reset */ 72 reg = dwc3_readl(dwc->regs, DWC3_GCTL); 73 reg |= DWC3_GCTL_CORESOFTRESET; 74 dwc3_writel(dwc->regs, DWC3_GCTL, reg); 75 76 /* Assert USB3 PHY reset */ 77 reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0)); 78 reg |= DWC3_GUSB3PIPECTL_PHYSOFTRST; 79 dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg); 80 81 /* Assert USB2 PHY reset */ 82 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0)); 83 reg |= DWC3_GUSB2PHYCFG_PHYSOFTRST; 84 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg); 85 86 usb_phy_init(dwc->usb2_phy); 87 usb_phy_init(dwc->usb3_phy); 88 ret = phy_init(dwc->usb2_generic_phy); 89 if (ret < 0) 90 return ret; 91 92 ret = phy_init(dwc->usb3_generic_phy); 93 if (ret < 0) { 94 phy_exit(dwc->usb2_generic_phy); 95 return ret; 96 } 97 mdelay(100); 98 99 /* Clear USB3 PHY reset */ 100 reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0)); 101 reg &= ~DWC3_GUSB3PIPECTL_PHYSOFTRST; 102 dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg); 103 104 /* Clear USB2 PHY reset */ 105 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0)); 106 reg &= ~DWC3_GUSB2PHYCFG_PHYSOFTRST; 107 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg); 108 109 mdelay(100); 110 111 /* After PHYs are stable we can take Core out of reset state */ 112 reg = dwc3_readl(dwc->regs, DWC3_GCTL); 113 reg &= ~DWC3_GCTL_CORESOFTRESET; 114 dwc3_writel(dwc->regs, DWC3_GCTL, reg); 115 116 return 0; 117 } 118 119 /** 120 * dwc3_soft_reset - Issue soft reset 121 * @dwc: Pointer to our controller context structure 122 */ 123 static int dwc3_soft_reset(struct dwc3 *dwc) 124 { 125 unsigned long timeout; 126 u32 reg; 127 128 timeout = jiffies + msecs_to_jiffies(500); 129 dwc3_writel(dwc->regs, DWC3_DCTL, DWC3_DCTL_CSFTRST); 130 do { 131 reg = dwc3_readl(dwc->regs, DWC3_DCTL); 132 if (!(reg & DWC3_DCTL_CSFTRST)) 133 break; 134 135 if (time_after(jiffies, timeout)) { 136 dev_err(dwc->dev, "Reset Timed Out\n"); 137 return -ETIMEDOUT; 138 } 139 140 cpu_relax(); 141 } while (true); 142 143 return 0; 144 } 145 146 /** 147 * dwc3_free_one_event_buffer - Frees one event buffer 148 * @dwc: Pointer to our controller context structure 149 * @evt: Pointer to event buffer to be freed 150 */ 151 static void dwc3_free_one_event_buffer(struct dwc3 *dwc, 152 struct dwc3_event_buffer *evt) 153 { 154 dma_free_coherent(dwc->dev, evt->length, evt->buf, evt->dma); 155 } 156 157 /** 158 * dwc3_alloc_one_event_buffer - Allocates one event buffer structure 159 * @dwc: Pointer to our controller context structure 160 * @length: size of the event buffer 161 * 162 * Returns a pointer to the allocated event buffer structure on success 163 * otherwise ERR_PTR(errno). 164 */ 165 static struct dwc3_event_buffer *dwc3_alloc_one_event_buffer(struct dwc3 *dwc, 166 unsigned length) 167 { 168 struct dwc3_event_buffer *evt; 169 170 evt = devm_kzalloc(dwc->dev, sizeof(*evt), GFP_KERNEL); 171 if (!evt) 172 return ERR_PTR(-ENOMEM); 173 174 evt->dwc = dwc; 175 evt->length = length; 176 evt->buf = dma_alloc_coherent(dwc->dev, length, 177 &evt->dma, GFP_KERNEL); 178 if (!evt->buf) 179 return ERR_PTR(-ENOMEM); 180 181 return evt; 182 } 183 184 /** 185 * dwc3_free_event_buffers - frees all allocated event buffers 186 * @dwc: Pointer to our controller context structure 187 */ 188 static void dwc3_free_event_buffers(struct dwc3 *dwc) 189 { 190 struct dwc3_event_buffer *evt; 191 int i; 192 193 for (i = 0; i < dwc->num_event_buffers; i++) { 194 evt = dwc->ev_buffs[i]; 195 if (evt) 196 dwc3_free_one_event_buffer(dwc, evt); 197 } 198 } 199 200 /** 201 * dwc3_alloc_event_buffers - Allocates @num event buffers of size @length 202 * @dwc: pointer to our controller context structure 203 * @length: size of event buffer 204 * 205 * Returns 0 on success otherwise negative errno. In the error case, dwc 206 * may contain some buffers allocated but not all which were requested. 207 */ 208 static int dwc3_alloc_event_buffers(struct dwc3 *dwc, unsigned length) 209 { 210 int num; 211 int i; 212 213 num = DWC3_NUM_INT(dwc->hwparams.hwparams1); 214 dwc->num_event_buffers = num; 215 216 dwc->ev_buffs = devm_kzalloc(dwc->dev, sizeof(*dwc->ev_buffs) * num, 217 GFP_KERNEL); 218 if (!dwc->ev_buffs) 219 return -ENOMEM; 220 221 for (i = 0; i < num; i++) { 222 struct dwc3_event_buffer *evt; 223 224 evt = dwc3_alloc_one_event_buffer(dwc, length); 225 if (IS_ERR(evt)) { 226 dev_err(dwc->dev, "can't allocate event buffer\n"); 227 return PTR_ERR(evt); 228 } 229 dwc->ev_buffs[i] = evt; 230 } 231 232 return 0; 233 } 234 235 /** 236 * dwc3_event_buffers_setup - setup our allocated event buffers 237 * @dwc: pointer to our controller context structure 238 * 239 * Returns 0 on success otherwise negative errno. 240 */ 241 static int dwc3_event_buffers_setup(struct dwc3 *dwc) 242 { 243 struct dwc3_event_buffer *evt; 244 int n; 245 246 for (n = 0; n < dwc->num_event_buffers; n++) { 247 evt = dwc->ev_buffs[n]; 248 dev_dbg(dwc->dev, "Event buf %p dma %08llx length %d\n", 249 evt->buf, (unsigned long long) evt->dma, 250 evt->length); 251 252 evt->lpos = 0; 253 254 dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(n), 255 lower_32_bits(evt->dma)); 256 dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(n), 257 upper_32_bits(evt->dma)); 258 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(n), 259 DWC3_GEVNTSIZ_SIZE(evt->length)); 260 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(n), 0); 261 } 262 263 return 0; 264 } 265 266 static void dwc3_event_buffers_cleanup(struct dwc3 *dwc) 267 { 268 struct dwc3_event_buffer *evt; 269 int n; 270 271 for (n = 0; n < dwc->num_event_buffers; n++) { 272 evt = dwc->ev_buffs[n]; 273 274 evt->lpos = 0; 275 276 dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(n), 0); 277 dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(n), 0); 278 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(n), DWC3_GEVNTSIZ_INTMASK 279 | DWC3_GEVNTSIZ_SIZE(0)); 280 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(n), 0); 281 } 282 } 283 284 static int dwc3_alloc_scratch_buffers(struct dwc3 *dwc) 285 { 286 if (!dwc->has_hibernation) 287 return 0; 288 289 if (!dwc->nr_scratch) 290 return 0; 291 292 dwc->scratchbuf = kmalloc_array(dwc->nr_scratch, 293 DWC3_SCRATCHBUF_SIZE, GFP_KERNEL); 294 if (!dwc->scratchbuf) 295 return -ENOMEM; 296 297 return 0; 298 } 299 300 static int dwc3_setup_scratch_buffers(struct dwc3 *dwc) 301 { 302 dma_addr_t scratch_addr; 303 u32 param; 304 int ret; 305 306 if (!dwc->has_hibernation) 307 return 0; 308 309 if (!dwc->nr_scratch) 310 return 0; 311 312 /* should never fall here */ 313 if (!WARN_ON(dwc->scratchbuf)) 314 return 0; 315 316 scratch_addr = dma_map_single(dwc->dev, dwc->scratchbuf, 317 dwc->nr_scratch * DWC3_SCRATCHBUF_SIZE, 318 DMA_BIDIRECTIONAL); 319 if (dma_mapping_error(dwc->dev, scratch_addr)) { 320 dev_err(dwc->dev, "failed to map scratch buffer\n"); 321 ret = -EFAULT; 322 goto err0; 323 } 324 325 dwc->scratch_addr = scratch_addr; 326 327 param = lower_32_bits(scratch_addr); 328 329 ret = dwc3_send_gadget_generic_command(dwc, 330 DWC3_DGCMD_SET_SCRATCHPAD_ADDR_LO, param); 331 if (ret < 0) 332 goto err1; 333 334 param = upper_32_bits(scratch_addr); 335 336 ret = dwc3_send_gadget_generic_command(dwc, 337 DWC3_DGCMD_SET_SCRATCHPAD_ADDR_HI, param); 338 if (ret < 0) 339 goto err1; 340 341 return 0; 342 343 err1: 344 dma_unmap_single(dwc->dev, dwc->scratch_addr, dwc->nr_scratch * 345 DWC3_SCRATCHBUF_SIZE, DMA_BIDIRECTIONAL); 346 347 err0: 348 return ret; 349 } 350 351 static void dwc3_free_scratch_buffers(struct dwc3 *dwc) 352 { 353 if (!dwc->has_hibernation) 354 return; 355 356 if (!dwc->nr_scratch) 357 return; 358 359 /* should never fall here */ 360 if (!WARN_ON(dwc->scratchbuf)) 361 return; 362 363 dma_unmap_single(dwc->dev, dwc->scratch_addr, dwc->nr_scratch * 364 DWC3_SCRATCHBUF_SIZE, DMA_BIDIRECTIONAL); 365 kfree(dwc->scratchbuf); 366 } 367 368 static void dwc3_core_num_eps(struct dwc3 *dwc) 369 { 370 struct dwc3_hwparams *parms = &dwc->hwparams; 371 372 dwc->num_in_eps = DWC3_NUM_IN_EPS(parms); 373 dwc->num_out_eps = DWC3_NUM_EPS(parms) - dwc->num_in_eps; 374 375 dwc3_trace(trace_dwc3_core, "found %d IN and %d OUT endpoints", 376 dwc->num_in_eps, dwc->num_out_eps); 377 } 378 379 static void dwc3_cache_hwparams(struct dwc3 *dwc) 380 { 381 struct dwc3_hwparams *parms = &dwc->hwparams; 382 383 parms->hwparams0 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS0); 384 parms->hwparams1 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS1); 385 parms->hwparams2 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS2); 386 parms->hwparams3 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS3); 387 parms->hwparams4 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS4); 388 parms->hwparams5 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS5); 389 parms->hwparams6 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS6); 390 parms->hwparams7 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS7); 391 parms->hwparams8 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS8); 392 } 393 394 /** 395 * dwc3_phy_setup - Configure USB PHY Interface of DWC3 Core 396 * @dwc: Pointer to our controller context structure 397 * 398 * Returns 0 on success. The USB PHY interfaces are configured but not 399 * initialized. The PHY interfaces and the PHYs get initialized together with 400 * the core in dwc3_core_init. 401 */ 402 static int dwc3_phy_setup(struct dwc3 *dwc) 403 { 404 u32 reg; 405 int ret; 406 407 reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0)); 408 409 /* 410 * Above 1.94a, it is recommended to set DWC3_GUSB3PIPECTL_SUSPHY 411 * to '0' during coreConsultant configuration. So default value 412 * will be '0' when the core is reset. Application needs to set it 413 * to '1' after the core initialization is completed. 414 */ 415 if (dwc->revision > DWC3_REVISION_194A) 416 reg |= DWC3_GUSB3PIPECTL_SUSPHY; 417 418 if (dwc->u2ss_inp3_quirk) 419 reg |= DWC3_GUSB3PIPECTL_U2SSINP3OK; 420 421 if (dwc->req_p1p2p3_quirk) 422 reg |= DWC3_GUSB3PIPECTL_REQP1P2P3; 423 424 if (dwc->del_p1p2p3_quirk) 425 reg |= DWC3_GUSB3PIPECTL_DEP1P2P3_EN; 426 427 if (dwc->del_phy_power_chg_quirk) 428 reg |= DWC3_GUSB3PIPECTL_DEPOCHANGE; 429 430 if (dwc->lfps_filter_quirk) 431 reg |= DWC3_GUSB3PIPECTL_LFPSFILT; 432 433 if (dwc->rx_detect_poll_quirk) 434 reg |= DWC3_GUSB3PIPECTL_RX_DETOPOLL; 435 436 if (dwc->tx_de_emphasis_quirk) 437 reg |= DWC3_GUSB3PIPECTL_TX_DEEPH(dwc->tx_de_emphasis); 438 439 if (dwc->dis_u3_susphy_quirk) 440 reg &= ~DWC3_GUSB3PIPECTL_SUSPHY; 441 442 dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg); 443 444 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0)); 445 446 /* Select the HS PHY interface */ 447 switch (DWC3_GHWPARAMS3_HSPHY_IFC(dwc->hwparams.hwparams3)) { 448 case DWC3_GHWPARAMS3_HSPHY_IFC_UTMI_ULPI: 449 if (dwc->hsphy_interface && 450 !strncmp(dwc->hsphy_interface, "utmi", 4)) { 451 reg &= ~DWC3_GUSB2PHYCFG_ULPI_UTMI; 452 break; 453 } else if (dwc->hsphy_interface && 454 !strncmp(dwc->hsphy_interface, "ulpi", 4)) { 455 reg |= DWC3_GUSB2PHYCFG_ULPI_UTMI; 456 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg); 457 } else { 458 /* Relying on default value. */ 459 if (!(reg & DWC3_GUSB2PHYCFG_ULPI_UTMI)) 460 break; 461 } 462 /* FALLTHROUGH */ 463 case DWC3_GHWPARAMS3_HSPHY_IFC_ULPI: 464 /* Making sure the interface and PHY are operational */ 465 ret = dwc3_soft_reset(dwc); 466 if (ret) 467 return ret; 468 469 udelay(1); 470 471 ret = dwc3_ulpi_init(dwc); 472 if (ret) 473 return ret; 474 /* FALLTHROUGH */ 475 default: 476 break; 477 } 478 479 /* 480 * Above 1.94a, it is recommended to set DWC3_GUSB2PHYCFG_SUSPHY to 481 * '0' during coreConsultant configuration. So default value will 482 * be '0' when the core is reset. Application needs to set it to 483 * '1' after the core initialization is completed. 484 */ 485 if (dwc->revision > DWC3_REVISION_194A) 486 reg |= DWC3_GUSB2PHYCFG_SUSPHY; 487 488 if (dwc->dis_u2_susphy_quirk) 489 reg &= ~DWC3_GUSB2PHYCFG_SUSPHY; 490 491 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg); 492 493 return 0; 494 } 495 496 /** 497 * dwc3_core_init - Low-level initialization of DWC3 Core 498 * @dwc: Pointer to our controller context structure 499 * 500 * Returns 0 on success otherwise negative errno. 501 */ 502 static int dwc3_core_init(struct dwc3 *dwc) 503 { 504 u32 hwparams4 = dwc->hwparams.hwparams4; 505 u32 reg; 506 int ret; 507 508 reg = dwc3_readl(dwc->regs, DWC3_GSNPSID); 509 /* This should read as U3 followed by revision number */ 510 if ((reg & DWC3_GSNPSID_MASK) != 0x55330000) { 511 dev_err(dwc->dev, "this is not a DesignWare USB3 DRD Core\n"); 512 ret = -ENODEV; 513 goto err0; 514 } 515 dwc->revision = reg; 516 517 /* 518 * Write Linux Version Code to our GUID register so it's easy to figure 519 * out which kernel version a bug was found. 520 */ 521 dwc3_writel(dwc->regs, DWC3_GUID, LINUX_VERSION_CODE); 522 523 /* Handle USB2.0-only core configuration */ 524 if (DWC3_GHWPARAMS3_SSPHY_IFC(dwc->hwparams.hwparams3) == 525 DWC3_GHWPARAMS3_SSPHY_IFC_DIS) { 526 if (dwc->maximum_speed == USB_SPEED_SUPER) 527 dwc->maximum_speed = USB_SPEED_HIGH; 528 } 529 530 /* issue device SoftReset too */ 531 ret = dwc3_soft_reset(dwc); 532 if (ret) 533 goto err0; 534 535 ret = dwc3_core_soft_reset(dwc); 536 if (ret) 537 goto err0; 538 539 reg = dwc3_readl(dwc->regs, DWC3_GCTL); 540 reg &= ~DWC3_GCTL_SCALEDOWN_MASK; 541 542 switch (DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1)) { 543 case DWC3_GHWPARAMS1_EN_PWROPT_CLK: 544 /** 545 * WORKAROUND: DWC3 revisions between 2.10a and 2.50a have an 546 * issue which would cause xHCI compliance tests to fail. 547 * 548 * Because of that we cannot enable clock gating on such 549 * configurations. 550 * 551 * Refers to: 552 * 553 * STAR#9000588375: Clock Gating, SOF Issues when ref_clk-Based 554 * SOF/ITP Mode Used 555 */ 556 if ((dwc->dr_mode == USB_DR_MODE_HOST || 557 dwc->dr_mode == USB_DR_MODE_OTG) && 558 (dwc->revision >= DWC3_REVISION_210A && 559 dwc->revision <= DWC3_REVISION_250A)) 560 reg |= DWC3_GCTL_DSBLCLKGTNG | DWC3_GCTL_SOFITPSYNC; 561 else 562 reg &= ~DWC3_GCTL_DSBLCLKGTNG; 563 break; 564 case DWC3_GHWPARAMS1_EN_PWROPT_HIB: 565 /* enable hibernation here */ 566 dwc->nr_scratch = DWC3_GHWPARAMS4_HIBER_SCRATCHBUFS(hwparams4); 567 568 /* 569 * REVISIT Enabling this bit so that host-mode hibernation 570 * will work. Device-mode hibernation is not yet implemented. 571 */ 572 reg |= DWC3_GCTL_GBLHIBERNATIONEN; 573 break; 574 default: 575 dev_dbg(dwc->dev, "No power optimization available\n"); 576 } 577 578 /* check if current dwc3 is on simulation board */ 579 if (dwc->hwparams.hwparams6 & DWC3_GHWPARAMS6_EN_FPGA) { 580 dev_dbg(dwc->dev, "it is on FPGA board\n"); 581 dwc->is_fpga = true; 582 } 583 584 WARN_ONCE(dwc->disable_scramble_quirk && !dwc->is_fpga, 585 "disable_scramble cannot be used on non-FPGA builds\n"); 586 587 if (dwc->disable_scramble_quirk && dwc->is_fpga) 588 reg |= DWC3_GCTL_DISSCRAMBLE; 589 else 590 reg &= ~DWC3_GCTL_DISSCRAMBLE; 591 592 if (dwc->u2exit_lfps_quirk) 593 reg |= DWC3_GCTL_U2EXIT_LFPS; 594 595 /* 596 * WORKAROUND: DWC3 revisions <1.90a have a bug 597 * where the device can fail to connect at SuperSpeed 598 * and falls back to high-speed mode which causes 599 * the device to enter a Connect/Disconnect loop 600 */ 601 if (dwc->revision < DWC3_REVISION_190A) 602 reg |= DWC3_GCTL_U2RSTECN; 603 604 dwc3_core_num_eps(dwc); 605 606 dwc3_writel(dwc->regs, DWC3_GCTL, reg); 607 608 ret = dwc3_alloc_scratch_buffers(dwc); 609 if (ret) 610 goto err1; 611 612 ret = dwc3_setup_scratch_buffers(dwc); 613 if (ret) 614 goto err2; 615 616 return 0; 617 618 err2: 619 dwc3_free_scratch_buffers(dwc); 620 621 err1: 622 usb_phy_shutdown(dwc->usb2_phy); 623 usb_phy_shutdown(dwc->usb3_phy); 624 phy_exit(dwc->usb2_generic_phy); 625 phy_exit(dwc->usb3_generic_phy); 626 627 err0: 628 return ret; 629 } 630 631 static void dwc3_core_exit(struct dwc3 *dwc) 632 { 633 dwc3_free_scratch_buffers(dwc); 634 usb_phy_shutdown(dwc->usb2_phy); 635 usb_phy_shutdown(dwc->usb3_phy); 636 phy_exit(dwc->usb2_generic_phy); 637 phy_exit(dwc->usb3_generic_phy); 638 } 639 640 static int dwc3_core_get_phy(struct dwc3 *dwc) 641 { 642 struct device *dev = dwc->dev; 643 struct device_node *node = dev->of_node; 644 int ret; 645 646 if (node) { 647 dwc->usb2_phy = devm_usb_get_phy_by_phandle(dev, "usb-phy", 0); 648 dwc->usb3_phy = devm_usb_get_phy_by_phandle(dev, "usb-phy", 1); 649 } else { 650 dwc->usb2_phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB2); 651 dwc->usb3_phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB3); 652 } 653 654 if (IS_ERR(dwc->usb2_phy)) { 655 ret = PTR_ERR(dwc->usb2_phy); 656 if (ret == -ENXIO || ret == -ENODEV) { 657 dwc->usb2_phy = NULL; 658 } else if (ret == -EPROBE_DEFER) { 659 return ret; 660 } else { 661 dev_err(dev, "no usb2 phy configured\n"); 662 return ret; 663 } 664 } 665 666 if (IS_ERR(dwc->usb3_phy)) { 667 ret = PTR_ERR(dwc->usb3_phy); 668 if (ret == -ENXIO || ret == -ENODEV) { 669 dwc->usb3_phy = NULL; 670 } else if (ret == -EPROBE_DEFER) { 671 return ret; 672 } else { 673 dev_err(dev, "no usb3 phy configured\n"); 674 return ret; 675 } 676 } 677 678 dwc->usb2_generic_phy = devm_phy_get(dev, "usb2-phy"); 679 if (IS_ERR(dwc->usb2_generic_phy)) { 680 ret = PTR_ERR(dwc->usb2_generic_phy); 681 if (ret == -ENOSYS || ret == -ENODEV) { 682 dwc->usb2_generic_phy = NULL; 683 } else if (ret == -EPROBE_DEFER) { 684 return ret; 685 } else { 686 dev_err(dev, "no usb2 phy configured\n"); 687 return ret; 688 } 689 } 690 691 dwc->usb3_generic_phy = devm_phy_get(dev, "usb3-phy"); 692 if (IS_ERR(dwc->usb3_generic_phy)) { 693 ret = PTR_ERR(dwc->usb3_generic_phy); 694 if (ret == -ENOSYS || ret == -ENODEV) { 695 dwc->usb3_generic_phy = NULL; 696 } else if (ret == -EPROBE_DEFER) { 697 return ret; 698 } else { 699 dev_err(dev, "no usb3 phy configured\n"); 700 return ret; 701 } 702 } 703 704 return 0; 705 } 706 707 static int dwc3_core_init_mode(struct dwc3 *dwc) 708 { 709 struct device *dev = dwc->dev; 710 int ret; 711 712 switch (dwc->dr_mode) { 713 case USB_DR_MODE_PERIPHERAL: 714 dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_DEVICE); 715 ret = dwc3_gadget_init(dwc); 716 if (ret) { 717 dev_err(dev, "failed to initialize gadget\n"); 718 return ret; 719 } 720 break; 721 case USB_DR_MODE_HOST: 722 dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_HOST); 723 ret = dwc3_host_init(dwc); 724 if (ret) { 725 dev_err(dev, "failed to initialize host\n"); 726 return ret; 727 } 728 break; 729 case USB_DR_MODE_OTG: 730 dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_OTG); 731 ret = dwc3_host_init(dwc); 732 if (ret) { 733 dev_err(dev, "failed to initialize host\n"); 734 return ret; 735 } 736 737 ret = dwc3_gadget_init(dwc); 738 if (ret) { 739 dev_err(dev, "failed to initialize gadget\n"); 740 return ret; 741 } 742 break; 743 default: 744 dev_err(dev, "Unsupported mode of operation %d\n", dwc->dr_mode); 745 return -EINVAL; 746 } 747 748 return 0; 749 } 750 751 static void dwc3_core_exit_mode(struct dwc3 *dwc) 752 { 753 switch (dwc->dr_mode) { 754 case USB_DR_MODE_PERIPHERAL: 755 dwc3_gadget_exit(dwc); 756 break; 757 case USB_DR_MODE_HOST: 758 dwc3_host_exit(dwc); 759 break; 760 case USB_DR_MODE_OTG: 761 dwc3_host_exit(dwc); 762 dwc3_gadget_exit(dwc); 763 break; 764 default: 765 /* do nothing */ 766 break; 767 } 768 } 769 770 #define DWC3_ALIGN_MASK (16 - 1) 771 772 static int dwc3_probe(struct platform_device *pdev) 773 { 774 struct device *dev = &pdev->dev; 775 struct dwc3_platform_data *pdata = dev_get_platdata(dev); 776 struct device_node *node = dev->of_node; 777 struct resource *res; 778 struct dwc3 *dwc; 779 u8 lpm_nyet_threshold; 780 u8 tx_de_emphasis; 781 u8 hird_threshold; 782 783 int ret; 784 785 void __iomem *regs; 786 void *mem; 787 788 mem = devm_kzalloc(dev, sizeof(*dwc) + DWC3_ALIGN_MASK, GFP_KERNEL); 789 if (!mem) 790 return -ENOMEM; 791 792 dwc = PTR_ALIGN(mem, DWC3_ALIGN_MASK + 1); 793 dwc->mem = mem; 794 dwc->dev = dev; 795 796 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); 797 if (!res) { 798 dev_err(dev, "missing IRQ\n"); 799 return -ENODEV; 800 } 801 dwc->xhci_resources[1].start = res->start; 802 dwc->xhci_resources[1].end = res->end; 803 dwc->xhci_resources[1].flags = res->flags; 804 dwc->xhci_resources[1].name = res->name; 805 806 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 807 if (!res) { 808 dev_err(dev, "missing memory resource\n"); 809 return -ENODEV; 810 } 811 812 dwc->xhci_resources[0].start = res->start; 813 dwc->xhci_resources[0].end = dwc->xhci_resources[0].start + 814 DWC3_XHCI_REGS_END; 815 dwc->xhci_resources[0].flags = res->flags; 816 dwc->xhci_resources[0].name = res->name; 817 818 res->start += DWC3_GLOBALS_REGS_START; 819 820 /* 821 * Request memory region but exclude xHCI regs, 822 * since it will be requested by the xhci-plat driver. 823 */ 824 regs = devm_ioremap_resource(dev, res); 825 if (IS_ERR(regs)) { 826 ret = PTR_ERR(regs); 827 goto err0; 828 } 829 830 dwc->regs = regs; 831 dwc->regs_size = resource_size(res); 832 833 /* default to highest possible threshold */ 834 lpm_nyet_threshold = 0xff; 835 836 /* default to -3.5dB de-emphasis */ 837 tx_de_emphasis = 1; 838 839 /* 840 * default to assert utmi_sleep_n and use maximum allowed HIRD 841 * threshold value of 0b1100 842 */ 843 hird_threshold = 12; 844 845 if (node) { 846 dwc->maximum_speed = of_usb_get_maximum_speed(node); 847 dwc->has_lpm_erratum = of_property_read_bool(node, 848 "snps,has-lpm-erratum"); 849 of_property_read_u8(node, "snps,lpm-nyet-threshold", 850 &lpm_nyet_threshold); 851 dwc->is_utmi_l1_suspend = of_property_read_bool(node, 852 "snps,is-utmi-l1-suspend"); 853 of_property_read_u8(node, "snps,hird-threshold", 854 &hird_threshold); 855 dwc->usb3_lpm_capable = of_property_read_bool(node, 856 "snps,usb3_lpm_capable"); 857 858 dwc->needs_fifo_resize = of_property_read_bool(node, 859 "tx-fifo-resize"); 860 dwc->dr_mode = of_usb_get_dr_mode(node); 861 862 dwc->disable_scramble_quirk = of_property_read_bool(node, 863 "snps,disable_scramble_quirk"); 864 dwc->u2exit_lfps_quirk = of_property_read_bool(node, 865 "snps,u2exit_lfps_quirk"); 866 dwc->u2ss_inp3_quirk = of_property_read_bool(node, 867 "snps,u2ss_inp3_quirk"); 868 dwc->req_p1p2p3_quirk = of_property_read_bool(node, 869 "snps,req_p1p2p3_quirk"); 870 dwc->del_p1p2p3_quirk = of_property_read_bool(node, 871 "snps,del_p1p2p3_quirk"); 872 dwc->del_phy_power_chg_quirk = of_property_read_bool(node, 873 "snps,del_phy_power_chg_quirk"); 874 dwc->lfps_filter_quirk = of_property_read_bool(node, 875 "snps,lfps_filter_quirk"); 876 dwc->rx_detect_poll_quirk = of_property_read_bool(node, 877 "snps,rx_detect_poll_quirk"); 878 dwc->dis_u3_susphy_quirk = of_property_read_bool(node, 879 "snps,dis_u3_susphy_quirk"); 880 dwc->dis_u2_susphy_quirk = of_property_read_bool(node, 881 "snps,dis_u2_susphy_quirk"); 882 883 dwc->tx_de_emphasis_quirk = of_property_read_bool(node, 884 "snps,tx_de_emphasis_quirk"); 885 of_property_read_u8(node, "snps,tx_de_emphasis", 886 &tx_de_emphasis); 887 of_property_read_string(node, "snps,hsphy_interface", 888 &dwc->hsphy_interface); 889 } else if (pdata) { 890 dwc->maximum_speed = pdata->maximum_speed; 891 dwc->has_lpm_erratum = pdata->has_lpm_erratum; 892 if (pdata->lpm_nyet_threshold) 893 lpm_nyet_threshold = pdata->lpm_nyet_threshold; 894 dwc->is_utmi_l1_suspend = pdata->is_utmi_l1_suspend; 895 if (pdata->hird_threshold) 896 hird_threshold = pdata->hird_threshold; 897 898 dwc->needs_fifo_resize = pdata->tx_fifo_resize; 899 dwc->usb3_lpm_capable = pdata->usb3_lpm_capable; 900 dwc->dr_mode = pdata->dr_mode; 901 902 dwc->disable_scramble_quirk = pdata->disable_scramble_quirk; 903 dwc->u2exit_lfps_quirk = pdata->u2exit_lfps_quirk; 904 dwc->u2ss_inp3_quirk = pdata->u2ss_inp3_quirk; 905 dwc->req_p1p2p3_quirk = pdata->req_p1p2p3_quirk; 906 dwc->del_p1p2p3_quirk = pdata->del_p1p2p3_quirk; 907 dwc->del_phy_power_chg_quirk = pdata->del_phy_power_chg_quirk; 908 dwc->lfps_filter_quirk = pdata->lfps_filter_quirk; 909 dwc->rx_detect_poll_quirk = pdata->rx_detect_poll_quirk; 910 dwc->dis_u3_susphy_quirk = pdata->dis_u3_susphy_quirk; 911 dwc->dis_u2_susphy_quirk = pdata->dis_u2_susphy_quirk; 912 913 dwc->tx_de_emphasis_quirk = pdata->tx_de_emphasis_quirk; 914 if (pdata->tx_de_emphasis) 915 tx_de_emphasis = pdata->tx_de_emphasis; 916 917 dwc->hsphy_interface = pdata->hsphy_interface; 918 } 919 920 /* default to superspeed if no maximum_speed passed */ 921 if (dwc->maximum_speed == USB_SPEED_UNKNOWN) 922 dwc->maximum_speed = USB_SPEED_SUPER; 923 924 dwc->lpm_nyet_threshold = lpm_nyet_threshold; 925 dwc->tx_de_emphasis = tx_de_emphasis; 926 927 dwc->hird_threshold = hird_threshold 928 | (dwc->is_utmi_l1_suspend << 4); 929 930 platform_set_drvdata(pdev, dwc); 931 dwc3_cache_hwparams(dwc); 932 933 ret = dwc3_phy_setup(dwc); 934 if (ret) 935 goto err0; 936 937 ret = dwc3_core_get_phy(dwc); 938 if (ret) 939 goto err0; 940 941 spin_lock_init(&dwc->lock); 942 943 if (!dev->dma_mask) { 944 dev->dma_mask = dev->parent->dma_mask; 945 dev->dma_parms = dev->parent->dma_parms; 946 dma_set_coherent_mask(dev, dev->parent->coherent_dma_mask); 947 } 948 949 pm_runtime_enable(dev); 950 pm_runtime_get_sync(dev); 951 pm_runtime_forbid(dev); 952 953 ret = dwc3_alloc_event_buffers(dwc, DWC3_EVENT_BUFFERS_SIZE); 954 if (ret) { 955 dev_err(dwc->dev, "failed to allocate event buffers\n"); 956 ret = -ENOMEM; 957 goto err1; 958 } 959 960 if (IS_ENABLED(CONFIG_USB_DWC3_HOST)) 961 dwc->dr_mode = USB_DR_MODE_HOST; 962 else if (IS_ENABLED(CONFIG_USB_DWC3_GADGET)) 963 dwc->dr_mode = USB_DR_MODE_PERIPHERAL; 964 965 if (dwc->dr_mode == USB_DR_MODE_UNKNOWN) 966 dwc->dr_mode = USB_DR_MODE_OTG; 967 968 ret = dwc3_core_init(dwc); 969 if (ret) { 970 dev_err(dev, "failed to initialize core\n"); 971 goto err1; 972 } 973 974 usb_phy_set_suspend(dwc->usb2_phy, 0); 975 usb_phy_set_suspend(dwc->usb3_phy, 0); 976 ret = phy_power_on(dwc->usb2_generic_phy); 977 if (ret < 0) 978 goto err2; 979 980 ret = phy_power_on(dwc->usb3_generic_phy); 981 if (ret < 0) 982 goto err3; 983 984 ret = dwc3_event_buffers_setup(dwc); 985 if (ret) { 986 dev_err(dwc->dev, "failed to setup event buffers\n"); 987 goto err4; 988 } 989 990 ret = dwc3_core_init_mode(dwc); 991 if (ret) 992 goto err5; 993 994 ret = dwc3_debugfs_init(dwc); 995 if (ret) { 996 dev_err(dev, "failed to initialize debugfs\n"); 997 goto err6; 998 } 999 1000 pm_runtime_allow(dev); 1001 1002 return 0; 1003 1004 err6: 1005 dwc3_core_exit_mode(dwc); 1006 1007 err5: 1008 dwc3_event_buffers_cleanup(dwc); 1009 1010 err4: 1011 phy_power_off(dwc->usb3_generic_phy); 1012 1013 err3: 1014 phy_power_off(dwc->usb2_generic_phy); 1015 1016 err2: 1017 usb_phy_set_suspend(dwc->usb2_phy, 1); 1018 usb_phy_set_suspend(dwc->usb3_phy, 1); 1019 dwc3_core_exit(dwc); 1020 1021 err1: 1022 dwc3_free_event_buffers(dwc); 1023 dwc3_ulpi_exit(dwc); 1024 1025 err0: 1026 /* 1027 * restore res->start back to its original value so that, in case the 1028 * probe is deferred, we don't end up getting error in request the 1029 * memory region the next time probe is called. 1030 */ 1031 res->start -= DWC3_GLOBALS_REGS_START; 1032 1033 return ret; 1034 } 1035 1036 static int dwc3_remove(struct platform_device *pdev) 1037 { 1038 struct dwc3 *dwc = platform_get_drvdata(pdev); 1039 struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1040 1041 /* 1042 * restore res->start back to its original value so that, in case the 1043 * probe is deferred, we don't end up getting error in request the 1044 * memory region the next time probe is called. 1045 */ 1046 res->start -= DWC3_GLOBALS_REGS_START; 1047 1048 dwc3_debugfs_exit(dwc); 1049 dwc3_core_exit_mode(dwc); 1050 dwc3_event_buffers_cleanup(dwc); 1051 dwc3_free_event_buffers(dwc); 1052 1053 usb_phy_set_suspend(dwc->usb2_phy, 1); 1054 usb_phy_set_suspend(dwc->usb3_phy, 1); 1055 phy_power_off(dwc->usb2_generic_phy); 1056 phy_power_off(dwc->usb3_generic_phy); 1057 1058 dwc3_core_exit(dwc); 1059 dwc3_ulpi_exit(dwc); 1060 1061 pm_runtime_put_sync(&pdev->dev); 1062 pm_runtime_disable(&pdev->dev); 1063 1064 return 0; 1065 } 1066 1067 #ifdef CONFIG_PM_SLEEP 1068 static int dwc3_suspend(struct device *dev) 1069 { 1070 struct dwc3 *dwc = dev_get_drvdata(dev); 1071 unsigned long flags; 1072 1073 spin_lock_irqsave(&dwc->lock, flags); 1074 1075 switch (dwc->dr_mode) { 1076 case USB_DR_MODE_PERIPHERAL: 1077 case USB_DR_MODE_OTG: 1078 dwc3_gadget_suspend(dwc); 1079 /* FALLTHROUGH */ 1080 case USB_DR_MODE_HOST: 1081 default: 1082 dwc3_event_buffers_cleanup(dwc); 1083 break; 1084 } 1085 1086 dwc->gctl = dwc3_readl(dwc->regs, DWC3_GCTL); 1087 spin_unlock_irqrestore(&dwc->lock, flags); 1088 1089 usb_phy_shutdown(dwc->usb3_phy); 1090 usb_phy_shutdown(dwc->usb2_phy); 1091 phy_exit(dwc->usb2_generic_phy); 1092 phy_exit(dwc->usb3_generic_phy); 1093 1094 return 0; 1095 } 1096 1097 static int dwc3_resume(struct device *dev) 1098 { 1099 struct dwc3 *dwc = dev_get_drvdata(dev); 1100 unsigned long flags; 1101 int ret; 1102 1103 usb_phy_init(dwc->usb3_phy); 1104 usb_phy_init(dwc->usb2_phy); 1105 ret = phy_init(dwc->usb2_generic_phy); 1106 if (ret < 0) 1107 return ret; 1108 1109 ret = phy_init(dwc->usb3_generic_phy); 1110 if (ret < 0) 1111 goto err_usb2phy_init; 1112 1113 spin_lock_irqsave(&dwc->lock, flags); 1114 1115 dwc3_event_buffers_setup(dwc); 1116 dwc3_writel(dwc->regs, DWC3_GCTL, dwc->gctl); 1117 1118 switch (dwc->dr_mode) { 1119 case USB_DR_MODE_PERIPHERAL: 1120 case USB_DR_MODE_OTG: 1121 dwc3_gadget_resume(dwc); 1122 /* FALLTHROUGH */ 1123 case USB_DR_MODE_HOST: 1124 default: 1125 /* do nothing */ 1126 break; 1127 } 1128 1129 spin_unlock_irqrestore(&dwc->lock, flags); 1130 1131 pm_runtime_disable(dev); 1132 pm_runtime_set_active(dev); 1133 pm_runtime_enable(dev); 1134 1135 return 0; 1136 1137 err_usb2phy_init: 1138 phy_exit(dwc->usb2_generic_phy); 1139 1140 return ret; 1141 } 1142 1143 static const struct dev_pm_ops dwc3_dev_pm_ops = { 1144 SET_SYSTEM_SLEEP_PM_OPS(dwc3_suspend, dwc3_resume) 1145 }; 1146 1147 #define DWC3_PM_OPS &(dwc3_dev_pm_ops) 1148 #else 1149 #define DWC3_PM_OPS NULL 1150 #endif 1151 1152 #ifdef CONFIG_OF 1153 static const struct of_device_id of_dwc3_match[] = { 1154 { 1155 .compatible = "snps,dwc3" 1156 }, 1157 { 1158 .compatible = "synopsys,dwc3" 1159 }, 1160 { }, 1161 }; 1162 MODULE_DEVICE_TABLE(of, of_dwc3_match); 1163 #endif 1164 1165 #ifdef CONFIG_ACPI 1166 1167 #define ACPI_ID_INTEL_BSW "808622B7" 1168 1169 static const struct acpi_device_id dwc3_acpi_match[] = { 1170 { ACPI_ID_INTEL_BSW, 0 }, 1171 { }, 1172 }; 1173 MODULE_DEVICE_TABLE(acpi, dwc3_acpi_match); 1174 #endif 1175 1176 static struct platform_driver dwc3_driver = { 1177 .probe = dwc3_probe, 1178 .remove = dwc3_remove, 1179 .driver = { 1180 .name = "dwc3", 1181 .of_match_table = of_match_ptr(of_dwc3_match), 1182 .acpi_match_table = ACPI_PTR(dwc3_acpi_match), 1183 .pm = DWC3_PM_OPS, 1184 }, 1185 }; 1186 1187 module_platform_driver(dwc3_driver); 1188 1189 MODULE_ALIAS("platform:dwc3"); 1190 MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>"); 1191 MODULE_LICENSE("GPL v2"); 1192 MODULE_DESCRIPTION("DesignWare USB3 DRD Controller Driver"); 1193