1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * core.c - DesignWare USB3 DRD Controller Core file 4 * 5 * Copyright (C) 2010-2011 Texas Instruments Incorporated - https://www.ti.com 6 * 7 * Authors: Felipe Balbi <balbi@ti.com>, 8 * Sebastian Andrzej Siewior <bigeasy@linutronix.de> 9 */ 10 11 #include <linux/clk.h> 12 #include <linux/version.h> 13 #include <linux/module.h> 14 #include <linux/kernel.h> 15 #include <linux/slab.h> 16 #include <linux/spinlock.h> 17 #include <linux/platform_device.h> 18 #include <linux/pm_runtime.h> 19 #include <linux/interrupt.h> 20 #include <linux/ioport.h> 21 #include <linux/io.h> 22 #include <linux/list.h> 23 #include <linux/delay.h> 24 #include <linux/dma-mapping.h> 25 #include <linux/of.h> 26 #include <linux/of_graph.h> 27 #include <linux/acpi.h> 28 #include <linux/pinctrl/consumer.h> 29 #include <linux/reset.h> 30 #include <linux/bitfield.h> 31 32 #include <linux/usb/ch9.h> 33 #include <linux/usb/gadget.h> 34 #include <linux/usb/of.h> 35 #include <linux/usb/otg.h> 36 37 #include "core.h" 38 #include "gadget.h" 39 #include "io.h" 40 41 #include "debug.h" 42 43 #define DWC3_DEFAULT_AUTOSUSPEND_DELAY 5000 /* ms */ 44 45 /** 46 * dwc3_get_dr_mode - Validates and sets dr_mode 47 * @dwc: pointer to our context structure 48 */ 49 static int dwc3_get_dr_mode(struct dwc3 *dwc) 50 { 51 enum usb_dr_mode mode; 52 struct device *dev = dwc->dev; 53 unsigned int hw_mode; 54 55 if (dwc->dr_mode == USB_DR_MODE_UNKNOWN) 56 dwc->dr_mode = USB_DR_MODE_OTG; 57 58 mode = dwc->dr_mode; 59 hw_mode = DWC3_GHWPARAMS0_MODE(dwc->hwparams.hwparams0); 60 61 switch (hw_mode) { 62 case DWC3_GHWPARAMS0_MODE_GADGET: 63 if (IS_ENABLED(CONFIG_USB_DWC3_HOST)) { 64 dev_err(dev, 65 "Controller does not support host mode.\n"); 66 return -EINVAL; 67 } 68 mode = USB_DR_MODE_PERIPHERAL; 69 break; 70 case DWC3_GHWPARAMS0_MODE_HOST: 71 if (IS_ENABLED(CONFIG_USB_DWC3_GADGET)) { 72 dev_err(dev, 73 "Controller does not support device mode.\n"); 74 return -EINVAL; 75 } 76 mode = USB_DR_MODE_HOST; 77 break; 78 default: 79 if (IS_ENABLED(CONFIG_USB_DWC3_HOST)) 80 mode = USB_DR_MODE_HOST; 81 else if (IS_ENABLED(CONFIG_USB_DWC3_GADGET)) 82 mode = USB_DR_MODE_PERIPHERAL; 83 84 /* 85 * DWC_usb31 and DWC_usb3 v3.30a and higher do not support OTG 86 * mode. If the controller supports DRD but the dr_mode is not 87 * specified or set to OTG, then set the mode to peripheral. 88 */ 89 if (mode == USB_DR_MODE_OTG && !dwc->edev && 90 (!IS_ENABLED(CONFIG_USB_ROLE_SWITCH) || 91 !device_property_read_bool(dwc->dev, "usb-role-switch")) && 92 !DWC3_VER_IS_PRIOR(DWC3, 330A)) 93 mode = USB_DR_MODE_PERIPHERAL; 94 } 95 96 if (mode != dwc->dr_mode) { 97 dev_warn(dev, 98 "Configuration mismatch. dr_mode forced to %s\n", 99 mode == USB_DR_MODE_HOST ? "host" : "gadget"); 100 101 dwc->dr_mode = mode; 102 } 103 104 return 0; 105 } 106 107 void dwc3_enable_susphy(struct dwc3 *dwc, bool enable) 108 { 109 u32 reg; 110 111 reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0)); 112 if (enable && !dwc->dis_u3_susphy_quirk) 113 reg |= DWC3_GUSB3PIPECTL_SUSPHY; 114 else 115 reg &= ~DWC3_GUSB3PIPECTL_SUSPHY; 116 117 dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg); 118 119 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0)); 120 if (enable && !dwc->dis_u2_susphy_quirk) 121 reg |= DWC3_GUSB2PHYCFG_SUSPHY; 122 else 123 reg &= ~DWC3_GUSB2PHYCFG_SUSPHY; 124 125 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg); 126 } 127 128 void dwc3_set_prtcap(struct dwc3 *dwc, u32 mode) 129 { 130 u32 reg; 131 132 reg = dwc3_readl(dwc->regs, DWC3_GCTL); 133 reg &= ~(DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_OTG)); 134 reg |= DWC3_GCTL_PRTCAPDIR(mode); 135 dwc3_writel(dwc->regs, DWC3_GCTL, reg); 136 137 dwc->current_dr_role = mode; 138 } 139 140 static void __dwc3_set_mode(struct work_struct *work) 141 { 142 struct dwc3 *dwc = work_to_dwc(work); 143 unsigned long flags; 144 int ret; 145 u32 reg; 146 u32 desired_dr_role; 147 148 mutex_lock(&dwc->mutex); 149 spin_lock_irqsave(&dwc->lock, flags); 150 desired_dr_role = dwc->desired_dr_role; 151 spin_unlock_irqrestore(&dwc->lock, flags); 152 153 pm_runtime_get_sync(dwc->dev); 154 155 if (dwc->current_dr_role == DWC3_GCTL_PRTCAP_OTG) 156 dwc3_otg_update(dwc, 0); 157 158 if (!desired_dr_role) 159 goto out; 160 161 if (desired_dr_role == dwc->current_dr_role) 162 goto out; 163 164 if (desired_dr_role == DWC3_GCTL_PRTCAP_OTG && dwc->edev) 165 goto out; 166 167 switch (dwc->current_dr_role) { 168 case DWC3_GCTL_PRTCAP_HOST: 169 dwc3_host_exit(dwc); 170 break; 171 case DWC3_GCTL_PRTCAP_DEVICE: 172 dwc3_gadget_exit(dwc); 173 dwc3_event_buffers_cleanup(dwc); 174 break; 175 case DWC3_GCTL_PRTCAP_OTG: 176 dwc3_otg_exit(dwc); 177 spin_lock_irqsave(&dwc->lock, flags); 178 dwc->desired_otg_role = DWC3_OTG_ROLE_IDLE; 179 spin_unlock_irqrestore(&dwc->lock, flags); 180 dwc3_otg_update(dwc, 1); 181 break; 182 default: 183 break; 184 } 185 186 /* 187 * When current_dr_role is not set, there's no role switching. 188 * Only perform GCTL.CoreSoftReset when there's DRD role switching. 189 */ 190 if (dwc->current_dr_role && ((DWC3_IP_IS(DWC3) || 191 DWC3_VER_IS_PRIOR(DWC31, 190A)) && 192 desired_dr_role != DWC3_GCTL_PRTCAP_OTG)) { 193 reg = dwc3_readl(dwc->regs, DWC3_GCTL); 194 reg |= DWC3_GCTL_CORESOFTRESET; 195 dwc3_writel(dwc->regs, DWC3_GCTL, reg); 196 197 /* 198 * Wait for internal clocks to synchronized. DWC_usb31 and 199 * DWC_usb32 may need at least 50ms (less for DWC_usb3). To 200 * keep it consistent across different IPs, let's wait up to 201 * 100ms before clearing GCTL.CORESOFTRESET. 202 */ 203 msleep(100); 204 205 reg = dwc3_readl(dwc->regs, DWC3_GCTL); 206 reg &= ~DWC3_GCTL_CORESOFTRESET; 207 dwc3_writel(dwc->regs, DWC3_GCTL, reg); 208 } 209 210 spin_lock_irqsave(&dwc->lock, flags); 211 212 dwc3_set_prtcap(dwc, desired_dr_role); 213 214 spin_unlock_irqrestore(&dwc->lock, flags); 215 216 switch (desired_dr_role) { 217 case DWC3_GCTL_PRTCAP_HOST: 218 ret = dwc3_host_init(dwc); 219 if (ret) { 220 dev_err(dwc->dev, "failed to initialize host\n"); 221 } else { 222 if (dwc->usb2_phy) 223 otg_set_vbus(dwc->usb2_phy->otg, true); 224 phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_HOST); 225 phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_HOST); 226 if (dwc->dis_split_quirk) { 227 reg = dwc3_readl(dwc->regs, DWC3_GUCTL3); 228 reg |= DWC3_GUCTL3_SPLITDISABLE; 229 dwc3_writel(dwc->regs, DWC3_GUCTL3, reg); 230 } 231 } 232 break; 233 case DWC3_GCTL_PRTCAP_DEVICE: 234 dwc3_core_soft_reset(dwc); 235 236 dwc3_event_buffers_setup(dwc); 237 238 if (dwc->usb2_phy) 239 otg_set_vbus(dwc->usb2_phy->otg, false); 240 phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_DEVICE); 241 phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_DEVICE); 242 243 ret = dwc3_gadget_init(dwc); 244 if (ret) 245 dev_err(dwc->dev, "failed to initialize peripheral\n"); 246 break; 247 case DWC3_GCTL_PRTCAP_OTG: 248 dwc3_otg_init(dwc); 249 dwc3_otg_update(dwc, 0); 250 break; 251 default: 252 break; 253 } 254 255 out: 256 pm_runtime_mark_last_busy(dwc->dev); 257 pm_runtime_put_autosuspend(dwc->dev); 258 mutex_unlock(&dwc->mutex); 259 } 260 261 void dwc3_set_mode(struct dwc3 *dwc, u32 mode) 262 { 263 unsigned long flags; 264 265 if (dwc->dr_mode != USB_DR_MODE_OTG) 266 return; 267 268 spin_lock_irqsave(&dwc->lock, flags); 269 dwc->desired_dr_role = mode; 270 spin_unlock_irqrestore(&dwc->lock, flags); 271 272 queue_work(system_freezable_wq, &dwc->drd_work); 273 } 274 275 u32 dwc3_core_fifo_space(struct dwc3_ep *dep, u8 type) 276 { 277 struct dwc3 *dwc = dep->dwc; 278 u32 reg; 279 280 dwc3_writel(dwc->regs, DWC3_GDBGFIFOSPACE, 281 DWC3_GDBGFIFOSPACE_NUM(dep->number) | 282 DWC3_GDBGFIFOSPACE_TYPE(type)); 283 284 reg = dwc3_readl(dwc->regs, DWC3_GDBGFIFOSPACE); 285 286 return DWC3_GDBGFIFOSPACE_SPACE_AVAILABLE(reg); 287 } 288 289 /** 290 * dwc3_core_soft_reset - Issues core soft reset and PHY reset 291 * @dwc: pointer to our context structure 292 */ 293 int dwc3_core_soft_reset(struct dwc3 *dwc) 294 { 295 u32 reg; 296 int retries = 1000; 297 298 /* 299 * We're resetting only the device side because, if we're in host mode, 300 * XHCI driver will reset the host block. If dwc3 was configured for 301 * host-only mode, then we can return early. 302 */ 303 if (dwc->current_dr_role == DWC3_GCTL_PRTCAP_HOST) 304 return 0; 305 306 reg = dwc3_readl(dwc->regs, DWC3_DCTL); 307 reg |= DWC3_DCTL_CSFTRST; 308 reg &= ~DWC3_DCTL_RUN_STOP; 309 dwc3_gadget_dctl_write_safe(dwc, reg); 310 311 /* 312 * For DWC_usb31 controller 1.90a and later, the DCTL.CSFRST bit 313 * is cleared only after all the clocks are synchronized. This can 314 * take a little more than 50ms. Set the polling rate at 20ms 315 * for 10 times instead. 316 */ 317 if (DWC3_VER_IS_WITHIN(DWC31, 190A, ANY) || DWC3_IP_IS(DWC32)) 318 retries = 10; 319 320 do { 321 reg = dwc3_readl(dwc->regs, DWC3_DCTL); 322 if (!(reg & DWC3_DCTL_CSFTRST)) 323 goto done; 324 325 if (DWC3_VER_IS_WITHIN(DWC31, 190A, ANY) || DWC3_IP_IS(DWC32)) 326 msleep(20); 327 else 328 udelay(1); 329 } while (--retries); 330 331 dev_warn(dwc->dev, "DWC3 controller soft reset failed.\n"); 332 return -ETIMEDOUT; 333 334 done: 335 /* 336 * For DWC_usb31 controller 1.80a and prior, once DCTL.CSFRST bit 337 * is cleared, we must wait at least 50ms before accessing the PHY 338 * domain (synchronization delay). 339 */ 340 if (DWC3_VER_IS_WITHIN(DWC31, ANY, 180A)) 341 msleep(50); 342 343 return 0; 344 } 345 346 /* 347 * dwc3_frame_length_adjustment - Adjusts frame length if required 348 * @dwc3: Pointer to our controller context structure 349 */ 350 static void dwc3_frame_length_adjustment(struct dwc3 *dwc) 351 { 352 u32 reg; 353 u32 dft; 354 355 if (DWC3_VER_IS_PRIOR(DWC3, 250A)) 356 return; 357 358 if (dwc->fladj == 0) 359 return; 360 361 reg = dwc3_readl(dwc->regs, DWC3_GFLADJ); 362 dft = reg & DWC3_GFLADJ_30MHZ_MASK; 363 if (dft != dwc->fladj) { 364 reg &= ~DWC3_GFLADJ_30MHZ_MASK; 365 reg |= DWC3_GFLADJ_30MHZ_SDBND_SEL | dwc->fladj; 366 dwc3_writel(dwc->regs, DWC3_GFLADJ, reg); 367 } 368 } 369 370 /** 371 * dwc3_ref_clk_period - Reference clock period configuration 372 * Default reference clock period depends on hardware 373 * configuration. For systems with reference clock that differs 374 * from the default, this will set clock period in DWC3_GUCTL 375 * register. 376 * @dwc: Pointer to our controller context structure 377 */ 378 static void dwc3_ref_clk_period(struct dwc3 *dwc) 379 { 380 unsigned long period; 381 unsigned long fladj; 382 unsigned long decr; 383 unsigned long rate; 384 u32 reg; 385 386 if (dwc->ref_clk) { 387 rate = clk_get_rate(dwc->ref_clk); 388 if (!rate) 389 return; 390 period = NSEC_PER_SEC / rate; 391 } else if (dwc->ref_clk_per) { 392 period = dwc->ref_clk_per; 393 rate = NSEC_PER_SEC / period; 394 } else { 395 return; 396 } 397 398 reg = dwc3_readl(dwc->regs, DWC3_GUCTL); 399 reg &= ~DWC3_GUCTL_REFCLKPER_MASK; 400 reg |= FIELD_PREP(DWC3_GUCTL_REFCLKPER_MASK, period); 401 dwc3_writel(dwc->regs, DWC3_GUCTL, reg); 402 403 if (DWC3_VER_IS_PRIOR(DWC3, 250A)) 404 return; 405 406 /* 407 * The calculation below is 408 * 409 * 125000 * (NSEC_PER_SEC / (rate * period) - 1) 410 * 411 * but rearranged for fixed-point arithmetic. The division must be 412 * 64-bit because 125000 * NSEC_PER_SEC doesn't fit in 32 bits (and 413 * neither does rate * period). 414 * 415 * Note that rate * period ~= NSEC_PER_SECOND, minus the number of 416 * nanoseconds of error caused by the truncation which happened during 417 * the division when calculating rate or period (whichever one was 418 * derived from the other). We first calculate the relative error, then 419 * scale it to units of 8 ppm. 420 */ 421 fladj = div64_u64(125000ULL * NSEC_PER_SEC, (u64)rate * period); 422 fladj -= 125000; 423 424 /* 425 * The documented 240MHz constant is scaled by 2 to get PLS1 as well. 426 */ 427 decr = 480000000 / rate; 428 429 reg = dwc3_readl(dwc->regs, DWC3_GFLADJ); 430 reg &= ~DWC3_GFLADJ_REFCLK_FLADJ_MASK 431 & ~DWC3_GFLADJ_240MHZDECR 432 & ~DWC3_GFLADJ_240MHZDECR_PLS1; 433 reg |= FIELD_PREP(DWC3_GFLADJ_REFCLK_FLADJ_MASK, fladj) 434 | FIELD_PREP(DWC3_GFLADJ_240MHZDECR, decr >> 1) 435 | FIELD_PREP(DWC3_GFLADJ_240MHZDECR_PLS1, decr & 1); 436 437 if (dwc->gfladj_refclk_lpm_sel) 438 reg |= DWC3_GFLADJ_REFCLK_LPM_SEL; 439 440 dwc3_writel(dwc->regs, DWC3_GFLADJ, reg); 441 } 442 443 /** 444 * dwc3_free_one_event_buffer - Frees one event buffer 445 * @dwc: Pointer to our controller context structure 446 * @evt: Pointer to event buffer to be freed 447 */ 448 static void dwc3_free_one_event_buffer(struct dwc3 *dwc, 449 struct dwc3_event_buffer *evt) 450 { 451 dma_free_coherent(dwc->sysdev, evt->length, evt->buf, evt->dma); 452 } 453 454 /** 455 * dwc3_alloc_one_event_buffer - Allocates one event buffer structure 456 * @dwc: Pointer to our controller context structure 457 * @length: size of the event buffer 458 * 459 * Returns a pointer to the allocated event buffer structure on success 460 * otherwise ERR_PTR(errno). 461 */ 462 static struct dwc3_event_buffer *dwc3_alloc_one_event_buffer(struct dwc3 *dwc, 463 unsigned int length) 464 { 465 struct dwc3_event_buffer *evt; 466 467 evt = devm_kzalloc(dwc->dev, sizeof(*evt), GFP_KERNEL); 468 if (!evt) 469 return ERR_PTR(-ENOMEM); 470 471 evt->dwc = dwc; 472 evt->length = length; 473 evt->cache = devm_kzalloc(dwc->dev, length, GFP_KERNEL); 474 if (!evt->cache) 475 return ERR_PTR(-ENOMEM); 476 477 evt->buf = dma_alloc_coherent(dwc->sysdev, length, 478 &evt->dma, GFP_KERNEL); 479 if (!evt->buf) 480 return ERR_PTR(-ENOMEM); 481 482 return evt; 483 } 484 485 /** 486 * dwc3_free_event_buffers - frees all allocated event buffers 487 * @dwc: Pointer to our controller context structure 488 */ 489 static void dwc3_free_event_buffers(struct dwc3 *dwc) 490 { 491 struct dwc3_event_buffer *evt; 492 493 evt = dwc->ev_buf; 494 if (evt) 495 dwc3_free_one_event_buffer(dwc, evt); 496 } 497 498 /** 499 * dwc3_alloc_event_buffers - Allocates @num event buffers of size @length 500 * @dwc: pointer to our controller context structure 501 * @length: size of event buffer 502 * 503 * Returns 0 on success otherwise negative errno. In the error case, dwc 504 * may contain some buffers allocated but not all which were requested. 505 */ 506 static int dwc3_alloc_event_buffers(struct dwc3 *dwc, unsigned int length) 507 { 508 struct dwc3_event_buffer *evt; 509 unsigned int hw_mode; 510 511 hw_mode = DWC3_GHWPARAMS0_MODE(dwc->hwparams.hwparams0); 512 if (hw_mode == DWC3_GHWPARAMS0_MODE_HOST) { 513 dwc->ev_buf = NULL; 514 return 0; 515 } 516 517 evt = dwc3_alloc_one_event_buffer(dwc, length); 518 if (IS_ERR(evt)) { 519 dev_err(dwc->dev, "can't allocate event buffer\n"); 520 return PTR_ERR(evt); 521 } 522 dwc->ev_buf = evt; 523 524 return 0; 525 } 526 527 /** 528 * dwc3_event_buffers_setup - setup our allocated event buffers 529 * @dwc: pointer to our controller context structure 530 * 531 * Returns 0 on success otherwise negative errno. 532 */ 533 int dwc3_event_buffers_setup(struct dwc3 *dwc) 534 { 535 struct dwc3_event_buffer *evt; 536 537 if (!dwc->ev_buf) 538 return 0; 539 540 evt = dwc->ev_buf; 541 evt->lpos = 0; 542 dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(0), 543 lower_32_bits(evt->dma)); 544 dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(0), 545 upper_32_bits(evt->dma)); 546 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0), 547 DWC3_GEVNTSIZ_SIZE(evt->length)); 548 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), 0); 549 550 return 0; 551 } 552 553 void dwc3_event_buffers_cleanup(struct dwc3 *dwc) 554 { 555 struct dwc3_event_buffer *evt; 556 u32 reg; 557 558 if (!dwc->ev_buf) 559 return; 560 /* 561 * Exynos platforms may not be able to access event buffer if the 562 * controller failed to halt on dwc3_core_exit(). 563 */ 564 reg = dwc3_readl(dwc->regs, DWC3_DSTS); 565 if (!(reg & DWC3_DSTS_DEVCTRLHLT)) 566 return; 567 568 evt = dwc->ev_buf; 569 570 evt->lpos = 0; 571 572 dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(0), 0); 573 dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(0), 0); 574 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0), DWC3_GEVNTSIZ_INTMASK 575 | DWC3_GEVNTSIZ_SIZE(0)); 576 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), 0); 577 } 578 579 static void dwc3_core_num_eps(struct dwc3 *dwc) 580 { 581 struct dwc3_hwparams *parms = &dwc->hwparams; 582 583 dwc->num_eps = DWC3_NUM_EPS(parms); 584 } 585 586 static void dwc3_cache_hwparams(struct dwc3 *dwc) 587 { 588 struct dwc3_hwparams *parms = &dwc->hwparams; 589 590 parms->hwparams0 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS0); 591 parms->hwparams1 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS1); 592 parms->hwparams2 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS2); 593 parms->hwparams3 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS3); 594 parms->hwparams4 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS4); 595 parms->hwparams5 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS5); 596 parms->hwparams6 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS6); 597 parms->hwparams7 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS7); 598 parms->hwparams8 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS8); 599 600 if (DWC3_IP_IS(DWC32)) 601 parms->hwparams9 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS9); 602 } 603 604 static int dwc3_core_ulpi_init(struct dwc3 *dwc) 605 { 606 int intf; 607 int ret = 0; 608 609 intf = DWC3_GHWPARAMS3_HSPHY_IFC(dwc->hwparams.hwparams3); 610 611 if (intf == DWC3_GHWPARAMS3_HSPHY_IFC_ULPI || 612 (intf == DWC3_GHWPARAMS3_HSPHY_IFC_UTMI_ULPI && 613 dwc->hsphy_interface && 614 !strncmp(dwc->hsphy_interface, "ulpi", 4))) 615 ret = dwc3_ulpi_init(dwc); 616 617 return ret; 618 } 619 620 /** 621 * dwc3_phy_setup - Configure USB PHY Interface of DWC3 Core 622 * @dwc: Pointer to our controller context structure 623 * 624 * Returns 0 on success. The USB PHY interfaces are configured but not 625 * initialized. The PHY interfaces and the PHYs get initialized together with 626 * the core in dwc3_core_init. 627 */ 628 static int dwc3_phy_setup(struct dwc3 *dwc) 629 { 630 u32 reg; 631 632 reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0)); 633 634 /* 635 * Make sure UX_EXIT_PX is cleared as that causes issues with some 636 * PHYs. Also, this bit is not supposed to be used in normal operation. 637 */ 638 reg &= ~DWC3_GUSB3PIPECTL_UX_EXIT_PX; 639 640 /* 641 * Above DWC_usb3.0 1.94a, it is recommended to set 642 * DWC3_GUSB3PIPECTL_SUSPHY to '0' during coreConsultant configuration. 643 * So default value will be '0' when the core is reset. Application 644 * needs to set it to '1' after the core initialization is completed. 645 * 646 * Similarly for DRD controllers, GUSB3PIPECTL.SUSPENDENABLE must be 647 * cleared after power-on reset, and it can be set after core 648 * initialization. 649 */ 650 reg &= ~DWC3_GUSB3PIPECTL_SUSPHY; 651 652 if (dwc->u2ss_inp3_quirk) 653 reg |= DWC3_GUSB3PIPECTL_U2SSINP3OK; 654 655 if (dwc->dis_rxdet_inp3_quirk) 656 reg |= DWC3_GUSB3PIPECTL_DISRXDETINP3; 657 658 if (dwc->req_p1p2p3_quirk) 659 reg |= DWC3_GUSB3PIPECTL_REQP1P2P3; 660 661 if (dwc->del_p1p2p3_quirk) 662 reg |= DWC3_GUSB3PIPECTL_DEP1P2P3_EN; 663 664 if (dwc->del_phy_power_chg_quirk) 665 reg |= DWC3_GUSB3PIPECTL_DEPOCHANGE; 666 667 if (dwc->lfps_filter_quirk) 668 reg |= DWC3_GUSB3PIPECTL_LFPSFILT; 669 670 if (dwc->rx_detect_poll_quirk) 671 reg |= DWC3_GUSB3PIPECTL_RX_DETOPOLL; 672 673 if (dwc->tx_de_emphasis_quirk) 674 reg |= DWC3_GUSB3PIPECTL_TX_DEEPH(dwc->tx_de_emphasis); 675 676 if (dwc->dis_del_phy_power_chg_quirk) 677 reg &= ~DWC3_GUSB3PIPECTL_DEPOCHANGE; 678 679 dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg); 680 681 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0)); 682 683 /* Select the HS PHY interface */ 684 switch (DWC3_GHWPARAMS3_HSPHY_IFC(dwc->hwparams.hwparams3)) { 685 case DWC3_GHWPARAMS3_HSPHY_IFC_UTMI_ULPI: 686 if (dwc->hsphy_interface && 687 !strncmp(dwc->hsphy_interface, "utmi", 4)) { 688 reg &= ~DWC3_GUSB2PHYCFG_ULPI_UTMI; 689 break; 690 } else if (dwc->hsphy_interface && 691 !strncmp(dwc->hsphy_interface, "ulpi", 4)) { 692 reg |= DWC3_GUSB2PHYCFG_ULPI_UTMI; 693 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg); 694 } else { 695 /* Relying on default value. */ 696 if (!(reg & DWC3_GUSB2PHYCFG_ULPI_UTMI)) 697 break; 698 } 699 fallthrough; 700 case DWC3_GHWPARAMS3_HSPHY_IFC_ULPI: 701 default: 702 break; 703 } 704 705 switch (dwc->hsphy_mode) { 706 case USBPHY_INTERFACE_MODE_UTMI: 707 reg &= ~(DWC3_GUSB2PHYCFG_PHYIF_MASK | 708 DWC3_GUSB2PHYCFG_USBTRDTIM_MASK); 709 reg |= DWC3_GUSB2PHYCFG_PHYIF(UTMI_PHYIF_8_BIT) | 710 DWC3_GUSB2PHYCFG_USBTRDTIM(USBTRDTIM_UTMI_8_BIT); 711 break; 712 case USBPHY_INTERFACE_MODE_UTMIW: 713 reg &= ~(DWC3_GUSB2PHYCFG_PHYIF_MASK | 714 DWC3_GUSB2PHYCFG_USBTRDTIM_MASK); 715 reg |= DWC3_GUSB2PHYCFG_PHYIF(UTMI_PHYIF_16_BIT) | 716 DWC3_GUSB2PHYCFG_USBTRDTIM(USBTRDTIM_UTMI_16_BIT); 717 break; 718 default: 719 break; 720 } 721 722 /* 723 * Above DWC_usb3.0 1.94a, it is recommended to set 724 * DWC3_GUSB2PHYCFG_SUSPHY to '0' during coreConsultant configuration. 725 * So default value will be '0' when the core is reset. Application 726 * needs to set it to '1' after the core initialization is completed. 727 * 728 * Similarly for DRD controllers, GUSB2PHYCFG.SUSPHY must be cleared 729 * after power-on reset, and it can be set after core initialization. 730 */ 731 reg &= ~DWC3_GUSB2PHYCFG_SUSPHY; 732 733 if (dwc->dis_enblslpm_quirk) 734 reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM; 735 else 736 reg |= DWC3_GUSB2PHYCFG_ENBLSLPM; 737 738 if (dwc->dis_u2_freeclk_exists_quirk || dwc->gfladj_refclk_lpm_sel) 739 reg &= ~DWC3_GUSB2PHYCFG_U2_FREECLK_EXISTS; 740 741 /* 742 * Some ULPI USB PHY does not support internal VBUS supply, to drive 743 * the CPEN pin requires the configuration of the ULPI DRVVBUSEXTERNAL 744 * bit of OTG_CTRL register. Controller configures the USB2 PHY 745 * ULPIEXTVBUSDRV bit[17] of the GUSB2PHYCFG register to drive vBus 746 * with an external supply. 747 */ 748 if (dwc->ulpi_ext_vbus_drv) 749 reg |= DWC3_GUSB2PHYCFG_ULPIEXTVBUSDRV; 750 751 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg); 752 753 return 0; 754 } 755 756 static int dwc3_phy_init(struct dwc3 *dwc) 757 { 758 int ret; 759 760 usb_phy_init(dwc->usb2_phy); 761 usb_phy_init(dwc->usb3_phy); 762 763 ret = phy_init(dwc->usb2_generic_phy); 764 if (ret < 0) 765 goto err_shutdown_usb3_phy; 766 767 ret = phy_init(dwc->usb3_generic_phy); 768 if (ret < 0) 769 goto err_exit_usb2_phy; 770 771 return 0; 772 773 err_exit_usb2_phy: 774 phy_exit(dwc->usb2_generic_phy); 775 err_shutdown_usb3_phy: 776 usb_phy_shutdown(dwc->usb3_phy); 777 usb_phy_shutdown(dwc->usb2_phy); 778 779 return ret; 780 } 781 782 static void dwc3_phy_exit(struct dwc3 *dwc) 783 { 784 phy_exit(dwc->usb3_generic_phy); 785 phy_exit(dwc->usb2_generic_phy); 786 787 usb_phy_shutdown(dwc->usb3_phy); 788 usb_phy_shutdown(dwc->usb2_phy); 789 } 790 791 static int dwc3_phy_power_on(struct dwc3 *dwc) 792 { 793 int ret; 794 795 usb_phy_set_suspend(dwc->usb2_phy, 0); 796 usb_phy_set_suspend(dwc->usb3_phy, 0); 797 798 ret = phy_power_on(dwc->usb2_generic_phy); 799 if (ret < 0) 800 goto err_suspend_usb3_phy; 801 802 ret = phy_power_on(dwc->usb3_generic_phy); 803 if (ret < 0) 804 goto err_power_off_usb2_phy; 805 806 return 0; 807 808 err_power_off_usb2_phy: 809 phy_power_off(dwc->usb2_generic_phy); 810 err_suspend_usb3_phy: 811 usb_phy_set_suspend(dwc->usb3_phy, 1); 812 usb_phy_set_suspend(dwc->usb2_phy, 1); 813 814 return ret; 815 } 816 817 static void dwc3_phy_power_off(struct dwc3 *dwc) 818 { 819 phy_power_off(dwc->usb3_generic_phy); 820 phy_power_off(dwc->usb2_generic_phy); 821 822 usb_phy_set_suspend(dwc->usb3_phy, 1); 823 usb_phy_set_suspend(dwc->usb2_phy, 1); 824 } 825 826 static int dwc3_clk_enable(struct dwc3 *dwc) 827 { 828 int ret; 829 830 ret = clk_prepare_enable(dwc->bus_clk); 831 if (ret) 832 return ret; 833 834 ret = clk_prepare_enable(dwc->ref_clk); 835 if (ret) 836 goto disable_bus_clk; 837 838 ret = clk_prepare_enable(dwc->susp_clk); 839 if (ret) 840 goto disable_ref_clk; 841 842 return 0; 843 844 disable_ref_clk: 845 clk_disable_unprepare(dwc->ref_clk); 846 disable_bus_clk: 847 clk_disable_unprepare(dwc->bus_clk); 848 return ret; 849 } 850 851 static void dwc3_clk_disable(struct dwc3 *dwc) 852 { 853 clk_disable_unprepare(dwc->susp_clk); 854 clk_disable_unprepare(dwc->ref_clk); 855 clk_disable_unprepare(dwc->bus_clk); 856 } 857 858 static void dwc3_core_exit(struct dwc3 *dwc) 859 { 860 dwc3_event_buffers_cleanup(dwc); 861 dwc3_phy_power_off(dwc); 862 dwc3_phy_exit(dwc); 863 dwc3_clk_disable(dwc); 864 reset_control_assert(dwc->reset); 865 } 866 867 static bool dwc3_core_is_valid(struct dwc3 *dwc) 868 { 869 u32 reg; 870 871 reg = dwc3_readl(dwc->regs, DWC3_GSNPSID); 872 dwc->ip = DWC3_GSNPS_ID(reg); 873 874 /* This should read as U3 followed by revision number */ 875 if (DWC3_IP_IS(DWC3)) { 876 dwc->revision = reg; 877 } else if (DWC3_IP_IS(DWC31) || DWC3_IP_IS(DWC32)) { 878 dwc->revision = dwc3_readl(dwc->regs, DWC3_VER_NUMBER); 879 dwc->version_type = dwc3_readl(dwc->regs, DWC3_VER_TYPE); 880 } else { 881 return false; 882 } 883 884 return true; 885 } 886 887 static void dwc3_core_setup_global_control(struct dwc3 *dwc) 888 { 889 unsigned int power_opt; 890 unsigned int hw_mode; 891 u32 reg; 892 893 reg = dwc3_readl(dwc->regs, DWC3_GCTL); 894 reg &= ~DWC3_GCTL_SCALEDOWN_MASK; 895 hw_mode = DWC3_GHWPARAMS0_MODE(dwc->hwparams.hwparams0); 896 power_opt = DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1); 897 898 switch (power_opt) { 899 case DWC3_GHWPARAMS1_EN_PWROPT_CLK: 900 /** 901 * WORKAROUND: DWC3 revisions between 2.10a and 2.50a have an 902 * issue which would cause xHCI compliance tests to fail. 903 * 904 * Because of that we cannot enable clock gating on such 905 * configurations. 906 * 907 * Refers to: 908 * 909 * STAR#9000588375: Clock Gating, SOF Issues when ref_clk-Based 910 * SOF/ITP Mode Used 911 */ 912 if ((dwc->dr_mode == USB_DR_MODE_HOST || 913 dwc->dr_mode == USB_DR_MODE_OTG) && 914 DWC3_VER_IS_WITHIN(DWC3, 210A, 250A)) 915 reg |= DWC3_GCTL_DSBLCLKGTNG | DWC3_GCTL_SOFITPSYNC; 916 else 917 reg &= ~DWC3_GCTL_DSBLCLKGTNG; 918 break; 919 case DWC3_GHWPARAMS1_EN_PWROPT_HIB: 920 /* 921 * REVISIT Enabling this bit so that host-mode hibernation 922 * will work. Device-mode hibernation is not yet implemented. 923 */ 924 reg |= DWC3_GCTL_GBLHIBERNATIONEN; 925 break; 926 default: 927 /* nothing */ 928 break; 929 } 930 931 /* 932 * This is a workaround for STAR#4846132, which only affects 933 * DWC_usb31 version2.00a operating in host mode. 934 * 935 * There is a problem in DWC_usb31 version 2.00a operating 936 * in host mode that would cause a CSR read timeout When CSR 937 * read coincides with RAM Clock Gating Entry. By disable 938 * Clock Gating, sacrificing power consumption for normal 939 * operation. 940 */ 941 if (power_opt != DWC3_GHWPARAMS1_EN_PWROPT_NO && 942 hw_mode != DWC3_GHWPARAMS0_MODE_GADGET && DWC3_VER_IS(DWC31, 200A)) 943 reg |= DWC3_GCTL_DSBLCLKGTNG; 944 945 /* check if current dwc3 is on simulation board */ 946 if (dwc->hwparams.hwparams6 & DWC3_GHWPARAMS6_EN_FPGA) { 947 dev_info(dwc->dev, "Running with FPGA optimizations\n"); 948 dwc->is_fpga = true; 949 } 950 951 WARN_ONCE(dwc->disable_scramble_quirk && !dwc->is_fpga, 952 "disable_scramble cannot be used on non-FPGA builds\n"); 953 954 if (dwc->disable_scramble_quirk && dwc->is_fpga) 955 reg |= DWC3_GCTL_DISSCRAMBLE; 956 else 957 reg &= ~DWC3_GCTL_DISSCRAMBLE; 958 959 if (dwc->u2exit_lfps_quirk) 960 reg |= DWC3_GCTL_U2EXIT_LFPS; 961 962 /* 963 * WORKAROUND: DWC3 revisions <1.90a have a bug 964 * where the device can fail to connect at SuperSpeed 965 * and falls back to high-speed mode which causes 966 * the device to enter a Connect/Disconnect loop 967 */ 968 if (DWC3_VER_IS_PRIOR(DWC3, 190A)) 969 reg |= DWC3_GCTL_U2RSTECN; 970 971 dwc3_writel(dwc->regs, DWC3_GCTL, reg); 972 } 973 974 static int dwc3_core_get_phy(struct dwc3 *dwc); 975 static int dwc3_core_ulpi_init(struct dwc3 *dwc); 976 977 /* set global incr burst type configuration registers */ 978 static void dwc3_set_incr_burst_type(struct dwc3 *dwc) 979 { 980 struct device *dev = dwc->dev; 981 /* incrx_mode : for INCR burst type. */ 982 bool incrx_mode; 983 /* incrx_size : for size of INCRX burst. */ 984 u32 incrx_size; 985 u32 *vals; 986 u32 cfg; 987 int ntype; 988 int ret; 989 int i; 990 991 cfg = dwc3_readl(dwc->regs, DWC3_GSBUSCFG0); 992 993 /* 994 * Handle property "snps,incr-burst-type-adjustment". 995 * Get the number of value from this property: 996 * result <= 0, means this property is not supported. 997 * result = 1, means INCRx burst mode supported. 998 * result > 1, means undefined length burst mode supported. 999 */ 1000 ntype = device_property_count_u32(dev, "snps,incr-burst-type-adjustment"); 1001 if (ntype <= 0) 1002 return; 1003 1004 vals = kcalloc(ntype, sizeof(u32), GFP_KERNEL); 1005 if (!vals) 1006 return; 1007 1008 /* Get INCR burst type, and parse it */ 1009 ret = device_property_read_u32_array(dev, 1010 "snps,incr-burst-type-adjustment", vals, ntype); 1011 if (ret) { 1012 kfree(vals); 1013 dev_err(dev, "Error to get property\n"); 1014 return; 1015 } 1016 1017 incrx_size = *vals; 1018 1019 if (ntype > 1) { 1020 /* INCRX (undefined length) burst mode */ 1021 incrx_mode = INCRX_UNDEF_LENGTH_BURST_MODE; 1022 for (i = 1; i < ntype; i++) { 1023 if (vals[i] > incrx_size) 1024 incrx_size = vals[i]; 1025 } 1026 } else { 1027 /* INCRX burst mode */ 1028 incrx_mode = INCRX_BURST_MODE; 1029 } 1030 1031 kfree(vals); 1032 1033 /* Enable Undefined Length INCR Burst and Enable INCRx Burst */ 1034 cfg &= ~DWC3_GSBUSCFG0_INCRBRST_MASK; 1035 if (incrx_mode) 1036 cfg |= DWC3_GSBUSCFG0_INCRBRSTENA; 1037 switch (incrx_size) { 1038 case 256: 1039 cfg |= DWC3_GSBUSCFG0_INCR256BRSTENA; 1040 break; 1041 case 128: 1042 cfg |= DWC3_GSBUSCFG0_INCR128BRSTENA; 1043 break; 1044 case 64: 1045 cfg |= DWC3_GSBUSCFG0_INCR64BRSTENA; 1046 break; 1047 case 32: 1048 cfg |= DWC3_GSBUSCFG0_INCR32BRSTENA; 1049 break; 1050 case 16: 1051 cfg |= DWC3_GSBUSCFG0_INCR16BRSTENA; 1052 break; 1053 case 8: 1054 cfg |= DWC3_GSBUSCFG0_INCR8BRSTENA; 1055 break; 1056 case 4: 1057 cfg |= DWC3_GSBUSCFG0_INCR4BRSTENA; 1058 break; 1059 case 1: 1060 break; 1061 default: 1062 dev_err(dev, "Invalid property\n"); 1063 break; 1064 } 1065 1066 dwc3_writel(dwc->regs, DWC3_GSBUSCFG0, cfg); 1067 } 1068 1069 static void dwc3_set_power_down_clk_scale(struct dwc3 *dwc) 1070 { 1071 u32 scale; 1072 u32 reg; 1073 1074 if (!dwc->susp_clk) 1075 return; 1076 1077 /* 1078 * The power down scale field specifies how many suspend_clk 1079 * periods fit into a 16KHz clock period. When performing 1080 * the division, round up the remainder. 1081 * 1082 * The power down scale value is calculated using the fastest 1083 * frequency of the suspend_clk. If it isn't fixed (but within 1084 * the accuracy requirement), the driver may not know the max 1085 * rate of the suspend_clk, so only update the power down scale 1086 * if the default is less than the calculated value from 1087 * clk_get_rate() or if the default is questionably high 1088 * (3x or more) to be within the requirement. 1089 */ 1090 scale = DIV_ROUND_UP(clk_get_rate(dwc->susp_clk), 16000); 1091 reg = dwc3_readl(dwc->regs, DWC3_GCTL); 1092 if ((reg & DWC3_GCTL_PWRDNSCALE_MASK) < DWC3_GCTL_PWRDNSCALE(scale) || 1093 (reg & DWC3_GCTL_PWRDNSCALE_MASK) > DWC3_GCTL_PWRDNSCALE(scale*3)) { 1094 reg &= ~(DWC3_GCTL_PWRDNSCALE_MASK); 1095 reg |= DWC3_GCTL_PWRDNSCALE(scale); 1096 dwc3_writel(dwc->regs, DWC3_GCTL, reg); 1097 } 1098 } 1099 1100 static void dwc3_config_threshold(struct dwc3 *dwc) 1101 { 1102 u32 reg; 1103 u8 rx_thr_num; 1104 u8 rx_maxburst; 1105 u8 tx_thr_num; 1106 u8 tx_maxburst; 1107 1108 /* 1109 * Must config both number of packets and max burst settings to enable 1110 * RX and/or TX threshold. 1111 */ 1112 if (!DWC3_IP_IS(DWC3) && dwc->dr_mode == USB_DR_MODE_HOST) { 1113 rx_thr_num = dwc->rx_thr_num_pkt_prd; 1114 rx_maxburst = dwc->rx_max_burst_prd; 1115 tx_thr_num = dwc->tx_thr_num_pkt_prd; 1116 tx_maxburst = dwc->tx_max_burst_prd; 1117 1118 if (rx_thr_num && rx_maxburst) { 1119 reg = dwc3_readl(dwc->regs, DWC3_GRXTHRCFG); 1120 reg |= DWC31_RXTHRNUMPKTSEL_PRD; 1121 1122 reg &= ~DWC31_RXTHRNUMPKT_PRD(~0); 1123 reg |= DWC31_RXTHRNUMPKT_PRD(rx_thr_num); 1124 1125 reg &= ~DWC31_MAXRXBURSTSIZE_PRD(~0); 1126 reg |= DWC31_MAXRXBURSTSIZE_PRD(rx_maxburst); 1127 1128 dwc3_writel(dwc->regs, DWC3_GRXTHRCFG, reg); 1129 } 1130 1131 if (tx_thr_num && tx_maxburst) { 1132 reg = dwc3_readl(dwc->regs, DWC3_GTXTHRCFG); 1133 reg |= DWC31_TXTHRNUMPKTSEL_PRD; 1134 1135 reg &= ~DWC31_TXTHRNUMPKT_PRD(~0); 1136 reg |= DWC31_TXTHRNUMPKT_PRD(tx_thr_num); 1137 1138 reg &= ~DWC31_MAXTXBURSTSIZE_PRD(~0); 1139 reg |= DWC31_MAXTXBURSTSIZE_PRD(tx_maxburst); 1140 1141 dwc3_writel(dwc->regs, DWC3_GTXTHRCFG, reg); 1142 } 1143 } 1144 1145 rx_thr_num = dwc->rx_thr_num_pkt; 1146 rx_maxburst = dwc->rx_max_burst; 1147 tx_thr_num = dwc->tx_thr_num_pkt; 1148 tx_maxburst = dwc->tx_max_burst; 1149 1150 if (DWC3_IP_IS(DWC3)) { 1151 if (rx_thr_num && rx_maxburst) { 1152 reg = dwc3_readl(dwc->regs, DWC3_GRXTHRCFG); 1153 reg |= DWC3_GRXTHRCFG_PKTCNTSEL; 1154 1155 reg &= ~DWC3_GRXTHRCFG_RXPKTCNT(~0); 1156 reg |= DWC3_GRXTHRCFG_RXPKTCNT(rx_thr_num); 1157 1158 reg &= ~DWC3_GRXTHRCFG_MAXRXBURSTSIZE(~0); 1159 reg |= DWC3_GRXTHRCFG_MAXRXBURSTSIZE(rx_maxburst); 1160 1161 dwc3_writel(dwc->regs, DWC3_GRXTHRCFG, reg); 1162 } 1163 1164 if (tx_thr_num && tx_maxburst) { 1165 reg = dwc3_readl(dwc->regs, DWC3_GTXTHRCFG); 1166 reg |= DWC3_GTXTHRCFG_PKTCNTSEL; 1167 1168 reg &= ~DWC3_GTXTHRCFG_TXPKTCNT(~0); 1169 reg |= DWC3_GTXTHRCFG_TXPKTCNT(tx_thr_num); 1170 1171 reg &= ~DWC3_GTXTHRCFG_MAXTXBURSTSIZE(~0); 1172 reg |= DWC3_GTXTHRCFG_MAXTXBURSTSIZE(tx_maxburst); 1173 1174 dwc3_writel(dwc->regs, DWC3_GTXTHRCFG, reg); 1175 } 1176 } else { 1177 if (rx_thr_num && rx_maxburst) { 1178 reg = dwc3_readl(dwc->regs, DWC3_GRXTHRCFG); 1179 reg |= DWC31_GRXTHRCFG_PKTCNTSEL; 1180 1181 reg &= ~DWC31_GRXTHRCFG_RXPKTCNT(~0); 1182 reg |= DWC31_GRXTHRCFG_RXPKTCNT(rx_thr_num); 1183 1184 reg &= ~DWC31_GRXTHRCFG_MAXRXBURSTSIZE(~0); 1185 reg |= DWC31_GRXTHRCFG_MAXRXBURSTSIZE(rx_maxburst); 1186 1187 dwc3_writel(dwc->regs, DWC3_GRXTHRCFG, reg); 1188 } 1189 1190 if (tx_thr_num && tx_maxburst) { 1191 reg = dwc3_readl(dwc->regs, DWC3_GTXTHRCFG); 1192 reg |= DWC31_GTXTHRCFG_PKTCNTSEL; 1193 1194 reg &= ~DWC31_GTXTHRCFG_TXPKTCNT(~0); 1195 reg |= DWC31_GTXTHRCFG_TXPKTCNT(tx_thr_num); 1196 1197 reg &= ~DWC31_GTXTHRCFG_MAXTXBURSTSIZE(~0); 1198 reg |= DWC31_GTXTHRCFG_MAXTXBURSTSIZE(tx_maxburst); 1199 1200 dwc3_writel(dwc->regs, DWC3_GTXTHRCFG, reg); 1201 } 1202 } 1203 } 1204 1205 /** 1206 * dwc3_core_init - Low-level initialization of DWC3 Core 1207 * @dwc: Pointer to our controller context structure 1208 * 1209 * Returns 0 on success otherwise negative errno. 1210 */ 1211 static int dwc3_core_init(struct dwc3 *dwc) 1212 { 1213 unsigned int hw_mode; 1214 u32 reg; 1215 int ret; 1216 1217 hw_mode = DWC3_GHWPARAMS0_MODE(dwc->hwparams.hwparams0); 1218 1219 /* 1220 * Write Linux Version Code to our GUID register so it's easy to figure 1221 * out which kernel version a bug was found. 1222 */ 1223 dwc3_writel(dwc->regs, DWC3_GUID, LINUX_VERSION_CODE); 1224 1225 ret = dwc3_phy_setup(dwc); 1226 if (ret) 1227 return ret; 1228 1229 if (!dwc->ulpi_ready) { 1230 ret = dwc3_core_ulpi_init(dwc); 1231 if (ret) { 1232 if (ret == -ETIMEDOUT) { 1233 dwc3_core_soft_reset(dwc); 1234 ret = -EPROBE_DEFER; 1235 } 1236 return ret; 1237 } 1238 dwc->ulpi_ready = true; 1239 } 1240 1241 if (!dwc->phys_ready) { 1242 ret = dwc3_core_get_phy(dwc); 1243 if (ret) 1244 goto err_exit_ulpi; 1245 dwc->phys_ready = true; 1246 } 1247 1248 ret = dwc3_phy_init(dwc); 1249 if (ret) 1250 goto err_exit_ulpi; 1251 1252 ret = dwc3_core_soft_reset(dwc); 1253 if (ret) 1254 goto err_exit_phy; 1255 1256 dwc3_core_setup_global_control(dwc); 1257 dwc3_core_num_eps(dwc); 1258 1259 /* Set power down scale of suspend_clk */ 1260 dwc3_set_power_down_clk_scale(dwc); 1261 1262 /* Adjust Frame Length */ 1263 dwc3_frame_length_adjustment(dwc); 1264 1265 /* Adjust Reference Clock Period */ 1266 dwc3_ref_clk_period(dwc); 1267 1268 dwc3_set_incr_burst_type(dwc); 1269 1270 ret = dwc3_phy_power_on(dwc); 1271 if (ret) 1272 goto err_exit_phy; 1273 1274 ret = dwc3_event_buffers_setup(dwc); 1275 if (ret) { 1276 dev_err(dwc->dev, "failed to setup event buffers\n"); 1277 goto err_power_off_phy; 1278 } 1279 1280 /* 1281 * ENDXFER polling is available on version 3.10a and later of 1282 * the DWC_usb3 controller. It is NOT available in the 1283 * DWC_usb31 controller. 1284 */ 1285 if (DWC3_VER_IS_WITHIN(DWC3, 310A, ANY)) { 1286 reg = dwc3_readl(dwc->regs, DWC3_GUCTL2); 1287 reg |= DWC3_GUCTL2_RST_ACTBITLATER; 1288 dwc3_writel(dwc->regs, DWC3_GUCTL2, reg); 1289 } 1290 1291 /* 1292 * STAR 9001285599: This issue affects DWC_usb3 version 3.20a 1293 * only. If the PM TIMER ECM is enabled through GUCTL2[19], the 1294 * link compliance test (TD7.21) may fail. If the ECN is not 1295 * enabled (GUCTL2[19] = 0), the controller will use the old timer 1296 * value (5us), which is still acceptable for the link compliance 1297 * test. Therefore, do not enable PM TIMER ECM in 3.20a by 1298 * setting GUCTL2[19] by default; instead, use GUCTL2[19] = 0. 1299 */ 1300 if (DWC3_VER_IS(DWC3, 320A)) { 1301 reg = dwc3_readl(dwc->regs, DWC3_GUCTL2); 1302 reg &= ~DWC3_GUCTL2_LC_TIMER; 1303 dwc3_writel(dwc->regs, DWC3_GUCTL2, reg); 1304 } 1305 1306 /* 1307 * When configured in HOST mode, after issuing U3/L2 exit controller 1308 * fails to send proper CRC checksum in CRC5 feild. Because of this 1309 * behaviour Transaction Error is generated, resulting in reset and 1310 * re-enumeration of usb device attached. All the termsel, xcvrsel, 1311 * opmode becomes 0 during end of resume. Enabling bit 10 of GUCTL1 1312 * will correct this problem. This option is to support certain 1313 * legacy ULPI PHYs. 1314 */ 1315 if (dwc->resume_hs_terminations) { 1316 reg = dwc3_readl(dwc->regs, DWC3_GUCTL1); 1317 reg |= DWC3_GUCTL1_RESUME_OPMODE_HS_HOST; 1318 dwc3_writel(dwc->regs, DWC3_GUCTL1, reg); 1319 } 1320 1321 if (!DWC3_VER_IS_PRIOR(DWC3, 250A)) { 1322 reg = dwc3_readl(dwc->regs, DWC3_GUCTL1); 1323 1324 /* 1325 * Enable hardware control of sending remote wakeup 1326 * in HS when the device is in the L1 state. 1327 */ 1328 if (!DWC3_VER_IS_PRIOR(DWC3, 290A)) 1329 reg |= DWC3_GUCTL1_DEV_L1_EXIT_BY_HW; 1330 1331 /* 1332 * Decouple USB 2.0 L1 & L2 events which will allow for 1333 * gadget driver to only receive U3/L2 suspend & wakeup 1334 * events and prevent the more frequent L1 LPM transitions 1335 * from interrupting the driver. 1336 */ 1337 if (!DWC3_VER_IS_PRIOR(DWC3, 300A)) 1338 reg |= DWC3_GUCTL1_DEV_DECOUPLE_L1L2_EVT; 1339 1340 if (dwc->dis_tx_ipgap_linecheck_quirk) 1341 reg |= DWC3_GUCTL1_TX_IPGAP_LINECHECK_DIS; 1342 1343 if (dwc->parkmode_disable_ss_quirk) 1344 reg |= DWC3_GUCTL1_PARKMODE_DISABLE_SS; 1345 1346 if (dwc->parkmode_disable_hs_quirk) 1347 reg |= DWC3_GUCTL1_PARKMODE_DISABLE_HS; 1348 1349 if (DWC3_VER_IS_WITHIN(DWC3, 290A, ANY) && 1350 (dwc->maximum_speed == USB_SPEED_HIGH || 1351 dwc->maximum_speed == USB_SPEED_FULL)) 1352 reg |= DWC3_GUCTL1_DEV_FORCE_20_CLK_FOR_30_CLK; 1353 1354 dwc3_writel(dwc->regs, DWC3_GUCTL1, reg); 1355 } 1356 1357 dwc3_config_threshold(dwc); 1358 1359 return 0; 1360 1361 err_power_off_phy: 1362 dwc3_phy_power_off(dwc); 1363 err_exit_phy: 1364 dwc3_phy_exit(dwc); 1365 err_exit_ulpi: 1366 dwc3_ulpi_exit(dwc); 1367 1368 return ret; 1369 } 1370 1371 static int dwc3_core_get_phy(struct dwc3 *dwc) 1372 { 1373 struct device *dev = dwc->dev; 1374 struct device_node *node = dev->of_node; 1375 int ret; 1376 1377 if (node) { 1378 dwc->usb2_phy = devm_usb_get_phy_by_phandle(dev, "usb-phy", 0); 1379 dwc->usb3_phy = devm_usb_get_phy_by_phandle(dev, "usb-phy", 1); 1380 } else { 1381 dwc->usb2_phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB2); 1382 dwc->usb3_phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB3); 1383 } 1384 1385 if (IS_ERR(dwc->usb2_phy)) { 1386 ret = PTR_ERR(dwc->usb2_phy); 1387 if (ret == -ENXIO || ret == -ENODEV) 1388 dwc->usb2_phy = NULL; 1389 else 1390 return dev_err_probe(dev, ret, "no usb2 phy configured\n"); 1391 } 1392 1393 if (IS_ERR(dwc->usb3_phy)) { 1394 ret = PTR_ERR(dwc->usb3_phy); 1395 if (ret == -ENXIO || ret == -ENODEV) 1396 dwc->usb3_phy = NULL; 1397 else 1398 return dev_err_probe(dev, ret, "no usb3 phy configured\n"); 1399 } 1400 1401 dwc->usb2_generic_phy = devm_phy_get(dev, "usb2-phy"); 1402 if (IS_ERR(dwc->usb2_generic_phy)) { 1403 ret = PTR_ERR(dwc->usb2_generic_phy); 1404 if (ret == -ENOSYS || ret == -ENODEV) 1405 dwc->usb2_generic_phy = NULL; 1406 else 1407 return dev_err_probe(dev, ret, "no usb2 phy configured\n"); 1408 } 1409 1410 dwc->usb3_generic_phy = devm_phy_get(dev, "usb3-phy"); 1411 if (IS_ERR(dwc->usb3_generic_phy)) { 1412 ret = PTR_ERR(dwc->usb3_generic_phy); 1413 if (ret == -ENOSYS || ret == -ENODEV) 1414 dwc->usb3_generic_phy = NULL; 1415 else 1416 return dev_err_probe(dev, ret, "no usb3 phy configured\n"); 1417 } 1418 1419 return 0; 1420 } 1421 1422 static int dwc3_core_init_mode(struct dwc3 *dwc) 1423 { 1424 struct device *dev = dwc->dev; 1425 int ret; 1426 1427 switch (dwc->dr_mode) { 1428 case USB_DR_MODE_PERIPHERAL: 1429 dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_DEVICE); 1430 1431 if (dwc->usb2_phy) 1432 otg_set_vbus(dwc->usb2_phy->otg, false); 1433 phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_DEVICE); 1434 phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_DEVICE); 1435 1436 ret = dwc3_gadget_init(dwc); 1437 if (ret) 1438 return dev_err_probe(dev, ret, "failed to initialize gadget\n"); 1439 break; 1440 case USB_DR_MODE_HOST: 1441 dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_HOST); 1442 1443 if (dwc->usb2_phy) 1444 otg_set_vbus(dwc->usb2_phy->otg, true); 1445 phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_HOST); 1446 phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_HOST); 1447 1448 ret = dwc3_host_init(dwc); 1449 if (ret) 1450 return dev_err_probe(dev, ret, "failed to initialize host\n"); 1451 break; 1452 case USB_DR_MODE_OTG: 1453 INIT_WORK(&dwc->drd_work, __dwc3_set_mode); 1454 ret = dwc3_drd_init(dwc); 1455 if (ret) 1456 return dev_err_probe(dev, ret, "failed to initialize dual-role\n"); 1457 break; 1458 default: 1459 dev_err(dev, "Unsupported mode of operation %d\n", dwc->dr_mode); 1460 return -EINVAL; 1461 } 1462 1463 return 0; 1464 } 1465 1466 static void dwc3_core_exit_mode(struct dwc3 *dwc) 1467 { 1468 switch (dwc->dr_mode) { 1469 case USB_DR_MODE_PERIPHERAL: 1470 dwc3_gadget_exit(dwc); 1471 break; 1472 case USB_DR_MODE_HOST: 1473 dwc3_host_exit(dwc); 1474 break; 1475 case USB_DR_MODE_OTG: 1476 dwc3_drd_exit(dwc); 1477 break; 1478 default: 1479 /* do nothing */ 1480 break; 1481 } 1482 1483 /* de-assert DRVVBUS for HOST and OTG mode */ 1484 dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_DEVICE); 1485 } 1486 1487 static void dwc3_get_properties(struct dwc3 *dwc) 1488 { 1489 struct device *dev = dwc->dev; 1490 u8 lpm_nyet_threshold; 1491 u8 tx_de_emphasis; 1492 u8 hird_threshold; 1493 u8 rx_thr_num_pkt = 0; 1494 u8 rx_max_burst = 0; 1495 u8 tx_thr_num_pkt = 0; 1496 u8 tx_max_burst = 0; 1497 u8 rx_thr_num_pkt_prd = 0; 1498 u8 rx_max_burst_prd = 0; 1499 u8 tx_thr_num_pkt_prd = 0; 1500 u8 tx_max_burst_prd = 0; 1501 u8 tx_fifo_resize_max_num; 1502 const char *usb_psy_name; 1503 int ret; 1504 1505 /* default to highest possible threshold */ 1506 lpm_nyet_threshold = 0xf; 1507 1508 /* default to -3.5dB de-emphasis */ 1509 tx_de_emphasis = 1; 1510 1511 /* 1512 * default to assert utmi_sleep_n and use maximum allowed HIRD 1513 * threshold value of 0b1100 1514 */ 1515 hird_threshold = 12; 1516 1517 /* 1518 * default to a TXFIFO size large enough to fit 6 max packets. This 1519 * allows for systems with larger bus latencies to have some headroom 1520 * for endpoints that have a large bMaxBurst value. 1521 */ 1522 tx_fifo_resize_max_num = 6; 1523 1524 dwc->maximum_speed = usb_get_maximum_speed(dev); 1525 dwc->max_ssp_rate = usb_get_maximum_ssp_rate(dev); 1526 dwc->dr_mode = usb_get_dr_mode(dev); 1527 dwc->hsphy_mode = of_usb_get_phy_mode(dev->of_node); 1528 1529 dwc->sysdev_is_parent = device_property_read_bool(dev, 1530 "linux,sysdev_is_parent"); 1531 if (dwc->sysdev_is_parent) 1532 dwc->sysdev = dwc->dev->parent; 1533 else 1534 dwc->sysdev = dwc->dev; 1535 1536 dwc->sys_wakeup = device_may_wakeup(dwc->sysdev); 1537 1538 ret = device_property_read_string(dev, "usb-psy-name", &usb_psy_name); 1539 if (ret >= 0) { 1540 dwc->usb_psy = power_supply_get_by_name(usb_psy_name); 1541 if (!dwc->usb_psy) 1542 dev_err(dev, "couldn't get usb power supply\n"); 1543 } 1544 1545 dwc->has_lpm_erratum = device_property_read_bool(dev, 1546 "snps,has-lpm-erratum"); 1547 device_property_read_u8(dev, "snps,lpm-nyet-threshold", 1548 &lpm_nyet_threshold); 1549 dwc->is_utmi_l1_suspend = device_property_read_bool(dev, 1550 "snps,is-utmi-l1-suspend"); 1551 device_property_read_u8(dev, "snps,hird-threshold", 1552 &hird_threshold); 1553 dwc->dis_start_transfer_quirk = device_property_read_bool(dev, 1554 "snps,dis-start-transfer-quirk"); 1555 dwc->usb3_lpm_capable = device_property_read_bool(dev, 1556 "snps,usb3_lpm_capable"); 1557 dwc->usb2_lpm_disable = device_property_read_bool(dev, 1558 "snps,usb2-lpm-disable"); 1559 dwc->usb2_gadget_lpm_disable = device_property_read_bool(dev, 1560 "snps,usb2-gadget-lpm-disable"); 1561 device_property_read_u8(dev, "snps,rx-thr-num-pkt", 1562 &rx_thr_num_pkt); 1563 device_property_read_u8(dev, "snps,rx-max-burst", 1564 &rx_max_burst); 1565 device_property_read_u8(dev, "snps,tx-thr-num-pkt", 1566 &tx_thr_num_pkt); 1567 device_property_read_u8(dev, "snps,tx-max-burst", 1568 &tx_max_burst); 1569 device_property_read_u8(dev, "snps,rx-thr-num-pkt-prd", 1570 &rx_thr_num_pkt_prd); 1571 device_property_read_u8(dev, "snps,rx-max-burst-prd", 1572 &rx_max_burst_prd); 1573 device_property_read_u8(dev, "snps,tx-thr-num-pkt-prd", 1574 &tx_thr_num_pkt_prd); 1575 device_property_read_u8(dev, "snps,tx-max-burst-prd", 1576 &tx_max_burst_prd); 1577 dwc->do_fifo_resize = device_property_read_bool(dev, 1578 "tx-fifo-resize"); 1579 if (dwc->do_fifo_resize) 1580 device_property_read_u8(dev, "tx-fifo-max-num", 1581 &tx_fifo_resize_max_num); 1582 1583 dwc->disable_scramble_quirk = device_property_read_bool(dev, 1584 "snps,disable_scramble_quirk"); 1585 dwc->u2exit_lfps_quirk = device_property_read_bool(dev, 1586 "snps,u2exit_lfps_quirk"); 1587 dwc->u2ss_inp3_quirk = device_property_read_bool(dev, 1588 "snps,u2ss_inp3_quirk"); 1589 dwc->req_p1p2p3_quirk = device_property_read_bool(dev, 1590 "snps,req_p1p2p3_quirk"); 1591 dwc->del_p1p2p3_quirk = device_property_read_bool(dev, 1592 "snps,del_p1p2p3_quirk"); 1593 dwc->del_phy_power_chg_quirk = device_property_read_bool(dev, 1594 "snps,del_phy_power_chg_quirk"); 1595 dwc->lfps_filter_quirk = device_property_read_bool(dev, 1596 "snps,lfps_filter_quirk"); 1597 dwc->rx_detect_poll_quirk = device_property_read_bool(dev, 1598 "snps,rx_detect_poll_quirk"); 1599 dwc->dis_u3_susphy_quirk = device_property_read_bool(dev, 1600 "snps,dis_u3_susphy_quirk"); 1601 dwc->dis_u2_susphy_quirk = device_property_read_bool(dev, 1602 "snps,dis_u2_susphy_quirk"); 1603 dwc->dis_enblslpm_quirk = device_property_read_bool(dev, 1604 "snps,dis_enblslpm_quirk"); 1605 dwc->dis_u1_entry_quirk = device_property_read_bool(dev, 1606 "snps,dis-u1-entry-quirk"); 1607 dwc->dis_u2_entry_quirk = device_property_read_bool(dev, 1608 "snps,dis-u2-entry-quirk"); 1609 dwc->dis_rxdet_inp3_quirk = device_property_read_bool(dev, 1610 "snps,dis_rxdet_inp3_quirk"); 1611 dwc->dis_u2_freeclk_exists_quirk = device_property_read_bool(dev, 1612 "snps,dis-u2-freeclk-exists-quirk"); 1613 dwc->dis_del_phy_power_chg_quirk = device_property_read_bool(dev, 1614 "snps,dis-del-phy-power-chg-quirk"); 1615 dwc->dis_tx_ipgap_linecheck_quirk = device_property_read_bool(dev, 1616 "snps,dis-tx-ipgap-linecheck-quirk"); 1617 dwc->resume_hs_terminations = device_property_read_bool(dev, 1618 "snps,resume-hs-terminations"); 1619 dwc->ulpi_ext_vbus_drv = device_property_read_bool(dev, 1620 "snps,ulpi-ext-vbus-drv"); 1621 dwc->parkmode_disable_ss_quirk = device_property_read_bool(dev, 1622 "snps,parkmode-disable-ss-quirk"); 1623 dwc->parkmode_disable_hs_quirk = device_property_read_bool(dev, 1624 "snps,parkmode-disable-hs-quirk"); 1625 dwc->gfladj_refclk_lpm_sel = device_property_read_bool(dev, 1626 "snps,gfladj-refclk-lpm-sel-quirk"); 1627 1628 dwc->tx_de_emphasis_quirk = device_property_read_bool(dev, 1629 "snps,tx_de_emphasis_quirk"); 1630 device_property_read_u8(dev, "snps,tx_de_emphasis", 1631 &tx_de_emphasis); 1632 device_property_read_string(dev, "snps,hsphy_interface", 1633 &dwc->hsphy_interface); 1634 device_property_read_u32(dev, "snps,quirk-frame-length-adjustment", 1635 &dwc->fladj); 1636 device_property_read_u32(dev, "snps,ref-clock-period-ns", 1637 &dwc->ref_clk_per); 1638 1639 dwc->dis_metastability_quirk = device_property_read_bool(dev, 1640 "snps,dis_metastability_quirk"); 1641 1642 dwc->dis_split_quirk = device_property_read_bool(dev, 1643 "snps,dis-split-quirk"); 1644 1645 dwc->lpm_nyet_threshold = lpm_nyet_threshold; 1646 dwc->tx_de_emphasis = tx_de_emphasis; 1647 1648 dwc->hird_threshold = hird_threshold; 1649 1650 dwc->rx_thr_num_pkt = rx_thr_num_pkt; 1651 dwc->rx_max_burst = rx_max_burst; 1652 1653 dwc->tx_thr_num_pkt = tx_thr_num_pkt; 1654 dwc->tx_max_burst = tx_max_burst; 1655 1656 dwc->rx_thr_num_pkt_prd = rx_thr_num_pkt_prd; 1657 dwc->rx_max_burst_prd = rx_max_burst_prd; 1658 1659 dwc->tx_thr_num_pkt_prd = tx_thr_num_pkt_prd; 1660 dwc->tx_max_burst_prd = tx_max_burst_prd; 1661 1662 dwc->imod_interval = 0; 1663 1664 dwc->tx_fifo_resize_max_num = tx_fifo_resize_max_num; 1665 } 1666 1667 /* check whether the core supports IMOD */ 1668 bool dwc3_has_imod(struct dwc3 *dwc) 1669 { 1670 return DWC3_VER_IS_WITHIN(DWC3, 300A, ANY) || 1671 DWC3_VER_IS_WITHIN(DWC31, 120A, ANY) || 1672 DWC3_IP_IS(DWC32); 1673 } 1674 1675 static void dwc3_check_params(struct dwc3 *dwc) 1676 { 1677 struct device *dev = dwc->dev; 1678 unsigned int hwparam_gen = 1679 DWC3_GHWPARAMS3_SSPHY_IFC(dwc->hwparams.hwparams3); 1680 1681 /* Check for proper value of imod_interval */ 1682 if (dwc->imod_interval && !dwc3_has_imod(dwc)) { 1683 dev_warn(dwc->dev, "Interrupt moderation not supported\n"); 1684 dwc->imod_interval = 0; 1685 } 1686 1687 /* 1688 * Workaround for STAR 9000961433 which affects only version 1689 * 3.00a of the DWC_usb3 core. This prevents the controller 1690 * interrupt from being masked while handling events. IMOD 1691 * allows us to work around this issue. Enable it for the 1692 * affected version. 1693 */ 1694 if (!dwc->imod_interval && 1695 DWC3_VER_IS(DWC3, 300A)) 1696 dwc->imod_interval = 1; 1697 1698 /* Check the maximum_speed parameter */ 1699 switch (dwc->maximum_speed) { 1700 case USB_SPEED_FULL: 1701 case USB_SPEED_HIGH: 1702 break; 1703 case USB_SPEED_SUPER: 1704 if (hwparam_gen == DWC3_GHWPARAMS3_SSPHY_IFC_DIS) 1705 dev_warn(dev, "UDC doesn't support Gen 1\n"); 1706 break; 1707 case USB_SPEED_SUPER_PLUS: 1708 if ((DWC3_IP_IS(DWC32) && 1709 hwparam_gen == DWC3_GHWPARAMS3_SSPHY_IFC_DIS) || 1710 (!DWC3_IP_IS(DWC32) && 1711 hwparam_gen != DWC3_GHWPARAMS3_SSPHY_IFC_GEN2)) 1712 dev_warn(dev, "UDC doesn't support SSP\n"); 1713 break; 1714 default: 1715 dev_err(dev, "invalid maximum_speed parameter %d\n", 1716 dwc->maximum_speed); 1717 fallthrough; 1718 case USB_SPEED_UNKNOWN: 1719 switch (hwparam_gen) { 1720 case DWC3_GHWPARAMS3_SSPHY_IFC_GEN2: 1721 dwc->maximum_speed = USB_SPEED_SUPER_PLUS; 1722 break; 1723 case DWC3_GHWPARAMS3_SSPHY_IFC_GEN1: 1724 if (DWC3_IP_IS(DWC32)) 1725 dwc->maximum_speed = USB_SPEED_SUPER_PLUS; 1726 else 1727 dwc->maximum_speed = USB_SPEED_SUPER; 1728 break; 1729 case DWC3_GHWPARAMS3_SSPHY_IFC_DIS: 1730 dwc->maximum_speed = USB_SPEED_HIGH; 1731 break; 1732 default: 1733 dwc->maximum_speed = USB_SPEED_SUPER; 1734 break; 1735 } 1736 break; 1737 } 1738 1739 /* 1740 * Currently the controller does not have visibility into the HW 1741 * parameter to determine the maximum number of lanes the HW supports. 1742 * If the number of lanes is not specified in the device property, then 1743 * set the default to support dual-lane for DWC_usb32 and single-lane 1744 * for DWC_usb31 for super-speed-plus. 1745 */ 1746 if (dwc->maximum_speed == USB_SPEED_SUPER_PLUS) { 1747 switch (dwc->max_ssp_rate) { 1748 case USB_SSP_GEN_2x1: 1749 if (hwparam_gen == DWC3_GHWPARAMS3_SSPHY_IFC_GEN1) 1750 dev_warn(dev, "UDC only supports Gen 1\n"); 1751 break; 1752 case USB_SSP_GEN_1x2: 1753 case USB_SSP_GEN_2x2: 1754 if (DWC3_IP_IS(DWC31)) 1755 dev_warn(dev, "UDC only supports single lane\n"); 1756 break; 1757 case USB_SSP_GEN_UNKNOWN: 1758 default: 1759 switch (hwparam_gen) { 1760 case DWC3_GHWPARAMS3_SSPHY_IFC_GEN2: 1761 if (DWC3_IP_IS(DWC32)) 1762 dwc->max_ssp_rate = USB_SSP_GEN_2x2; 1763 else 1764 dwc->max_ssp_rate = USB_SSP_GEN_2x1; 1765 break; 1766 case DWC3_GHWPARAMS3_SSPHY_IFC_GEN1: 1767 if (DWC3_IP_IS(DWC32)) 1768 dwc->max_ssp_rate = USB_SSP_GEN_1x2; 1769 break; 1770 } 1771 break; 1772 } 1773 } 1774 } 1775 1776 static struct extcon_dev *dwc3_get_extcon(struct dwc3 *dwc) 1777 { 1778 struct device *dev = dwc->dev; 1779 struct device_node *np_phy; 1780 struct extcon_dev *edev = NULL; 1781 const char *name; 1782 1783 if (device_property_read_bool(dev, "extcon")) 1784 return extcon_get_edev_by_phandle(dev, 0); 1785 1786 /* 1787 * Device tree platforms should get extcon via phandle. 1788 * On ACPI platforms, we get the name from a device property. 1789 * This device property is for kernel internal use only and 1790 * is expected to be set by the glue code. 1791 */ 1792 if (device_property_read_string(dev, "linux,extcon-name", &name) == 0) 1793 return extcon_get_extcon_dev(name); 1794 1795 /* 1796 * Check explicitly if "usb-role-switch" is used since 1797 * extcon_find_edev_by_node() can not be used to check the absence of 1798 * an extcon device. In the absence of an device it will always return 1799 * EPROBE_DEFER. 1800 */ 1801 if (IS_ENABLED(CONFIG_USB_ROLE_SWITCH) && 1802 device_property_read_bool(dev, "usb-role-switch")) 1803 return NULL; 1804 1805 /* 1806 * Try to get an extcon device from the USB PHY controller's "port" 1807 * node. Check if it has the "port" node first, to avoid printing the 1808 * error message from underlying code, as it's a valid case: extcon 1809 * device (and "port" node) may be missing in case of "usb-role-switch" 1810 * or OTG mode. 1811 */ 1812 np_phy = of_parse_phandle(dev->of_node, "phys", 0); 1813 if (of_graph_is_present(np_phy)) { 1814 struct device_node *np_conn; 1815 1816 np_conn = of_graph_get_remote_node(np_phy, -1, -1); 1817 if (np_conn) 1818 edev = extcon_find_edev_by_node(np_conn); 1819 of_node_put(np_conn); 1820 } 1821 of_node_put(np_phy); 1822 1823 return edev; 1824 } 1825 1826 static int dwc3_get_clocks(struct dwc3 *dwc) 1827 { 1828 struct device *dev = dwc->dev; 1829 1830 if (!dev->of_node) 1831 return 0; 1832 1833 /* 1834 * Clocks are optional, but new DT platforms should support all clocks 1835 * as required by the DT-binding. 1836 * Some devices have different clock names in legacy device trees, 1837 * check for them to retain backwards compatibility. 1838 */ 1839 dwc->bus_clk = devm_clk_get_optional(dev, "bus_early"); 1840 if (IS_ERR(dwc->bus_clk)) { 1841 return dev_err_probe(dev, PTR_ERR(dwc->bus_clk), 1842 "could not get bus clock\n"); 1843 } 1844 1845 if (dwc->bus_clk == NULL) { 1846 dwc->bus_clk = devm_clk_get_optional(dev, "bus_clk"); 1847 if (IS_ERR(dwc->bus_clk)) { 1848 return dev_err_probe(dev, PTR_ERR(dwc->bus_clk), 1849 "could not get bus clock\n"); 1850 } 1851 } 1852 1853 dwc->ref_clk = devm_clk_get_optional(dev, "ref"); 1854 if (IS_ERR(dwc->ref_clk)) { 1855 return dev_err_probe(dev, PTR_ERR(dwc->ref_clk), 1856 "could not get ref clock\n"); 1857 } 1858 1859 if (dwc->ref_clk == NULL) { 1860 dwc->ref_clk = devm_clk_get_optional(dev, "ref_clk"); 1861 if (IS_ERR(dwc->ref_clk)) { 1862 return dev_err_probe(dev, PTR_ERR(dwc->ref_clk), 1863 "could not get ref clock\n"); 1864 } 1865 } 1866 1867 dwc->susp_clk = devm_clk_get_optional(dev, "suspend"); 1868 if (IS_ERR(dwc->susp_clk)) { 1869 return dev_err_probe(dev, PTR_ERR(dwc->susp_clk), 1870 "could not get suspend clock\n"); 1871 } 1872 1873 if (dwc->susp_clk == NULL) { 1874 dwc->susp_clk = devm_clk_get_optional(dev, "suspend_clk"); 1875 if (IS_ERR(dwc->susp_clk)) { 1876 return dev_err_probe(dev, PTR_ERR(dwc->susp_clk), 1877 "could not get suspend clock\n"); 1878 } 1879 } 1880 1881 return 0; 1882 } 1883 1884 static int dwc3_probe(struct platform_device *pdev) 1885 { 1886 struct device *dev = &pdev->dev; 1887 struct resource *res, dwc_res; 1888 void __iomem *regs; 1889 struct dwc3 *dwc; 1890 int ret; 1891 1892 dwc = devm_kzalloc(dev, sizeof(*dwc), GFP_KERNEL); 1893 if (!dwc) 1894 return -ENOMEM; 1895 1896 dwc->dev = dev; 1897 1898 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1899 if (!res) { 1900 dev_err(dev, "missing memory resource\n"); 1901 return -ENODEV; 1902 } 1903 1904 dwc->xhci_resources[0].start = res->start; 1905 dwc->xhci_resources[0].end = dwc->xhci_resources[0].start + 1906 DWC3_XHCI_REGS_END; 1907 dwc->xhci_resources[0].flags = res->flags; 1908 dwc->xhci_resources[0].name = res->name; 1909 1910 /* 1911 * Request memory region but exclude xHCI regs, 1912 * since it will be requested by the xhci-plat driver. 1913 */ 1914 dwc_res = *res; 1915 dwc_res.start += DWC3_GLOBALS_REGS_START; 1916 1917 if (dev->of_node) { 1918 struct device_node *parent = of_get_parent(dev->of_node); 1919 1920 if (of_device_is_compatible(parent, "realtek,rtd-dwc3")) { 1921 dwc_res.start -= DWC3_GLOBALS_REGS_START; 1922 dwc_res.start += DWC3_RTK_RTD_GLOBALS_REGS_START; 1923 } 1924 1925 of_node_put(parent); 1926 } 1927 1928 regs = devm_ioremap_resource(dev, &dwc_res); 1929 if (IS_ERR(regs)) 1930 return PTR_ERR(regs); 1931 1932 dwc->regs = regs; 1933 dwc->regs_size = resource_size(&dwc_res); 1934 1935 dwc3_get_properties(dwc); 1936 1937 dwc->reset = devm_reset_control_array_get_optional_shared(dev); 1938 if (IS_ERR(dwc->reset)) { 1939 ret = PTR_ERR(dwc->reset); 1940 goto err_put_psy; 1941 } 1942 1943 ret = dwc3_get_clocks(dwc); 1944 if (ret) 1945 goto err_put_psy; 1946 1947 ret = reset_control_deassert(dwc->reset); 1948 if (ret) 1949 goto err_put_psy; 1950 1951 ret = dwc3_clk_enable(dwc); 1952 if (ret) 1953 goto err_assert_reset; 1954 1955 if (!dwc3_core_is_valid(dwc)) { 1956 dev_err(dwc->dev, "this is not a DesignWare USB3 DRD Core\n"); 1957 ret = -ENODEV; 1958 goto err_disable_clks; 1959 } 1960 1961 platform_set_drvdata(pdev, dwc); 1962 dwc3_cache_hwparams(dwc); 1963 1964 if (!dwc->sysdev_is_parent && 1965 DWC3_GHWPARAMS0_AWIDTH(dwc->hwparams.hwparams0) == 64) { 1966 ret = dma_set_mask_and_coherent(dwc->sysdev, DMA_BIT_MASK(64)); 1967 if (ret) 1968 goto err_disable_clks; 1969 } 1970 1971 spin_lock_init(&dwc->lock); 1972 mutex_init(&dwc->mutex); 1973 1974 pm_runtime_get_noresume(dev); 1975 pm_runtime_set_active(dev); 1976 pm_runtime_use_autosuspend(dev); 1977 pm_runtime_set_autosuspend_delay(dev, DWC3_DEFAULT_AUTOSUSPEND_DELAY); 1978 pm_runtime_enable(dev); 1979 1980 pm_runtime_forbid(dev); 1981 1982 ret = dwc3_alloc_event_buffers(dwc, DWC3_EVENT_BUFFERS_SIZE); 1983 if (ret) { 1984 dev_err(dwc->dev, "failed to allocate event buffers\n"); 1985 ret = -ENOMEM; 1986 goto err_allow_rpm; 1987 } 1988 1989 dwc->edev = dwc3_get_extcon(dwc); 1990 if (IS_ERR(dwc->edev)) { 1991 ret = dev_err_probe(dwc->dev, PTR_ERR(dwc->edev), "failed to get extcon\n"); 1992 goto err_free_event_buffers; 1993 } 1994 1995 ret = dwc3_get_dr_mode(dwc); 1996 if (ret) 1997 goto err_free_event_buffers; 1998 1999 ret = dwc3_core_init(dwc); 2000 if (ret) { 2001 dev_err_probe(dev, ret, "failed to initialize core\n"); 2002 goto err_free_event_buffers; 2003 } 2004 2005 dwc3_check_params(dwc); 2006 dwc3_debugfs_init(dwc); 2007 2008 ret = dwc3_core_init_mode(dwc); 2009 if (ret) 2010 goto err_exit_debugfs; 2011 2012 pm_runtime_put(dev); 2013 2014 dma_set_max_seg_size(dev, UINT_MAX); 2015 2016 return 0; 2017 2018 err_exit_debugfs: 2019 dwc3_debugfs_exit(dwc); 2020 dwc3_event_buffers_cleanup(dwc); 2021 dwc3_phy_power_off(dwc); 2022 dwc3_phy_exit(dwc); 2023 dwc3_ulpi_exit(dwc); 2024 err_free_event_buffers: 2025 dwc3_free_event_buffers(dwc); 2026 err_allow_rpm: 2027 pm_runtime_allow(dev); 2028 pm_runtime_disable(dev); 2029 pm_runtime_dont_use_autosuspend(dev); 2030 pm_runtime_set_suspended(dev); 2031 pm_runtime_put_noidle(dev); 2032 err_disable_clks: 2033 dwc3_clk_disable(dwc); 2034 err_assert_reset: 2035 reset_control_assert(dwc->reset); 2036 err_put_psy: 2037 if (dwc->usb_psy) 2038 power_supply_put(dwc->usb_psy); 2039 2040 return ret; 2041 } 2042 2043 static void dwc3_remove(struct platform_device *pdev) 2044 { 2045 struct dwc3 *dwc = platform_get_drvdata(pdev); 2046 2047 pm_runtime_get_sync(&pdev->dev); 2048 2049 dwc3_core_exit_mode(dwc); 2050 dwc3_debugfs_exit(dwc); 2051 2052 dwc3_core_exit(dwc); 2053 dwc3_ulpi_exit(dwc); 2054 2055 pm_runtime_allow(&pdev->dev); 2056 pm_runtime_disable(&pdev->dev); 2057 pm_runtime_dont_use_autosuspend(&pdev->dev); 2058 pm_runtime_put_noidle(&pdev->dev); 2059 /* 2060 * HACK: Clear the driver data, which is currently accessed by parent 2061 * glue drivers, before allowing the parent to suspend. 2062 */ 2063 platform_set_drvdata(pdev, NULL); 2064 pm_runtime_set_suspended(&pdev->dev); 2065 2066 dwc3_free_event_buffers(dwc); 2067 2068 if (dwc->usb_psy) 2069 power_supply_put(dwc->usb_psy); 2070 } 2071 2072 #ifdef CONFIG_PM 2073 static int dwc3_core_init_for_resume(struct dwc3 *dwc) 2074 { 2075 int ret; 2076 2077 ret = reset_control_deassert(dwc->reset); 2078 if (ret) 2079 return ret; 2080 2081 ret = dwc3_clk_enable(dwc); 2082 if (ret) 2083 goto assert_reset; 2084 2085 ret = dwc3_core_init(dwc); 2086 if (ret) 2087 goto disable_clks; 2088 2089 return 0; 2090 2091 disable_clks: 2092 dwc3_clk_disable(dwc); 2093 assert_reset: 2094 reset_control_assert(dwc->reset); 2095 2096 return ret; 2097 } 2098 2099 static int dwc3_suspend_common(struct dwc3 *dwc, pm_message_t msg) 2100 { 2101 u32 reg; 2102 2103 switch (dwc->current_dr_role) { 2104 case DWC3_GCTL_PRTCAP_DEVICE: 2105 if (pm_runtime_suspended(dwc->dev)) 2106 break; 2107 dwc3_gadget_suspend(dwc); 2108 synchronize_irq(dwc->irq_gadget); 2109 dwc3_core_exit(dwc); 2110 break; 2111 case DWC3_GCTL_PRTCAP_HOST: 2112 if (!PMSG_IS_AUTO(msg) && !device_may_wakeup(dwc->dev)) { 2113 dwc3_core_exit(dwc); 2114 break; 2115 } 2116 2117 /* Let controller to suspend HSPHY before PHY driver suspends */ 2118 if (dwc->dis_u2_susphy_quirk || 2119 dwc->dis_enblslpm_quirk) { 2120 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0)); 2121 reg |= DWC3_GUSB2PHYCFG_ENBLSLPM | 2122 DWC3_GUSB2PHYCFG_SUSPHY; 2123 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg); 2124 2125 /* Give some time for USB2 PHY to suspend */ 2126 usleep_range(5000, 6000); 2127 } 2128 2129 phy_pm_runtime_put_sync(dwc->usb2_generic_phy); 2130 phy_pm_runtime_put_sync(dwc->usb3_generic_phy); 2131 break; 2132 case DWC3_GCTL_PRTCAP_OTG: 2133 /* do nothing during runtime_suspend */ 2134 if (PMSG_IS_AUTO(msg)) 2135 break; 2136 2137 if (dwc->current_otg_role == DWC3_OTG_ROLE_DEVICE) { 2138 dwc3_gadget_suspend(dwc); 2139 synchronize_irq(dwc->irq_gadget); 2140 } 2141 2142 dwc3_otg_exit(dwc); 2143 dwc3_core_exit(dwc); 2144 break; 2145 default: 2146 /* do nothing */ 2147 break; 2148 } 2149 2150 return 0; 2151 } 2152 2153 static int dwc3_resume_common(struct dwc3 *dwc, pm_message_t msg) 2154 { 2155 int ret; 2156 u32 reg; 2157 2158 switch (dwc->current_dr_role) { 2159 case DWC3_GCTL_PRTCAP_DEVICE: 2160 ret = dwc3_core_init_for_resume(dwc); 2161 if (ret) 2162 return ret; 2163 2164 dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_DEVICE); 2165 dwc3_gadget_resume(dwc); 2166 break; 2167 case DWC3_GCTL_PRTCAP_HOST: 2168 if (!PMSG_IS_AUTO(msg) && !device_may_wakeup(dwc->dev)) { 2169 ret = dwc3_core_init_for_resume(dwc); 2170 if (ret) 2171 return ret; 2172 dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_HOST); 2173 break; 2174 } 2175 /* Restore GUSB2PHYCFG bits that were modified in suspend */ 2176 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0)); 2177 if (dwc->dis_u2_susphy_quirk) 2178 reg &= ~DWC3_GUSB2PHYCFG_SUSPHY; 2179 2180 if (dwc->dis_enblslpm_quirk) 2181 reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM; 2182 2183 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg); 2184 2185 phy_pm_runtime_get_sync(dwc->usb2_generic_phy); 2186 phy_pm_runtime_get_sync(dwc->usb3_generic_phy); 2187 break; 2188 case DWC3_GCTL_PRTCAP_OTG: 2189 /* nothing to do on runtime_resume */ 2190 if (PMSG_IS_AUTO(msg)) 2191 break; 2192 2193 ret = dwc3_core_init_for_resume(dwc); 2194 if (ret) 2195 return ret; 2196 2197 dwc3_set_prtcap(dwc, dwc->current_dr_role); 2198 2199 dwc3_otg_init(dwc); 2200 if (dwc->current_otg_role == DWC3_OTG_ROLE_HOST) { 2201 dwc3_otg_host_init(dwc); 2202 } else if (dwc->current_otg_role == DWC3_OTG_ROLE_DEVICE) { 2203 dwc3_gadget_resume(dwc); 2204 } 2205 2206 break; 2207 default: 2208 /* do nothing */ 2209 break; 2210 } 2211 2212 return 0; 2213 } 2214 2215 static int dwc3_runtime_checks(struct dwc3 *dwc) 2216 { 2217 switch (dwc->current_dr_role) { 2218 case DWC3_GCTL_PRTCAP_DEVICE: 2219 if (dwc->connected) 2220 return -EBUSY; 2221 break; 2222 case DWC3_GCTL_PRTCAP_HOST: 2223 default: 2224 /* do nothing */ 2225 break; 2226 } 2227 2228 return 0; 2229 } 2230 2231 static int dwc3_runtime_suspend(struct device *dev) 2232 { 2233 struct dwc3 *dwc = dev_get_drvdata(dev); 2234 int ret; 2235 2236 if (dwc3_runtime_checks(dwc)) 2237 return -EBUSY; 2238 2239 ret = dwc3_suspend_common(dwc, PMSG_AUTO_SUSPEND); 2240 if (ret) 2241 return ret; 2242 2243 return 0; 2244 } 2245 2246 static int dwc3_runtime_resume(struct device *dev) 2247 { 2248 struct dwc3 *dwc = dev_get_drvdata(dev); 2249 int ret; 2250 2251 ret = dwc3_resume_common(dwc, PMSG_AUTO_RESUME); 2252 if (ret) 2253 return ret; 2254 2255 switch (dwc->current_dr_role) { 2256 case DWC3_GCTL_PRTCAP_DEVICE: 2257 dwc3_gadget_process_pending_events(dwc); 2258 break; 2259 case DWC3_GCTL_PRTCAP_HOST: 2260 default: 2261 /* do nothing */ 2262 break; 2263 } 2264 2265 pm_runtime_mark_last_busy(dev); 2266 2267 return 0; 2268 } 2269 2270 static int dwc3_runtime_idle(struct device *dev) 2271 { 2272 struct dwc3 *dwc = dev_get_drvdata(dev); 2273 2274 switch (dwc->current_dr_role) { 2275 case DWC3_GCTL_PRTCAP_DEVICE: 2276 if (dwc3_runtime_checks(dwc)) 2277 return -EBUSY; 2278 break; 2279 case DWC3_GCTL_PRTCAP_HOST: 2280 default: 2281 /* do nothing */ 2282 break; 2283 } 2284 2285 pm_runtime_mark_last_busy(dev); 2286 pm_runtime_autosuspend(dev); 2287 2288 return 0; 2289 } 2290 #endif /* CONFIG_PM */ 2291 2292 #ifdef CONFIG_PM_SLEEP 2293 static int dwc3_suspend(struct device *dev) 2294 { 2295 struct dwc3 *dwc = dev_get_drvdata(dev); 2296 int ret; 2297 2298 ret = dwc3_suspend_common(dwc, PMSG_SUSPEND); 2299 if (ret) 2300 return ret; 2301 2302 pinctrl_pm_select_sleep_state(dev); 2303 2304 return 0; 2305 } 2306 2307 static int dwc3_resume(struct device *dev) 2308 { 2309 struct dwc3 *dwc = dev_get_drvdata(dev); 2310 int ret; 2311 2312 pinctrl_pm_select_default_state(dev); 2313 2314 ret = dwc3_resume_common(dwc, PMSG_RESUME); 2315 if (ret) 2316 return ret; 2317 2318 pm_runtime_disable(dev); 2319 pm_runtime_set_active(dev); 2320 pm_runtime_enable(dev); 2321 2322 return 0; 2323 } 2324 2325 static void dwc3_complete(struct device *dev) 2326 { 2327 struct dwc3 *dwc = dev_get_drvdata(dev); 2328 u32 reg; 2329 2330 if (dwc->current_dr_role == DWC3_GCTL_PRTCAP_HOST && 2331 dwc->dis_split_quirk) { 2332 reg = dwc3_readl(dwc->regs, DWC3_GUCTL3); 2333 reg |= DWC3_GUCTL3_SPLITDISABLE; 2334 dwc3_writel(dwc->regs, DWC3_GUCTL3, reg); 2335 } 2336 } 2337 #else 2338 #define dwc3_complete NULL 2339 #endif /* CONFIG_PM_SLEEP */ 2340 2341 static const struct dev_pm_ops dwc3_dev_pm_ops = { 2342 SET_SYSTEM_SLEEP_PM_OPS(dwc3_suspend, dwc3_resume) 2343 .complete = dwc3_complete, 2344 SET_RUNTIME_PM_OPS(dwc3_runtime_suspend, dwc3_runtime_resume, 2345 dwc3_runtime_idle) 2346 }; 2347 2348 #ifdef CONFIG_OF 2349 static const struct of_device_id of_dwc3_match[] = { 2350 { 2351 .compatible = "snps,dwc3" 2352 }, 2353 { 2354 .compatible = "synopsys,dwc3" 2355 }, 2356 { }, 2357 }; 2358 MODULE_DEVICE_TABLE(of, of_dwc3_match); 2359 #endif 2360 2361 #ifdef CONFIG_ACPI 2362 2363 #define ACPI_ID_INTEL_BSW "808622B7" 2364 2365 static const struct acpi_device_id dwc3_acpi_match[] = { 2366 { ACPI_ID_INTEL_BSW, 0 }, 2367 { }, 2368 }; 2369 MODULE_DEVICE_TABLE(acpi, dwc3_acpi_match); 2370 #endif 2371 2372 static struct platform_driver dwc3_driver = { 2373 .probe = dwc3_probe, 2374 .remove_new = dwc3_remove, 2375 .driver = { 2376 .name = "dwc3", 2377 .of_match_table = of_match_ptr(of_dwc3_match), 2378 .acpi_match_table = ACPI_PTR(dwc3_acpi_match), 2379 .pm = &dwc3_dev_pm_ops, 2380 }, 2381 }; 2382 2383 module_platform_driver(dwc3_driver); 2384 2385 MODULE_ALIAS("platform:dwc3"); 2386 MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>"); 2387 MODULE_LICENSE("GPL v2"); 2388 MODULE_DESCRIPTION("DesignWare USB3 DRD Controller Driver"); 2389