1 // SPDX-License-Identifier: GPL-2.0 2 /** 3 * core.c - DesignWare USB3 DRD Controller Core file 4 * 5 * Copyright (C) 2010-2011 Texas Instruments Incorporated - https://www.ti.com 6 * 7 * Authors: Felipe Balbi <balbi@ti.com>, 8 * Sebastian Andrzej Siewior <bigeasy@linutronix.de> 9 */ 10 11 #include <linux/clk.h> 12 #include <linux/version.h> 13 #include <linux/module.h> 14 #include <linux/kernel.h> 15 #include <linux/slab.h> 16 #include <linux/spinlock.h> 17 #include <linux/platform_device.h> 18 #include <linux/pm_runtime.h> 19 #include <linux/interrupt.h> 20 #include <linux/ioport.h> 21 #include <linux/io.h> 22 #include <linux/list.h> 23 #include <linux/delay.h> 24 #include <linux/dma-mapping.h> 25 #include <linux/of.h> 26 #include <linux/acpi.h> 27 #include <linux/pinctrl/consumer.h> 28 #include <linux/reset.h> 29 30 #include <linux/usb/ch9.h> 31 #include <linux/usb/gadget.h> 32 #include <linux/usb/of.h> 33 #include <linux/usb/otg.h> 34 35 #include "core.h" 36 #include "gadget.h" 37 #include "io.h" 38 39 #include "debug.h" 40 41 #define DWC3_DEFAULT_AUTOSUSPEND_DELAY 5000 /* ms */ 42 43 /** 44 * dwc3_get_dr_mode - Validates and sets dr_mode 45 * @dwc: pointer to our context structure 46 */ 47 static int dwc3_get_dr_mode(struct dwc3 *dwc) 48 { 49 enum usb_dr_mode mode; 50 struct device *dev = dwc->dev; 51 unsigned int hw_mode; 52 53 if (dwc->dr_mode == USB_DR_MODE_UNKNOWN) 54 dwc->dr_mode = USB_DR_MODE_OTG; 55 56 mode = dwc->dr_mode; 57 hw_mode = DWC3_GHWPARAMS0_MODE(dwc->hwparams.hwparams0); 58 59 switch (hw_mode) { 60 case DWC3_GHWPARAMS0_MODE_GADGET: 61 if (IS_ENABLED(CONFIG_USB_DWC3_HOST)) { 62 dev_err(dev, 63 "Controller does not support host mode.\n"); 64 return -EINVAL; 65 } 66 mode = USB_DR_MODE_PERIPHERAL; 67 break; 68 case DWC3_GHWPARAMS0_MODE_HOST: 69 if (IS_ENABLED(CONFIG_USB_DWC3_GADGET)) { 70 dev_err(dev, 71 "Controller does not support device mode.\n"); 72 return -EINVAL; 73 } 74 mode = USB_DR_MODE_HOST; 75 break; 76 default: 77 if (IS_ENABLED(CONFIG_USB_DWC3_HOST)) 78 mode = USB_DR_MODE_HOST; 79 else if (IS_ENABLED(CONFIG_USB_DWC3_GADGET)) 80 mode = USB_DR_MODE_PERIPHERAL; 81 82 /* 83 * DWC_usb31 and DWC_usb3 v3.30a and higher do not support OTG 84 * mode. If the controller supports DRD but the dr_mode is not 85 * specified or set to OTG, then set the mode to peripheral. 86 */ 87 if (mode == USB_DR_MODE_OTG && 88 (!IS_ENABLED(CONFIG_USB_ROLE_SWITCH) || 89 !device_property_read_bool(dwc->dev, "usb-role-switch")) && 90 !DWC3_VER_IS_PRIOR(DWC3, 330A)) 91 mode = USB_DR_MODE_PERIPHERAL; 92 } 93 94 if (mode != dwc->dr_mode) { 95 dev_warn(dev, 96 "Configuration mismatch. dr_mode forced to %s\n", 97 mode == USB_DR_MODE_HOST ? "host" : "gadget"); 98 99 dwc->dr_mode = mode; 100 } 101 102 return 0; 103 } 104 105 void dwc3_set_prtcap(struct dwc3 *dwc, u32 mode) 106 { 107 u32 reg; 108 109 reg = dwc3_readl(dwc->regs, DWC3_GCTL); 110 reg &= ~(DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_OTG)); 111 reg |= DWC3_GCTL_PRTCAPDIR(mode); 112 dwc3_writel(dwc->regs, DWC3_GCTL, reg); 113 114 dwc->current_dr_role = mode; 115 } 116 117 static void __dwc3_set_mode(struct work_struct *work) 118 { 119 struct dwc3 *dwc = work_to_dwc(work); 120 unsigned long flags; 121 int ret; 122 123 if (dwc->dr_mode != USB_DR_MODE_OTG) 124 return; 125 126 pm_runtime_get_sync(dwc->dev); 127 128 if (dwc->current_dr_role == DWC3_GCTL_PRTCAP_OTG) 129 dwc3_otg_update(dwc, 0); 130 131 if (!dwc->desired_dr_role) 132 goto out; 133 134 if (dwc->desired_dr_role == dwc->current_dr_role) 135 goto out; 136 137 if (dwc->desired_dr_role == DWC3_GCTL_PRTCAP_OTG && dwc->edev) 138 goto out; 139 140 switch (dwc->current_dr_role) { 141 case DWC3_GCTL_PRTCAP_HOST: 142 dwc3_host_exit(dwc); 143 break; 144 case DWC3_GCTL_PRTCAP_DEVICE: 145 dwc3_gadget_exit(dwc); 146 dwc3_event_buffers_cleanup(dwc); 147 break; 148 case DWC3_GCTL_PRTCAP_OTG: 149 dwc3_otg_exit(dwc); 150 spin_lock_irqsave(&dwc->lock, flags); 151 dwc->desired_otg_role = DWC3_OTG_ROLE_IDLE; 152 spin_unlock_irqrestore(&dwc->lock, flags); 153 dwc3_otg_update(dwc, 1); 154 break; 155 default: 156 break; 157 } 158 159 spin_lock_irqsave(&dwc->lock, flags); 160 161 dwc3_set_prtcap(dwc, dwc->desired_dr_role); 162 163 spin_unlock_irqrestore(&dwc->lock, flags); 164 165 switch (dwc->desired_dr_role) { 166 case DWC3_GCTL_PRTCAP_HOST: 167 ret = dwc3_host_init(dwc); 168 if (ret) { 169 dev_err(dwc->dev, "failed to initialize host\n"); 170 } else { 171 if (dwc->usb2_phy) 172 otg_set_vbus(dwc->usb2_phy->otg, true); 173 phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_HOST); 174 phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_HOST); 175 } 176 break; 177 case DWC3_GCTL_PRTCAP_DEVICE: 178 dwc3_event_buffers_setup(dwc); 179 180 if (dwc->usb2_phy) 181 otg_set_vbus(dwc->usb2_phy->otg, false); 182 phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_DEVICE); 183 phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_DEVICE); 184 185 ret = dwc3_gadget_init(dwc); 186 if (ret) 187 dev_err(dwc->dev, "failed to initialize peripheral\n"); 188 break; 189 case DWC3_GCTL_PRTCAP_OTG: 190 dwc3_otg_init(dwc); 191 dwc3_otg_update(dwc, 0); 192 break; 193 default: 194 break; 195 } 196 197 out: 198 pm_runtime_mark_last_busy(dwc->dev); 199 pm_runtime_put_autosuspend(dwc->dev); 200 } 201 202 void dwc3_set_mode(struct dwc3 *dwc, u32 mode) 203 { 204 unsigned long flags; 205 206 spin_lock_irqsave(&dwc->lock, flags); 207 dwc->desired_dr_role = mode; 208 spin_unlock_irqrestore(&dwc->lock, flags); 209 210 queue_work(system_freezable_wq, &dwc->drd_work); 211 } 212 213 u32 dwc3_core_fifo_space(struct dwc3_ep *dep, u8 type) 214 { 215 struct dwc3 *dwc = dep->dwc; 216 u32 reg; 217 218 dwc3_writel(dwc->regs, DWC3_GDBGFIFOSPACE, 219 DWC3_GDBGFIFOSPACE_NUM(dep->number) | 220 DWC3_GDBGFIFOSPACE_TYPE(type)); 221 222 reg = dwc3_readl(dwc->regs, DWC3_GDBGFIFOSPACE); 223 224 return DWC3_GDBGFIFOSPACE_SPACE_AVAILABLE(reg); 225 } 226 227 /** 228 * dwc3_core_soft_reset - Issues core soft reset and PHY reset 229 * @dwc: pointer to our context structure 230 */ 231 static int dwc3_core_soft_reset(struct dwc3 *dwc) 232 { 233 u32 reg; 234 int retries = 1000; 235 int ret; 236 237 usb_phy_init(dwc->usb2_phy); 238 usb_phy_init(dwc->usb3_phy); 239 ret = phy_init(dwc->usb2_generic_phy); 240 if (ret < 0) 241 return ret; 242 243 ret = phy_init(dwc->usb3_generic_phy); 244 if (ret < 0) { 245 phy_exit(dwc->usb2_generic_phy); 246 return ret; 247 } 248 249 /* 250 * We're resetting only the device side because, if we're in host mode, 251 * XHCI driver will reset the host block. If dwc3 was configured for 252 * host-only mode, then we can return early. 253 */ 254 if (dwc->current_dr_role == DWC3_GCTL_PRTCAP_HOST) 255 return 0; 256 257 reg = dwc3_readl(dwc->regs, DWC3_DCTL); 258 reg |= DWC3_DCTL_CSFTRST; 259 dwc3_writel(dwc->regs, DWC3_DCTL, reg); 260 261 /* 262 * For DWC_usb31 controller 1.90a and later, the DCTL.CSFRST bit 263 * is cleared only after all the clocks are synchronized. This can 264 * take a little more than 50ms. Set the polling rate at 20ms 265 * for 10 times instead. 266 */ 267 if (DWC3_VER_IS_WITHIN(DWC31, 190A, ANY) || DWC3_IP_IS(DWC32)) 268 retries = 10; 269 270 do { 271 reg = dwc3_readl(dwc->regs, DWC3_DCTL); 272 if (!(reg & DWC3_DCTL_CSFTRST)) 273 goto done; 274 275 if (DWC3_VER_IS_WITHIN(DWC31, 190A, ANY) || DWC3_IP_IS(DWC32)) 276 msleep(20); 277 else 278 udelay(1); 279 } while (--retries); 280 281 phy_exit(dwc->usb3_generic_phy); 282 phy_exit(dwc->usb2_generic_phy); 283 284 return -ETIMEDOUT; 285 286 done: 287 /* 288 * For DWC_usb31 controller 1.80a and prior, once DCTL.CSFRST bit 289 * is cleared, we must wait at least 50ms before accessing the PHY 290 * domain (synchronization delay). 291 */ 292 if (DWC3_VER_IS_WITHIN(DWC31, ANY, 180A)) 293 msleep(50); 294 295 return 0; 296 } 297 298 /* 299 * dwc3_frame_length_adjustment - Adjusts frame length if required 300 * @dwc3: Pointer to our controller context structure 301 */ 302 static void dwc3_frame_length_adjustment(struct dwc3 *dwc) 303 { 304 u32 reg; 305 u32 dft; 306 307 if (DWC3_VER_IS_PRIOR(DWC3, 250A)) 308 return; 309 310 if (dwc->fladj == 0) 311 return; 312 313 reg = dwc3_readl(dwc->regs, DWC3_GFLADJ); 314 dft = reg & DWC3_GFLADJ_30MHZ_MASK; 315 if (dft != dwc->fladj) { 316 reg &= ~DWC3_GFLADJ_30MHZ_MASK; 317 reg |= DWC3_GFLADJ_30MHZ_SDBND_SEL | dwc->fladj; 318 dwc3_writel(dwc->regs, DWC3_GFLADJ, reg); 319 } 320 } 321 322 /** 323 * dwc3_free_one_event_buffer - Frees one event buffer 324 * @dwc: Pointer to our controller context structure 325 * @evt: Pointer to event buffer to be freed 326 */ 327 static void dwc3_free_one_event_buffer(struct dwc3 *dwc, 328 struct dwc3_event_buffer *evt) 329 { 330 dma_free_coherent(dwc->sysdev, evt->length, evt->buf, evt->dma); 331 } 332 333 /** 334 * dwc3_alloc_one_event_buffer - Allocates one event buffer structure 335 * @dwc: Pointer to our controller context structure 336 * @length: size of the event buffer 337 * 338 * Returns a pointer to the allocated event buffer structure on success 339 * otherwise ERR_PTR(errno). 340 */ 341 static struct dwc3_event_buffer *dwc3_alloc_one_event_buffer(struct dwc3 *dwc, 342 unsigned length) 343 { 344 struct dwc3_event_buffer *evt; 345 346 evt = devm_kzalloc(dwc->dev, sizeof(*evt), GFP_KERNEL); 347 if (!evt) 348 return ERR_PTR(-ENOMEM); 349 350 evt->dwc = dwc; 351 evt->length = length; 352 evt->cache = devm_kzalloc(dwc->dev, length, GFP_KERNEL); 353 if (!evt->cache) 354 return ERR_PTR(-ENOMEM); 355 356 evt->buf = dma_alloc_coherent(dwc->sysdev, length, 357 &evt->dma, GFP_KERNEL); 358 if (!evt->buf) 359 return ERR_PTR(-ENOMEM); 360 361 return evt; 362 } 363 364 /** 365 * dwc3_free_event_buffers - frees all allocated event buffers 366 * @dwc: Pointer to our controller context structure 367 */ 368 static void dwc3_free_event_buffers(struct dwc3 *dwc) 369 { 370 struct dwc3_event_buffer *evt; 371 372 evt = dwc->ev_buf; 373 if (evt) 374 dwc3_free_one_event_buffer(dwc, evt); 375 } 376 377 /** 378 * dwc3_alloc_event_buffers - Allocates @num event buffers of size @length 379 * @dwc: pointer to our controller context structure 380 * @length: size of event buffer 381 * 382 * Returns 0 on success otherwise negative errno. In the error case, dwc 383 * may contain some buffers allocated but not all which were requested. 384 */ 385 static int dwc3_alloc_event_buffers(struct dwc3 *dwc, unsigned length) 386 { 387 struct dwc3_event_buffer *evt; 388 389 evt = dwc3_alloc_one_event_buffer(dwc, length); 390 if (IS_ERR(evt)) { 391 dev_err(dwc->dev, "can't allocate event buffer\n"); 392 return PTR_ERR(evt); 393 } 394 dwc->ev_buf = evt; 395 396 return 0; 397 } 398 399 /** 400 * dwc3_event_buffers_setup - setup our allocated event buffers 401 * @dwc: pointer to our controller context structure 402 * 403 * Returns 0 on success otherwise negative errno. 404 */ 405 int dwc3_event_buffers_setup(struct dwc3 *dwc) 406 { 407 struct dwc3_event_buffer *evt; 408 409 evt = dwc->ev_buf; 410 evt->lpos = 0; 411 dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(0), 412 lower_32_bits(evt->dma)); 413 dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(0), 414 upper_32_bits(evt->dma)); 415 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0), 416 DWC3_GEVNTSIZ_SIZE(evt->length)); 417 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), 0); 418 419 return 0; 420 } 421 422 void dwc3_event_buffers_cleanup(struct dwc3 *dwc) 423 { 424 struct dwc3_event_buffer *evt; 425 426 evt = dwc->ev_buf; 427 428 evt->lpos = 0; 429 430 dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(0), 0); 431 dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(0), 0); 432 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0), DWC3_GEVNTSIZ_INTMASK 433 | DWC3_GEVNTSIZ_SIZE(0)); 434 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), 0); 435 } 436 437 static int dwc3_alloc_scratch_buffers(struct dwc3 *dwc) 438 { 439 if (!dwc->has_hibernation) 440 return 0; 441 442 if (!dwc->nr_scratch) 443 return 0; 444 445 dwc->scratchbuf = kmalloc_array(dwc->nr_scratch, 446 DWC3_SCRATCHBUF_SIZE, GFP_KERNEL); 447 if (!dwc->scratchbuf) 448 return -ENOMEM; 449 450 return 0; 451 } 452 453 static int dwc3_setup_scratch_buffers(struct dwc3 *dwc) 454 { 455 dma_addr_t scratch_addr; 456 u32 param; 457 int ret; 458 459 if (!dwc->has_hibernation) 460 return 0; 461 462 if (!dwc->nr_scratch) 463 return 0; 464 465 /* should never fall here */ 466 if (!WARN_ON(dwc->scratchbuf)) 467 return 0; 468 469 scratch_addr = dma_map_single(dwc->sysdev, dwc->scratchbuf, 470 dwc->nr_scratch * DWC3_SCRATCHBUF_SIZE, 471 DMA_BIDIRECTIONAL); 472 if (dma_mapping_error(dwc->sysdev, scratch_addr)) { 473 dev_err(dwc->sysdev, "failed to map scratch buffer\n"); 474 ret = -EFAULT; 475 goto err0; 476 } 477 478 dwc->scratch_addr = scratch_addr; 479 480 param = lower_32_bits(scratch_addr); 481 482 ret = dwc3_send_gadget_generic_command(dwc, 483 DWC3_DGCMD_SET_SCRATCHPAD_ADDR_LO, param); 484 if (ret < 0) 485 goto err1; 486 487 param = upper_32_bits(scratch_addr); 488 489 ret = dwc3_send_gadget_generic_command(dwc, 490 DWC3_DGCMD_SET_SCRATCHPAD_ADDR_HI, param); 491 if (ret < 0) 492 goto err1; 493 494 return 0; 495 496 err1: 497 dma_unmap_single(dwc->sysdev, dwc->scratch_addr, dwc->nr_scratch * 498 DWC3_SCRATCHBUF_SIZE, DMA_BIDIRECTIONAL); 499 500 err0: 501 return ret; 502 } 503 504 static void dwc3_free_scratch_buffers(struct dwc3 *dwc) 505 { 506 if (!dwc->has_hibernation) 507 return; 508 509 if (!dwc->nr_scratch) 510 return; 511 512 /* should never fall here */ 513 if (!WARN_ON(dwc->scratchbuf)) 514 return; 515 516 dma_unmap_single(dwc->sysdev, dwc->scratch_addr, dwc->nr_scratch * 517 DWC3_SCRATCHBUF_SIZE, DMA_BIDIRECTIONAL); 518 kfree(dwc->scratchbuf); 519 } 520 521 static void dwc3_core_num_eps(struct dwc3 *dwc) 522 { 523 struct dwc3_hwparams *parms = &dwc->hwparams; 524 525 dwc->num_eps = DWC3_NUM_EPS(parms); 526 } 527 528 static void dwc3_cache_hwparams(struct dwc3 *dwc) 529 { 530 struct dwc3_hwparams *parms = &dwc->hwparams; 531 532 parms->hwparams0 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS0); 533 parms->hwparams1 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS1); 534 parms->hwparams2 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS2); 535 parms->hwparams3 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS3); 536 parms->hwparams4 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS4); 537 parms->hwparams5 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS5); 538 parms->hwparams6 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS6); 539 parms->hwparams7 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS7); 540 parms->hwparams8 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS8); 541 } 542 543 static int dwc3_core_ulpi_init(struct dwc3 *dwc) 544 { 545 int intf; 546 int ret = 0; 547 548 intf = DWC3_GHWPARAMS3_HSPHY_IFC(dwc->hwparams.hwparams3); 549 550 if (intf == DWC3_GHWPARAMS3_HSPHY_IFC_ULPI || 551 (intf == DWC3_GHWPARAMS3_HSPHY_IFC_UTMI_ULPI && 552 dwc->hsphy_interface && 553 !strncmp(dwc->hsphy_interface, "ulpi", 4))) 554 ret = dwc3_ulpi_init(dwc); 555 556 return ret; 557 } 558 559 /** 560 * dwc3_phy_setup - Configure USB PHY Interface of DWC3 Core 561 * @dwc: Pointer to our controller context structure 562 * 563 * Returns 0 on success. The USB PHY interfaces are configured but not 564 * initialized. The PHY interfaces and the PHYs get initialized together with 565 * the core in dwc3_core_init. 566 */ 567 static int dwc3_phy_setup(struct dwc3 *dwc) 568 { 569 unsigned int hw_mode; 570 u32 reg; 571 572 hw_mode = DWC3_GHWPARAMS0_MODE(dwc->hwparams.hwparams0); 573 574 reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0)); 575 576 /* 577 * Make sure UX_EXIT_PX is cleared as that causes issues with some 578 * PHYs. Also, this bit is not supposed to be used in normal operation. 579 */ 580 reg &= ~DWC3_GUSB3PIPECTL_UX_EXIT_PX; 581 582 /* 583 * Above 1.94a, it is recommended to set DWC3_GUSB3PIPECTL_SUSPHY 584 * to '0' during coreConsultant configuration. So default value 585 * will be '0' when the core is reset. Application needs to set it 586 * to '1' after the core initialization is completed. 587 */ 588 if (!DWC3_VER_IS_WITHIN(DWC3, ANY, 194A)) 589 reg |= DWC3_GUSB3PIPECTL_SUSPHY; 590 591 /* 592 * For DRD controllers, GUSB3PIPECTL.SUSPENDENABLE must be cleared after 593 * power-on reset, and it can be set after core initialization, which is 594 * after device soft-reset during initialization. 595 */ 596 if (hw_mode == DWC3_GHWPARAMS0_MODE_DRD) 597 reg &= ~DWC3_GUSB3PIPECTL_SUSPHY; 598 599 if (dwc->u2ss_inp3_quirk) 600 reg |= DWC3_GUSB3PIPECTL_U2SSINP3OK; 601 602 if (dwc->dis_rxdet_inp3_quirk) 603 reg |= DWC3_GUSB3PIPECTL_DISRXDETINP3; 604 605 if (dwc->req_p1p2p3_quirk) 606 reg |= DWC3_GUSB3PIPECTL_REQP1P2P3; 607 608 if (dwc->del_p1p2p3_quirk) 609 reg |= DWC3_GUSB3PIPECTL_DEP1P2P3_EN; 610 611 if (dwc->del_phy_power_chg_quirk) 612 reg |= DWC3_GUSB3PIPECTL_DEPOCHANGE; 613 614 if (dwc->lfps_filter_quirk) 615 reg |= DWC3_GUSB3PIPECTL_LFPSFILT; 616 617 if (dwc->rx_detect_poll_quirk) 618 reg |= DWC3_GUSB3PIPECTL_RX_DETOPOLL; 619 620 if (dwc->tx_de_emphasis_quirk) 621 reg |= DWC3_GUSB3PIPECTL_TX_DEEPH(dwc->tx_de_emphasis); 622 623 if (dwc->dis_u3_susphy_quirk) 624 reg &= ~DWC3_GUSB3PIPECTL_SUSPHY; 625 626 if (dwc->dis_del_phy_power_chg_quirk) 627 reg &= ~DWC3_GUSB3PIPECTL_DEPOCHANGE; 628 629 dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg); 630 631 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0)); 632 633 /* Select the HS PHY interface */ 634 switch (DWC3_GHWPARAMS3_HSPHY_IFC(dwc->hwparams.hwparams3)) { 635 case DWC3_GHWPARAMS3_HSPHY_IFC_UTMI_ULPI: 636 if (dwc->hsphy_interface && 637 !strncmp(dwc->hsphy_interface, "utmi", 4)) { 638 reg &= ~DWC3_GUSB2PHYCFG_ULPI_UTMI; 639 break; 640 } else if (dwc->hsphy_interface && 641 !strncmp(dwc->hsphy_interface, "ulpi", 4)) { 642 reg |= DWC3_GUSB2PHYCFG_ULPI_UTMI; 643 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg); 644 } else { 645 /* Relying on default value. */ 646 if (!(reg & DWC3_GUSB2PHYCFG_ULPI_UTMI)) 647 break; 648 } 649 /* FALLTHROUGH */ 650 case DWC3_GHWPARAMS3_HSPHY_IFC_ULPI: 651 /* FALLTHROUGH */ 652 default: 653 break; 654 } 655 656 switch (dwc->hsphy_mode) { 657 case USBPHY_INTERFACE_MODE_UTMI: 658 reg &= ~(DWC3_GUSB2PHYCFG_PHYIF_MASK | 659 DWC3_GUSB2PHYCFG_USBTRDTIM_MASK); 660 reg |= DWC3_GUSB2PHYCFG_PHYIF(UTMI_PHYIF_8_BIT) | 661 DWC3_GUSB2PHYCFG_USBTRDTIM(USBTRDTIM_UTMI_8_BIT); 662 break; 663 case USBPHY_INTERFACE_MODE_UTMIW: 664 reg &= ~(DWC3_GUSB2PHYCFG_PHYIF_MASK | 665 DWC3_GUSB2PHYCFG_USBTRDTIM_MASK); 666 reg |= DWC3_GUSB2PHYCFG_PHYIF(UTMI_PHYIF_16_BIT) | 667 DWC3_GUSB2PHYCFG_USBTRDTIM(USBTRDTIM_UTMI_16_BIT); 668 break; 669 default: 670 break; 671 } 672 673 /* 674 * Above 1.94a, it is recommended to set DWC3_GUSB2PHYCFG_SUSPHY to 675 * '0' during coreConsultant configuration. So default value will 676 * be '0' when the core is reset. Application needs to set it to 677 * '1' after the core initialization is completed. 678 */ 679 if (!DWC3_VER_IS_WITHIN(DWC3, ANY, 194A)) 680 reg |= DWC3_GUSB2PHYCFG_SUSPHY; 681 682 /* 683 * For DRD controllers, GUSB2PHYCFG.SUSPHY must be cleared after 684 * power-on reset, and it can be set after core initialization, which is 685 * after device soft-reset during initialization. 686 */ 687 if (hw_mode == DWC3_GHWPARAMS0_MODE_DRD) 688 reg &= ~DWC3_GUSB2PHYCFG_SUSPHY; 689 690 if (dwc->dis_u2_susphy_quirk) 691 reg &= ~DWC3_GUSB2PHYCFG_SUSPHY; 692 693 if (dwc->dis_enblslpm_quirk) 694 reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM; 695 else 696 reg |= DWC3_GUSB2PHYCFG_ENBLSLPM; 697 698 if (dwc->dis_u2_freeclk_exists_quirk) 699 reg &= ~DWC3_GUSB2PHYCFG_U2_FREECLK_EXISTS; 700 701 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg); 702 703 return 0; 704 } 705 706 static void dwc3_core_exit(struct dwc3 *dwc) 707 { 708 dwc3_event_buffers_cleanup(dwc); 709 710 usb_phy_shutdown(dwc->usb2_phy); 711 usb_phy_shutdown(dwc->usb3_phy); 712 phy_exit(dwc->usb2_generic_phy); 713 phy_exit(dwc->usb3_generic_phy); 714 715 usb_phy_set_suspend(dwc->usb2_phy, 1); 716 usb_phy_set_suspend(dwc->usb3_phy, 1); 717 phy_power_off(dwc->usb2_generic_phy); 718 phy_power_off(dwc->usb3_generic_phy); 719 clk_bulk_disable_unprepare(dwc->num_clks, dwc->clks); 720 reset_control_assert(dwc->reset); 721 } 722 723 static bool dwc3_core_is_valid(struct dwc3 *dwc) 724 { 725 u32 reg; 726 727 reg = dwc3_readl(dwc->regs, DWC3_GSNPSID); 728 dwc->ip = DWC3_GSNPS_ID(reg); 729 730 /* This should read as U3 followed by revision number */ 731 if (DWC3_IP_IS(DWC3)) { 732 dwc->revision = reg; 733 } else if (DWC3_IP_IS(DWC31) || DWC3_IP_IS(DWC32)) { 734 dwc->revision = dwc3_readl(dwc->regs, DWC3_VER_NUMBER); 735 dwc->version_type = dwc3_readl(dwc->regs, DWC3_VER_TYPE); 736 } else { 737 return false; 738 } 739 740 return true; 741 } 742 743 static void dwc3_core_setup_global_control(struct dwc3 *dwc) 744 { 745 u32 hwparams4 = dwc->hwparams.hwparams4; 746 u32 reg; 747 748 reg = dwc3_readl(dwc->regs, DWC3_GCTL); 749 reg &= ~DWC3_GCTL_SCALEDOWN_MASK; 750 751 switch (DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1)) { 752 case DWC3_GHWPARAMS1_EN_PWROPT_CLK: 753 /** 754 * WORKAROUND: DWC3 revisions between 2.10a and 2.50a have an 755 * issue which would cause xHCI compliance tests to fail. 756 * 757 * Because of that we cannot enable clock gating on such 758 * configurations. 759 * 760 * Refers to: 761 * 762 * STAR#9000588375: Clock Gating, SOF Issues when ref_clk-Based 763 * SOF/ITP Mode Used 764 */ 765 if ((dwc->dr_mode == USB_DR_MODE_HOST || 766 dwc->dr_mode == USB_DR_MODE_OTG) && 767 DWC3_VER_IS_WITHIN(DWC3, 210A, 250A)) 768 reg |= DWC3_GCTL_DSBLCLKGTNG | DWC3_GCTL_SOFITPSYNC; 769 else 770 reg &= ~DWC3_GCTL_DSBLCLKGTNG; 771 break; 772 case DWC3_GHWPARAMS1_EN_PWROPT_HIB: 773 /* enable hibernation here */ 774 dwc->nr_scratch = DWC3_GHWPARAMS4_HIBER_SCRATCHBUFS(hwparams4); 775 776 /* 777 * REVISIT Enabling this bit so that host-mode hibernation 778 * will work. Device-mode hibernation is not yet implemented. 779 */ 780 reg |= DWC3_GCTL_GBLHIBERNATIONEN; 781 break; 782 default: 783 /* nothing */ 784 break; 785 } 786 787 /* check if current dwc3 is on simulation board */ 788 if (dwc->hwparams.hwparams6 & DWC3_GHWPARAMS6_EN_FPGA) { 789 dev_info(dwc->dev, "Running with FPGA optimizations\n"); 790 dwc->is_fpga = true; 791 } 792 793 WARN_ONCE(dwc->disable_scramble_quirk && !dwc->is_fpga, 794 "disable_scramble cannot be used on non-FPGA builds\n"); 795 796 if (dwc->disable_scramble_quirk && dwc->is_fpga) 797 reg |= DWC3_GCTL_DISSCRAMBLE; 798 else 799 reg &= ~DWC3_GCTL_DISSCRAMBLE; 800 801 if (dwc->u2exit_lfps_quirk) 802 reg |= DWC3_GCTL_U2EXIT_LFPS; 803 804 /* 805 * WORKAROUND: DWC3 revisions <1.90a have a bug 806 * where the device can fail to connect at SuperSpeed 807 * and falls back to high-speed mode which causes 808 * the device to enter a Connect/Disconnect loop 809 */ 810 if (DWC3_VER_IS_PRIOR(DWC3, 190A)) 811 reg |= DWC3_GCTL_U2RSTECN; 812 813 dwc3_writel(dwc->regs, DWC3_GCTL, reg); 814 } 815 816 static int dwc3_core_get_phy(struct dwc3 *dwc); 817 static int dwc3_core_ulpi_init(struct dwc3 *dwc); 818 819 /* set global incr burst type configuration registers */ 820 static void dwc3_set_incr_burst_type(struct dwc3 *dwc) 821 { 822 struct device *dev = dwc->dev; 823 /* incrx_mode : for INCR burst type. */ 824 bool incrx_mode; 825 /* incrx_size : for size of INCRX burst. */ 826 u32 incrx_size; 827 u32 *vals; 828 u32 cfg; 829 int ntype; 830 int ret; 831 int i; 832 833 cfg = dwc3_readl(dwc->regs, DWC3_GSBUSCFG0); 834 835 /* 836 * Handle property "snps,incr-burst-type-adjustment". 837 * Get the number of value from this property: 838 * result <= 0, means this property is not supported. 839 * result = 1, means INCRx burst mode supported. 840 * result > 1, means undefined length burst mode supported. 841 */ 842 ntype = device_property_count_u32(dev, "snps,incr-burst-type-adjustment"); 843 if (ntype <= 0) 844 return; 845 846 vals = kcalloc(ntype, sizeof(u32), GFP_KERNEL); 847 if (!vals) { 848 dev_err(dev, "Error to get memory\n"); 849 return; 850 } 851 852 /* Get INCR burst type, and parse it */ 853 ret = device_property_read_u32_array(dev, 854 "snps,incr-burst-type-adjustment", vals, ntype); 855 if (ret) { 856 kfree(vals); 857 dev_err(dev, "Error to get property\n"); 858 return; 859 } 860 861 incrx_size = *vals; 862 863 if (ntype > 1) { 864 /* INCRX (undefined length) burst mode */ 865 incrx_mode = INCRX_UNDEF_LENGTH_BURST_MODE; 866 for (i = 1; i < ntype; i++) { 867 if (vals[i] > incrx_size) 868 incrx_size = vals[i]; 869 } 870 } else { 871 /* INCRX burst mode */ 872 incrx_mode = INCRX_BURST_MODE; 873 } 874 875 kfree(vals); 876 877 /* Enable Undefined Length INCR Burst and Enable INCRx Burst */ 878 cfg &= ~DWC3_GSBUSCFG0_INCRBRST_MASK; 879 if (incrx_mode) 880 cfg |= DWC3_GSBUSCFG0_INCRBRSTENA; 881 switch (incrx_size) { 882 case 256: 883 cfg |= DWC3_GSBUSCFG0_INCR256BRSTENA; 884 break; 885 case 128: 886 cfg |= DWC3_GSBUSCFG0_INCR128BRSTENA; 887 break; 888 case 64: 889 cfg |= DWC3_GSBUSCFG0_INCR64BRSTENA; 890 break; 891 case 32: 892 cfg |= DWC3_GSBUSCFG0_INCR32BRSTENA; 893 break; 894 case 16: 895 cfg |= DWC3_GSBUSCFG0_INCR16BRSTENA; 896 break; 897 case 8: 898 cfg |= DWC3_GSBUSCFG0_INCR8BRSTENA; 899 break; 900 case 4: 901 cfg |= DWC3_GSBUSCFG0_INCR4BRSTENA; 902 break; 903 case 1: 904 break; 905 default: 906 dev_err(dev, "Invalid property\n"); 907 break; 908 } 909 910 dwc3_writel(dwc->regs, DWC3_GSBUSCFG0, cfg); 911 } 912 913 /** 914 * dwc3_core_init - Low-level initialization of DWC3 Core 915 * @dwc: Pointer to our controller context structure 916 * 917 * Returns 0 on success otherwise negative errno. 918 */ 919 static int dwc3_core_init(struct dwc3 *dwc) 920 { 921 unsigned int hw_mode; 922 u32 reg; 923 int ret; 924 925 hw_mode = DWC3_GHWPARAMS0_MODE(dwc->hwparams.hwparams0); 926 927 /* 928 * Write Linux Version Code to our GUID register so it's easy to figure 929 * out which kernel version a bug was found. 930 */ 931 dwc3_writel(dwc->regs, DWC3_GUID, LINUX_VERSION_CODE); 932 933 /* Handle USB2.0-only core configuration */ 934 if (DWC3_GHWPARAMS3_SSPHY_IFC(dwc->hwparams.hwparams3) == 935 DWC3_GHWPARAMS3_SSPHY_IFC_DIS) { 936 if (dwc->maximum_speed == USB_SPEED_SUPER) 937 dwc->maximum_speed = USB_SPEED_HIGH; 938 } 939 940 ret = dwc3_phy_setup(dwc); 941 if (ret) 942 goto err0; 943 944 if (!dwc->ulpi_ready) { 945 ret = dwc3_core_ulpi_init(dwc); 946 if (ret) 947 goto err0; 948 dwc->ulpi_ready = true; 949 } 950 951 if (!dwc->phys_ready) { 952 ret = dwc3_core_get_phy(dwc); 953 if (ret) 954 goto err0a; 955 dwc->phys_ready = true; 956 } 957 958 ret = dwc3_core_soft_reset(dwc); 959 if (ret) 960 goto err0a; 961 962 if (hw_mode == DWC3_GHWPARAMS0_MODE_DRD && 963 !DWC3_VER_IS_WITHIN(DWC3, ANY, 194A)) { 964 if (!dwc->dis_u3_susphy_quirk) { 965 reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0)); 966 reg |= DWC3_GUSB3PIPECTL_SUSPHY; 967 dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg); 968 } 969 970 if (!dwc->dis_u2_susphy_quirk) { 971 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0)); 972 reg |= DWC3_GUSB2PHYCFG_SUSPHY; 973 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg); 974 } 975 } 976 977 dwc3_core_setup_global_control(dwc); 978 dwc3_core_num_eps(dwc); 979 980 ret = dwc3_setup_scratch_buffers(dwc); 981 if (ret) 982 goto err1; 983 984 /* Adjust Frame Length */ 985 dwc3_frame_length_adjustment(dwc); 986 987 dwc3_set_incr_burst_type(dwc); 988 989 usb_phy_set_suspend(dwc->usb2_phy, 0); 990 usb_phy_set_suspend(dwc->usb3_phy, 0); 991 ret = phy_power_on(dwc->usb2_generic_phy); 992 if (ret < 0) 993 goto err2; 994 995 ret = phy_power_on(dwc->usb3_generic_phy); 996 if (ret < 0) 997 goto err3; 998 999 ret = dwc3_event_buffers_setup(dwc); 1000 if (ret) { 1001 dev_err(dwc->dev, "failed to setup event buffers\n"); 1002 goto err4; 1003 } 1004 1005 /* 1006 * ENDXFER polling is available on version 3.10a and later of 1007 * the DWC_usb3 controller. It is NOT available in the 1008 * DWC_usb31 controller. 1009 */ 1010 if (DWC3_VER_IS_WITHIN(DWC3, 310A, ANY)) { 1011 reg = dwc3_readl(dwc->regs, DWC3_GUCTL2); 1012 reg |= DWC3_GUCTL2_RST_ACTBITLATER; 1013 dwc3_writel(dwc->regs, DWC3_GUCTL2, reg); 1014 } 1015 1016 if (!DWC3_VER_IS_PRIOR(DWC3, 250A)) { 1017 reg = dwc3_readl(dwc->regs, DWC3_GUCTL1); 1018 1019 /* 1020 * Enable hardware control of sending remote wakeup 1021 * in HS when the device is in the L1 state. 1022 */ 1023 if (!DWC3_VER_IS_PRIOR(DWC3, 290A)) 1024 reg |= DWC3_GUCTL1_DEV_L1_EXIT_BY_HW; 1025 1026 if (dwc->dis_tx_ipgap_linecheck_quirk) 1027 reg |= DWC3_GUCTL1_TX_IPGAP_LINECHECK_DIS; 1028 1029 if (dwc->parkmode_disable_ss_quirk) 1030 reg |= DWC3_GUCTL1_PARKMODE_DISABLE_SS; 1031 1032 dwc3_writel(dwc->regs, DWC3_GUCTL1, reg); 1033 } 1034 1035 if (dwc->dr_mode == USB_DR_MODE_HOST || 1036 dwc->dr_mode == USB_DR_MODE_OTG) { 1037 reg = dwc3_readl(dwc->regs, DWC3_GUCTL); 1038 1039 /* 1040 * Enable Auto retry Feature to make the controller operating in 1041 * Host mode on seeing transaction errors(CRC errors or internal 1042 * overrun scenerios) on IN transfers to reply to the device 1043 * with a non-terminating retry ACK (i.e, an ACK transcation 1044 * packet with Retry=1 & Nump != 0) 1045 */ 1046 reg |= DWC3_GUCTL_HSTINAUTORETRY; 1047 1048 dwc3_writel(dwc->regs, DWC3_GUCTL, reg); 1049 } 1050 1051 /* 1052 * Must config both number of packets and max burst settings to enable 1053 * RX and/or TX threshold. 1054 */ 1055 if (!DWC3_IP_IS(DWC3) && dwc->dr_mode == USB_DR_MODE_HOST) { 1056 u8 rx_thr_num = dwc->rx_thr_num_pkt_prd; 1057 u8 rx_maxburst = dwc->rx_max_burst_prd; 1058 u8 tx_thr_num = dwc->tx_thr_num_pkt_prd; 1059 u8 tx_maxburst = dwc->tx_max_burst_prd; 1060 1061 if (rx_thr_num && rx_maxburst) { 1062 reg = dwc3_readl(dwc->regs, DWC3_GRXTHRCFG); 1063 reg |= DWC31_RXTHRNUMPKTSEL_PRD; 1064 1065 reg &= ~DWC31_RXTHRNUMPKT_PRD(~0); 1066 reg |= DWC31_RXTHRNUMPKT_PRD(rx_thr_num); 1067 1068 reg &= ~DWC31_MAXRXBURSTSIZE_PRD(~0); 1069 reg |= DWC31_MAXRXBURSTSIZE_PRD(rx_maxburst); 1070 1071 dwc3_writel(dwc->regs, DWC3_GRXTHRCFG, reg); 1072 } 1073 1074 if (tx_thr_num && tx_maxburst) { 1075 reg = dwc3_readl(dwc->regs, DWC3_GTXTHRCFG); 1076 reg |= DWC31_TXTHRNUMPKTSEL_PRD; 1077 1078 reg &= ~DWC31_TXTHRNUMPKT_PRD(~0); 1079 reg |= DWC31_TXTHRNUMPKT_PRD(tx_thr_num); 1080 1081 reg &= ~DWC31_MAXTXBURSTSIZE_PRD(~0); 1082 reg |= DWC31_MAXTXBURSTSIZE_PRD(tx_maxburst); 1083 1084 dwc3_writel(dwc->regs, DWC3_GTXTHRCFG, reg); 1085 } 1086 } 1087 1088 return 0; 1089 1090 err4: 1091 phy_power_off(dwc->usb3_generic_phy); 1092 1093 err3: 1094 phy_power_off(dwc->usb2_generic_phy); 1095 1096 err2: 1097 usb_phy_set_suspend(dwc->usb2_phy, 1); 1098 usb_phy_set_suspend(dwc->usb3_phy, 1); 1099 1100 err1: 1101 usb_phy_shutdown(dwc->usb2_phy); 1102 usb_phy_shutdown(dwc->usb3_phy); 1103 phy_exit(dwc->usb2_generic_phy); 1104 phy_exit(dwc->usb3_generic_phy); 1105 1106 err0a: 1107 dwc3_ulpi_exit(dwc); 1108 1109 err0: 1110 return ret; 1111 } 1112 1113 static int dwc3_core_get_phy(struct dwc3 *dwc) 1114 { 1115 struct device *dev = dwc->dev; 1116 struct device_node *node = dev->of_node; 1117 int ret; 1118 1119 if (node) { 1120 dwc->usb2_phy = devm_usb_get_phy_by_phandle(dev, "usb-phy", 0); 1121 dwc->usb3_phy = devm_usb_get_phy_by_phandle(dev, "usb-phy", 1); 1122 } else { 1123 dwc->usb2_phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB2); 1124 dwc->usb3_phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB3); 1125 } 1126 1127 if (IS_ERR(dwc->usb2_phy)) { 1128 ret = PTR_ERR(dwc->usb2_phy); 1129 if (ret == -ENXIO || ret == -ENODEV) { 1130 dwc->usb2_phy = NULL; 1131 } else if (ret == -EPROBE_DEFER) { 1132 return ret; 1133 } else { 1134 dev_err(dev, "no usb2 phy configured\n"); 1135 return ret; 1136 } 1137 } 1138 1139 if (IS_ERR(dwc->usb3_phy)) { 1140 ret = PTR_ERR(dwc->usb3_phy); 1141 if (ret == -ENXIO || ret == -ENODEV) { 1142 dwc->usb3_phy = NULL; 1143 } else if (ret == -EPROBE_DEFER) { 1144 return ret; 1145 } else { 1146 dev_err(dev, "no usb3 phy configured\n"); 1147 return ret; 1148 } 1149 } 1150 1151 dwc->usb2_generic_phy = devm_phy_get(dev, "usb2-phy"); 1152 if (IS_ERR(dwc->usb2_generic_phy)) { 1153 ret = PTR_ERR(dwc->usb2_generic_phy); 1154 if (ret == -ENOSYS || ret == -ENODEV) { 1155 dwc->usb2_generic_phy = NULL; 1156 } else if (ret == -EPROBE_DEFER) { 1157 return ret; 1158 } else { 1159 dev_err(dev, "no usb2 phy configured\n"); 1160 return ret; 1161 } 1162 } 1163 1164 dwc->usb3_generic_phy = devm_phy_get(dev, "usb3-phy"); 1165 if (IS_ERR(dwc->usb3_generic_phy)) { 1166 ret = PTR_ERR(dwc->usb3_generic_phy); 1167 if (ret == -ENOSYS || ret == -ENODEV) { 1168 dwc->usb3_generic_phy = NULL; 1169 } else if (ret == -EPROBE_DEFER) { 1170 return ret; 1171 } else { 1172 dev_err(dev, "no usb3 phy configured\n"); 1173 return ret; 1174 } 1175 } 1176 1177 return 0; 1178 } 1179 1180 static int dwc3_core_init_mode(struct dwc3 *dwc) 1181 { 1182 struct device *dev = dwc->dev; 1183 int ret; 1184 1185 switch (dwc->dr_mode) { 1186 case USB_DR_MODE_PERIPHERAL: 1187 dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_DEVICE); 1188 1189 if (dwc->usb2_phy) 1190 otg_set_vbus(dwc->usb2_phy->otg, false); 1191 phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_DEVICE); 1192 phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_DEVICE); 1193 1194 ret = dwc3_gadget_init(dwc); 1195 if (ret) { 1196 if (ret != -EPROBE_DEFER) 1197 dev_err(dev, "failed to initialize gadget\n"); 1198 return ret; 1199 } 1200 break; 1201 case USB_DR_MODE_HOST: 1202 dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_HOST); 1203 1204 if (dwc->usb2_phy) 1205 otg_set_vbus(dwc->usb2_phy->otg, true); 1206 phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_HOST); 1207 phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_HOST); 1208 1209 ret = dwc3_host_init(dwc); 1210 if (ret) { 1211 if (ret != -EPROBE_DEFER) 1212 dev_err(dev, "failed to initialize host\n"); 1213 return ret; 1214 } 1215 break; 1216 case USB_DR_MODE_OTG: 1217 INIT_WORK(&dwc->drd_work, __dwc3_set_mode); 1218 ret = dwc3_drd_init(dwc); 1219 if (ret) { 1220 if (ret != -EPROBE_DEFER) 1221 dev_err(dev, "failed to initialize dual-role\n"); 1222 return ret; 1223 } 1224 break; 1225 default: 1226 dev_err(dev, "Unsupported mode of operation %d\n", dwc->dr_mode); 1227 return -EINVAL; 1228 } 1229 1230 return 0; 1231 } 1232 1233 static void dwc3_core_exit_mode(struct dwc3 *dwc) 1234 { 1235 switch (dwc->dr_mode) { 1236 case USB_DR_MODE_PERIPHERAL: 1237 dwc3_gadget_exit(dwc); 1238 break; 1239 case USB_DR_MODE_HOST: 1240 dwc3_host_exit(dwc); 1241 break; 1242 case USB_DR_MODE_OTG: 1243 dwc3_drd_exit(dwc); 1244 break; 1245 default: 1246 /* do nothing */ 1247 break; 1248 } 1249 1250 /* de-assert DRVVBUS for HOST and OTG mode */ 1251 dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_DEVICE); 1252 } 1253 1254 static void dwc3_get_properties(struct dwc3 *dwc) 1255 { 1256 struct device *dev = dwc->dev; 1257 u8 lpm_nyet_threshold; 1258 u8 tx_de_emphasis; 1259 u8 hird_threshold; 1260 u8 rx_thr_num_pkt_prd; 1261 u8 rx_max_burst_prd; 1262 u8 tx_thr_num_pkt_prd; 1263 u8 tx_max_burst_prd; 1264 1265 /* default to highest possible threshold */ 1266 lpm_nyet_threshold = 0xf; 1267 1268 /* default to -3.5dB de-emphasis */ 1269 tx_de_emphasis = 1; 1270 1271 /* 1272 * default to assert utmi_sleep_n and use maximum allowed HIRD 1273 * threshold value of 0b1100 1274 */ 1275 hird_threshold = 12; 1276 1277 dwc->maximum_speed = usb_get_maximum_speed(dev); 1278 dwc->dr_mode = usb_get_dr_mode(dev); 1279 dwc->hsphy_mode = of_usb_get_phy_mode(dev->of_node); 1280 1281 dwc->sysdev_is_parent = device_property_read_bool(dev, 1282 "linux,sysdev_is_parent"); 1283 if (dwc->sysdev_is_parent) 1284 dwc->sysdev = dwc->dev->parent; 1285 else 1286 dwc->sysdev = dwc->dev; 1287 1288 dwc->has_lpm_erratum = device_property_read_bool(dev, 1289 "snps,has-lpm-erratum"); 1290 device_property_read_u8(dev, "snps,lpm-nyet-threshold", 1291 &lpm_nyet_threshold); 1292 dwc->is_utmi_l1_suspend = device_property_read_bool(dev, 1293 "snps,is-utmi-l1-suspend"); 1294 device_property_read_u8(dev, "snps,hird-threshold", 1295 &hird_threshold); 1296 dwc->dis_start_transfer_quirk = device_property_read_bool(dev, 1297 "snps,dis-start-transfer-quirk"); 1298 dwc->usb3_lpm_capable = device_property_read_bool(dev, 1299 "snps,usb3_lpm_capable"); 1300 dwc->usb2_lpm_disable = device_property_read_bool(dev, 1301 "snps,usb2-lpm-disable"); 1302 device_property_read_u8(dev, "snps,rx-thr-num-pkt-prd", 1303 &rx_thr_num_pkt_prd); 1304 device_property_read_u8(dev, "snps,rx-max-burst-prd", 1305 &rx_max_burst_prd); 1306 device_property_read_u8(dev, "snps,tx-thr-num-pkt-prd", 1307 &tx_thr_num_pkt_prd); 1308 device_property_read_u8(dev, "snps,tx-max-burst-prd", 1309 &tx_max_burst_prd); 1310 1311 dwc->disable_scramble_quirk = device_property_read_bool(dev, 1312 "snps,disable_scramble_quirk"); 1313 dwc->u2exit_lfps_quirk = device_property_read_bool(dev, 1314 "snps,u2exit_lfps_quirk"); 1315 dwc->u2ss_inp3_quirk = device_property_read_bool(dev, 1316 "snps,u2ss_inp3_quirk"); 1317 dwc->req_p1p2p3_quirk = device_property_read_bool(dev, 1318 "snps,req_p1p2p3_quirk"); 1319 dwc->del_p1p2p3_quirk = device_property_read_bool(dev, 1320 "snps,del_p1p2p3_quirk"); 1321 dwc->del_phy_power_chg_quirk = device_property_read_bool(dev, 1322 "snps,del_phy_power_chg_quirk"); 1323 dwc->lfps_filter_quirk = device_property_read_bool(dev, 1324 "snps,lfps_filter_quirk"); 1325 dwc->rx_detect_poll_quirk = device_property_read_bool(dev, 1326 "snps,rx_detect_poll_quirk"); 1327 dwc->dis_u3_susphy_quirk = device_property_read_bool(dev, 1328 "snps,dis_u3_susphy_quirk"); 1329 dwc->dis_u2_susphy_quirk = device_property_read_bool(dev, 1330 "snps,dis_u2_susphy_quirk"); 1331 dwc->dis_enblslpm_quirk = device_property_read_bool(dev, 1332 "snps,dis_enblslpm_quirk"); 1333 dwc->dis_u1_entry_quirk = device_property_read_bool(dev, 1334 "snps,dis-u1-entry-quirk"); 1335 dwc->dis_u2_entry_quirk = device_property_read_bool(dev, 1336 "snps,dis-u2-entry-quirk"); 1337 dwc->dis_rxdet_inp3_quirk = device_property_read_bool(dev, 1338 "snps,dis_rxdet_inp3_quirk"); 1339 dwc->dis_u2_freeclk_exists_quirk = device_property_read_bool(dev, 1340 "snps,dis-u2-freeclk-exists-quirk"); 1341 dwc->dis_del_phy_power_chg_quirk = device_property_read_bool(dev, 1342 "snps,dis-del-phy-power-chg-quirk"); 1343 dwc->dis_tx_ipgap_linecheck_quirk = device_property_read_bool(dev, 1344 "snps,dis-tx-ipgap-linecheck-quirk"); 1345 dwc->parkmode_disable_ss_quirk = device_property_read_bool(dev, 1346 "snps,parkmode-disable-ss-quirk"); 1347 1348 dwc->tx_de_emphasis_quirk = device_property_read_bool(dev, 1349 "snps,tx_de_emphasis_quirk"); 1350 device_property_read_u8(dev, "snps,tx_de_emphasis", 1351 &tx_de_emphasis); 1352 device_property_read_string(dev, "snps,hsphy_interface", 1353 &dwc->hsphy_interface); 1354 device_property_read_u32(dev, "snps,quirk-frame-length-adjustment", 1355 &dwc->fladj); 1356 1357 dwc->dis_metastability_quirk = device_property_read_bool(dev, 1358 "snps,dis_metastability_quirk"); 1359 1360 dwc->lpm_nyet_threshold = lpm_nyet_threshold; 1361 dwc->tx_de_emphasis = tx_de_emphasis; 1362 1363 dwc->hird_threshold = hird_threshold; 1364 1365 dwc->rx_thr_num_pkt_prd = rx_thr_num_pkt_prd; 1366 dwc->rx_max_burst_prd = rx_max_burst_prd; 1367 1368 dwc->tx_thr_num_pkt_prd = tx_thr_num_pkt_prd; 1369 dwc->tx_max_burst_prd = tx_max_burst_prd; 1370 1371 dwc->imod_interval = 0; 1372 } 1373 1374 /* check whether the core supports IMOD */ 1375 bool dwc3_has_imod(struct dwc3 *dwc) 1376 { 1377 return DWC3_VER_IS_WITHIN(DWC3, 300A, ANY) || 1378 DWC3_VER_IS_WITHIN(DWC31, 120A, ANY) || 1379 DWC3_IP_IS(DWC32); 1380 } 1381 1382 static void dwc3_check_params(struct dwc3 *dwc) 1383 { 1384 struct device *dev = dwc->dev; 1385 1386 /* Check for proper value of imod_interval */ 1387 if (dwc->imod_interval && !dwc3_has_imod(dwc)) { 1388 dev_warn(dwc->dev, "Interrupt moderation not supported\n"); 1389 dwc->imod_interval = 0; 1390 } 1391 1392 /* 1393 * Workaround for STAR 9000961433 which affects only version 1394 * 3.00a of the DWC_usb3 core. This prevents the controller 1395 * interrupt from being masked while handling events. IMOD 1396 * allows us to work around this issue. Enable it for the 1397 * affected version. 1398 */ 1399 if (!dwc->imod_interval && 1400 DWC3_VER_IS(DWC3, 300A)) 1401 dwc->imod_interval = 1; 1402 1403 /* Check the maximum_speed parameter */ 1404 switch (dwc->maximum_speed) { 1405 case USB_SPEED_LOW: 1406 case USB_SPEED_FULL: 1407 case USB_SPEED_HIGH: 1408 case USB_SPEED_SUPER: 1409 case USB_SPEED_SUPER_PLUS: 1410 break; 1411 default: 1412 dev_err(dev, "invalid maximum_speed parameter %d\n", 1413 dwc->maximum_speed); 1414 /* fall through */ 1415 case USB_SPEED_UNKNOWN: 1416 /* default to superspeed */ 1417 dwc->maximum_speed = USB_SPEED_SUPER; 1418 1419 /* 1420 * default to superspeed plus if we are capable. 1421 */ 1422 if ((DWC3_IP_IS(DWC31) || DWC3_IP_IS(DWC32)) && 1423 (DWC3_GHWPARAMS3_SSPHY_IFC(dwc->hwparams.hwparams3) == 1424 DWC3_GHWPARAMS3_SSPHY_IFC_GEN2)) 1425 dwc->maximum_speed = USB_SPEED_SUPER_PLUS; 1426 1427 break; 1428 } 1429 } 1430 1431 static int dwc3_probe(struct platform_device *pdev) 1432 { 1433 struct device *dev = &pdev->dev; 1434 struct resource *res, dwc_res; 1435 struct dwc3 *dwc; 1436 1437 int ret; 1438 1439 void __iomem *regs; 1440 1441 dwc = devm_kzalloc(dev, sizeof(*dwc), GFP_KERNEL); 1442 if (!dwc) 1443 return -ENOMEM; 1444 1445 dwc->dev = dev; 1446 1447 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1448 if (!res) { 1449 dev_err(dev, "missing memory resource\n"); 1450 return -ENODEV; 1451 } 1452 1453 dwc->xhci_resources[0].start = res->start; 1454 dwc->xhci_resources[0].end = dwc->xhci_resources[0].start + 1455 DWC3_XHCI_REGS_END; 1456 dwc->xhci_resources[0].flags = res->flags; 1457 dwc->xhci_resources[0].name = res->name; 1458 1459 /* 1460 * Request memory region but exclude xHCI regs, 1461 * since it will be requested by the xhci-plat driver. 1462 */ 1463 dwc_res = *res; 1464 dwc_res.start += DWC3_GLOBALS_REGS_START; 1465 1466 regs = devm_ioremap_resource(dev, &dwc_res); 1467 if (IS_ERR(regs)) 1468 return PTR_ERR(regs); 1469 1470 dwc->regs = regs; 1471 dwc->regs_size = resource_size(&dwc_res); 1472 1473 dwc3_get_properties(dwc); 1474 1475 dwc->reset = devm_reset_control_array_get(dev, true, true); 1476 if (IS_ERR(dwc->reset)) 1477 return PTR_ERR(dwc->reset); 1478 1479 if (dev->of_node) { 1480 ret = devm_clk_bulk_get_all(dev, &dwc->clks); 1481 if (ret == -EPROBE_DEFER) 1482 return ret; 1483 /* 1484 * Clocks are optional, but new DT platforms should support all 1485 * clocks as required by the DT-binding. 1486 */ 1487 if (ret < 0) 1488 dwc->num_clks = 0; 1489 else 1490 dwc->num_clks = ret; 1491 1492 } 1493 1494 ret = reset_control_deassert(dwc->reset); 1495 if (ret) 1496 return ret; 1497 1498 ret = clk_bulk_prepare_enable(dwc->num_clks, dwc->clks); 1499 if (ret) 1500 goto assert_reset; 1501 1502 if (!dwc3_core_is_valid(dwc)) { 1503 dev_err(dwc->dev, "this is not a DesignWare USB3 DRD Core\n"); 1504 ret = -ENODEV; 1505 goto disable_clks; 1506 } 1507 1508 platform_set_drvdata(pdev, dwc); 1509 dwc3_cache_hwparams(dwc); 1510 1511 spin_lock_init(&dwc->lock); 1512 1513 pm_runtime_set_active(dev); 1514 pm_runtime_use_autosuspend(dev); 1515 pm_runtime_set_autosuspend_delay(dev, DWC3_DEFAULT_AUTOSUSPEND_DELAY); 1516 pm_runtime_enable(dev); 1517 ret = pm_runtime_get_sync(dev); 1518 if (ret < 0) 1519 goto err1; 1520 1521 pm_runtime_forbid(dev); 1522 1523 ret = dwc3_alloc_event_buffers(dwc, DWC3_EVENT_BUFFERS_SIZE); 1524 if (ret) { 1525 dev_err(dwc->dev, "failed to allocate event buffers\n"); 1526 ret = -ENOMEM; 1527 goto err2; 1528 } 1529 1530 ret = dwc3_get_dr_mode(dwc); 1531 if (ret) 1532 goto err3; 1533 1534 ret = dwc3_alloc_scratch_buffers(dwc); 1535 if (ret) 1536 goto err3; 1537 1538 ret = dwc3_core_init(dwc); 1539 if (ret) { 1540 if (ret != -EPROBE_DEFER) 1541 dev_err(dev, "failed to initialize core: %d\n", ret); 1542 goto err4; 1543 } 1544 1545 dwc3_check_params(dwc); 1546 1547 ret = dwc3_core_init_mode(dwc); 1548 if (ret) 1549 goto err5; 1550 1551 dwc3_debugfs_init(dwc); 1552 pm_runtime_put(dev); 1553 1554 return 0; 1555 1556 err5: 1557 dwc3_event_buffers_cleanup(dwc); 1558 dwc3_ulpi_exit(dwc); 1559 1560 err4: 1561 dwc3_free_scratch_buffers(dwc); 1562 1563 err3: 1564 dwc3_free_event_buffers(dwc); 1565 1566 err2: 1567 pm_runtime_allow(&pdev->dev); 1568 1569 err1: 1570 pm_runtime_put_sync(&pdev->dev); 1571 pm_runtime_disable(&pdev->dev); 1572 1573 disable_clks: 1574 clk_bulk_disable_unprepare(dwc->num_clks, dwc->clks); 1575 assert_reset: 1576 reset_control_assert(dwc->reset); 1577 1578 return ret; 1579 } 1580 1581 static int dwc3_remove(struct platform_device *pdev) 1582 { 1583 struct dwc3 *dwc = platform_get_drvdata(pdev); 1584 1585 pm_runtime_get_sync(&pdev->dev); 1586 1587 dwc3_debugfs_exit(dwc); 1588 dwc3_core_exit_mode(dwc); 1589 1590 dwc3_core_exit(dwc); 1591 dwc3_ulpi_exit(dwc); 1592 1593 pm_runtime_put_sync(&pdev->dev); 1594 pm_runtime_allow(&pdev->dev); 1595 pm_runtime_disable(&pdev->dev); 1596 1597 dwc3_free_event_buffers(dwc); 1598 dwc3_free_scratch_buffers(dwc); 1599 1600 return 0; 1601 } 1602 1603 #ifdef CONFIG_PM 1604 static int dwc3_core_init_for_resume(struct dwc3 *dwc) 1605 { 1606 int ret; 1607 1608 ret = reset_control_deassert(dwc->reset); 1609 if (ret) 1610 return ret; 1611 1612 ret = clk_bulk_prepare_enable(dwc->num_clks, dwc->clks); 1613 if (ret) 1614 goto assert_reset; 1615 1616 ret = dwc3_core_init(dwc); 1617 if (ret) 1618 goto disable_clks; 1619 1620 return 0; 1621 1622 disable_clks: 1623 clk_bulk_disable_unprepare(dwc->num_clks, dwc->clks); 1624 assert_reset: 1625 reset_control_assert(dwc->reset); 1626 1627 return ret; 1628 } 1629 1630 static int dwc3_suspend_common(struct dwc3 *dwc, pm_message_t msg) 1631 { 1632 unsigned long flags; 1633 u32 reg; 1634 1635 switch (dwc->current_dr_role) { 1636 case DWC3_GCTL_PRTCAP_DEVICE: 1637 if (pm_runtime_suspended(dwc->dev)) 1638 break; 1639 spin_lock_irqsave(&dwc->lock, flags); 1640 dwc3_gadget_suspend(dwc); 1641 spin_unlock_irqrestore(&dwc->lock, flags); 1642 synchronize_irq(dwc->irq_gadget); 1643 dwc3_core_exit(dwc); 1644 break; 1645 case DWC3_GCTL_PRTCAP_HOST: 1646 if (!PMSG_IS_AUTO(msg)) { 1647 dwc3_core_exit(dwc); 1648 break; 1649 } 1650 1651 /* Let controller to suspend HSPHY before PHY driver suspends */ 1652 if (dwc->dis_u2_susphy_quirk || 1653 dwc->dis_enblslpm_quirk) { 1654 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0)); 1655 reg |= DWC3_GUSB2PHYCFG_ENBLSLPM | 1656 DWC3_GUSB2PHYCFG_SUSPHY; 1657 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg); 1658 1659 /* Give some time for USB2 PHY to suspend */ 1660 usleep_range(5000, 6000); 1661 } 1662 1663 phy_pm_runtime_put_sync(dwc->usb2_generic_phy); 1664 phy_pm_runtime_put_sync(dwc->usb3_generic_phy); 1665 break; 1666 case DWC3_GCTL_PRTCAP_OTG: 1667 /* do nothing during runtime_suspend */ 1668 if (PMSG_IS_AUTO(msg)) 1669 break; 1670 1671 if (dwc->current_otg_role == DWC3_OTG_ROLE_DEVICE) { 1672 spin_lock_irqsave(&dwc->lock, flags); 1673 dwc3_gadget_suspend(dwc); 1674 spin_unlock_irqrestore(&dwc->lock, flags); 1675 synchronize_irq(dwc->irq_gadget); 1676 } 1677 1678 dwc3_otg_exit(dwc); 1679 dwc3_core_exit(dwc); 1680 break; 1681 default: 1682 /* do nothing */ 1683 break; 1684 } 1685 1686 return 0; 1687 } 1688 1689 static int dwc3_resume_common(struct dwc3 *dwc, pm_message_t msg) 1690 { 1691 unsigned long flags; 1692 int ret; 1693 u32 reg; 1694 1695 switch (dwc->current_dr_role) { 1696 case DWC3_GCTL_PRTCAP_DEVICE: 1697 ret = dwc3_core_init_for_resume(dwc); 1698 if (ret) 1699 return ret; 1700 1701 dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_DEVICE); 1702 spin_lock_irqsave(&dwc->lock, flags); 1703 dwc3_gadget_resume(dwc); 1704 spin_unlock_irqrestore(&dwc->lock, flags); 1705 break; 1706 case DWC3_GCTL_PRTCAP_HOST: 1707 if (!PMSG_IS_AUTO(msg)) { 1708 ret = dwc3_core_init_for_resume(dwc); 1709 if (ret) 1710 return ret; 1711 dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_HOST); 1712 break; 1713 } 1714 /* Restore GUSB2PHYCFG bits that were modified in suspend */ 1715 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0)); 1716 if (dwc->dis_u2_susphy_quirk) 1717 reg &= ~DWC3_GUSB2PHYCFG_SUSPHY; 1718 1719 if (dwc->dis_enblslpm_quirk) 1720 reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM; 1721 1722 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg); 1723 1724 phy_pm_runtime_get_sync(dwc->usb2_generic_phy); 1725 phy_pm_runtime_get_sync(dwc->usb3_generic_phy); 1726 break; 1727 case DWC3_GCTL_PRTCAP_OTG: 1728 /* nothing to do on runtime_resume */ 1729 if (PMSG_IS_AUTO(msg)) 1730 break; 1731 1732 ret = dwc3_core_init(dwc); 1733 if (ret) 1734 return ret; 1735 1736 dwc3_set_prtcap(dwc, dwc->current_dr_role); 1737 1738 dwc3_otg_init(dwc); 1739 if (dwc->current_otg_role == DWC3_OTG_ROLE_HOST) { 1740 dwc3_otg_host_init(dwc); 1741 } else if (dwc->current_otg_role == DWC3_OTG_ROLE_DEVICE) { 1742 spin_lock_irqsave(&dwc->lock, flags); 1743 dwc3_gadget_resume(dwc); 1744 spin_unlock_irqrestore(&dwc->lock, flags); 1745 } 1746 1747 break; 1748 default: 1749 /* do nothing */ 1750 break; 1751 } 1752 1753 return 0; 1754 } 1755 1756 static int dwc3_runtime_checks(struct dwc3 *dwc) 1757 { 1758 switch (dwc->current_dr_role) { 1759 case DWC3_GCTL_PRTCAP_DEVICE: 1760 if (dwc->connected) 1761 return -EBUSY; 1762 break; 1763 case DWC3_GCTL_PRTCAP_HOST: 1764 default: 1765 /* do nothing */ 1766 break; 1767 } 1768 1769 return 0; 1770 } 1771 1772 static int dwc3_runtime_suspend(struct device *dev) 1773 { 1774 struct dwc3 *dwc = dev_get_drvdata(dev); 1775 int ret; 1776 1777 if (dwc3_runtime_checks(dwc)) 1778 return -EBUSY; 1779 1780 ret = dwc3_suspend_common(dwc, PMSG_AUTO_SUSPEND); 1781 if (ret) 1782 return ret; 1783 1784 device_init_wakeup(dev, true); 1785 1786 return 0; 1787 } 1788 1789 static int dwc3_runtime_resume(struct device *dev) 1790 { 1791 struct dwc3 *dwc = dev_get_drvdata(dev); 1792 int ret; 1793 1794 device_init_wakeup(dev, false); 1795 1796 ret = dwc3_resume_common(dwc, PMSG_AUTO_RESUME); 1797 if (ret) 1798 return ret; 1799 1800 switch (dwc->current_dr_role) { 1801 case DWC3_GCTL_PRTCAP_DEVICE: 1802 dwc3_gadget_process_pending_events(dwc); 1803 break; 1804 case DWC3_GCTL_PRTCAP_HOST: 1805 default: 1806 /* do nothing */ 1807 break; 1808 } 1809 1810 pm_runtime_mark_last_busy(dev); 1811 1812 return 0; 1813 } 1814 1815 static int dwc3_runtime_idle(struct device *dev) 1816 { 1817 struct dwc3 *dwc = dev_get_drvdata(dev); 1818 1819 switch (dwc->current_dr_role) { 1820 case DWC3_GCTL_PRTCAP_DEVICE: 1821 if (dwc3_runtime_checks(dwc)) 1822 return -EBUSY; 1823 break; 1824 case DWC3_GCTL_PRTCAP_HOST: 1825 default: 1826 /* do nothing */ 1827 break; 1828 } 1829 1830 pm_runtime_mark_last_busy(dev); 1831 pm_runtime_autosuspend(dev); 1832 1833 return 0; 1834 } 1835 #endif /* CONFIG_PM */ 1836 1837 #ifdef CONFIG_PM_SLEEP 1838 static int dwc3_suspend(struct device *dev) 1839 { 1840 struct dwc3 *dwc = dev_get_drvdata(dev); 1841 int ret; 1842 1843 ret = dwc3_suspend_common(dwc, PMSG_SUSPEND); 1844 if (ret) 1845 return ret; 1846 1847 pinctrl_pm_select_sleep_state(dev); 1848 1849 return 0; 1850 } 1851 1852 static int dwc3_resume(struct device *dev) 1853 { 1854 struct dwc3 *dwc = dev_get_drvdata(dev); 1855 int ret; 1856 1857 pinctrl_pm_select_default_state(dev); 1858 1859 ret = dwc3_resume_common(dwc, PMSG_RESUME); 1860 if (ret) 1861 return ret; 1862 1863 pm_runtime_disable(dev); 1864 pm_runtime_set_active(dev); 1865 pm_runtime_enable(dev); 1866 1867 return 0; 1868 } 1869 #endif /* CONFIG_PM_SLEEP */ 1870 1871 static const struct dev_pm_ops dwc3_dev_pm_ops = { 1872 SET_SYSTEM_SLEEP_PM_OPS(dwc3_suspend, dwc3_resume) 1873 SET_RUNTIME_PM_OPS(dwc3_runtime_suspend, dwc3_runtime_resume, 1874 dwc3_runtime_idle) 1875 }; 1876 1877 #ifdef CONFIG_OF 1878 static const struct of_device_id of_dwc3_match[] = { 1879 { 1880 .compatible = "snps,dwc3" 1881 }, 1882 { 1883 .compatible = "synopsys,dwc3" 1884 }, 1885 { }, 1886 }; 1887 MODULE_DEVICE_TABLE(of, of_dwc3_match); 1888 #endif 1889 1890 #ifdef CONFIG_ACPI 1891 1892 #define ACPI_ID_INTEL_BSW "808622B7" 1893 1894 static const struct acpi_device_id dwc3_acpi_match[] = { 1895 { ACPI_ID_INTEL_BSW, 0 }, 1896 { }, 1897 }; 1898 MODULE_DEVICE_TABLE(acpi, dwc3_acpi_match); 1899 #endif 1900 1901 static struct platform_driver dwc3_driver = { 1902 .probe = dwc3_probe, 1903 .remove = dwc3_remove, 1904 .driver = { 1905 .name = "dwc3", 1906 .of_match_table = of_match_ptr(of_dwc3_match), 1907 .acpi_match_table = ACPI_PTR(dwc3_acpi_match), 1908 .pm = &dwc3_dev_pm_ops, 1909 }, 1910 }; 1911 1912 module_platform_driver(dwc3_driver); 1913 1914 MODULE_ALIAS("platform:dwc3"); 1915 MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>"); 1916 MODULE_LICENSE("GPL v2"); 1917 MODULE_DESCRIPTION("DesignWare USB3 DRD Controller Driver"); 1918