1 // SPDX-License-Identifier: GPL-2.0 2 /** 3 * core.c - DesignWare USB3 DRD Controller Core file 4 * 5 * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com 6 * 7 * Authors: Felipe Balbi <balbi@ti.com>, 8 * Sebastian Andrzej Siewior <bigeasy@linutronix.de> 9 */ 10 11 #include <linux/clk.h> 12 #include <linux/version.h> 13 #include <linux/module.h> 14 #include <linux/kernel.h> 15 #include <linux/slab.h> 16 #include <linux/spinlock.h> 17 #include <linux/platform_device.h> 18 #include <linux/pm_runtime.h> 19 #include <linux/interrupt.h> 20 #include <linux/ioport.h> 21 #include <linux/io.h> 22 #include <linux/list.h> 23 #include <linux/delay.h> 24 #include <linux/dma-mapping.h> 25 #include <linux/of.h> 26 #include <linux/acpi.h> 27 #include <linux/pinctrl/consumer.h> 28 #include <linux/reset.h> 29 30 #include <linux/usb/ch9.h> 31 #include <linux/usb/gadget.h> 32 #include <linux/usb/of.h> 33 #include <linux/usb/otg.h> 34 35 #include "core.h" 36 #include "gadget.h" 37 #include "io.h" 38 39 #include "debug.h" 40 41 #define DWC3_DEFAULT_AUTOSUSPEND_DELAY 5000 /* ms */ 42 43 /** 44 * dwc3_get_dr_mode - Validates and sets dr_mode 45 * @dwc: pointer to our context structure 46 */ 47 static int dwc3_get_dr_mode(struct dwc3 *dwc) 48 { 49 enum usb_dr_mode mode; 50 struct device *dev = dwc->dev; 51 unsigned int hw_mode; 52 53 if (dwc->dr_mode == USB_DR_MODE_UNKNOWN) 54 dwc->dr_mode = USB_DR_MODE_OTG; 55 56 mode = dwc->dr_mode; 57 hw_mode = DWC3_GHWPARAMS0_MODE(dwc->hwparams.hwparams0); 58 59 switch (hw_mode) { 60 case DWC3_GHWPARAMS0_MODE_GADGET: 61 if (IS_ENABLED(CONFIG_USB_DWC3_HOST)) { 62 dev_err(dev, 63 "Controller does not support host mode.\n"); 64 return -EINVAL; 65 } 66 mode = USB_DR_MODE_PERIPHERAL; 67 break; 68 case DWC3_GHWPARAMS0_MODE_HOST: 69 if (IS_ENABLED(CONFIG_USB_DWC3_GADGET)) { 70 dev_err(dev, 71 "Controller does not support device mode.\n"); 72 return -EINVAL; 73 } 74 mode = USB_DR_MODE_HOST; 75 break; 76 default: 77 if (IS_ENABLED(CONFIG_USB_DWC3_HOST)) 78 mode = USB_DR_MODE_HOST; 79 else if (IS_ENABLED(CONFIG_USB_DWC3_GADGET)) 80 mode = USB_DR_MODE_PERIPHERAL; 81 82 /* 83 * DWC_usb31 and DWC_usb3 v3.30a and higher do not support OTG 84 * mode. If the controller supports DRD but the dr_mode is not 85 * specified or set to OTG, then set the mode to peripheral. 86 */ 87 if (mode == USB_DR_MODE_OTG && 88 dwc->revision >= DWC3_REVISION_330A) 89 mode = USB_DR_MODE_PERIPHERAL; 90 } 91 92 if (mode != dwc->dr_mode) { 93 dev_warn(dev, 94 "Configuration mismatch. dr_mode forced to %s\n", 95 mode == USB_DR_MODE_HOST ? "host" : "gadget"); 96 97 dwc->dr_mode = mode; 98 } 99 100 return 0; 101 } 102 103 void dwc3_set_prtcap(struct dwc3 *dwc, u32 mode) 104 { 105 u32 reg; 106 107 reg = dwc3_readl(dwc->regs, DWC3_GCTL); 108 reg &= ~(DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_OTG)); 109 reg |= DWC3_GCTL_PRTCAPDIR(mode); 110 dwc3_writel(dwc->regs, DWC3_GCTL, reg); 111 112 dwc->current_dr_role = mode; 113 } 114 115 static void __dwc3_set_mode(struct work_struct *work) 116 { 117 struct dwc3 *dwc = work_to_dwc(work); 118 unsigned long flags; 119 int ret; 120 121 if (dwc->dr_mode != USB_DR_MODE_OTG) 122 return; 123 124 if (dwc->current_dr_role == DWC3_GCTL_PRTCAP_OTG) 125 dwc3_otg_update(dwc, 0); 126 127 if (!dwc->desired_dr_role) 128 return; 129 130 if (dwc->desired_dr_role == dwc->current_dr_role) 131 return; 132 133 if (dwc->desired_dr_role == DWC3_GCTL_PRTCAP_OTG && dwc->edev) 134 return; 135 136 switch (dwc->current_dr_role) { 137 case DWC3_GCTL_PRTCAP_HOST: 138 dwc3_host_exit(dwc); 139 break; 140 case DWC3_GCTL_PRTCAP_DEVICE: 141 dwc3_gadget_exit(dwc); 142 dwc3_event_buffers_cleanup(dwc); 143 break; 144 case DWC3_GCTL_PRTCAP_OTG: 145 dwc3_otg_exit(dwc); 146 spin_lock_irqsave(&dwc->lock, flags); 147 dwc->desired_otg_role = DWC3_OTG_ROLE_IDLE; 148 spin_unlock_irqrestore(&dwc->lock, flags); 149 dwc3_otg_update(dwc, 1); 150 break; 151 default: 152 break; 153 } 154 155 spin_lock_irqsave(&dwc->lock, flags); 156 157 dwc3_set_prtcap(dwc, dwc->desired_dr_role); 158 159 spin_unlock_irqrestore(&dwc->lock, flags); 160 161 switch (dwc->desired_dr_role) { 162 case DWC3_GCTL_PRTCAP_HOST: 163 ret = dwc3_host_init(dwc); 164 if (ret) { 165 dev_err(dwc->dev, "failed to initialize host\n"); 166 } else { 167 if (dwc->usb2_phy) 168 otg_set_vbus(dwc->usb2_phy->otg, true); 169 phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_HOST); 170 phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_HOST); 171 } 172 break; 173 case DWC3_GCTL_PRTCAP_DEVICE: 174 dwc3_event_buffers_setup(dwc); 175 176 if (dwc->usb2_phy) 177 otg_set_vbus(dwc->usb2_phy->otg, false); 178 phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_DEVICE); 179 phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_DEVICE); 180 181 ret = dwc3_gadget_init(dwc); 182 if (ret) 183 dev_err(dwc->dev, "failed to initialize peripheral\n"); 184 break; 185 case DWC3_GCTL_PRTCAP_OTG: 186 dwc3_otg_init(dwc); 187 dwc3_otg_update(dwc, 0); 188 break; 189 default: 190 break; 191 } 192 193 } 194 195 void dwc3_set_mode(struct dwc3 *dwc, u32 mode) 196 { 197 unsigned long flags; 198 199 spin_lock_irqsave(&dwc->lock, flags); 200 dwc->desired_dr_role = mode; 201 spin_unlock_irqrestore(&dwc->lock, flags); 202 203 queue_work(system_freezable_wq, &dwc->drd_work); 204 } 205 206 u32 dwc3_core_fifo_space(struct dwc3_ep *dep, u8 type) 207 { 208 struct dwc3 *dwc = dep->dwc; 209 u32 reg; 210 211 dwc3_writel(dwc->regs, DWC3_GDBGFIFOSPACE, 212 DWC3_GDBGFIFOSPACE_NUM(dep->number) | 213 DWC3_GDBGFIFOSPACE_TYPE(type)); 214 215 reg = dwc3_readl(dwc->regs, DWC3_GDBGFIFOSPACE); 216 217 return DWC3_GDBGFIFOSPACE_SPACE_AVAILABLE(reg); 218 } 219 220 /** 221 * dwc3_core_soft_reset - Issues core soft reset and PHY reset 222 * @dwc: pointer to our context structure 223 */ 224 static int dwc3_core_soft_reset(struct dwc3 *dwc) 225 { 226 u32 reg; 227 int retries = 1000; 228 int ret; 229 230 usb_phy_init(dwc->usb2_phy); 231 usb_phy_init(dwc->usb3_phy); 232 ret = phy_init(dwc->usb2_generic_phy); 233 if (ret < 0) 234 return ret; 235 236 ret = phy_init(dwc->usb3_generic_phy); 237 if (ret < 0) { 238 phy_exit(dwc->usb2_generic_phy); 239 return ret; 240 } 241 242 /* 243 * We're resetting only the device side because, if we're in host mode, 244 * XHCI driver will reset the host block. If dwc3 was configured for 245 * host-only mode, then we can return early. 246 */ 247 if (dwc->current_dr_role == DWC3_GCTL_PRTCAP_HOST) 248 return 0; 249 250 reg = dwc3_readl(dwc->regs, DWC3_DCTL); 251 reg |= DWC3_DCTL_CSFTRST; 252 dwc3_writel(dwc->regs, DWC3_DCTL, reg); 253 254 /* 255 * For DWC_usb31 controller 1.90a and later, the DCTL.CSFRST bit 256 * is cleared only after all the clocks are synchronized. This can 257 * take a little more than 50ms. Set the polling rate at 20ms 258 * for 10 times instead. 259 */ 260 if (dwc3_is_usb31(dwc) && dwc->revision >= DWC3_USB31_REVISION_190A) 261 retries = 10; 262 263 do { 264 reg = dwc3_readl(dwc->regs, DWC3_DCTL); 265 if (!(reg & DWC3_DCTL_CSFTRST)) 266 goto done; 267 268 if (dwc3_is_usb31(dwc) && 269 dwc->revision >= DWC3_USB31_REVISION_190A) 270 msleep(20); 271 else 272 udelay(1); 273 } while (--retries); 274 275 phy_exit(dwc->usb3_generic_phy); 276 phy_exit(dwc->usb2_generic_phy); 277 278 return -ETIMEDOUT; 279 280 done: 281 /* 282 * For DWC_usb31 controller 1.80a and prior, once DCTL.CSFRST bit 283 * is cleared, we must wait at least 50ms before accessing the PHY 284 * domain (synchronization delay). 285 */ 286 if (dwc3_is_usb31(dwc) && dwc->revision <= DWC3_USB31_REVISION_180A) 287 msleep(50); 288 289 return 0; 290 } 291 292 static const struct clk_bulk_data dwc3_core_clks[] = { 293 { .id = "ref" }, 294 { .id = "bus_early" }, 295 { .id = "suspend" }, 296 }; 297 298 /* 299 * dwc3_frame_length_adjustment - Adjusts frame length if required 300 * @dwc3: Pointer to our controller context structure 301 */ 302 static void dwc3_frame_length_adjustment(struct dwc3 *dwc) 303 { 304 u32 reg; 305 u32 dft; 306 307 if (dwc->revision < DWC3_REVISION_250A) 308 return; 309 310 if (dwc->fladj == 0) 311 return; 312 313 reg = dwc3_readl(dwc->regs, DWC3_GFLADJ); 314 dft = reg & DWC3_GFLADJ_30MHZ_MASK; 315 if (dft != dwc->fladj) { 316 reg &= ~DWC3_GFLADJ_30MHZ_MASK; 317 reg |= DWC3_GFLADJ_30MHZ_SDBND_SEL | dwc->fladj; 318 dwc3_writel(dwc->regs, DWC3_GFLADJ, reg); 319 } 320 } 321 322 /** 323 * dwc3_free_one_event_buffer - Frees one event buffer 324 * @dwc: Pointer to our controller context structure 325 * @evt: Pointer to event buffer to be freed 326 */ 327 static void dwc3_free_one_event_buffer(struct dwc3 *dwc, 328 struct dwc3_event_buffer *evt) 329 { 330 dma_free_coherent(dwc->sysdev, evt->length, evt->buf, evt->dma); 331 } 332 333 /** 334 * dwc3_alloc_one_event_buffer - Allocates one event buffer structure 335 * @dwc: Pointer to our controller context structure 336 * @length: size of the event buffer 337 * 338 * Returns a pointer to the allocated event buffer structure on success 339 * otherwise ERR_PTR(errno). 340 */ 341 static struct dwc3_event_buffer *dwc3_alloc_one_event_buffer(struct dwc3 *dwc, 342 unsigned length) 343 { 344 struct dwc3_event_buffer *evt; 345 346 evt = devm_kzalloc(dwc->dev, sizeof(*evt), GFP_KERNEL); 347 if (!evt) 348 return ERR_PTR(-ENOMEM); 349 350 evt->dwc = dwc; 351 evt->length = length; 352 evt->cache = devm_kzalloc(dwc->dev, length, GFP_KERNEL); 353 if (!evt->cache) 354 return ERR_PTR(-ENOMEM); 355 356 evt->buf = dma_alloc_coherent(dwc->sysdev, length, 357 &evt->dma, GFP_KERNEL); 358 if (!evt->buf) 359 return ERR_PTR(-ENOMEM); 360 361 return evt; 362 } 363 364 /** 365 * dwc3_free_event_buffers - frees all allocated event buffers 366 * @dwc: Pointer to our controller context structure 367 */ 368 static void dwc3_free_event_buffers(struct dwc3 *dwc) 369 { 370 struct dwc3_event_buffer *evt; 371 372 evt = dwc->ev_buf; 373 if (evt) 374 dwc3_free_one_event_buffer(dwc, evt); 375 } 376 377 /** 378 * dwc3_alloc_event_buffers - Allocates @num event buffers of size @length 379 * @dwc: pointer to our controller context structure 380 * @length: size of event buffer 381 * 382 * Returns 0 on success otherwise negative errno. In the error case, dwc 383 * may contain some buffers allocated but not all which were requested. 384 */ 385 static int dwc3_alloc_event_buffers(struct dwc3 *dwc, unsigned length) 386 { 387 struct dwc3_event_buffer *evt; 388 389 evt = dwc3_alloc_one_event_buffer(dwc, length); 390 if (IS_ERR(evt)) { 391 dev_err(dwc->dev, "can't allocate event buffer\n"); 392 return PTR_ERR(evt); 393 } 394 dwc->ev_buf = evt; 395 396 return 0; 397 } 398 399 /** 400 * dwc3_event_buffers_setup - setup our allocated event buffers 401 * @dwc: pointer to our controller context structure 402 * 403 * Returns 0 on success otherwise negative errno. 404 */ 405 int dwc3_event_buffers_setup(struct dwc3 *dwc) 406 { 407 struct dwc3_event_buffer *evt; 408 409 evt = dwc->ev_buf; 410 evt->lpos = 0; 411 dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(0), 412 lower_32_bits(evt->dma)); 413 dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(0), 414 upper_32_bits(evt->dma)); 415 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0), 416 DWC3_GEVNTSIZ_SIZE(evt->length)); 417 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), 0); 418 419 return 0; 420 } 421 422 void dwc3_event_buffers_cleanup(struct dwc3 *dwc) 423 { 424 struct dwc3_event_buffer *evt; 425 426 evt = dwc->ev_buf; 427 428 evt->lpos = 0; 429 430 dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(0), 0); 431 dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(0), 0); 432 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0), DWC3_GEVNTSIZ_INTMASK 433 | DWC3_GEVNTSIZ_SIZE(0)); 434 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), 0); 435 } 436 437 static int dwc3_alloc_scratch_buffers(struct dwc3 *dwc) 438 { 439 if (!dwc->has_hibernation) 440 return 0; 441 442 if (!dwc->nr_scratch) 443 return 0; 444 445 dwc->scratchbuf = kmalloc_array(dwc->nr_scratch, 446 DWC3_SCRATCHBUF_SIZE, GFP_KERNEL); 447 if (!dwc->scratchbuf) 448 return -ENOMEM; 449 450 return 0; 451 } 452 453 static int dwc3_setup_scratch_buffers(struct dwc3 *dwc) 454 { 455 dma_addr_t scratch_addr; 456 u32 param; 457 int ret; 458 459 if (!dwc->has_hibernation) 460 return 0; 461 462 if (!dwc->nr_scratch) 463 return 0; 464 465 /* should never fall here */ 466 if (!WARN_ON(dwc->scratchbuf)) 467 return 0; 468 469 scratch_addr = dma_map_single(dwc->sysdev, dwc->scratchbuf, 470 dwc->nr_scratch * DWC3_SCRATCHBUF_SIZE, 471 DMA_BIDIRECTIONAL); 472 if (dma_mapping_error(dwc->sysdev, scratch_addr)) { 473 dev_err(dwc->sysdev, "failed to map scratch buffer\n"); 474 ret = -EFAULT; 475 goto err0; 476 } 477 478 dwc->scratch_addr = scratch_addr; 479 480 param = lower_32_bits(scratch_addr); 481 482 ret = dwc3_send_gadget_generic_command(dwc, 483 DWC3_DGCMD_SET_SCRATCHPAD_ADDR_LO, param); 484 if (ret < 0) 485 goto err1; 486 487 param = upper_32_bits(scratch_addr); 488 489 ret = dwc3_send_gadget_generic_command(dwc, 490 DWC3_DGCMD_SET_SCRATCHPAD_ADDR_HI, param); 491 if (ret < 0) 492 goto err1; 493 494 return 0; 495 496 err1: 497 dma_unmap_single(dwc->sysdev, dwc->scratch_addr, dwc->nr_scratch * 498 DWC3_SCRATCHBUF_SIZE, DMA_BIDIRECTIONAL); 499 500 err0: 501 return ret; 502 } 503 504 static void dwc3_free_scratch_buffers(struct dwc3 *dwc) 505 { 506 if (!dwc->has_hibernation) 507 return; 508 509 if (!dwc->nr_scratch) 510 return; 511 512 /* should never fall here */ 513 if (!WARN_ON(dwc->scratchbuf)) 514 return; 515 516 dma_unmap_single(dwc->sysdev, dwc->scratch_addr, dwc->nr_scratch * 517 DWC3_SCRATCHBUF_SIZE, DMA_BIDIRECTIONAL); 518 kfree(dwc->scratchbuf); 519 } 520 521 static void dwc3_core_num_eps(struct dwc3 *dwc) 522 { 523 struct dwc3_hwparams *parms = &dwc->hwparams; 524 525 dwc->num_eps = DWC3_NUM_EPS(parms); 526 } 527 528 static void dwc3_cache_hwparams(struct dwc3 *dwc) 529 { 530 struct dwc3_hwparams *parms = &dwc->hwparams; 531 532 parms->hwparams0 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS0); 533 parms->hwparams1 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS1); 534 parms->hwparams2 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS2); 535 parms->hwparams3 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS3); 536 parms->hwparams4 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS4); 537 parms->hwparams5 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS5); 538 parms->hwparams6 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS6); 539 parms->hwparams7 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS7); 540 parms->hwparams8 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS8); 541 } 542 543 static int dwc3_core_ulpi_init(struct dwc3 *dwc) 544 { 545 int intf; 546 int ret = 0; 547 548 intf = DWC3_GHWPARAMS3_HSPHY_IFC(dwc->hwparams.hwparams3); 549 550 if (intf == DWC3_GHWPARAMS3_HSPHY_IFC_ULPI || 551 (intf == DWC3_GHWPARAMS3_HSPHY_IFC_UTMI_ULPI && 552 dwc->hsphy_interface && 553 !strncmp(dwc->hsphy_interface, "ulpi", 4))) 554 ret = dwc3_ulpi_init(dwc); 555 556 return ret; 557 } 558 559 /** 560 * dwc3_phy_setup - Configure USB PHY Interface of DWC3 Core 561 * @dwc: Pointer to our controller context structure 562 * 563 * Returns 0 on success. The USB PHY interfaces are configured but not 564 * initialized. The PHY interfaces and the PHYs get initialized together with 565 * the core in dwc3_core_init. 566 */ 567 static int dwc3_phy_setup(struct dwc3 *dwc) 568 { 569 unsigned int hw_mode; 570 u32 reg; 571 572 hw_mode = DWC3_GHWPARAMS0_MODE(dwc->hwparams.hwparams0); 573 574 reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0)); 575 576 /* 577 * Make sure UX_EXIT_PX is cleared as that causes issues with some 578 * PHYs. Also, this bit is not supposed to be used in normal operation. 579 */ 580 reg &= ~DWC3_GUSB3PIPECTL_UX_EXIT_PX; 581 582 /* 583 * Above 1.94a, it is recommended to set DWC3_GUSB3PIPECTL_SUSPHY 584 * to '0' during coreConsultant configuration. So default value 585 * will be '0' when the core is reset. Application needs to set it 586 * to '1' after the core initialization is completed. 587 */ 588 if (dwc->revision > DWC3_REVISION_194A) 589 reg |= DWC3_GUSB3PIPECTL_SUSPHY; 590 591 /* 592 * For DRD controllers, GUSB3PIPECTL.SUSPENDENABLE must be cleared after 593 * power-on reset, and it can be set after core initialization, which is 594 * after device soft-reset during initialization. 595 */ 596 if (hw_mode == DWC3_GHWPARAMS0_MODE_DRD) 597 reg &= ~DWC3_GUSB3PIPECTL_SUSPHY; 598 599 if (dwc->u2ss_inp3_quirk) 600 reg |= DWC3_GUSB3PIPECTL_U2SSINP3OK; 601 602 if (dwc->dis_rxdet_inp3_quirk) 603 reg |= DWC3_GUSB3PIPECTL_DISRXDETINP3; 604 605 if (dwc->req_p1p2p3_quirk) 606 reg |= DWC3_GUSB3PIPECTL_REQP1P2P3; 607 608 if (dwc->del_p1p2p3_quirk) 609 reg |= DWC3_GUSB3PIPECTL_DEP1P2P3_EN; 610 611 if (dwc->del_phy_power_chg_quirk) 612 reg |= DWC3_GUSB3PIPECTL_DEPOCHANGE; 613 614 if (dwc->lfps_filter_quirk) 615 reg |= DWC3_GUSB3PIPECTL_LFPSFILT; 616 617 if (dwc->rx_detect_poll_quirk) 618 reg |= DWC3_GUSB3PIPECTL_RX_DETOPOLL; 619 620 if (dwc->tx_de_emphasis_quirk) 621 reg |= DWC3_GUSB3PIPECTL_TX_DEEPH(dwc->tx_de_emphasis); 622 623 if (dwc->dis_u3_susphy_quirk) 624 reg &= ~DWC3_GUSB3PIPECTL_SUSPHY; 625 626 if (dwc->dis_del_phy_power_chg_quirk) 627 reg &= ~DWC3_GUSB3PIPECTL_DEPOCHANGE; 628 629 dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg); 630 631 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0)); 632 633 /* Select the HS PHY interface */ 634 switch (DWC3_GHWPARAMS3_HSPHY_IFC(dwc->hwparams.hwparams3)) { 635 case DWC3_GHWPARAMS3_HSPHY_IFC_UTMI_ULPI: 636 if (dwc->hsphy_interface && 637 !strncmp(dwc->hsphy_interface, "utmi", 4)) { 638 reg &= ~DWC3_GUSB2PHYCFG_ULPI_UTMI; 639 break; 640 } else if (dwc->hsphy_interface && 641 !strncmp(dwc->hsphy_interface, "ulpi", 4)) { 642 reg |= DWC3_GUSB2PHYCFG_ULPI_UTMI; 643 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg); 644 } else { 645 /* Relying on default value. */ 646 if (!(reg & DWC3_GUSB2PHYCFG_ULPI_UTMI)) 647 break; 648 } 649 /* FALLTHROUGH */ 650 case DWC3_GHWPARAMS3_HSPHY_IFC_ULPI: 651 /* FALLTHROUGH */ 652 default: 653 break; 654 } 655 656 switch (dwc->hsphy_mode) { 657 case USBPHY_INTERFACE_MODE_UTMI: 658 reg &= ~(DWC3_GUSB2PHYCFG_PHYIF_MASK | 659 DWC3_GUSB2PHYCFG_USBTRDTIM_MASK); 660 reg |= DWC3_GUSB2PHYCFG_PHYIF(UTMI_PHYIF_8_BIT) | 661 DWC3_GUSB2PHYCFG_USBTRDTIM(USBTRDTIM_UTMI_8_BIT); 662 break; 663 case USBPHY_INTERFACE_MODE_UTMIW: 664 reg &= ~(DWC3_GUSB2PHYCFG_PHYIF_MASK | 665 DWC3_GUSB2PHYCFG_USBTRDTIM_MASK); 666 reg |= DWC3_GUSB2PHYCFG_PHYIF(UTMI_PHYIF_16_BIT) | 667 DWC3_GUSB2PHYCFG_USBTRDTIM(USBTRDTIM_UTMI_16_BIT); 668 break; 669 default: 670 break; 671 } 672 673 /* 674 * Above 1.94a, it is recommended to set DWC3_GUSB2PHYCFG_SUSPHY to 675 * '0' during coreConsultant configuration. So default value will 676 * be '0' when the core is reset. Application needs to set it to 677 * '1' after the core initialization is completed. 678 */ 679 if (dwc->revision > DWC3_REVISION_194A) 680 reg |= DWC3_GUSB2PHYCFG_SUSPHY; 681 682 /* 683 * For DRD controllers, GUSB2PHYCFG.SUSPHY must be cleared after 684 * power-on reset, and it can be set after core initialization, which is 685 * after device soft-reset during initialization. 686 */ 687 if (hw_mode == DWC3_GHWPARAMS0_MODE_DRD) 688 reg &= ~DWC3_GUSB2PHYCFG_SUSPHY; 689 690 if (dwc->dis_u2_susphy_quirk) 691 reg &= ~DWC3_GUSB2PHYCFG_SUSPHY; 692 693 if (dwc->dis_enblslpm_quirk) 694 reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM; 695 else 696 reg |= DWC3_GUSB2PHYCFG_ENBLSLPM; 697 698 if (dwc->dis_u2_freeclk_exists_quirk) 699 reg &= ~DWC3_GUSB2PHYCFG_U2_FREECLK_EXISTS; 700 701 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg); 702 703 return 0; 704 } 705 706 static void dwc3_core_exit(struct dwc3 *dwc) 707 { 708 dwc3_event_buffers_cleanup(dwc); 709 710 usb_phy_shutdown(dwc->usb2_phy); 711 usb_phy_shutdown(dwc->usb3_phy); 712 phy_exit(dwc->usb2_generic_phy); 713 phy_exit(dwc->usb3_generic_phy); 714 715 usb_phy_set_suspend(dwc->usb2_phy, 1); 716 usb_phy_set_suspend(dwc->usb3_phy, 1); 717 phy_power_off(dwc->usb2_generic_phy); 718 phy_power_off(dwc->usb3_generic_phy); 719 clk_bulk_disable_unprepare(dwc->num_clks, dwc->clks); 720 reset_control_assert(dwc->reset); 721 } 722 723 static bool dwc3_core_is_valid(struct dwc3 *dwc) 724 { 725 u32 reg; 726 727 reg = dwc3_readl(dwc->regs, DWC3_GSNPSID); 728 729 /* This should read as U3 followed by revision number */ 730 if ((reg & DWC3_GSNPSID_MASK) == 0x55330000) { 731 /* Detected DWC_usb3 IP */ 732 dwc->revision = reg; 733 } else if ((reg & DWC3_GSNPSID_MASK) == 0x33310000) { 734 /* Detected DWC_usb31 IP */ 735 dwc->revision = dwc3_readl(dwc->regs, DWC3_VER_NUMBER); 736 dwc->revision |= DWC3_REVISION_IS_DWC31; 737 dwc->version_type = dwc3_readl(dwc->regs, DWC3_VER_TYPE); 738 } else { 739 return false; 740 } 741 742 return true; 743 } 744 745 static void dwc3_core_setup_global_control(struct dwc3 *dwc) 746 { 747 u32 hwparams4 = dwc->hwparams.hwparams4; 748 u32 reg; 749 750 reg = dwc3_readl(dwc->regs, DWC3_GCTL); 751 reg &= ~DWC3_GCTL_SCALEDOWN_MASK; 752 753 switch (DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1)) { 754 case DWC3_GHWPARAMS1_EN_PWROPT_CLK: 755 /** 756 * WORKAROUND: DWC3 revisions between 2.10a and 2.50a have an 757 * issue which would cause xHCI compliance tests to fail. 758 * 759 * Because of that we cannot enable clock gating on such 760 * configurations. 761 * 762 * Refers to: 763 * 764 * STAR#9000588375: Clock Gating, SOF Issues when ref_clk-Based 765 * SOF/ITP Mode Used 766 */ 767 if ((dwc->dr_mode == USB_DR_MODE_HOST || 768 dwc->dr_mode == USB_DR_MODE_OTG) && 769 (dwc->revision >= DWC3_REVISION_210A && 770 dwc->revision <= DWC3_REVISION_250A)) 771 reg |= DWC3_GCTL_DSBLCLKGTNG | DWC3_GCTL_SOFITPSYNC; 772 else 773 reg &= ~DWC3_GCTL_DSBLCLKGTNG; 774 break; 775 case DWC3_GHWPARAMS1_EN_PWROPT_HIB: 776 /* enable hibernation here */ 777 dwc->nr_scratch = DWC3_GHWPARAMS4_HIBER_SCRATCHBUFS(hwparams4); 778 779 /* 780 * REVISIT Enabling this bit so that host-mode hibernation 781 * will work. Device-mode hibernation is not yet implemented. 782 */ 783 reg |= DWC3_GCTL_GBLHIBERNATIONEN; 784 break; 785 default: 786 /* nothing */ 787 break; 788 } 789 790 /* check if current dwc3 is on simulation board */ 791 if (dwc->hwparams.hwparams6 & DWC3_GHWPARAMS6_EN_FPGA) { 792 dev_info(dwc->dev, "Running with FPGA optimizations\n"); 793 dwc->is_fpga = true; 794 } 795 796 WARN_ONCE(dwc->disable_scramble_quirk && !dwc->is_fpga, 797 "disable_scramble cannot be used on non-FPGA builds\n"); 798 799 if (dwc->disable_scramble_quirk && dwc->is_fpga) 800 reg |= DWC3_GCTL_DISSCRAMBLE; 801 else 802 reg &= ~DWC3_GCTL_DISSCRAMBLE; 803 804 if (dwc->u2exit_lfps_quirk) 805 reg |= DWC3_GCTL_U2EXIT_LFPS; 806 807 /* 808 * WORKAROUND: DWC3 revisions <1.90a have a bug 809 * where the device can fail to connect at SuperSpeed 810 * and falls back to high-speed mode which causes 811 * the device to enter a Connect/Disconnect loop 812 */ 813 if (dwc->revision < DWC3_REVISION_190A) 814 reg |= DWC3_GCTL_U2RSTECN; 815 816 dwc3_writel(dwc->regs, DWC3_GCTL, reg); 817 } 818 819 static int dwc3_core_get_phy(struct dwc3 *dwc); 820 static int dwc3_core_ulpi_init(struct dwc3 *dwc); 821 822 /* set global incr burst type configuration registers */ 823 static void dwc3_set_incr_burst_type(struct dwc3 *dwc) 824 { 825 struct device *dev = dwc->dev; 826 /* incrx_mode : for INCR burst type. */ 827 bool incrx_mode; 828 /* incrx_size : for size of INCRX burst. */ 829 u32 incrx_size; 830 u32 *vals; 831 u32 cfg; 832 int ntype; 833 int ret; 834 int i; 835 836 cfg = dwc3_readl(dwc->regs, DWC3_GSBUSCFG0); 837 838 /* 839 * Handle property "snps,incr-burst-type-adjustment". 840 * Get the number of value from this property: 841 * result <= 0, means this property is not supported. 842 * result = 1, means INCRx burst mode supported. 843 * result > 1, means undefined length burst mode supported. 844 */ 845 ntype = device_property_count_u32(dev, "snps,incr-burst-type-adjustment"); 846 if (ntype <= 0) 847 return; 848 849 vals = kcalloc(ntype, sizeof(u32), GFP_KERNEL); 850 if (!vals) { 851 dev_err(dev, "Error to get memory\n"); 852 return; 853 } 854 855 /* Get INCR burst type, and parse it */ 856 ret = device_property_read_u32_array(dev, 857 "snps,incr-burst-type-adjustment", vals, ntype); 858 if (ret) { 859 kfree(vals); 860 dev_err(dev, "Error to get property\n"); 861 return; 862 } 863 864 incrx_size = *vals; 865 866 if (ntype > 1) { 867 /* INCRX (undefined length) burst mode */ 868 incrx_mode = INCRX_UNDEF_LENGTH_BURST_MODE; 869 for (i = 1; i < ntype; i++) { 870 if (vals[i] > incrx_size) 871 incrx_size = vals[i]; 872 } 873 } else { 874 /* INCRX burst mode */ 875 incrx_mode = INCRX_BURST_MODE; 876 } 877 878 kfree(vals); 879 880 /* Enable Undefined Length INCR Burst and Enable INCRx Burst */ 881 cfg &= ~DWC3_GSBUSCFG0_INCRBRST_MASK; 882 if (incrx_mode) 883 cfg |= DWC3_GSBUSCFG0_INCRBRSTENA; 884 switch (incrx_size) { 885 case 256: 886 cfg |= DWC3_GSBUSCFG0_INCR256BRSTENA; 887 break; 888 case 128: 889 cfg |= DWC3_GSBUSCFG0_INCR128BRSTENA; 890 break; 891 case 64: 892 cfg |= DWC3_GSBUSCFG0_INCR64BRSTENA; 893 break; 894 case 32: 895 cfg |= DWC3_GSBUSCFG0_INCR32BRSTENA; 896 break; 897 case 16: 898 cfg |= DWC3_GSBUSCFG0_INCR16BRSTENA; 899 break; 900 case 8: 901 cfg |= DWC3_GSBUSCFG0_INCR8BRSTENA; 902 break; 903 case 4: 904 cfg |= DWC3_GSBUSCFG0_INCR4BRSTENA; 905 break; 906 case 1: 907 break; 908 default: 909 dev_err(dev, "Invalid property\n"); 910 break; 911 } 912 913 dwc3_writel(dwc->regs, DWC3_GSBUSCFG0, cfg); 914 } 915 916 /** 917 * dwc3_core_init - Low-level initialization of DWC3 Core 918 * @dwc: Pointer to our controller context structure 919 * 920 * Returns 0 on success otherwise negative errno. 921 */ 922 static int dwc3_core_init(struct dwc3 *dwc) 923 { 924 unsigned int hw_mode; 925 u32 reg; 926 int ret; 927 928 hw_mode = DWC3_GHWPARAMS0_MODE(dwc->hwparams.hwparams0); 929 930 /* 931 * Write Linux Version Code to our GUID register so it's easy to figure 932 * out which kernel version a bug was found. 933 */ 934 dwc3_writel(dwc->regs, DWC3_GUID, LINUX_VERSION_CODE); 935 936 /* Handle USB2.0-only core configuration */ 937 if (DWC3_GHWPARAMS3_SSPHY_IFC(dwc->hwparams.hwparams3) == 938 DWC3_GHWPARAMS3_SSPHY_IFC_DIS) { 939 if (dwc->maximum_speed == USB_SPEED_SUPER) 940 dwc->maximum_speed = USB_SPEED_HIGH; 941 } 942 943 ret = dwc3_phy_setup(dwc); 944 if (ret) 945 goto err0; 946 947 if (!dwc->ulpi_ready) { 948 ret = dwc3_core_ulpi_init(dwc); 949 if (ret) 950 goto err0; 951 dwc->ulpi_ready = true; 952 } 953 954 if (!dwc->phys_ready) { 955 ret = dwc3_core_get_phy(dwc); 956 if (ret) 957 goto err0a; 958 dwc->phys_ready = true; 959 } 960 961 ret = dwc3_core_soft_reset(dwc); 962 if (ret) 963 goto err0a; 964 965 if (hw_mode == DWC3_GHWPARAMS0_MODE_DRD && 966 dwc->revision > DWC3_REVISION_194A) { 967 if (!dwc->dis_u3_susphy_quirk) { 968 reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0)); 969 reg |= DWC3_GUSB3PIPECTL_SUSPHY; 970 dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg); 971 } 972 973 if (!dwc->dis_u2_susphy_quirk) { 974 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0)); 975 reg |= DWC3_GUSB2PHYCFG_SUSPHY; 976 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg); 977 } 978 } 979 980 dwc3_core_setup_global_control(dwc); 981 dwc3_core_num_eps(dwc); 982 983 ret = dwc3_setup_scratch_buffers(dwc); 984 if (ret) 985 goto err1; 986 987 /* Adjust Frame Length */ 988 dwc3_frame_length_adjustment(dwc); 989 990 dwc3_set_incr_burst_type(dwc); 991 992 usb_phy_set_suspend(dwc->usb2_phy, 0); 993 usb_phy_set_suspend(dwc->usb3_phy, 0); 994 ret = phy_power_on(dwc->usb2_generic_phy); 995 if (ret < 0) 996 goto err2; 997 998 ret = phy_power_on(dwc->usb3_generic_phy); 999 if (ret < 0) 1000 goto err3; 1001 1002 ret = dwc3_event_buffers_setup(dwc); 1003 if (ret) { 1004 dev_err(dwc->dev, "failed to setup event buffers\n"); 1005 goto err4; 1006 } 1007 1008 /* 1009 * ENDXFER polling is available on version 3.10a and later of 1010 * the DWC_usb3 controller. It is NOT available in the 1011 * DWC_usb31 controller. 1012 */ 1013 if (!dwc3_is_usb31(dwc) && dwc->revision >= DWC3_REVISION_310A) { 1014 reg = dwc3_readl(dwc->regs, DWC3_GUCTL2); 1015 reg |= DWC3_GUCTL2_RST_ACTBITLATER; 1016 dwc3_writel(dwc->regs, DWC3_GUCTL2, reg); 1017 } 1018 1019 if (dwc->revision >= DWC3_REVISION_250A) { 1020 reg = dwc3_readl(dwc->regs, DWC3_GUCTL1); 1021 1022 /* 1023 * Enable hardware control of sending remote wakeup 1024 * in HS when the device is in the L1 state. 1025 */ 1026 if (dwc->revision >= DWC3_REVISION_290A) 1027 reg |= DWC3_GUCTL1_DEV_L1_EXIT_BY_HW; 1028 1029 if (dwc->dis_tx_ipgap_linecheck_quirk) 1030 reg |= DWC3_GUCTL1_TX_IPGAP_LINECHECK_DIS; 1031 1032 dwc3_writel(dwc->regs, DWC3_GUCTL1, reg); 1033 } 1034 1035 if (dwc->dr_mode == USB_DR_MODE_HOST || 1036 dwc->dr_mode == USB_DR_MODE_OTG) { 1037 reg = dwc3_readl(dwc->regs, DWC3_GUCTL); 1038 1039 /* 1040 * Enable Auto retry Feature to make the controller operating in 1041 * Host mode on seeing transaction errors(CRC errors or internal 1042 * overrun scenerios) on IN transfers to reply to the device 1043 * with a non-terminating retry ACK (i.e, an ACK transcation 1044 * packet with Retry=1 & Nump != 0) 1045 */ 1046 reg |= DWC3_GUCTL_HSTINAUTORETRY; 1047 1048 dwc3_writel(dwc->regs, DWC3_GUCTL, reg); 1049 } 1050 1051 /* 1052 * Must config both number of packets and max burst settings to enable 1053 * RX and/or TX threshold. 1054 */ 1055 if (dwc3_is_usb31(dwc) && dwc->dr_mode == USB_DR_MODE_HOST) { 1056 u8 rx_thr_num = dwc->rx_thr_num_pkt_prd; 1057 u8 rx_maxburst = dwc->rx_max_burst_prd; 1058 u8 tx_thr_num = dwc->tx_thr_num_pkt_prd; 1059 u8 tx_maxburst = dwc->tx_max_burst_prd; 1060 1061 if (rx_thr_num && rx_maxburst) { 1062 reg = dwc3_readl(dwc->regs, DWC3_GRXTHRCFG); 1063 reg |= DWC31_RXTHRNUMPKTSEL_PRD; 1064 1065 reg &= ~DWC31_RXTHRNUMPKT_PRD(~0); 1066 reg |= DWC31_RXTHRNUMPKT_PRD(rx_thr_num); 1067 1068 reg &= ~DWC31_MAXRXBURSTSIZE_PRD(~0); 1069 reg |= DWC31_MAXRXBURSTSIZE_PRD(rx_maxburst); 1070 1071 dwc3_writel(dwc->regs, DWC3_GRXTHRCFG, reg); 1072 } 1073 1074 if (tx_thr_num && tx_maxburst) { 1075 reg = dwc3_readl(dwc->regs, DWC3_GTXTHRCFG); 1076 reg |= DWC31_TXTHRNUMPKTSEL_PRD; 1077 1078 reg &= ~DWC31_TXTHRNUMPKT_PRD(~0); 1079 reg |= DWC31_TXTHRNUMPKT_PRD(tx_thr_num); 1080 1081 reg &= ~DWC31_MAXTXBURSTSIZE_PRD(~0); 1082 reg |= DWC31_MAXTXBURSTSIZE_PRD(tx_maxburst); 1083 1084 dwc3_writel(dwc->regs, DWC3_GTXTHRCFG, reg); 1085 } 1086 } 1087 1088 return 0; 1089 1090 err4: 1091 phy_power_off(dwc->usb3_generic_phy); 1092 1093 err3: 1094 phy_power_off(dwc->usb2_generic_phy); 1095 1096 err2: 1097 usb_phy_set_suspend(dwc->usb2_phy, 1); 1098 usb_phy_set_suspend(dwc->usb3_phy, 1); 1099 1100 err1: 1101 usb_phy_shutdown(dwc->usb2_phy); 1102 usb_phy_shutdown(dwc->usb3_phy); 1103 phy_exit(dwc->usb2_generic_phy); 1104 phy_exit(dwc->usb3_generic_phy); 1105 1106 err0a: 1107 dwc3_ulpi_exit(dwc); 1108 1109 err0: 1110 return ret; 1111 } 1112 1113 static int dwc3_core_get_phy(struct dwc3 *dwc) 1114 { 1115 struct device *dev = dwc->dev; 1116 struct device_node *node = dev->of_node; 1117 int ret; 1118 1119 if (node) { 1120 dwc->usb2_phy = devm_usb_get_phy_by_phandle(dev, "usb-phy", 0); 1121 dwc->usb3_phy = devm_usb_get_phy_by_phandle(dev, "usb-phy", 1); 1122 } else { 1123 dwc->usb2_phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB2); 1124 dwc->usb3_phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB3); 1125 } 1126 1127 if (IS_ERR(dwc->usb2_phy)) { 1128 ret = PTR_ERR(dwc->usb2_phy); 1129 if (ret == -ENXIO || ret == -ENODEV) { 1130 dwc->usb2_phy = NULL; 1131 } else if (ret == -EPROBE_DEFER) { 1132 return ret; 1133 } else { 1134 dev_err(dev, "no usb2 phy configured\n"); 1135 return ret; 1136 } 1137 } 1138 1139 if (IS_ERR(dwc->usb3_phy)) { 1140 ret = PTR_ERR(dwc->usb3_phy); 1141 if (ret == -ENXIO || ret == -ENODEV) { 1142 dwc->usb3_phy = NULL; 1143 } else if (ret == -EPROBE_DEFER) { 1144 return ret; 1145 } else { 1146 dev_err(dev, "no usb3 phy configured\n"); 1147 return ret; 1148 } 1149 } 1150 1151 dwc->usb2_generic_phy = devm_phy_get(dev, "usb2-phy"); 1152 if (IS_ERR(dwc->usb2_generic_phy)) { 1153 ret = PTR_ERR(dwc->usb2_generic_phy); 1154 if (ret == -ENOSYS || ret == -ENODEV) { 1155 dwc->usb2_generic_phy = NULL; 1156 } else if (ret == -EPROBE_DEFER) { 1157 return ret; 1158 } else { 1159 dev_err(dev, "no usb2 phy configured\n"); 1160 return ret; 1161 } 1162 } 1163 1164 dwc->usb3_generic_phy = devm_phy_get(dev, "usb3-phy"); 1165 if (IS_ERR(dwc->usb3_generic_phy)) { 1166 ret = PTR_ERR(dwc->usb3_generic_phy); 1167 if (ret == -ENOSYS || ret == -ENODEV) { 1168 dwc->usb3_generic_phy = NULL; 1169 } else if (ret == -EPROBE_DEFER) { 1170 return ret; 1171 } else { 1172 dev_err(dev, "no usb3 phy configured\n"); 1173 return ret; 1174 } 1175 } 1176 1177 return 0; 1178 } 1179 1180 static int dwc3_core_init_mode(struct dwc3 *dwc) 1181 { 1182 struct device *dev = dwc->dev; 1183 int ret; 1184 1185 switch (dwc->dr_mode) { 1186 case USB_DR_MODE_PERIPHERAL: 1187 dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_DEVICE); 1188 1189 if (dwc->usb2_phy) 1190 otg_set_vbus(dwc->usb2_phy->otg, false); 1191 phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_DEVICE); 1192 phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_DEVICE); 1193 1194 ret = dwc3_gadget_init(dwc); 1195 if (ret) { 1196 if (ret != -EPROBE_DEFER) 1197 dev_err(dev, "failed to initialize gadget\n"); 1198 return ret; 1199 } 1200 break; 1201 case USB_DR_MODE_HOST: 1202 dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_HOST); 1203 1204 if (dwc->usb2_phy) 1205 otg_set_vbus(dwc->usb2_phy->otg, true); 1206 phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_HOST); 1207 phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_HOST); 1208 1209 ret = dwc3_host_init(dwc); 1210 if (ret) { 1211 if (ret != -EPROBE_DEFER) 1212 dev_err(dev, "failed to initialize host\n"); 1213 return ret; 1214 } 1215 break; 1216 case USB_DR_MODE_OTG: 1217 INIT_WORK(&dwc->drd_work, __dwc3_set_mode); 1218 ret = dwc3_drd_init(dwc); 1219 if (ret) { 1220 if (ret != -EPROBE_DEFER) 1221 dev_err(dev, "failed to initialize dual-role\n"); 1222 return ret; 1223 } 1224 break; 1225 default: 1226 dev_err(dev, "Unsupported mode of operation %d\n", dwc->dr_mode); 1227 return -EINVAL; 1228 } 1229 1230 return 0; 1231 } 1232 1233 static void dwc3_core_exit_mode(struct dwc3 *dwc) 1234 { 1235 switch (dwc->dr_mode) { 1236 case USB_DR_MODE_PERIPHERAL: 1237 dwc3_gadget_exit(dwc); 1238 break; 1239 case USB_DR_MODE_HOST: 1240 dwc3_host_exit(dwc); 1241 break; 1242 case USB_DR_MODE_OTG: 1243 dwc3_drd_exit(dwc); 1244 break; 1245 default: 1246 /* do nothing */ 1247 break; 1248 } 1249 1250 /* de-assert DRVVBUS for HOST and OTG mode */ 1251 dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_DEVICE); 1252 } 1253 1254 static void dwc3_get_properties(struct dwc3 *dwc) 1255 { 1256 struct device *dev = dwc->dev; 1257 u8 lpm_nyet_threshold; 1258 u8 tx_de_emphasis; 1259 u8 hird_threshold; 1260 u8 rx_thr_num_pkt_prd; 1261 u8 rx_max_burst_prd; 1262 u8 tx_thr_num_pkt_prd; 1263 u8 tx_max_burst_prd; 1264 1265 /* default to highest possible threshold */ 1266 lpm_nyet_threshold = 0xf; 1267 1268 /* default to -3.5dB de-emphasis */ 1269 tx_de_emphasis = 1; 1270 1271 /* 1272 * default to assert utmi_sleep_n and use maximum allowed HIRD 1273 * threshold value of 0b1100 1274 */ 1275 hird_threshold = 12; 1276 1277 dwc->maximum_speed = usb_get_maximum_speed(dev); 1278 dwc->dr_mode = usb_get_dr_mode(dev); 1279 dwc->hsphy_mode = of_usb_get_phy_mode(dev->of_node); 1280 1281 dwc->sysdev_is_parent = device_property_read_bool(dev, 1282 "linux,sysdev_is_parent"); 1283 if (dwc->sysdev_is_parent) 1284 dwc->sysdev = dwc->dev->parent; 1285 else 1286 dwc->sysdev = dwc->dev; 1287 1288 dwc->has_lpm_erratum = device_property_read_bool(dev, 1289 "snps,has-lpm-erratum"); 1290 device_property_read_u8(dev, "snps,lpm-nyet-threshold", 1291 &lpm_nyet_threshold); 1292 dwc->is_utmi_l1_suspend = device_property_read_bool(dev, 1293 "snps,is-utmi-l1-suspend"); 1294 device_property_read_u8(dev, "snps,hird-threshold", 1295 &hird_threshold); 1296 dwc->dis_start_transfer_quirk = device_property_read_bool(dev, 1297 "snps,dis-start-transfer-quirk"); 1298 dwc->usb3_lpm_capable = device_property_read_bool(dev, 1299 "snps,usb3_lpm_capable"); 1300 dwc->usb2_lpm_disable = device_property_read_bool(dev, 1301 "snps,usb2-lpm-disable"); 1302 device_property_read_u8(dev, "snps,rx-thr-num-pkt-prd", 1303 &rx_thr_num_pkt_prd); 1304 device_property_read_u8(dev, "snps,rx-max-burst-prd", 1305 &rx_max_burst_prd); 1306 device_property_read_u8(dev, "snps,tx-thr-num-pkt-prd", 1307 &tx_thr_num_pkt_prd); 1308 device_property_read_u8(dev, "snps,tx-max-burst-prd", 1309 &tx_max_burst_prd); 1310 1311 dwc->disable_scramble_quirk = device_property_read_bool(dev, 1312 "snps,disable_scramble_quirk"); 1313 dwc->u2exit_lfps_quirk = device_property_read_bool(dev, 1314 "snps,u2exit_lfps_quirk"); 1315 dwc->u2ss_inp3_quirk = device_property_read_bool(dev, 1316 "snps,u2ss_inp3_quirk"); 1317 dwc->req_p1p2p3_quirk = device_property_read_bool(dev, 1318 "snps,req_p1p2p3_quirk"); 1319 dwc->del_p1p2p3_quirk = device_property_read_bool(dev, 1320 "snps,del_p1p2p3_quirk"); 1321 dwc->del_phy_power_chg_quirk = device_property_read_bool(dev, 1322 "snps,del_phy_power_chg_quirk"); 1323 dwc->lfps_filter_quirk = device_property_read_bool(dev, 1324 "snps,lfps_filter_quirk"); 1325 dwc->rx_detect_poll_quirk = device_property_read_bool(dev, 1326 "snps,rx_detect_poll_quirk"); 1327 dwc->dis_u3_susphy_quirk = device_property_read_bool(dev, 1328 "snps,dis_u3_susphy_quirk"); 1329 dwc->dis_u2_susphy_quirk = device_property_read_bool(dev, 1330 "snps,dis_u2_susphy_quirk"); 1331 dwc->dis_enblslpm_quirk = device_property_read_bool(dev, 1332 "snps,dis_enblslpm_quirk"); 1333 dwc->dis_u1_entry_quirk = device_property_read_bool(dev, 1334 "snps,dis-u1-entry-quirk"); 1335 dwc->dis_u2_entry_quirk = device_property_read_bool(dev, 1336 "snps,dis-u2-entry-quirk"); 1337 dwc->dis_rxdet_inp3_quirk = device_property_read_bool(dev, 1338 "snps,dis_rxdet_inp3_quirk"); 1339 dwc->dis_u2_freeclk_exists_quirk = device_property_read_bool(dev, 1340 "snps,dis-u2-freeclk-exists-quirk"); 1341 dwc->dis_del_phy_power_chg_quirk = device_property_read_bool(dev, 1342 "snps,dis-del-phy-power-chg-quirk"); 1343 dwc->dis_tx_ipgap_linecheck_quirk = device_property_read_bool(dev, 1344 "snps,dis-tx-ipgap-linecheck-quirk"); 1345 1346 dwc->tx_de_emphasis_quirk = device_property_read_bool(dev, 1347 "snps,tx_de_emphasis_quirk"); 1348 device_property_read_u8(dev, "snps,tx_de_emphasis", 1349 &tx_de_emphasis); 1350 device_property_read_string(dev, "snps,hsphy_interface", 1351 &dwc->hsphy_interface); 1352 device_property_read_u32(dev, "snps,quirk-frame-length-adjustment", 1353 &dwc->fladj); 1354 1355 dwc->dis_metastability_quirk = device_property_read_bool(dev, 1356 "snps,dis_metastability_quirk"); 1357 1358 dwc->lpm_nyet_threshold = lpm_nyet_threshold; 1359 dwc->tx_de_emphasis = tx_de_emphasis; 1360 1361 dwc->hird_threshold = hird_threshold; 1362 1363 dwc->rx_thr_num_pkt_prd = rx_thr_num_pkt_prd; 1364 dwc->rx_max_burst_prd = rx_max_burst_prd; 1365 1366 dwc->tx_thr_num_pkt_prd = tx_thr_num_pkt_prd; 1367 dwc->tx_max_burst_prd = tx_max_burst_prd; 1368 1369 dwc->imod_interval = 0; 1370 } 1371 1372 /* check whether the core supports IMOD */ 1373 bool dwc3_has_imod(struct dwc3 *dwc) 1374 { 1375 return ((dwc3_is_usb3(dwc) && 1376 dwc->revision >= DWC3_REVISION_300A) || 1377 (dwc3_is_usb31(dwc) && 1378 dwc->revision >= DWC3_USB31_REVISION_120A)); 1379 } 1380 1381 static void dwc3_check_params(struct dwc3 *dwc) 1382 { 1383 struct device *dev = dwc->dev; 1384 1385 /* Check for proper value of imod_interval */ 1386 if (dwc->imod_interval && !dwc3_has_imod(dwc)) { 1387 dev_warn(dwc->dev, "Interrupt moderation not supported\n"); 1388 dwc->imod_interval = 0; 1389 } 1390 1391 /* 1392 * Workaround for STAR 9000961433 which affects only version 1393 * 3.00a of the DWC_usb3 core. This prevents the controller 1394 * interrupt from being masked while handling events. IMOD 1395 * allows us to work around this issue. Enable it for the 1396 * affected version. 1397 */ 1398 if (!dwc->imod_interval && 1399 (dwc->revision == DWC3_REVISION_300A)) 1400 dwc->imod_interval = 1; 1401 1402 /* Check the maximum_speed parameter */ 1403 switch (dwc->maximum_speed) { 1404 case USB_SPEED_LOW: 1405 case USB_SPEED_FULL: 1406 case USB_SPEED_HIGH: 1407 case USB_SPEED_SUPER: 1408 case USB_SPEED_SUPER_PLUS: 1409 break; 1410 default: 1411 dev_err(dev, "invalid maximum_speed parameter %d\n", 1412 dwc->maximum_speed); 1413 /* fall through */ 1414 case USB_SPEED_UNKNOWN: 1415 /* default to superspeed */ 1416 dwc->maximum_speed = USB_SPEED_SUPER; 1417 1418 /* 1419 * default to superspeed plus if we are capable. 1420 */ 1421 if (dwc3_is_usb31(dwc) && 1422 (DWC3_GHWPARAMS3_SSPHY_IFC(dwc->hwparams.hwparams3) == 1423 DWC3_GHWPARAMS3_SSPHY_IFC_GEN2)) 1424 dwc->maximum_speed = USB_SPEED_SUPER_PLUS; 1425 1426 break; 1427 } 1428 } 1429 1430 static int dwc3_probe(struct platform_device *pdev) 1431 { 1432 struct device *dev = &pdev->dev; 1433 struct resource *res, dwc_res; 1434 struct dwc3 *dwc; 1435 1436 int ret; 1437 1438 void __iomem *regs; 1439 1440 dwc = devm_kzalloc(dev, sizeof(*dwc), GFP_KERNEL); 1441 if (!dwc) 1442 return -ENOMEM; 1443 1444 dwc->clks = devm_kmemdup(dev, dwc3_core_clks, sizeof(dwc3_core_clks), 1445 GFP_KERNEL); 1446 if (!dwc->clks) 1447 return -ENOMEM; 1448 1449 dwc->dev = dev; 1450 1451 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1452 if (!res) { 1453 dev_err(dev, "missing memory resource\n"); 1454 return -ENODEV; 1455 } 1456 1457 dwc->xhci_resources[0].start = res->start; 1458 dwc->xhci_resources[0].end = dwc->xhci_resources[0].start + 1459 DWC3_XHCI_REGS_END; 1460 dwc->xhci_resources[0].flags = res->flags; 1461 dwc->xhci_resources[0].name = res->name; 1462 1463 /* 1464 * Request memory region but exclude xHCI regs, 1465 * since it will be requested by the xhci-plat driver. 1466 */ 1467 dwc_res = *res; 1468 dwc_res.start += DWC3_GLOBALS_REGS_START; 1469 1470 regs = devm_ioremap_resource(dev, &dwc_res); 1471 if (IS_ERR(regs)) 1472 return PTR_ERR(regs); 1473 1474 dwc->regs = regs; 1475 dwc->regs_size = resource_size(&dwc_res); 1476 1477 dwc3_get_properties(dwc); 1478 1479 dwc->reset = devm_reset_control_get_optional_shared(dev, NULL); 1480 if (IS_ERR(dwc->reset)) 1481 return PTR_ERR(dwc->reset); 1482 1483 if (dev->of_node) { 1484 dwc->num_clks = ARRAY_SIZE(dwc3_core_clks); 1485 1486 ret = devm_clk_bulk_get(dev, dwc->num_clks, dwc->clks); 1487 if (ret == -EPROBE_DEFER) 1488 return ret; 1489 /* 1490 * Clocks are optional, but new DT platforms should support all 1491 * clocks as required by the DT-binding. 1492 */ 1493 if (ret) 1494 dwc->num_clks = 0; 1495 } 1496 1497 ret = reset_control_deassert(dwc->reset); 1498 if (ret) 1499 return ret; 1500 1501 ret = clk_bulk_prepare_enable(dwc->num_clks, dwc->clks); 1502 if (ret) 1503 goto assert_reset; 1504 1505 if (!dwc3_core_is_valid(dwc)) { 1506 dev_err(dwc->dev, "this is not a DesignWare USB3 DRD Core\n"); 1507 ret = -ENODEV; 1508 goto disable_clks; 1509 } 1510 1511 platform_set_drvdata(pdev, dwc); 1512 dwc3_cache_hwparams(dwc); 1513 1514 spin_lock_init(&dwc->lock); 1515 1516 pm_runtime_set_active(dev); 1517 pm_runtime_use_autosuspend(dev); 1518 pm_runtime_set_autosuspend_delay(dev, DWC3_DEFAULT_AUTOSUSPEND_DELAY); 1519 pm_runtime_enable(dev); 1520 ret = pm_runtime_get_sync(dev); 1521 if (ret < 0) 1522 goto err1; 1523 1524 pm_runtime_forbid(dev); 1525 1526 ret = dwc3_alloc_event_buffers(dwc, DWC3_EVENT_BUFFERS_SIZE); 1527 if (ret) { 1528 dev_err(dwc->dev, "failed to allocate event buffers\n"); 1529 ret = -ENOMEM; 1530 goto err2; 1531 } 1532 1533 ret = dwc3_get_dr_mode(dwc); 1534 if (ret) 1535 goto err3; 1536 1537 ret = dwc3_alloc_scratch_buffers(dwc); 1538 if (ret) 1539 goto err3; 1540 1541 ret = dwc3_core_init(dwc); 1542 if (ret) { 1543 if (ret != -EPROBE_DEFER) 1544 dev_err(dev, "failed to initialize core: %d\n", ret); 1545 goto err4; 1546 } 1547 1548 dwc3_check_params(dwc); 1549 1550 ret = dwc3_core_init_mode(dwc); 1551 if (ret) 1552 goto err5; 1553 1554 dwc3_debugfs_init(dwc); 1555 pm_runtime_put(dev); 1556 1557 return 0; 1558 1559 err5: 1560 dwc3_event_buffers_cleanup(dwc); 1561 dwc3_ulpi_exit(dwc); 1562 1563 err4: 1564 dwc3_free_scratch_buffers(dwc); 1565 1566 err3: 1567 dwc3_free_event_buffers(dwc); 1568 1569 err2: 1570 pm_runtime_allow(&pdev->dev); 1571 1572 err1: 1573 pm_runtime_put_sync(&pdev->dev); 1574 pm_runtime_disable(&pdev->dev); 1575 1576 disable_clks: 1577 clk_bulk_disable_unprepare(dwc->num_clks, dwc->clks); 1578 assert_reset: 1579 reset_control_assert(dwc->reset); 1580 1581 return ret; 1582 } 1583 1584 static int dwc3_remove(struct platform_device *pdev) 1585 { 1586 struct dwc3 *dwc = platform_get_drvdata(pdev); 1587 1588 pm_runtime_get_sync(&pdev->dev); 1589 1590 dwc3_debugfs_exit(dwc); 1591 dwc3_core_exit_mode(dwc); 1592 1593 dwc3_core_exit(dwc); 1594 dwc3_ulpi_exit(dwc); 1595 1596 pm_runtime_put_sync(&pdev->dev); 1597 pm_runtime_allow(&pdev->dev); 1598 pm_runtime_disable(&pdev->dev); 1599 1600 dwc3_free_event_buffers(dwc); 1601 dwc3_free_scratch_buffers(dwc); 1602 1603 return 0; 1604 } 1605 1606 #ifdef CONFIG_PM 1607 static int dwc3_core_init_for_resume(struct dwc3 *dwc) 1608 { 1609 int ret; 1610 1611 ret = reset_control_deassert(dwc->reset); 1612 if (ret) 1613 return ret; 1614 1615 ret = clk_bulk_prepare_enable(dwc->num_clks, dwc->clks); 1616 if (ret) 1617 goto assert_reset; 1618 1619 ret = dwc3_core_init(dwc); 1620 if (ret) 1621 goto disable_clks; 1622 1623 return 0; 1624 1625 disable_clks: 1626 clk_bulk_disable_unprepare(dwc->num_clks, dwc->clks); 1627 assert_reset: 1628 reset_control_assert(dwc->reset); 1629 1630 return ret; 1631 } 1632 1633 static int dwc3_suspend_common(struct dwc3 *dwc, pm_message_t msg) 1634 { 1635 unsigned long flags; 1636 u32 reg; 1637 1638 switch (dwc->current_dr_role) { 1639 case DWC3_GCTL_PRTCAP_DEVICE: 1640 spin_lock_irqsave(&dwc->lock, flags); 1641 dwc3_gadget_suspend(dwc); 1642 spin_unlock_irqrestore(&dwc->lock, flags); 1643 synchronize_irq(dwc->irq_gadget); 1644 dwc3_core_exit(dwc); 1645 break; 1646 case DWC3_GCTL_PRTCAP_HOST: 1647 if (!PMSG_IS_AUTO(msg)) { 1648 dwc3_core_exit(dwc); 1649 break; 1650 } 1651 1652 /* Let controller to suspend HSPHY before PHY driver suspends */ 1653 if (dwc->dis_u2_susphy_quirk || 1654 dwc->dis_enblslpm_quirk) { 1655 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0)); 1656 reg |= DWC3_GUSB2PHYCFG_ENBLSLPM | 1657 DWC3_GUSB2PHYCFG_SUSPHY; 1658 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg); 1659 1660 /* Give some time for USB2 PHY to suspend */ 1661 usleep_range(5000, 6000); 1662 } 1663 1664 phy_pm_runtime_put_sync(dwc->usb2_generic_phy); 1665 phy_pm_runtime_put_sync(dwc->usb3_generic_phy); 1666 break; 1667 case DWC3_GCTL_PRTCAP_OTG: 1668 /* do nothing during runtime_suspend */ 1669 if (PMSG_IS_AUTO(msg)) 1670 break; 1671 1672 if (dwc->current_otg_role == DWC3_OTG_ROLE_DEVICE) { 1673 spin_lock_irqsave(&dwc->lock, flags); 1674 dwc3_gadget_suspend(dwc); 1675 spin_unlock_irqrestore(&dwc->lock, flags); 1676 synchronize_irq(dwc->irq_gadget); 1677 } 1678 1679 dwc3_otg_exit(dwc); 1680 dwc3_core_exit(dwc); 1681 break; 1682 default: 1683 /* do nothing */ 1684 break; 1685 } 1686 1687 return 0; 1688 } 1689 1690 static int dwc3_resume_common(struct dwc3 *dwc, pm_message_t msg) 1691 { 1692 unsigned long flags; 1693 int ret; 1694 u32 reg; 1695 1696 switch (dwc->current_dr_role) { 1697 case DWC3_GCTL_PRTCAP_DEVICE: 1698 ret = dwc3_core_init_for_resume(dwc); 1699 if (ret) 1700 return ret; 1701 1702 dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_DEVICE); 1703 spin_lock_irqsave(&dwc->lock, flags); 1704 dwc3_gadget_resume(dwc); 1705 spin_unlock_irqrestore(&dwc->lock, flags); 1706 break; 1707 case DWC3_GCTL_PRTCAP_HOST: 1708 if (!PMSG_IS_AUTO(msg)) { 1709 ret = dwc3_core_init_for_resume(dwc); 1710 if (ret) 1711 return ret; 1712 dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_HOST); 1713 break; 1714 } 1715 /* Restore GUSB2PHYCFG bits that were modified in suspend */ 1716 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0)); 1717 if (dwc->dis_u2_susphy_quirk) 1718 reg &= ~DWC3_GUSB2PHYCFG_SUSPHY; 1719 1720 if (dwc->dis_enblslpm_quirk) 1721 reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM; 1722 1723 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg); 1724 1725 phy_pm_runtime_get_sync(dwc->usb2_generic_phy); 1726 phy_pm_runtime_get_sync(dwc->usb3_generic_phy); 1727 break; 1728 case DWC3_GCTL_PRTCAP_OTG: 1729 /* nothing to do on runtime_resume */ 1730 if (PMSG_IS_AUTO(msg)) 1731 break; 1732 1733 ret = dwc3_core_init(dwc); 1734 if (ret) 1735 return ret; 1736 1737 dwc3_set_prtcap(dwc, dwc->current_dr_role); 1738 1739 dwc3_otg_init(dwc); 1740 if (dwc->current_otg_role == DWC3_OTG_ROLE_HOST) { 1741 dwc3_otg_host_init(dwc); 1742 } else if (dwc->current_otg_role == DWC3_OTG_ROLE_DEVICE) { 1743 spin_lock_irqsave(&dwc->lock, flags); 1744 dwc3_gadget_resume(dwc); 1745 spin_unlock_irqrestore(&dwc->lock, flags); 1746 } 1747 1748 break; 1749 default: 1750 /* do nothing */ 1751 break; 1752 } 1753 1754 return 0; 1755 } 1756 1757 static int dwc3_runtime_checks(struct dwc3 *dwc) 1758 { 1759 switch (dwc->current_dr_role) { 1760 case DWC3_GCTL_PRTCAP_DEVICE: 1761 if (dwc->connected) 1762 return -EBUSY; 1763 break; 1764 case DWC3_GCTL_PRTCAP_HOST: 1765 default: 1766 /* do nothing */ 1767 break; 1768 } 1769 1770 return 0; 1771 } 1772 1773 static int dwc3_runtime_suspend(struct device *dev) 1774 { 1775 struct dwc3 *dwc = dev_get_drvdata(dev); 1776 int ret; 1777 1778 if (dwc3_runtime_checks(dwc)) 1779 return -EBUSY; 1780 1781 ret = dwc3_suspend_common(dwc, PMSG_AUTO_SUSPEND); 1782 if (ret) 1783 return ret; 1784 1785 device_init_wakeup(dev, true); 1786 1787 return 0; 1788 } 1789 1790 static int dwc3_runtime_resume(struct device *dev) 1791 { 1792 struct dwc3 *dwc = dev_get_drvdata(dev); 1793 int ret; 1794 1795 device_init_wakeup(dev, false); 1796 1797 ret = dwc3_resume_common(dwc, PMSG_AUTO_RESUME); 1798 if (ret) 1799 return ret; 1800 1801 switch (dwc->current_dr_role) { 1802 case DWC3_GCTL_PRTCAP_DEVICE: 1803 dwc3_gadget_process_pending_events(dwc); 1804 break; 1805 case DWC3_GCTL_PRTCAP_HOST: 1806 default: 1807 /* do nothing */ 1808 break; 1809 } 1810 1811 pm_runtime_mark_last_busy(dev); 1812 1813 return 0; 1814 } 1815 1816 static int dwc3_runtime_idle(struct device *dev) 1817 { 1818 struct dwc3 *dwc = dev_get_drvdata(dev); 1819 1820 switch (dwc->current_dr_role) { 1821 case DWC3_GCTL_PRTCAP_DEVICE: 1822 if (dwc3_runtime_checks(dwc)) 1823 return -EBUSY; 1824 break; 1825 case DWC3_GCTL_PRTCAP_HOST: 1826 default: 1827 /* do nothing */ 1828 break; 1829 } 1830 1831 pm_runtime_mark_last_busy(dev); 1832 pm_runtime_autosuspend(dev); 1833 1834 return 0; 1835 } 1836 #endif /* CONFIG_PM */ 1837 1838 #ifdef CONFIG_PM_SLEEP 1839 static int dwc3_suspend(struct device *dev) 1840 { 1841 struct dwc3 *dwc = dev_get_drvdata(dev); 1842 int ret; 1843 1844 ret = dwc3_suspend_common(dwc, PMSG_SUSPEND); 1845 if (ret) 1846 return ret; 1847 1848 pinctrl_pm_select_sleep_state(dev); 1849 1850 return 0; 1851 } 1852 1853 static int dwc3_resume(struct device *dev) 1854 { 1855 struct dwc3 *dwc = dev_get_drvdata(dev); 1856 int ret; 1857 1858 pinctrl_pm_select_default_state(dev); 1859 1860 ret = dwc3_resume_common(dwc, PMSG_RESUME); 1861 if (ret) 1862 return ret; 1863 1864 pm_runtime_disable(dev); 1865 pm_runtime_set_active(dev); 1866 pm_runtime_enable(dev); 1867 1868 return 0; 1869 } 1870 #endif /* CONFIG_PM_SLEEP */ 1871 1872 static const struct dev_pm_ops dwc3_dev_pm_ops = { 1873 SET_SYSTEM_SLEEP_PM_OPS(dwc3_suspend, dwc3_resume) 1874 SET_RUNTIME_PM_OPS(dwc3_runtime_suspend, dwc3_runtime_resume, 1875 dwc3_runtime_idle) 1876 }; 1877 1878 #ifdef CONFIG_OF 1879 static const struct of_device_id of_dwc3_match[] = { 1880 { 1881 .compatible = "snps,dwc3" 1882 }, 1883 { 1884 .compatible = "synopsys,dwc3" 1885 }, 1886 { }, 1887 }; 1888 MODULE_DEVICE_TABLE(of, of_dwc3_match); 1889 #endif 1890 1891 #ifdef CONFIG_ACPI 1892 1893 #define ACPI_ID_INTEL_BSW "808622B7" 1894 1895 static const struct acpi_device_id dwc3_acpi_match[] = { 1896 { ACPI_ID_INTEL_BSW, 0 }, 1897 { }, 1898 }; 1899 MODULE_DEVICE_TABLE(acpi, dwc3_acpi_match); 1900 #endif 1901 1902 static struct platform_driver dwc3_driver = { 1903 .probe = dwc3_probe, 1904 .remove = dwc3_remove, 1905 .driver = { 1906 .name = "dwc3", 1907 .of_match_table = of_match_ptr(of_dwc3_match), 1908 .acpi_match_table = ACPI_PTR(dwc3_acpi_match), 1909 .pm = &dwc3_dev_pm_ops, 1910 }, 1911 }; 1912 1913 module_platform_driver(dwc3_driver); 1914 1915 MODULE_ALIAS("platform:dwc3"); 1916 MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>"); 1917 MODULE_LICENSE("GPL v2"); 1918 MODULE_DESCRIPTION("DesignWare USB3 DRD Controller Driver"); 1919