1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * core.c - DesignWare USB3 DRD Controller Core file 4 * 5 * Copyright (C) 2010-2011 Texas Instruments Incorporated - https://www.ti.com 6 * 7 * Authors: Felipe Balbi <balbi@ti.com>, 8 * Sebastian Andrzej Siewior <bigeasy@linutronix.de> 9 */ 10 11 #include <linux/clk.h> 12 #include <linux/version.h> 13 #include <linux/module.h> 14 #include <linux/kernel.h> 15 #include <linux/slab.h> 16 #include <linux/spinlock.h> 17 #include <linux/platform_device.h> 18 #include <linux/pm_runtime.h> 19 #include <linux/interrupt.h> 20 #include <linux/ioport.h> 21 #include <linux/io.h> 22 #include <linux/list.h> 23 #include <linux/delay.h> 24 #include <linux/dma-mapping.h> 25 #include <linux/of.h> 26 #include <linux/of_graph.h> 27 #include <linux/acpi.h> 28 #include <linux/pinctrl/consumer.h> 29 #include <linux/reset.h> 30 #include <linux/bitfield.h> 31 32 #include <linux/usb/ch9.h> 33 #include <linux/usb/gadget.h> 34 #include <linux/usb/of.h> 35 #include <linux/usb/otg.h> 36 37 #include "core.h" 38 #include "gadget.h" 39 #include "io.h" 40 41 #include "debug.h" 42 43 #define DWC3_DEFAULT_AUTOSUSPEND_DELAY 5000 /* ms */ 44 45 /** 46 * dwc3_get_dr_mode - Validates and sets dr_mode 47 * @dwc: pointer to our context structure 48 */ 49 static int dwc3_get_dr_mode(struct dwc3 *dwc) 50 { 51 enum usb_dr_mode mode; 52 struct device *dev = dwc->dev; 53 unsigned int hw_mode; 54 55 if (dwc->dr_mode == USB_DR_MODE_UNKNOWN) 56 dwc->dr_mode = USB_DR_MODE_OTG; 57 58 mode = dwc->dr_mode; 59 hw_mode = DWC3_GHWPARAMS0_MODE(dwc->hwparams.hwparams0); 60 61 switch (hw_mode) { 62 case DWC3_GHWPARAMS0_MODE_GADGET: 63 if (IS_ENABLED(CONFIG_USB_DWC3_HOST)) { 64 dev_err(dev, 65 "Controller does not support host mode.\n"); 66 return -EINVAL; 67 } 68 mode = USB_DR_MODE_PERIPHERAL; 69 break; 70 case DWC3_GHWPARAMS0_MODE_HOST: 71 if (IS_ENABLED(CONFIG_USB_DWC3_GADGET)) { 72 dev_err(dev, 73 "Controller does not support device mode.\n"); 74 return -EINVAL; 75 } 76 mode = USB_DR_MODE_HOST; 77 break; 78 default: 79 if (IS_ENABLED(CONFIG_USB_DWC3_HOST)) 80 mode = USB_DR_MODE_HOST; 81 else if (IS_ENABLED(CONFIG_USB_DWC3_GADGET)) 82 mode = USB_DR_MODE_PERIPHERAL; 83 84 /* 85 * DWC_usb31 and DWC_usb3 v3.30a and higher do not support OTG 86 * mode. If the controller supports DRD but the dr_mode is not 87 * specified or set to OTG, then set the mode to peripheral. 88 */ 89 if (mode == USB_DR_MODE_OTG && !dwc->edev && 90 (!IS_ENABLED(CONFIG_USB_ROLE_SWITCH) || 91 !device_property_read_bool(dwc->dev, "usb-role-switch")) && 92 !DWC3_VER_IS_PRIOR(DWC3, 330A)) 93 mode = USB_DR_MODE_PERIPHERAL; 94 } 95 96 if (mode != dwc->dr_mode) { 97 dev_warn(dev, 98 "Configuration mismatch. dr_mode forced to %s\n", 99 mode == USB_DR_MODE_HOST ? "host" : "gadget"); 100 101 dwc->dr_mode = mode; 102 } 103 104 return 0; 105 } 106 107 void dwc3_set_prtcap(struct dwc3 *dwc, u32 mode) 108 { 109 u32 reg; 110 111 reg = dwc3_readl(dwc->regs, DWC3_GCTL); 112 reg &= ~(DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_OTG)); 113 reg |= DWC3_GCTL_PRTCAPDIR(mode); 114 dwc3_writel(dwc->regs, DWC3_GCTL, reg); 115 116 dwc->current_dr_role = mode; 117 } 118 119 static void __dwc3_set_mode(struct work_struct *work) 120 { 121 struct dwc3 *dwc = work_to_dwc(work); 122 unsigned long flags; 123 int ret; 124 u32 reg; 125 126 mutex_lock(&dwc->mutex); 127 128 pm_runtime_get_sync(dwc->dev); 129 130 if (dwc->current_dr_role == DWC3_GCTL_PRTCAP_OTG) 131 dwc3_otg_update(dwc, 0); 132 133 if (!dwc->desired_dr_role) 134 goto out; 135 136 if (dwc->desired_dr_role == dwc->current_dr_role) 137 goto out; 138 139 if (dwc->desired_dr_role == DWC3_GCTL_PRTCAP_OTG && dwc->edev) 140 goto out; 141 142 switch (dwc->current_dr_role) { 143 case DWC3_GCTL_PRTCAP_HOST: 144 dwc3_host_exit(dwc); 145 break; 146 case DWC3_GCTL_PRTCAP_DEVICE: 147 dwc3_gadget_exit(dwc); 148 dwc3_event_buffers_cleanup(dwc); 149 break; 150 case DWC3_GCTL_PRTCAP_OTG: 151 dwc3_otg_exit(dwc); 152 spin_lock_irqsave(&dwc->lock, flags); 153 dwc->desired_otg_role = DWC3_OTG_ROLE_IDLE; 154 spin_unlock_irqrestore(&dwc->lock, flags); 155 dwc3_otg_update(dwc, 1); 156 break; 157 default: 158 break; 159 } 160 161 /* 162 * When current_dr_role is not set, there's no role switching. 163 * Only perform GCTL.CoreSoftReset when there's DRD role switching. 164 */ 165 if (dwc->current_dr_role && ((DWC3_IP_IS(DWC3) || 166 DWC3_VER_IS_PRIOR(DWC31, 190A)) && 167 dwc->desired_dr_role != DWC3_GCTL_PRTCAP_OTG)) { 168 reg = dwc3_readl(dwc->regs, DWC3_GCTL); 169 reg |= DWC3_GCTL_CORESOFTRESET; 170 dwc3_writel(dwc->regs, DWC3_GCTL, reg); 171 172 /* 173 * Wait for internal clocks to synchronized. DWC_usb31 and 174 * DWC_usb32 may need at least 50ms (less for DWC_usb3). To 175 * keep it consistent across different IPs, let's wait up to 176 * 100ms before clearing GCTL.CORESOFTRESET. 177 */ 178 msleep(100); 179 180 reg = dwc3_readl(dwc->regs, DWC3_GCTL); 181 reg &= ~DWC3_GCTL_CORESOFTRESET; 182 dwc3_writel(dwc->regs, DWC3_GCTL, reg); 183 } 184 185 spin_lock_irqsave(&dwc->lock, flags); 186 187 dwc3_set_prtcap(dwc, dwc->desired_dr_role); 188 189 spin_unlock_irqrestore(&dwc->lock, flags); 190 191 switch (dwc->desired_dr_role) { 192 case DWC3_GCTL_PRTCAP_HOST: 193 ret = dwc3_host_init(dwc); 194 if (ret) { 195 dev_err(dwc->dev, "failed to initialize host\n"); 196 } else { 197 if (dwc->usb2_phy) 198 otg_set_vbus(dwc->usb2_phy->otg, true); 199 phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_HOST); 200 phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_HOST); 201 if (dwc->dis_split_quirk) { 202 reg = dwc3_readl(dwc->regs, DWC3_GUCTL3); 203 reg |= DWC3_GUCTL3_SPLITDISABLE; 204 dwc3_writel(dwc->regs, DWC3_GUCTL3, reg); 205 } 206 } 207 break; 208 case DWC3_GCTL_PRTCAP_DEVICE: 209 dwc3_core_soft_reset(dwc); 210 211 dwc3_event_buffers_setup(dwc); 212 213 if (dwc->usb2_phy) 214 otg_set_vbus(dwc->usb2_phy->otg, false); 215 phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_DEVICE); 216 phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_DEVICE); 217 218 ret = dwc3_gadget_init(dwc); 219 if (ret) 220 dev_err(dwc->dev, "failed to initialize peripheral\n"); 221 break; 222 case DWC3_GCTL_PRTCAP_OTG: 223 dwc3_otg_init(dwc); 224 dwc3_otg_update(dwc, 0); 225 break; 226 default: 227 break; 228 } 229 230 out: 231 pm_runtime_mark_last_busy(dwc->dev); 232 pm_runtime_put_autosuspend(dwc->dev); 233 mutex_unlock(&dwc->mutex); 234 } 235 236 void dwc3_set_mode(struct dwc3 *dwc, u32 mode) 237 { 238 unsigned long flags; 239 240 if (dwc->dr_mode != USB_DR_MODE_OTG) 241 return; 242 243 spin_lock_irqsave(&dwc->lock, flags); 244 dwc->desired_dr_role = mode; 245 spin_unlock_irqrestore(&dwc->lock, flags); 246 247 queue_work(system_freezable_wq, &dwc->drd_work); 248 } 249 250 u32 dwc3_core_fifo_space(struct dwc3_ep *dep, u8 type) 251 { 252 struct dwc3 *dwc = dep->dwc; 253 u32 reg; 254 255 dwc3_writel(dwc->regs, DWC3_GDBGFIFOSPACE, 256 DWC3_GDBGFIFOSPACE_NUM(dep->number) | 257 DWC3_GDBGFIFOSPACE_TYPE(type)); 258 259 reg = dwc3_readl(dwc->regs, DWC3_GDBGFIFOSPACE); 260 261 return DWC3_GDBGFIFOSPACE_SPACE_AVAILABLE(reg); 262 } 263 264 /** 265 * dwc3_core_soft_reset - Issues core soft reset and PHY reset 266 * @dwc: pointer to our context structure 267 */ 268 int dwc3_core_soft_reset(struct dwc3 *dwc) 269 { 270 u32 reg; 271 int retries = 1000; 272 273 /* 274 * We're resetting only the device side because, if we're in host mode, 275 * XHCI driver will reset the host block. If dwc3 was configured for 276 * host-only mode, then we can return early. 277 */ 278 if (dwc->current_dr_role == DWC3_GCTL_PRTCAP_HOST) 279 return 0; 280 281 reg = dwc3_readl(dwc->regs, DWC3_DCTL); 282 reg |= DWC3_DCTL_CSFTRST; 283 reg &= ~DWC3_DCTL_RUN_STOP; 284 dwc3_gadget_dctl_write_safe(dwc, reg); 285 286 /* 287 * For DWC_usb31 controller 1.90a and later, the DCTL.CSFRST bit 288 * is cleared only after all the clocks are synchronized. This can 289 * take a little more than 50ms. Set the polling rate at 20ms 290 * for 10 times instead. 291 */ 292 if (DWC3_VER_IS_WITHIN(DWC31, 190A, ANY) || DWC3_IP_IS(DWC32)) 293 retries = 10; 294 295 do { 296 reg = dwc3_readl(dwc->regs, DWC3_DCTL); 297 if (!(reg & DWC3_DCTL_CSFTRST)) 298 goto done; 299 300 if (DWC3_VER_IS_WITHIN(DWC31, 190A, ANY) || DWC3_IP_IS(DWC32)) 301 msleep(20); 302 else 303 udelay(1); 304 } while (--retries); 305 306 dev_warn(dwc->dev, "DWC3 controller soft reset failed.\n"); 307 return -ETIMEDOUT; 308 309 done: 310 /* 311 * For DWC_usb31 controller 1.80a and prior, once DCTL.CSFRST bit 312 * is cleared, we must wait at least 50ms before accessing the PHY 313 * domain (synchronization delay). 314 */ 315 if (DWC3_VER_IS_WITHIN(DWC31, ANY, 180A)) 316 msleep(50); 317 318 return 0; 319 } 320 321 /* 322 * dwc3_frame_length_adjustment - Adjusts frame length if required 323 * @dwc3: Pointer to our controller context structure 324 */ 325 static void dwc3_frame_length_adjustment(struct dwc3 *dwc) 326 { 327 u32 reg; 328 u32 dft; 329 330 if (DWC3_VER_IS_PRIOR(DWC3, 250A)) 331 return; 332 333 if (dwc->fladj == 0) 334 return; 335 336 reg = dwc3_readl(dwc->regs, DWC3_GFLADJ); 337 dft = reg & DWC3_GFLADJ_30MHZ_MASK; 338 if (dft != dwc->fladj) { 339 reg &= ~DWC3_GFLADJ_30MHZ_MASK; 340 reg |= DWC3_GFLADJ_30MHZ_SDBND_SEL | dwc->fladj; 341 dwc3_writel(dwc->regs, DWC3_GFLADJ, reg); 342 } 343 } 344 345 /** 346 * dwc3_ref_clk_period - Reference clock period configuration 347 * Default reference clock period depends on hardware 348 * configuration. For systems with reference clock that differs 349 * from the default, this will set clock period in DWC3_GUCTL 350 * register. 351 * @dwc: Pointer to our controller context structure 352 */ 353 static void dwc3_ref_clk_period(struct dwc3 *dwc) 354 { 355 unsigned long period; 356 unsigned long fladj; 357 unsigned long decr; 358 unsigned long rate; 359 u32 reg; 360 361 if (dwc->ref_clk) { 362 rate = clk_get_rate(dwc->ref_clk); 363 if (!rate) 364 return; 365 period = NSEC_PER_SEC / rate; 366 } else if (dwc->ref_clk_per) { 367 period = dwc->ref_clk_per; 368 rate = NSEC_PER_SEC / period; 369 } else { 370 return; 371 } 372 373 reg = dwc3_readl(dwc->regs, DWC3_GUCTL); 374 reg &= ~DWC3_GUCTL_REFCLKPER_MASK; 375 reg |= FIELD_PREP(DWC3_GUCTL_REFCLKPER_MASK, period); 376 dwc3_writel(dwc->regs, DWC3_GUCTL, reg); 377 378 if (DWC3_VER_IS_PRIOR(DWC3, 250A)) 379 return; 380 381 /* 382 * The calculation below is 383 * 384 * 125000 * (NSEC_PER_SEC / (rate * period) - 1) 385 * 386 * but rearranged for fixed-point arithmetic. The division must be 387 * 64-bit because 125000 * NSEC_PER_SEC doesn't fit in 32 bits (and 388 * neither does rate * period). 389 * 390 * Note that rate * period ~= NSEC_PER_SECOND, minus the number of 391 * nanoseconds of error caused by the truncation which happened during 392 * the division when calculating rate or period (whichever one was 393 * derived from the other). We first calculate the relative error, then 394 * scale it to units of 8 ppm. 395 */ 396 fladj = div64_u64(125000ULL * NSEC_PER_SEC, (u64)rate * period); 397 fladj -= 125000; 398 399 /* 400 * The documented 240MHz constant is scaled by 2 to get PLS1 as well. 401 */ 402 decr = 480000000 / rate; 403 404 reg = dwc3_readl(dwc->regs, DWC3_GFLADJ); 405 reg &= ~DWC3_GFLADJ_REFCLK_FLADJ_MASK 406 & ~DWC3_GFLADJ_240MHZDECR 407 & ~DWC3_GFLADJ_240MHZDECR_PLS1; 408 reg |= FIELD_PREP(DWC3_GFLADJ_REFCLK_FLADJ_MASK, fladj) 409 | FIELD_PREP(DWC3_GFLADJ_240MHZDECR, decr >> 1) 410 | FIELD_PREP(DWC3_GFLADJ_240MHZDECR_PLS1, decr & 1); 411 dwc3_writel(dwc->regs, DWC3_GFLADJ, reg); 412 } 413 414 /** 415 * dwc3_free_one_event_buffer - Frees one event buffer 416 * @dwc: Pointer to our controller context structure 417 * @evt: Pointer to event buffer to be freed 418 */ 419 static void dwc3_free_one_event_buffer(struct dwc3 *dwc, 420 struct dwc3_event_buffer *evt) 421 { 422 dma_free_coherent(dwc->sysdev, evt->length, evt->buf, evt->dma); 423 } 424 425 /** 426 * dwc3_alloc_one_event_buffer - Allocates one event buffer structure 427 * @dwc: Pointer to our controller context structure 428 * @length: size of the event buffer 429 * 430 * Returns a pointer to the allocated event buffer structure on success 431 * otherwise ERR_PTR(errno). 432 */ 433 static struct dwc3_event_buffer *dwc3_alloc_one_event_buffer(struct dwc3 *dwc, 434 unsigned int length) 435 { 436 struct dwc3_event_buffer *evt; 437 438 evt = devm_kzalloc(dwc->dev, sizeof(*evt), GFP_KERNEL); 439 if (!evt) 440 return ERR_PTR(-ENOMEM); 441 442 evt->dwc = dwc; 443 evt->length = length; 444 evt->cache = devm_kzalloc(dwc->dev, length, GFP_KERNEL); 445 if (!evt->cache) 446 return ERR_PTR(-ENOMEM); 447 448 evt->buf = dma_alloc_coherent(dwc->sysdev, length, 449 &evt->dma, GFP_KERNEL); 450 if (!evt->buf) 451 return ERR_PTR(-ENOMEM); 452 453 return evt; 454 } 455 456 /** 457 * dwc3_free_event_buffers - frees all allocated event buffers 458 * @dwc: Pointer to our controller context structure 459 */ 460 static void dwc3_free_event_buffers(struct dwc3 *dwc) 461 { 462 struct dwc3_event_buffer *evt; 463 464 evt = dwc->ev_buf; 465 if (evt) 466 dwc3_free_one_event_buffer(dwc, evt); 467 } 468 469 /** 470 * dwc3_alloc_event_buffers - Allocates @num event buffers of size @length 471 * @dwc: pointer to our controller context structure 472 * @length: size of event buffer 473 * 474 * Returns 0 on success otherwise negative errno. In the error case, dwc 475 * may contain some buffers allocated but not all which were requested. 476 */ 477 static int dwc3_alloc_event_buffers(struct dwc3 *dwc, unsigned int length) 478 { 479 struct dwc3_event_buffer *evt; 480 481 evt = dwc3_alloc_one_event_buffer(dwc, length); 482 if (IS_ERR(evt)) { 483 dev_err(dwc->dev, "can't allocate event buffer\n"); 484 return PTR_ERR(evt); 485 } 486 dwc->ev_buf = evt; 487 488 return 0; 489 } 490 491 /** 492 * dwc3_event_buffers_setup - setup our allocated event buffers 493 * @dwc: pointer to our controller context structure 494 * 495 * Returns 0 on success otherwise negative errno. 496 */ 497 int dwc3_event_buffers_setup(struct dwc3 *dwc) 498 { 499 struct dwc3_event_buffer *evt; 500 501 evt = dwc->ev_buf; 502 evt->lpos = 0; 503 dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(0), 504 lower_32_bits(evt->dma)); 505 dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(0), 506 upper_32_bits(evt->dma)); 507 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0), 508 DWC3_GEVNTSIZ_SIZE(evt->length)); 509 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), 0); 510 511 return 0; 512 } 513 514 void dwc3_event_buffers_cleanup(struct dwc3 *dwc) 515 { 516 struct dwc3_event_buffer *evt; 517 518 evt = dwc->ev_buf; 519 520 evt->lpos = 0; 521 522 dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(0), 0); 523 dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(0), 0); 524 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0), DWC3_GEVNTSIZ_INTMASK 525 | DWC3_GEVNTSIZ_SIZE(0)); 526 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), 0); 527 } 528 529 static int dwc3_alloc_scratch_buffers(struct dwc3 *dwc) 530 { 531 if (!dwc->has_hibernation) 532 return 0; 533 534 if (!dwc->nr_scratch) 535 return 0; 536 537 dwc->scratchbuf = kmalloc_array(dwc->nr_scratch, 538 DWC3_SCRATCHBUF_SIZE, GFP_KERNEL); 539 if (!dwc->scratchbuf) 540 return -ENOMEM; 541 542 return 0; 543 } 544 545 static int dwc3_setup_scratch_buffers(struct dwc3 *dwc) 546 { 547 dma_addr_t scratch_addr; 548 u32 param; 549 int ret; 550 551 if (!dwc->has_hibernation) 552 return 0; 553 554 if (!dwc->nr_scratch) 555 return 0; 556 557 /* should never fall here */ 558 if (!WARN_ON(dwc->scratchbuf)) 559 return 0; 560 561 scratch_addr = dma_map_single(dwc->sysdev, dwc->scratchbuf, 562 dwc->nr_scratch * DWC3_SCRATCHBUF_SIZE, 563 DMA_BIDIRECTIONAL); 564 if (dma_mapping_error(dwc->sysdev, scratch_addr)) { 565 dev_err(dwc->sysdev, "failed to map scratch buffer\n"); 566 ret = -EFAULT; 567 goto err0; 568 } 569 570 dwc->scratch_addr = scratch_addr; 571 572 param = lower_32_bits(scratch_addr); 573 574 ret = dwc3_send_gadget_generic_command(dwc, 575 DWC3_DGCMD_SET_SCRATCHPAD_ADDR_LO, param); 576 if (ret < 0) 577 goto err1; 578 579 param = upper_32_bits(scratch_addr); 580 581 ret = dwc3_send_gadget_generic_command(dwc, 582 DWC3_DGCMD_SET_SCRATCHPAD_ADDR_HI, param); 583 if (ret < 0) 584 goto err1; 585 586 return 0; 587 588 err1: 589 dma_unmap_single(dwc->sysdev, dwc->scratch_addr, dwc->nr_scratch * 590 DWC3_SCRATCHBUF_SIZE, DMA_BIDIRECTIONAL); 591 592 err0: 593 return ret; 594 } 595 596 static void dwc3_free_scratch_buffers(struct dwc3 *dwc) 597 { 598 if (!dwc->has_hibernation) 599 return; 600 601 if (!dwc->nr_scratch) 602 return; 603 604 /* should never fall here */ 605 if (!WARN_ON(dwc->scratchbuf)) 606 return; 607 608 dma_unmap_single(dwc->sysdev, dwc->scratch_addr, dwc->nr_scratch * 609 DWC3_SCRATCHBUF_SIZE, DMA_BIDIRECTIONAL); 610 kfree(dwc->scratchbuf); 611 } 612 613 static void dwc3_core_num_eps(struct dwc3 *dwc) 614 { 615 struct dwc3_hwparams *parms = &dwc->hwparams; 616 617 dwc->num_eps = DWC3_NUM_EPS(parms); 618 } 619 620 static void dwc3_cache_hwparams(struct dwc3 *dwc) 621 { 622 struct dwc3_hwparams *parms = &dwc->hwparams; 623 624 parms->hwparams0 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS0); 625 parms->hwparams1 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS1); 626 parms->hwparams2 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS2); 627 parms->hwparams3 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS3); 628 parms->hwparams4 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS4); 629 parms->hwparams5 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS5); 630 parms->hwparams6 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS6); 631 parms->hwparams7 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS7); 632 parms->hwparams8 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS8); 633 634 if (DWC3_IP_IS(DWC32)) 635 parms->hwparams9 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS9); 636 } 637 638 static int dwc3_core_ulpi_init(struct dwc3 *dwc) 639 { 640 int intf; 641 int ret = 0; 642 643 intf = DWC3_GHWPARAMS3_HSPHY_IFC(dwc->hwparams.hwparams3); 644 645 if (intf == DWC3_GHWPARAMS3_HSPHY_IFC_ULPI || 646 (intf == DWC3_GHWPARAMS3_HSPHY_IFC_UTMI_ULPI && 647 dwc->hsphy_interface && 648 !strncmp(dwc->hsphy_interface, "ulpi", 4))) 649 ret = dwc3_ulpi_init(dwc); 650 651 return ret; 652 } 653 654 /** 655 * dwc3_phy_setup - Configure USB PHY Interface of DWC3 Core 656 * @dwc: Pointer to our controller context structure 657 * 658 * Returns 0 on success. The USB PHY interfaces are configured but not 659 * initialized. The PHY interfaces and the PHYs get initialized together with 660 * the core in dwc3_core_init. 661 */ 662 static int dwc3_phy_setup(struct dwc3 *dwc) 663 { 664 unsigned int hw_mode; 665 u32 reg; 666 667 hw_mode = DWC3_GHWPARAMS0_MODE(dwc->hwparams.hwparams0); 668 669 reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0)); 670 671 /* 672 * Make sure UX_EXIT_PX is cleared as that causes issues with some 673 * PHYs. Also, this bit is not supposed to be used in normal operation. 674 */ 675 reg &= ~DWC3_GUSB3PIPECTL_UX_EXIT_PX; 676 677 /* 678 * Above 1.94a, it is recommended to set DWC3_GUSB3PIPECTL_SUSPHY 679 * to '0' during coreConsultant configuration. So default value 680 * will be '0' when the core is reset. Application needs to set it 681 * to '1' after the core initialization is completed. 682 */ 683 if (!DWC3_VER_IS_WITHIN(DWC3, ANY, 194A)) 684 reg |= DWC3_GUSB3PIPECTL_SUSPHY; 685 686 /* 687 * For DRD controllers, GUSB3PIPECTL.SUSPENDENABLE must be cleared after 688 * power-on reset, and it can be set after core initialization, which is 689 * after device soft-reset during initialization. 690 */ 691 if (hw_mode == DWC3_GHWPARAMS0_MODE_DRD) 692 reg &= ~DWC3_GUSB3PIPECTL_SUSPHY; 693 694 if (dwc->u2ss_inp3_quirk) 695 reg |= DWC3_GUSB3PIPECTL_U2SSINP3OK; 696 697 if (dwc->dis_rxdet_inp3_quirk) 698 reg |= DWC3_GUSB3PIPECTL_DISRXDETINP3; 699 700 if (dwc->req_p1p2p3_quirk) 701 reg |= DWC3_GUSB3PIPECTL_REQP1P2P3; 702 703 if (dwc->del_p1p2p3_quirk) 704 reg |= DWC3_GUSB3PIPECTL_DEP1P2P3_EN; 705 706 if (dwc->del_phy_power_chg_quirk) 707 reg |= DWC3_GUSB3PIPECTL_DEPOCHANGE; 708 709 if (dwc->lfps_filter_quirk) 710 reg |= DWC3_GUSB3PIPECTL_LFPSFILT; 711 712 if (dwc->rx_detect_poll_quirk) 713 reg |= DWC3_GUSB3PIPECTL_RX_DETOPOLL; 714 715 if (dwc->tx_de_emphasis_quirk) 716 reg |= DWC3_GUSB3PIPECTL_TX_DEEPH(dwc->tx_de_emphasis); 717 718 if (dwc->dis_u3_susphy_quirk) 719 reg &= ~DWC3_GUSB3PIPECTL_SUSPHY; 720 721 if (dwc->dis_del_phy_power_chg_quirk) 722 reg &= ~DWC3_GUSB3PIPECTL_DEPOCHANGE; 723 724 dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg); 725 726 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0)); 727 728 /* Select the HS PHY interface */ 729 switch (DWC3_GHWPARAMS3_HSPHY_IFC(dwc->hwparams.hwparams3)) { 730 case DWC3_GHWPARAMS3_HSPHY_IFC_UTMI_ULPI: 731 if (dwc->hsphy_interface && 732 !strncmp(dwc->hsphy_interface, "utmi", 4)) { 733 reg &= ~DWC3_GUSB2PHYCFG_ULPI_UTMI; 734 break; 735 } else if (dwc->hsphy_interface && 736 !strncmp(dwc->hsphy_interface, "ulpi", 4)) { 737 reg |= DWC3_GUSB2PHYCFG_ULPI_UTMI; 738 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg); 739 } else { 740 /* Relying on default value. */ 741 if (!(reg & DWC3_GUSB2PHYCFG_ULPI_UTMI)) 742 break; 743 } 744 fallthrough; 745 case DWC3_GHWPARAMS3_HSPHY_IFC_ULPI: 746 default: 747 break; 748 } 749 750 switch (dwc->hsphy_mode) { 751 case USBPHY_INTERFACE_MODE_UTMI: 752 reg &= ~(DWC3_GUSB2PHYCFG_PHYIF_MASK | 753 DWC3_GUSB2PHYCFG_USBTRDTIM_MASK); 754 reg |= DWC3_GUSB2PHYCFG_PHYIF(UTMI_PHYIF_8_BIT) | 755 DWC3_GUSB2PHYCFG_USBTRDTIM(USBTRDTIM_UTMI_8_BIT); 756 break; 757 case USBPHY_INTERFACE_MODE_UTMIW: 758 reg &= ~(DWC3_GUSB2PHYCFG_PHYIF_MASK | 759 DWC3_GUSB2PHYCFG_USBTRDTIM_MASK); 760 reg |= DWC3_GUSB2PHYCFG_PHYIF(UTMI_PHYIF_16_BIT) | 761 DWC3_GUSB2PHYCFG_USBTRDTIM(USBTRDTIM_UTMI_16_BIT); 762 break; 763 default: 764 break; 765 } 766 767 /* 768 * Above 1.94a, it is recommended to set DWC3_GUSB2PHYCFG_SUSPHY to 769 * '0' during coreConsultant configuration. So default value will 770 * be '0' when the core is reset. Application needs to set it to 771 * '1' after the core initialization is completed. 772 */ 773 if (!DWC3_VER_IS_WITHIN(DWC3, ANY, 194A)) 774 reg |= DWC3_GUSB2PHYCFG_SUSPHY; 775 776 /* 777 * For DRD controllers, GUSB2PHYCFG.SUSPHY must be cleared after 778 * power-on reset, and it can be set after core initialization, which is 779 * after device soft-reset during initialization. 780 */ 781 if (hw_mode == DWC3_GHWPARAMS0_MODE_DRD) 782 reg &= ~DWC3_GUSB2PHYCFG_SUSPHY; 783 784 if (dwc->dis_u2_susphy_quirk) 785 reg &= ~DWC3_GUSB2PHYCFG_SUSPHY; 786 787 if (dwc->dis_enblslpm_quirk) 788 reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM; 789 else 790 reg |= DWC3_GUSB2PHYCFG_ENBLSLPM; 791 792 if (dwc->dis_u2_freeclk_exists_quirk) 793 reg &= ~DWC3_GUSB2PHYCFG_U2_FREECLK_EXISTS; 794 795 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg); 796 797 return 0; 798 } 799 800 static int dwc3_clk_enable(struct dwc3 *dwc) 801 { 802 int ret; 803 804 ret = clk_prepare_enable(dwc->bus_clk); 805 if (ret) 806 return ret; 807 808 ret = clk_prepare_enable(dwc->ref_clk); 809 if (ret) 810 goto disable_bus_clk; 811 812 ret = clk_prepare_enable(dwc->susp_clk); 813 if (ret) 814 goto disable_ref_clk; 815 816 return 0; 817 818 disable_ref_clk: 819 clk_disable_unprepare(dwc->ref_clk); 820 disable_bus_clk: 821 clk_disable_unprepare(dwc->bus_clk); 822 return ret; 823 } 824 825 static void dwc3_clk_disable(struct dwc3 *dwc) 826 { 827 clk_disable_unprepare(dwc->susp_clk); 828 clk_disable_unprepare(dwc->ref_clk); 829 clk_disable_unprepare(dwc->bus_clk); 830 } 831 832 static void dwc3_core_exit(struct dwc3 *dwc) 833 { 834 dwc3_event_buffers_cleanup(dwc); 835 836 usb_phy_set_suspend(dwc->usb2_phy, 1); 837 usb_phy_set_suspend(dwc->usb3_phy, 1); 838 phy_power_off(dwc->usb2_generic_phy); 839 phy_power_off(dwc->usb3_generic_phy); 840 841 usb_phy_shutdown(dwc->usb2_phy); 842 usb_phy_shutdown(dwc->usb3_phy); 843 phy_exit(dwc->usb2_generic_phy); 844 phy_exit(dwc->usb3_generic_phy); 845 846 dwc3_clk_disable(dwc); 847 reset_control_assert(dwc->reset); 848 } 849 850 static bool dwc3_core_is_valid(struct dwc3 *dwc) 851 { 852 u32 reg; 853 854 reg = dwc3_readl(dwc->regs, DWC3_GSNPSID); 855 dwc->ip = DWC3_GSNPS_ID(reg); 856 857 /* This should read as U3 followed by revision number */ 858 if (DWC3_IP_IS(DWC3)) { 859 dwc->revision = reg; 860 } else if (DWC3_IP_IS(DWC31) || DWC3_IP_IS(DWC32)) { 861 dwc->revision = dwc3_readl(dwc->regs, DWC3_VER_NUMBER); 862 dwc->version_type = dwc3_readl(dwc->regs, DWC3_VER_TYPE); 863 } else { 864 return false; 865 } 866 867 return true; 868 } 869 870 static void dwc3_core_setup_global_control(struct dwc3 *dwc) 871 { 872 u32 hwparams4 = dwc->hwparams.hwparams4; 873 u32 reg; 874 875 reg = dwc3_readl(dwc->regs, DWC3_GCTL); 876 reg &= ~DWC3_GCTL_SCALEDOWN_MASK; 877 878 switch (DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1)) { 879 case DWC3_GHWPARAMS1_EN_PWROPT_CLK: 880 /** 881 * WORKAROUND: DWC3 revisions between 2.10a and 2.50a have an 882 * issue which would cause xHCI compliance tests to fail. 883 * 884 * Because of that we cannot enable clock gating on such 885 * configurations. 886 * 887 * Refers to: 888 * 889 * STAR#9000588375: Clock Gating, SOF Issues when ref_clk-Based 890 * SOF/ITP Mode Used 891 */ 892 if ((dwc->dr_mode == USB_DR_MODE_HOST || 893 dwc->dr_mode == USB_DR_MODE_OTG) && 894 DWC3_VER_IS_WITHIN(DWC3, 210A, 250A)) 895 reg |= DWC3_GCTL_DSBLCLKGTNG | DWC3_GCTL_SOFITPSYNC; 896 else 897 reg &= ~DWC3_GCTL_DSBLCLKGTNG; 898 break; 899 case DWC3_GHWPARAMS1_EN_PWROPT_HIB: 900 /* enable hibernation here */ 901 dwc->nr_scratch = DWC3_GHWPARAMS4_HIBER_SCRATCHBUFS(hwparams4); 902 903 /* 904 * REVISIT Enabling this bit so that host-mode hibernation 905 * will work. Device-mode hibernation is not yet implemented. 906 */ 907 reg |= DWC3_GCTL_GBLHIBERNATIONEN; 908 break; 909 default: 910 /* nothing */ 911 break; 912 } 913 914 /* check if current dwc3 is on simulation board */ 915 if (dwc->hwparams.hwparams6 & DWC3_GHWPARAMS6_EN_FPGA) { 916 dev_info(dwc->dev, "Running with FPGA optimizations\n"); 917 dwc->is_fpga = true; 918 } 919 920 WARN_ONCE(dwc->disable_scramble_quirk && !dwc->is_fpga, 921 "disable_scramble cannot be used on non-FPGA builds\n"); 922 923 if (dwc->disable_scramble_quirk && dwc->is_fpga) 924 reg |= DWC3_GCTL_DISSCRAMBLE; 925 else 926 reg &= ~DWC3_GCTL_DISSCRAMBLE; 927 928 if (dwc->u2exit_lfps_quirk) 929 reg |= DWC3_GCTL_U2EXIT_LFPS; 930 931 /* 932 * WORKAROUND: DWC3 revisions <1.90a have a bug 933 * where the device can fail to connect at SuperSpeed 934 * and falls back to high-speed mode which causes 935 * the device to enter a Connect/Disconnect loop 936 */ 937 if (DWC3_VER_IS_PRIOR(DWC3, 190A)) 938 reg |= DWC3_GCTL_U2RSTECN; 939 940 dwc3_writel(dwc->regs, DWC3_GCTL, reg); 941 } 942 943 static int dwc3_core_get_phy(struct dwc3 *dwc); 944 static int dwc3_core_ulpi_init(struct dwc3 *dwc); 945 946 /* set global incr burst type configuration registers */ 947 static void dwc3_set_incr_burst_type(struct dwc3 *dwc) 948 { 949 struct device *dev = dwc->dev; 950 /* incrx_mode : for INCR burst type. */ 951 bool incrx_mode; 952 /* incrx_size : for size of INCRX burst. */ 953 u32 incrx_size; 954 u32 *vals; 955 u32 cfg; 956 int ntype; 957 int ret; 958 int i; 959 960 cfg = dwc3_readl(dwc->regs, DWC3_GSBUSCFG0); 961 962 /* 963 * Handle property "snps,incr-burst-type-adjustment". 964 * Get the number of value from this property: 965 * result <= 0, means this property is not supported. 966 * result = 1, means INCRx burst mode supported. 967 * result > 1, means undefined length burst mode supported. 968 */ 969 ntype = device_property_count_u32(dev, "snps,incr-burst-type-adjustment"); 970 if (ntype <= 0) 971 return; 972 973 vals = kcalloc(ntype, sizeof(u32), GFP_KERNEL); 974 if (!vals) 975 return; 976 977 /* Get INCR burst type, and parse it */ 978 ret = device_property_read_u32_array(dev, 979 "snps,incr-burst-type-adjustment", vals, ntype); 980 if (ret) { 981 kfree(vals); 982 dev_err(dev, "Error to get property\n"); 983 return; 984 } 985 986 incrx_size = *vals; 987 988 if (ntype > 1) { 989 /* INCRX (undefined length) burst mode */ 990 incrx_mode = INCRX_UNDEF_LENGTH_BURST_MODE; 991 for (i = 1; i < ntype; i++) { 992 if (vals[i] > incrx_size) 993 incrx_size = vals[i]; 994 } 995 } else { 996 /* INCRX burst mode */ 997 incrx_mode = INCRX_BURST_MODE; 998 } 999 1000 kfree(vals); 1001 1002 /* Enable Undefined Length INCR Burst and Enable INCRx Burst */ 1003 cfg &= ~DWC3_GSBUSCFG0_INCRBRST_MASK; 1004 if (incrx_mode) 1005 cfg |= DWC3_GSBUSCFG0_INCRBRSTENA; 1006 switch (incrx_size) { 1007 case 256: 1008 cfg |= DWC3_GSBUSCFG0_INCR256BRSTENA; 1009 break; 1010 case 128: 1011 cfg |= DWC3_GSBUSCFG0_INCR128BRSTENA; 1012 break; 1013 case 64: 1014 cfg |= DWC3_GSBUSCFG0_INCR64BRSTENA; 1015 break; 1016 case 32: 1017 cfg |= DWC3_GSBUSCFG0_INCR32BRSTENA; 1018 break; 1019 case 16: 1020 cfg |= DWC3_GSBUSCFG0_INCR16BRSTENA; 1021 break; 1022 case 8: 1023 cfg |= DWC3_GSBUSCFG0_INCR8BRSTENA; 1024 break; 1025 case 4: 1026 cfg |= DWC3_GSBUSCFG0_INCR4BRSTENA; 1027 break; 1028 case 1: 1029 break; 1030 default: 1031 dev_err(dev, "Invalid property\n"); 1032 break; 1033 } 1034 1035 dwc3_writel(dwc->regs, DWC3_GSBUSCFG0, cfg); 1036 } 1037 1038 static void dwc3_set_power_down_clk_scale(struct dwc3 *dwc) 1039 { 1040 u32 scale; 1041 u32 reg; 1042 1043 if (!dwc->susp_clk) 1044 return; 1045 1046 /* 1047 * The power down scale field specifies how many suspend_clk 1048 * periods fit into a 16KHz clock period. When performing 1049 * the division, round up the remainder. 1050 * 1051 * The power down scale value is calculated using the fastest 1052 * frequency of the suspend_clk. If it isn't fixed (but within 1053 * the accuracy requirement), the driver may not know the max 1054 * rate of the suspend_clk, so only update the power down scale 1055 * if the default is less than the calculated value from 1056 * clk_get_rate() or if the default is questionably high 1057 * (3x or more) to be within the requirement. 1058 */ 1059 scale = DIV_ROUND_UP(clk_get_rate(dwc->susp_clk), 16000); 1060 reg = dwc3_readl(dwc->regs, DWC3_GCTL); 1061 if ((reg & DWC3_GCTL_PWRDNSCALE_MASK) < DWC3_GCTL_PWRDNSCALE(scale) || 1062 (reg & DWC3_GCTL_PWRDNSCALE_MASK) > DWC3_GCTL_PWRDNSCALE(scale*3)) { 1063 reg &= ~(DWC3_GCTL_PWRDNSCALE_MASK); 1064 reg |= DWC3_GCTL_PWRDNSCALE(scale); 1065 dwc3_writel(dwc->regs, DWC3_GCTL, reg); 1066 } 1067 } 1068 1069 /** 1070 * dwc3_core_init - Low-level initialization of DWC3 Core 1071 * @dwc: Pointer to our controller context structure 1072 * 1073 * Returns 0 on success otherwise negative errno. 1074 */ 1075 static int dwc3_core_init(struct dwc3 *dwc) 1076 { 1077 unsigned int hw_mode; 1078 u32 reg; 1079 int ret; 1080 1081 hw_mode = DWC3_GHWPARAMS0_MODE(dwc->hwparams.hwparams0); 1082 1083 /* 1084 * Write Linux Version Code to our GUID register so it's easy to figure 1085 * out which kernel version a bug was found. 1086 */ 1087 dwc3_writel(dwc->regs, DWC3_GUID, LINUX_VERSION_CODE); 1088 1089 ret = dwc3_phy_setup(dwc); 1090 if (ret) 1091 goto err0; 1092 1093 if (!dwc->ulpi_ready) { 1094 ret = dwc3_core_ulpi_init(dwc); 1095 if (ret) 1096 goto err0; 1097 dwc->ulpi_ready = true; 1098 } 1099 1100 if (!dwc->phys_ready) { 1101 ret = dwc3_core_get_phy(dwc); 1102 if (ret) 1103 goto err0a; 1104 dwc->phys_ready = true; 1105 } 1106 1107 usb_phy_init(dwc->usb2_phy); 1108 usb_phy_init(dwc->usb3_phy); 1109 ret = phy_init(dwc->usb2_generic_phy); 1110 if (ret < 0) 1111 goto err0a; 1112 1113 ret = phy_init(dwc->usb3_generic_phy); 1114 if (ret < 0) { 1115 phy_exit(dwc->usb2_generic_phy); 1116 goto err0a; 1117 } 1118 1119 ret = dwc3_core_soft_reset(dwc); 1120 if (ret) 1121 goto err1; 1122 1123 if (hw_mode == DWC3_GHWPARAMS0_MODE_DRD && 1124 !DWC3_VER_IS_WITHIN(DWC3, ANY, 194A)) { 1125 if (!dwc->dis_u3_susphy_quirk) { 1126 reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0)); 1127 reg |= DWC3_GUSB3PIPECTL_SUSPHY; 1128 dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg); 1129 } 1130 1131 if (!dwc->dis_u2_susphy_quirk) { 1132 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0)); 1133 reg |= DWC3_GUSB2PHYCFG_SUSPHY; 1134 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg); 1135 } 1136 } 1137 1138 dwc3_core_setup_global_control(dwc); 1139 dwc3_core_num_eps(dwc); 1140 1141 ret = dwc3_setup_scratch_buffers(dwc); 1142 if (ret) 1143 goto err1; 1144 1145 /* Set power down scale of suspend_clk */ 1146 dwc3_set_power_down_clk_scale(dwc); 1147 1148 /* Adjust Frame Length */ 1149 dwc3_frame_length_adjustment(dwc); 1150 1151 /* Adjust Reference Clock Period */ 1152 dwc3_ref_clk_period(dwc); 1153 1154 dwc3_set_incr_burst_type(dwc); 1155 1156 usb_phy_set_suspend(dwc->usb2_phy, 0); 1157 usb_phy_set_suspend(dwc->usb3_phy, 0); 1158 ret = phy_power_on(dwc->usb2_generic_phy); 1159 if (ret < 0) 1160 goto err2; 1161 1162 ret = phy_power_on(dwc->usb3_generic_phy); 1163 if (ret < 0) 1164 goto err3; 1165 1166 ret = dwc3_event_buffers_setup(dwc); 1167 if (ret) { 1168 dev_err(dwc->dev, "failed to setup event buffers\n"); 1169 goto err4; 1170 } 1171 1172 /* 1173 * ENDXFER polling is available on version 3.10a and later of 1174 * the DWC_usb3 controller. It is NOT available in the 1175 * DWC_usb31 controller. 1176 */ 1177 if (DWC3_VER_IS_WITHIN(DWC3, 310A, ANY)) { 1178 reg = dwc3_readl(dwc->regs, DWC3_GUCTL2); 1179 reg |= DWC3_GUCTL2_RST_ACTBITLATER; 1180 dwc3_writel(dwc->regs, DWC3_GUCTL2, reg); 1181 } 1182 1183 if (!DWC3_VER_IS_PRIOR(DWC3, 250A)) { 1184 reg = dwc3_readl(dwc->regs, DWC3_GUCTL1); 1185 1186 /* 1187 * Enable hardware control of sending remote wakeup 1188 * in HS when the device is in the L1 state. 1189 */ 1190 if (!DWC3_VER_IS_PRIOR(DWC3, 290A)) 1191 reg |= DWC3_GUCTL1_DEV_L1_EXIT_BY_HW; 1192 1193 /* 1194 * Decouple USB 2.0 L1 & L2 events which will allow for 1195 * gadget driver to only receive U3/L2 suspend & wakeup 1196 * events and prevent the more frequent L1 LPM transitions 1197 * from interrupting the driver. 1198 */ 1199 if (!DWC3_VER_IS_PRIOR(DWC3, 300A)) 1200 reg |= DWC3_GUCTL1_DEV_DECOUPLE_L1L2_EVT; 1201 1202 if (dwc->dis_tx_ipgap_linecheck_quirk) 1203 reg |= DWC3_GUCTL1_TX_IPGAP_LINECHECK_DIS; 1204 1205 if (dwc->parkmode_disable_ss_quirk) 1206 reg |= DWC3_GUCTL1_PARKMODE_DISABLE_SS; 1207 1208 if (DWC3_VER_IS_WITHIN(DWC3, 290A, ANY) && 1209 (dwc->maximum_speed == USB_SPEED_HIGH || 1210 dwc->maximum_speed == USB_SPEED_FULL)) 1211 reg |= DWC3_GUCTL1_DEV_FORCE_20_CLK_FOR_30_CLK; 1212 1213 dwc3_writel(dwc->regs, DWC3_GUCTL1, reg); 1214 } 1215 1216 if (dwc->dr_mode == USB_DR_MODE_HOST || 1217 dwc->dr_mode == USB_DR_MODE_OTG) { 1218 reg = dwc3_readl(dwc->regs, DWC3_GUCTL); 1219 1220 /* 1221 * Enable Auto retry Feature to make the controller operating in 1222 * Host mode on seeing transaction errors(CRC errors or internal 1223 * overrun scenerios) on IN transfers to reply to the device 1224 * with a non-terminating retry ACK (i.e, an ACK transcation 1225 * packet with Retry=1 & Nump != 0) 1226 */ 1227 reg |= DWC3_GUCTL_HSTINAUTORETRY; 1228 1229 dwc3_writel(dwc->regs, DWC3_GUCTL, reg); 1230 } 1231 1232 /* 1233 * Must config both number of packets and max burst settings to enable 1234 * RX and/or TX threshold. 1235 */ 1236 if (!DWC3_IP_IS(DWC3) && dwc->dr_mode == USB_DR_MODE_HOST) { 1237 u8 rx_thr_num = dwc->rx_thr_num_pkt_prd; 1238 u8 rx_maxburst = dwc->rx_max_burst_prd; 1239 u8 tx_thr_num = dwc->tx_thr_num_pkt_prd; 1240 u8 tx_maxburst = dwc->tx_max_burst_prd; 1241 1242 if (rx_thr_num && rx_maxburst) { 1243 reg = dwc3_readl(dwc->regs, DWC3_GRXTHRCFG); 1244 reg |= DWC31_RXTHRNUMPKTSEL_PRD; 1245 1246 reg &= ~DWC31_RXTHRNUMPKT_PRD(~0); 1247 reg |= DWC31_RXTHRNUMPKT_PRD(rx_thr_num); 1248 1249 reg &= ~DWC31_MAXRXBURSTSIZE_PRD(~0); 1250 reg |= DWC31_MAXRXBURSTSIZE_PRD(rx_maxburst); 1251 1252 dwc3_writel(dwc->regs, DWC3_GRXTHRCFG, reg); 1253 } 1254 1255 if (tx_thr_num && tx_maxburst) { 1256 reg = dwc3_readl(dwc->regs, DWC3_GTXTHRCFG); 1257 reg |= DWC31_TXTHRNUMPKTSEL_PRD; 1258 1259 reg &= ~DWC31_TXTHRNUMPKT_PRD(~0); 1260 reg |= DWC31_TXTHRNUMPKT_PRD(tx_thr_num); 1261 1262 reg &= ~DWC31_MAXTXBURSTSIZE_PRD(~0); 1263 reg |= DWC31_MAXTXBURSTSIZE_PRD(tx_maxburst); 1264 1265 dwc3_writel(dwc->regs, DWC3_GTXTHRCFG, reg); 1266 } 1267 } 1268 1269 return 0; 1270 1271 err4: 1272 phy_power_off(dwc->usb3_generic_phy); 1273 1274 err3: 1275 phy_power_off(dwc->usb2_generic_phy); 1276 1277 err2: 1278 usb_phy_set_suspend(dwc->usb2_phy, 1); 1279 usb_phy_set_suspend(dwc->usb3_phy, 1); 1280 1281 err1: 1282 usb_phy_shutdown(dwc->usb2_phy); 1283 usb_phy_shutdown(dwc->usb3_phy); 1284 phy_exit(dwc->usb2_generic_phy); 1285 phy_exit(dwc->usb3_generic_phy); 1286 1287 err0a: 1288 dwc3_ulpi_exit(dwc); 1289 1290 err0: 1291 return ret; 1292 } 1293 1294 static int dwc3_core_get_phy(struct dwc3 *dwc) 1295 { 1296 struct device *dev = dwc->dev; 1297 struct device_node *node = dev->of_node; 1298 int ret; 1299 1300 if (node) { 1301 dwc->usb2_phy = devm_usb_get_phy_by_phandle(dev, "usb-phy", 0); 1302 dwc->usb3_phy = devm_usb_get_phy_by_phandle(dev, "usb-phy", 1); 1303 } else { 1304 dwc->usb2_phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB2); 1305 dwc->usb3_phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB3); 1306 } 1307 1308 if (IS_ERR(dwc->usb2_phy)) { 1309 ret = PTR_ERR(dwc->usb2_phy); 1310 if (ret == -ENXIO || ret == -ENODEV) 1311 dwc->usb2_phy = NULL; 1312 else 1313 return dev_err_probe(dev, ret, "no usb2 phy configured\n"); 1314 } 1315 1316 if (IS_ERR(dwc->usb3_phy)) { 1317 ret = PTR_ERR(dwc->usb3_phy); 1318 if (ret == -ENXIO || ret == -ENODEV) 1319 dwc->usb3_phy = NULL; 1320 else 1321 return dev_err_probe(dev, ret, "no usb3 phy configured\n"); 1322 } 1323 1324 dwc->usb2_generic_phy = devm_phy_get(dev, "usb2-phy"); 1325 if (IS_ERR(dwc->usb2_generic_phy)) { 1326 ret = PTR_ERR(dwc->usb2_generic_phy); 1327 if (ret == -ENOSYS || ret == -ENODEV) 1328 dwc->usb2_generic_phy = NULL; 1329 else 1330 return dev_err_probe(dev, ret, "no usb2 phy configured\n"); 1331 } 1332 1333 dwc->usb3_generic_phy = devm_phy_get(dev, "usb3-phy"); 1334 if (IS_ERR(dwc->usb3_generic_phy)) { 1335 ret = PTR_ERR(dwc->usb3_generic_phy); 1336 if (ret == -ENOSYS || ret == -ENODEV) 1337 dwc->usb3_generic_phy = NULL; 1338 else 1339 return dev_err_probe(dev, ret, "no usb3 phy configured\n"); 1340 } 1341 1342 return 0; 1343 } 1344 1345 static int dwc3_core_init_mode(struct dwc3 *dwc) 1346 { 1347 struct device *dev = dwc->dev; 1348 int ret; 1349 1350 switch (dwc->dr_mode) { 1351 case USB_DR_MODE_PERIPHERAL: 1352 dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_DEVICE); 1353 1354 if (dwc->usb2_phy) 1355 otg_set_vbus(dwc->usb2_phy->otg, false); 1356 phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_DEVICE); 1357 phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_DEVICE); 1358 1359 ret = dwc3_gadget_init(dwc); 1360 if (ret) 1361 return dev_err_probe(dev, ret, "failed to initialize gadget\n"); 1362 break; 1363 case USB_DR_MODE_HOST: 1364 dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_HOST); 1365 1366 if (dwc->usb2_phy) 1367 otg_set_vbus(dwc->usb2_phy->otg, true); 1368 phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_HOST); 1369 phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_HOST); 1370 1371 ret = dwc3_host_init(dwc); 1372 if (ret) 1373 return dev_err_probe(dev, ret, "failed to initialize host\n"); 1374 break; 1375 case USB_DR_MODE_OTG: 1376 INIT_WORK(&dwc->drd_work, __dwc3_set_mode); 1377 ret = dwc3_drd_init(dwc); 1378 if (ret) 1379 return dev_err_probe(dev, ret, "failed to initialize dual-role\n"); 1380 break; 1381 default: 1382 dev_err(dev, "Unsupported mode of operation %d\n", dwc->dr_mode); 1383 return -EINVAL; 1384 } 1385 1386 return 0; 1387 } 1388 1389 static void dwc3_core_exit_mode(struct dwc3 *dwc) 1390 { 1391 switch (dwc->dr_mode) { 1392 case USB_DR_MODE_PERIPHERAL: 1393 dwc3_gadget_exit(dwc); 1394 break; 1395 case USB_DR_MODE_HOST: 1396 dwc3_host_exit(dwc); 1397 break; 1398 case USB_DR_MODE_OTG: 1399 dwc3_drd_exit(dwc); 1400 break; 1401 default: 1402 /* do nothing */ 1403 break; 1404 } 1405 1406 /* de-assert DRVVBUS for HOST and OTG mode */ 1407 dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_DEVICE); 1408 } 1409 1410 static void dwc3_get_properties(struct dwc3 *dwc) 1411 { 1412 struct device *dev = dwc->dev; 1413 u8 lpm_nyet_threshold; 1414 u8 tx_de_emphasis; 1415 u8 hird_threshold; 1416 u8 rx_thr_num_pkt_prd = 0; 1417 u8 rx_max_burst_prd = 0; 1418 u8 tx_thr_num_pkt_prd = 0; 1419 u8 tx_max_burst_prd = 0; 1420 u8 tx_fifo_resize_max_num; 1421 const char *usb_psy_name; 1422 int ret; 1423 1424 /* default to highest possible threshold */ 1425 lpm_nyet_threshold = 0xf; 1426 1427 /* default to -3.5dB de-emphasis */ 1428 tx_de_emphasis = 1; 1429 1430 /* 1431 * default to assert utmi_sleep_n and use maximum allowed HIRD 1432 * threshold value of 0b1100 1433 */ 1434 hird_threshold = 12; 1435 1436 /* 1437 * default to a TXFIFO size large enough to fit 6 max packets. This 1438 * allows for systems with larger bus latencies to have some headroom 1439 * for endpoints that have a large bMaxBurst value. 1440 */ 1441 tx_fifo_resize_max_num = 6; 1442 1443 dwc->maximum_speed = usb_get_maximum_speed(dev); 1444 dwc->max_ssp_rate = usb_get_maximum_ssp_rate(dev); 1445 dwc->dr_mode = usb_get_dr_mode(dev); 1446 dwc->hsphy_mode = of_usb_get_phy_mode(dev->of_node); 1447 1448 dwc->sysdev_is_parent = device_property_read_bool(dev, 1449 "linux,sysdev_is_parent"); 1450 if (dwc->sysdev_is_parent) 1451 dwc->sysdev = dwc->dev->parent; 1452 else 1453 dwc->sysdev = dwc->dev; 1454 1455 ret = device_property_read_string(dev, "usb-psy-name", &usb_psy_name); 1456 if (ret >= 0) { 1457 dwc->usb_psy = power_supply_get_by_name(usb_psy_name); 1458 if (!dwc->usb_psy) 1459 dev_err(dev, "couldn't get usb power supply\n"); 1460 } 1461 1462 dwc->has_lpm_erratum = device_property_read_bool(dev, 1463 "snps,has-lpm-erratum"); 1464 device_property_read_u8(dev, "snps,lpm-nyet-threshold", 1465 &lpm_nyet_threshold); 1466 dwc->is_utmi_l1_suspend = device_property_read_bool(dev, 1467 "snps,is-utmi-l1-suspend"); 1468 device_property_read_u8(dev, "snps,hird-threshold", 1469 &hird_threshold); 1470 dwc->dis_start_transfer_quirk = device_property_read_bool(dev, 1471 "snps,dis-start-transfer-quirk"); 1472 dwc->usb3_lpm_capable = device_property_read_bool(dev, 1473 "snps,usb3_lpm_capable"); 1474 dwc->usb2_lpm_disable = device_property_read_bool(dev, 1475 "snps,usb2-lpm-disable"); 1476 dwc->usb2_gadget_lpm_disable = device_property_read_bool(dev, 1477 "snps,usb2-gadget-lpm-disable"); 1478 device_property_read_u8(dev, "snps,rx-thr-num-pkt-prd", 1479 &rx_thr_num_pkt_prd); 1480 device_property_read_u8(dev, "snps,rx-max-burst-prd", 1481 &rx_max_burst_prd); 1482 device_property_read_u8(dev, "snps,tx-thr-num-pkt-prd", 1483 &tx_thr_num_pkt_prd); 1484 device_property_read_u8(dev, "snps,tx-max-burst-prd", 1485 &tx_max_burst_prd); 1486 dwc->do_fifo_resize = device_property_read_bool(dev, 1487 "tx-fifo-resize"); 1488 if (dwc->do_fifo_resize) 1489 device_property_read_u8(dev, "tx-fifo-max-num", 1490 &tx_fifo_resize_max_num); 1491 1492 dwc->disable_scramble_quirk = device_property_read_bool(dev, 1493 "snps,disable_scramble_quirk"); 1494 dwc->u2exit_lfps_quirk = device_property_read_bool(dev, 1495 "snps,u2exit_lfps_quirk"); 1496 dwc->u2ss_inp3_quirk = device_property_read_bool(dev, 1497 "snps,u2ss_inp3_quirk"); 1498 dwc->req_p1p2p3_quirk = device_property_read_bool(dev, 1499 "snps,req_p1p2p3_quirk"); 1500 dwc->del_p1p2p3_quirk = device_property_read_bool(dev, 1501 "snps,del_p1p2p3_quirk"); 1502 dwc->del_phy_power_chg_quirk = device_property_read_bool(dev, 1503 "snps,del_phy_power_chg_quirk"); 1504 dwc->lfps_filter_quirk = device_property_read_bool(dev, 1505 "snps,lfps_filter_quirk"); 1506 dwc->rx_detect_poll_quirk = device_property_read_bool(dev, 1507 "snps,rx_detect_poll_quirk"); 1508 dwc->dis_u3_susphy_quirk = device_property_read_bool(dev, 1509 "snps,dis_u3_susphy_quirk"); 1510 dwc->dis_u2_susphy_quirk = device_property_read_bool(dev, 1511 "snps,dis_u2_susphy_quirk"); 1512 dwc->dis_enblslpm_quirk = device_property_read_bool(dev, 1513 "snps,dis_enblslpm_quirk"); 1514 dwc->dis_u1_entry_quirk = device_property_read_bool(dev, 1515 "snps,dis-u1-entry-quirk"); 1516 dwc->dis_u2_entry_quirk = device_property_read_bool(dev, 1517 "snps,dis-u2-entry-quirk"); 1518 dwc->dis_rxdet_inp3_quirk = device_property_read_bool(dev, 1519 "snps,dis_rxdet_inp3_quirk"); 1520 dwc->dis_u2_freeclk_exists_quirk = device_property_read_bool(dev, 1521 "snps,dis-u2-freeclk-exists-quirk"); 1522 dwc->dis_del_phy_power_chg_quirk = device_property_read_bool(dev, 1523 "snps,dis-del-phy-power-chg-quirk"); 1524 dwc->dis_tx_ipgap_linecheck_quirk = device_property_read_bool(dev, 1525 "snps,dis-tx-ipgap-linecheck-quirk"); 1526 dwc->parkmode_disable_ss_quirk = device_property_read_bool(dev, 1527 "snps,parkmode-disable-ss-quirk"); 1528 1529 dwc->tx_de_emphasis_quirk = device_property_read_bool(dev, 1530 "snps,tx_de_emphasis_quirk"); 1531 device_property_read_u8(dev, "snps,tx_de_emphasis", 1532 &tx_de_emphasis); 1533 device_property_read_string(dev, "snps,hsphy_interface", 1534 &dwc->hsphy_interface); 1535 device_property_read_u32(dev, "snps,quirk-frame-length-adjustment", 1536 &dwc->fladj); 1537 device_property_read_u32(dev, "snps,ref-clock-period-ns", 1538 &dwc->ref_clk_per); 1539 1540 dwc->dis_metastability_quirk = device_property_read_bool(dev, 1541 "snps,dis_metastability_quirk"); 1542 1543 dwc->dis_split_quirk = device_property_read_bool(dev, 1544 "snps,dis-split-quirk"); 1545 1546 dwc->lpm_nyet_threshold = lpm_nyet_threshold; 1547 dwc->tx_de_emphasis = tx_de_emphasis; 1548 1549 dwc->hird_threshold = hird_threshold; 1550 1551 dwc->rx_thr_num_pkt_prd = rx_thr_num_pkt_prd; 1552 dwc->rx_max_burst_prd = rx_max_burst_prd; 1553 1554 dwc->tx_thr_num_pkt_prd = tx_thr_num_pkt_prd; 1555 dwc->tx_max_burst_prd = tx_max_burst_prd; 1556 1557 dwc->imod_interval = 0; 1558 1559 dwc->tx_fifo_resize_max_num = tx_fifo_resize_max_num; 1560 } 1561 1562 /* check whether the core supports IMOD */ 1563 bool dwc3_has_imod(struct dwc3 *dwc) 1564 { 1565 return DWC3_VER_IS_WITHIN(DWC3, 300A, ANY) || 1566 DWC3_VER_IS_WITHIN(DWC31, 120A, ANY) || 1567 DWC3_IP_IS(DWC32); 1568 } 1569 1570 static void dwc3_check_params(struct dwc3 *dwc) 1571 { 1572 struct device *dev = dwc->dev; 1573 unsigned int hwparam_gen = 1574 DWC3_GHWPARAMS3_SSPHY_IFC(dwc->hwparams.hwparams3); 1575 1576 /* Check for proper value of imod_interval */ 1577 if (dwc->imod_interval && !dwc3_has_imod(dwc)) { 1578 dev_warn(dwc->dev, "Interrupt moderation not supported\n"); 1579 dwc->imod_interval = 0; 1580 } 1581 1582 /* 1583 * Workaround for STAR 9000961433 which affects only version 1584 * 3.00a of the DWC_usb3 core. This prevents the controller 1585 * interrupt from being masked while handling events. IMOD 1586 * allows us to work around this issue. Enable it for the 1587 * affected version. 1588 */ 1589 if (!dwc->imod_interval && 1590 DWC3_VER_IS(DWC3, 300A)) 1591 dwc->imod_interval = 1; 1592 1593 /* Check the maximum_speed parameter */ 1594 switch (dwc->maximum_speed) { 1595 case USB_SPEED_FULL: 1596 case USB_SPEED_HIGH: 1597 break; 1598 case USB_SPEED_SUPER: 1599 if (hwparam_gen == DWC3_GHWPARAMS3_SSPHY_IFC_DIS) 1600 dev_warn(dev, "UDC doesn't support Gen 1\n"); 1601 break; 1602 case USB_SPEED_SUPER_PLUS: 1603 if ((DWC3_IP_IS(DWC32) && 1604 hwparam_gen == DWC3_GHWPARAMS3_SSPHY_IFC_DIS) || 1605 (!DWC3_IP_IS(DWC32) && 1606 hwparam_gen != DWC3_GHWPARAMS3_SSPHY_IFC_GEN2)) 1607 dev_warn(dev, "UDC doesn't support SSP\n"); 1608 break; 1609 default: 1610 dev_err(dev, "invalid maximum_speed parameter %d\n", 1611 dwc->maximum_speed); 1612 fallthrough; 1613 case USB_SPEED_UNKNOWN: 1614 switch (hwparam_gen) { 1615 case DWC3_GHWPARAMS3_SSPHY_IFC_GEN2: 1616 dwc->maximum_speed = USB_SPEED_SUPER_PLUS; 1617 break; 1618 case DWC3_GHWPARAMS3_SSPHY_IFC_GEN1: 1619 if (DWC3_IP_IS(DWC32)) 1620 dwc->maximum_speed = USB_SPEED_SUPER_PLUS; 1621 else 1622 dwc->maximum_speed = USB_SPEED_SUPER; 1623 break; 1624 case DWC3_GHWPARAMS3_SSPHY_IFC_DIS: 1625 dwc->maximum_speed = USB_SPEED_HIGH; 1626 break; 1627 default: 1628 dwc->maximum_speed = USB_SPEED_SUPER; 1629 break; 1630 } 1631 break; 1632 } 1633 1634 /* 1635 * Currently the controller does not have visibility into the HW 1636 * parameter to determine the maximum number of lanes the HW supports. 1637 * If the number of lanes is not specified in the device property, then 1638 * set the default to support dual-lane for DWC_usb32 and single-lane 1639 * for DWC_usb31 for super-speed-plus. 1640 */ 1641 if (dwc->maximum_speed == USB_SPEED_SUPER_PLUS) { 1642 switch (dwc->max_ssp_rate) { 1643 case USB_SSP_GEN_2x1: 1644 if (hwparam_gen == DWC3_GHWPARAMS3_SSPHY_IFC_GEN1) 1645 dev_warn(dev, "UDC only supports Gen 1\n"); 1646 break; 1647 case USB_SSP_GEN_1x2: 1648 case USB_SSP_GEN_2x2: 1649 if (DWC3_IP_IS(DWC31)) 1650 dev_warn(dev, "UDC only supports single lane\n"); 1651 break; 1652 case USB_SSP_GEN_UNKNOWN: 1653 default: 1654 switch (hwparam_gen) { 1655 case DWC3_GHWPARAMS3_SSPHY_IFC_GEN2: 1656 if (DWC3_IP_IS(DWC32)) 1657 dwc->max_ssp_rate = USB_SSP_GEN_2x2; 1658 else 1659 dwc->max_ssp_rate = USB_SSP_GEN_2x1; 1660 break; 1661 case DWC3_GHWPARAMS3_SSPHY_IFC_GEN1: 1662 if (DWC3_IP_IS(DWC32)) 1663 dwc->max_ssp_rate = USB_SSP_GEN_1x2; 1664 break; 1665 } 1666 break; 1667 } 1668 } 1669 } 1670 1671 static struct extcon_dev *dwc3_get_extcon(struct dwc3 *dwc) 1672 { 1673 struct device *dev = dwc->dev; 1674 struct device_node *np_phy; 1675 struct extcon_dev *edev = NULL; 1676 const char *name; 1677 1678 if (device_property_read_bool(dev, "extcon")) 1679 return extcon_get_edev_by_phandle(dev, 0); 1680 1681 /* 1682 * Device tree platforms should get extcon via phandle. 1683 * On ACPI platforms, we get the name from a device property. 1684 * This device property is for kernel internal use only and 1685 * is expected to be set by the glue code. 1686 */ 1687 if (device_property_read_string(dev, "linux,extcon-name", &name) == 0) 1688 return extcon_get_extcon_dev(name); 1689 1690 /* 1691 * Try to get an extcon device from the USB PHY controller's "port" 1692 * node. Check if it has the "port" node first, to avoid printing the 1693 * error message from underlying code, as it's a valid case: extcon 1694 * device (and "port" node) may be missing in case of "usb-role-switch" 1695 * or OTG mode. 1696 */ 1697 np_phy = of_parse_phandle(dev->of_node, "phys", 0); 1698 if (of_graph_is_present(np_phy)) { 1699 struct device_node *np_conn; 1700 1701 np_conn = of_graph_get_remote_node(np_phy, -1, -1); 1702 if (np_conn) 1703 edev = extcon_find_edev_by_node(np_conn); 1704 of_node_put(np_conn); 1705 } 1706 of_node_put(np_phy); 1707 1708 return edev; 1709 } 1710 1711 static int dwc3_probe(struct platform_device *pdev) 1712 { 1713 struct device *dev = &pdev->dev; 1714 struct resource *res, dwc_res; 1715 struct dwc3 *dwc; 1716 1717 int ret; 1718 1719 void __iomem *regs; 1720 1721 dwc = devm_kzalloc(dev, sizeof(*dwc), GFP_KERNEL); 1722 if (!dwc) 1723 return -ENOMEM; 1724 1725 dwc->dev = dev; 1726 1727 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1728 if (!res) { 1729 dev_err(dev, "missing memory resource\n"); 1730 return -ENODEV; 1731 } 1732 1733 dwc->xhci_resources[0].start = res->start; 1734 dwc->xhci_resources[0].end = dwc->xhci_resources[0].start + 1735 DWC3_XHCI_REGS_END; 1736 dwc->xhci_resources[0].flags = res->flags; 1737 dwc->xhci_resources[0].name = res->name; 1738 1739 /* 1740 * Request memory region but exclude xHCI regs, 1741 * since it will be requested by the xhci-plat driver. 1742 */ 1743 dwc_res = *res; 1744 dwc_res.start += DWC3_GLOBALS_REGS_START; 1745 1746 regs = devm_ioremap_resource(dev, &dwc_res); 1747 if (IS_ERR(regs)) 1748 return PTR_ERR(regs); 1749 1750 dwc->regs = regs; 1751 dwc->regs_size = resource_size(&dwc_res); 1752 1753 dwc3_get_properties(dwc); 1754 1755 if (!dwc->sysdev_is_parent) { 1756 ret = dma_set_mask_and_coherent(dwc->sysdev, DMA_BIT_MASK(64)); 1757 if (ret) 1758 return ret; 1759 } 1760 1761 dwc->reset = devm_reset_control_array_get_optional_shared(dev); 1762 if (IS_ERR(dwc->reset)) 1763 return PTR_ERR(dwc->reset); 1764 1765 if (dev->of_node) { 1766 /* 1767 * Clocks are optional, but new DT platforms should support all 1768 * clocks as required by the DT-binding. 1769 * Some devices have different clock names in legacy device trees, 1770 * check for them to retain backwards compatibility. 1771 */ 1772 dwc->bus_clk = devm_clk_get_optional(dev, "bus_early"); 1773 if (IS_ERR(dwc->bus_clk)) 1774 return dev_err_probe(dev, PTR_ERR(dwc->bus_clk), 1775 "could not get bus clock\n"); 1776 1777 if (dwc->bus_clk == NULL) { 1778 dwc->bus_clk = devm_clk_get_optional(dev, "bus_clk"); 1779 if (IS_ERR(dwc->bus_clk)) 1780 return dev_err_probe(dev, PTR_ERR(dwc->bus_clk), 1781 "could not get bus clock\n"); 1782 } 1783 1784 dwc->ref_clk = devm_clk_get_optional(dev, "ref"); 1785 if (IS_ERR(dwc->ref_clk)) 1786 return dev_err_probe(dev, PTR_ERR(dwc->ref_clk), 1787 "could not get ref clock\n"); 1788 1789 if (dwc->ref_clk == NULL) { 1790 dwc->ref_clk = devm_clk_get_optional(dev, "ref_clk"); 1791 if (IS_ERR(dwc->ref_clk)) 1792 return dev_err_probe(dev, PTR_ERR(dwc->ref_clk), 1793 "could not get ref clock\n"); 1794 } 1795 1796 dwc->susp_clk = devm_clk_get_optional(dev, "suspend"); 1797 if (IS_ERR(dwc->susp_clk)) 1798 return dev_err_probe(dev, PTR_ERR(dwc->susp_clk), 1799 "could not get suspend clock\n"); 1800 1801 if (dwc->susp_clk == NULL) { 1802 dwc->susp_clk = devm_clk_get_optional(dev, "suspend_clk"); 1803 if (IS_ERR(dwc->susp_clk)) 1804 return dev_err_probe(dev, PTR_ERR(dwc->susp_clk), 1805 "could not get suspend clock\n"); 1806 } 1807 } 1808 1809 ret = reset_control_deassert(dwc->reset); 1810 if (ret) 1811 return ret; 1812 1813 ret = dwc3_clk_enable(dwc); 1814 if (ret) 1815 goto assert_reset; 1816 1817 if (!dwc3_core_is_valid(dwc)) { 1818 dev_err(dwc->dev, "this is not a DesignWare USB3 DRD Core\n"); 1819 ret = -ENODEV; 1820 goto disable_clks; 1821 } 1822 1823 platform_set_drvdata(pdev, dwc); 1824 dwc3_cache_hwparams(dwc); 1825 1826 spin_lock_init(&dwc->lock); 1827 mutex_init(&dwc->mutex); 1828 1829 pm_runtime_set_active(dev); 1830 pm_runtime_use_autosuspend(dev); 1831 pm_runtime_set_autosuspend_delay(dev, DWC3_DEFAULT_AUTOSUSPEND_DELAY); 1832 pm_runtime_enable(dev); 1833 ret = pm_runtime_get_sync(dev); 1834 if (ret < 0) 1835 goto err1; 1836 1837 pm_runtime_forbid(dev); 1838 1839 ret = dwc3_alloc_event_buffers(dwc, DWC3_EVENT_BUFFERS_SIZE); 1840 if (ret) { 1841 dev_err(dwc->dev, "failed to allocate event buffers\n"); 1842 ret = -ENOMEM; 1843 goto err2; 1844 } 1845 1846 dwc->edev = dwc3_get_extcon(dwc); 1847 if (IS_ERR(dwc->edev)) { 1848 ret = PTR_ERR(dwc->edev); 1849 dev_err_probe(dwc->dev, ret, "failed to get extcon\n"); 1850 goto err3; 1851 } 1852 1853 ret = dwc3_get_dr_mode(dwc); 1854 if (ret) 1855 goto err3; 1856 1857 ret = dwc3_alloc_scratch_buffers(dwc); 1858 if (ret) 1859 goto err3; 1860 1861 ret = dwc3_core_init(dwc); 1862 if (ret) { 1863 dev_err_probe(dev, ret, "failed to initialize core\n"); 1864 goto err4; 1865 } 1866 1867 dwc3_check_params(dwc); 1868 dwc3_debugfs_init(dwc); 1869 1870 ret = dwc3_core_init_mode(dwc); 1871 if (ret) 1872 goto err5; 1873 1874 pm_runtime_put(dev); 1875 1876 return 0; 1877 1878 err5: 1879 dwc3_debugfs_exit(dwc); 1880 dwc3_event_buffers_cleanup(dwc); 1881 1882 usb_phy_set_suspend(dwc->usb2_phy, 1); 1883 usb_phy_set_suspend(dwc->usb3_phy, 1); 1884 phy_power_off(dwc->usb2_generic_phy); 1885 phy_power_off(dwc->usb3_generic_phy); 1886 1887 usb_phy_shutdown(dwc->usb2_phy); 1888 usb_phy_shutdown(dwc->usb3_phy); 1889 phy_exit(dwc->usb2_generic_phy); 1890 phy_exit(dwc->usb3_generic_phy); 1891 1892 dwc3_ulpi_exit(dwc); 1893 1894 err4: 1895 dwc3_free_scratch_buffers(dwc); 1896 1897 err3: 1898 dwc3_free_event_buffers(dwc); 1899 1900 err2: 1901 pm_runtime_allow(&pdev->dev); 1902 1903 err1: 1904 pm_runtime_put_sync(&pdev->dev); 1905 pm_runtime_disable(&pdev->dev); 1906 1907 disable_clks: 1908 dwc3_clk_disable(dwc); 1909 assert_reset: 1910 reset_control_assert(dwc->reset); 1911 1912 if (dwc->usb_psy) 1913 power_supply_put(dwc->usb_psy); 1914 1915 return ret; 1916 } 1917 1918 static int dwc3_remove(struct platform_device *pdev) 1919 { 1920 struct dwc3 *dwc = platform_get_drvdata(pdev); 1921 1922 pm_runtime_get_sync(&pdev->dev); 1923 1924 dwc3_core_exit_mode(dwc); 1925 dwc3_debugfs_exit(dwc); 1926 1927 dwc3_core_exit(dwc); 1928 dwc3_ulpi_exit(dwc); 1929 1930 pm_runtime_disable(&pdev->dev); 1931 pm_runtime_put_noidle(&pdev->dev); 1932 pm_runtime_set_suspended(&pdev->dev); 1933 1934 dwc3_free_event_buffers(dwc); 1935 dwc3_free_scratch_buffers(dwc); 1936 1937 if (dwc->usb_psy) 1938 power_supply_put(dwc->usb_psy); 1939 1940 return 0; 1941 } 1942 1943 #ifdef CONFIG_PM 1944 static int dwc3_core_init_for_resume(struct dwc3 *dwc) 1945 { 1946 int ret; 1947 1948 ret = reset_control_deassert(dwc->reset); 1949 if (ret) 1950 return ret; 1951 1952 ret = dwc3_clk_enable(dwc); 1953 if (ret) 1954 goto assert_reset; 1955 1956 ret = dwc3_core_init(dwc); 1957 if (ret) 1958 goto disable_clks; 1959 1960 return 0; 1961 1962 disable_clks: 1963 dwc3_clk_disable(dwc); 1964 assert_reset: 1965 reset_control_assert(dwc->reset); 1966 1967 return ret; 1968 } 1969 1970 static int dwc3_suspend_common(struct dwc3 *dwc, pm_message_t msg) 1971 { 1972 unsigned long flags; 1973 u32 reg; 1974 1975 switch (dwc->current_dr_role) { 1976 case DWC3_GCTL_PRTCAP_DEVICE: 1977 if (pm_runtime_suspended(dwc->dev)) 1978 break; 1979 spin_lock_irqsave(&dwc->lock, flags); 1980 dwc3_gadget_suspend(dwc); 1981 spin_unlock_irqrestore(&dwc->lock, flags); 1982 synchronize_irq(dwc->irq_gadget); 1983 dwc3_core_exit(dwc); 1984 break; 1985 case DWC3_GCTL_PRTCAP_HOST: 1986 if (!PMSG_IS_AUTO(msg) && !device_may_wakeup(dwc->dev)) { 1987 dwc3_core_exit(dwc); 1988 break; 1989 } 1990 1991 /* Let controller to suspend HSPHY before PHY driver suspends */ 1992 if (dwc->dis_u2_susphy_quirk || 1993 dwc->dis_enblslpm_quirk) { 1994 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0)); 1995 reg |= DWC3_GUSB2PHYCFG_ENBLSLPM | 1996 DWC3_GUSB2PHYCFG_SUSPHY; 1997 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg); 1998 1999 /* Give some time for USB2 PHY to suspend */ 2000 usleep_range(5000, 6000); 2001 } 2002 2003 phy_pm_runtime_put_sync(dwc->usb2_generic_phy); 2004 phy_pm_runtime_put_sync(dwc->usb3_generic_phy); 2005 break; 2006 case DWC3_GCTL_PRTCAP_OTG: 2007 /* do nothing during runtime_suspend */ 2008 if (PMSG_IS_AUTO(msg)) 2009 break; 2010 2011 if (dwc->current_otg_role == DWC3_OTG_ROLE_DEVICE) { 2012 spin_lock_irqsave(&dwc->lock, flags); 2013 dwc3_gadget_suspend(dwc); 2014 spin_unlock_irqrestore(&dwc->lock, flags); 2015 synchronize_irq(dwc->irq_gadget); 2016 } 2017 2018 dwc3_otg_exit(dwc); 2019 dwc3_core_exit(dwc); 2020 break; 2021 default: 2022 /* do nothing */ 2023 break; 2024 } 2025 2026 return 0; 2027 } 2028 2029 static int dwc3_resume_common(struct dwc3 *dwc, pm_message_t msg) 2030 { 2031 unsigned long flags; 2032 int ret; 2033 u32 reg; 2034 2035 switch (dwc->current_dr_role) { 2036 case DWC3_GCTL_PRTCAP_DEVICE: 2037 ret = dwc3_core_init_for_resume(dwc); 2038 if (ret) 2039 return ret; 2040 2041 dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_DEVICE); 2042 spin_lock_irqsave(&dwc->lock, flags); 2043 dwc3_gadget_resume(dwc); 2044 spin_unlock_irqrestore(&dwc->lock, flags); 2045 break; 2046 case DWC3_GCTL_PRTCAP_HOST: 2047 if (!PMSG_IS_AUTO(msg) && !device_may_wakeup(dwc->dev)) { 2048 ret = dwc3_core_init_for_resume(dwc); 2049 if (ret) 2050 return ret; 2051 dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_HOST); 2052 break; 2053 } 2054 /* Restore GUSB2PHYCFG bits that were modified in suspend */ 2055 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0)); 2056 if (dwc->dis_u2_susphy_quirk) 2057 reg &= ~DWC3_GUSB2PHYCFG_SUSPHY; 2058 2059 if (dwc->dis_enblslpm_quirk) 2060 reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM; 2061 2062 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg); 2063 2064 phy_pm_runtime_get_sync(dwc->usb2_generic_phy); 2065 phy_pm_runtime_get_sync(dwc->usb3_generic_phy); 2066 break; 2067 case DWC3_GCTL_PRTCAP_OTG: 2068 /* nothing to do on runtime_resume */ 2069 if (PMSG_IS_AUTO(msg)) 2070 break; 2071 2072 ret = dwc3_core_init_for_resume(dwc); 2073 if (ret) 2074 return ret; 2075 2076 dwc3_set_prtcap(dwc, dwc->current_dr_role); 2077 2078 dwc3_otg_init(dwc); 2079 if (dwc->current_otg_role == DWC3_OTG_ROLE_HOST) { 2080 dwc3_otg_host_init(dwc); 2081 } else if (dwc->current_otg_role == DWC3_OTG_ROLE_DEVICE) { 2082 spin_lock_irqsave(&dwc->lock, flags); 2083 dwc3_gadget_resume(dwc); 2084 spin_unlock_irqrestore(&dwc->lock, flags); 2085 } 2086 2087 break; 2088 default: 2089 /* do nothing */ 2090 break; 2091 } 2092 2093 return 0; 2094 } 2095 2096 static int dwc3_runtime_checks(struct dwc3 *dwc) 2097 { 2098 switch (dwc->current_dr_role) { 2099 case DWC3_GCTL_PRTCAP_DEVICE: 2100 if (dwc->connected) 2101 return -EBUSY; 2102 break; 2103 case DWC3_GCTL_PRTCAP_HOST: 2104 default: 2105 /* do nothing */ 2106 break; 2107 } 2108 2109 return 0; 2110 } 2111 2112 static int dwc3_runtime_suspend(struct device *dev) 2113 { 2114 struct dwc3 *dwc = dev_get_drvdata(dev); 2115 int ret; 2116 2117 if (dwc3_runtime_checks(dwc)) 2118 return -EBUSY; 2119 2120 ret = dwc3_suspend_common(dwc, PMSG_AUTO_SUSPEND); 2121 if (ret) 2122 return ret; 2123 2124 return 0; 2125 } 2126 2127 static int dwc3_runtime_resume(struct device *dev) 2128 { 2129 struct dwc3 *dwc = dev_get_drvdata(dev); 2130 int ret; 2131 2132 ret = dwc3_resume_common(dwc, PMSG_AUTO_RESUME); 2133 if (ret) 2134 return ret; 2135 2136 switch (dwc->current_dr_role) { 2137 case DWC3_GCTL_PRTCAP_DEVICE: 2138 dwc3_gadget_process_pending_events(dwc); 2139 break; 2140 case DWC3_GCTL_PRTCAP_HOST: 2141 default: 2142 /* do nothing */ 2143 break; 2144 } 2145 2146 pm_runtime_mark_last_busy(dev); 2147 2148 return 0; 2149 } 2150 2151 static int dwc3_runtime_idle(struct device *dev) 2152 { 2153 struct dwc3 *dwc = dev_get_drvdata(dev); 2154 2155 switch (dwc->current_dr_role) { 2156 case DWC3_GCTL_PRTCAP_DEVICE: 2157 if (dwc3_runtime_checks(dwc)) 2158 return -EBUSY; 2159 break; 2160 case DWC3_GCTL_PRTCAP_HOST: 2161 default: 2162 /* do nothing */ 2163 break; 2164 } 2165 2166 pm_runtime_mark_last_busy(dev); 2167 pm_runtime_autosuspend(dev); 2168 2169 return 0; 2170 } 2171 #endif /* CONFIG_PM */ 2172 2173 #ifdef CONFIG_PM_SLEEP 2174 static int dwc3_suspend(struct device *dev) 2175 { 2176 struct dwc3 *dwc = dev_get_drvdata(dev); 2177 int ret; 2178 2179 ret = dwc3_suspend_common(dwc, PMSG_SUSPEND); 2180 if (ret) 2181 return ret; 2182 2183 pinctrl_pm_select_sleep_state(dev); 2184 2185 return 0; 2186 } 2187 2188 static int dwc3_resume(struct device *dev) 2189 { 2190 struct dwc3 *dwc = dev_get_drvdata(dev); 2191 int ret; 2192 2193 pinctrl_pm_select_default_state(dev); 2194 2195 ret = dwc3_resume_common(dwc, PMSG_RESUME); 2196 if (ret) 2197 return ret; 2198 2199 pm_runtime_disable(dev); 2200 pm_runtime_set_active(dev); 2201 pm_runtime_enable(dev); 2202 2203 return 0; 2204 } 2205 2206 static void dwc3_complete(struct device *dev) 2207 { 2208 struct dwc3 *dwc = dev_get_drvdata(dev); 2209 u32 reg; 2210 2211 if (dwc->current_dr_role == DWC3_GCTL_PRTCAP_HOST && 2212 dwc->dis_split_quirk) { 2213 reg = dwc3_readl(dwc->regs, DWC3_GUCTL3); 2214 reg |= DWC3_GUCTL3_SPLITDISABLE; 2215 dwc3_writel(dwc->regs, DWC3_GUCTL3, reg); 2216 } 2217 } 2218 #else 2219 #define dwc3_complete NULL 2220 #endif /* CONFIG_PM_SLEEP */ 2221 2222 static const struct dev_pm_ops dwc3_dev_pm_ops = { 2223 SET_SYSTEM_SLEEP_PM_OPS(dwc3_suspend, dwc3_resume) 2224 .complete = dwc3_complete, 2225 SET_RUNTIME_PM_OPS(dwc3_runtime_suspend, dwc3_runtime_resume, 2226 dwc3_runtime_idle) 2227 }; 2228 2229 #ifdef CONFIG_OF 2230 static const struct of_device_id of_dwc3_match[] = { 2231 { 2232 .compatible = "snps,dwc3" 2233 }, 2234 { 2235 .compatible = "synopsys,dwc3" 2236 }, 2237 { }, 2238 }; 2239 MODULE_DEVICE_TABLE(of, of_dwc3_match); 2240 #endif 2241 2242 #ifdef CONFIG_ACPI 2243 2244 #define ACPI_ID_INTEL_BSW "808622B7" 2245 2246 static const struct acpi_device_id dwc3_acpi_match[] = { 2247 { ACPI_ID_INTEL_BSW, 0 }, 2248 { }, 2249 }; 2250 MODULE_DEVICE_TABLE(acpi, dwc3_acpi_match); 2251 #endif 2252 2253 static struct platform_driver dwc3_driver = { 2254 .probe = dwc3_probe, 2255 .remove = dwc3_remove, 2256 .driver = { 2257 .name = "dwc3", 2258 .of_match_table = of_match_ptr(of_dwc3_match), 2259 .acpi_match_table = ACPI_PTR(dwc3_acpi_match), 2260 .pm = &dwc3_dev_pm_ops, 2261 }, 2262 }; 2263 2264 module_platform_driver(dwc3_driver); 2265 2266 MODULE_ALIAS("platform:dwc3"); 2267 MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>"); 2268 MODULE_LICENSE("GPL v2"); 2269 MODULE_DESCRIPTION("DesignWare USB3 DRD Controller Driver"); 2270